FEDR27V6441L-002-03 Issue Date: Oct. 01, 2008 MR27V6441L 64M–Word × 1–Bit Serial Production Programmed ROM (P2ROM) GENERAL DESCRIPTION The MR27V6441L is a 64 Mbit Production Programmed Read-Only Memory, which is configured as 67,108,864 word × 1-bit. The MR27V6441L supports a simple read operation using a single 3.3V power supply and a Serial Peripheral Interface (SPI) compatible serial bus. The MR27V6441L have data programmed and have functions tested at LAPIS Semiconductor factory. (Using the DC pins for the programming function is NOT allowed.) FEATURES · 67,108,864-word × 1-bit configuration · +3.0 V to 3.6 V power supply · Access time 33 MHz serial clock (FAST-READ) 20 MHz serial clock (READ) · Read Identification Instruction · Active read current 30 mA MAX (FAST-READ) 20 mA MAX (READ) · Standby current 50 µA MAX · Serial Clock Input and Data Input/Output · Input Data Format 1-byte command code, 3-byte address, 1-byte dummy (FAST-READ) 1-byte command code, 3-byte address (READ) PIN CONFIGURATION (TOP VIEW) NC VCC NC DC NC NC #CS SO 1 16 SCLK 2 15 SI 3 14 NC 4 13 NC 5 12 NC 6 11 NC 7 10 VSS 8 9 NC 16SOP PACKAGES · MR27V6441L-xxxMP 16-pin plastic SOP (P-SOP16-375-1.27-K) PIN DESCRIPTIONS Pin name #CS Functions Chip Select SI Serial Data Input SO Serial Data Output SCLK VCC VSS DC NC Clock Input Power supply voltage Ground Don’t care ( 0v - Vcc ) <for reference> Program power supply voltage Vpp under Programming operation No connection 1/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM READ COMMAND DEFINITION Command Note Read Array (byte) 1st 03[H] 1 2nd AD1 2 3rd AD2 2 AD3 2 N byte read out until #CS goes high 3 4th Action Note: st 1. The 1 command 03[H] is a Read command 2. AD1 to AD3 are address input data 3. Data output Details of Command are shown as follows. 1-byte command code READ: 0 0 0 X A22 A21 A20 A15 A14 A13 A12 A6 A5 A4 A3 3-byte address AD1: AD2: AD3: A7 0 0 0 1 1 A19 A18 A17 A16 A11 A10 A9 A8 A2 A1 A0 Note: X: Dummy bit 2/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM FAST-READ COMMAND DEFINITION Command Note Read Array (byte) 1st 0B[H] 1 2nd AD1 2 3rd AD2 2 4th AD3 2 5th X 3 N byte read out until #CS goes high 4 Action Note: st 1. The 1 command 0B[H] is a Read command 2. AD1 to AD3 are address input data 3. X is a dummy cycle 4. Data output Details of Command are shown as follows. 1-byte command code FAST-READ: 3-byte address 0 0 0 0 1 0 1 1 AD1: X A22 A21 A20 A19 A18 A17 A16 AD2: A15 A14 A13 A12 A11 A10 A9 A8 AD3: A7 A6 A5 A4 A3 A2 A1 A0 Note: X: Dummy bit 3/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM READ IDENTIFICATION COMMAND DEFINITION Command 1 Note Read Array (byte) st Action 9F[H] 1 3 byte read out 2 Note: st 1. The 1 command 9F[H] is a Read Identification command 2. Identification output Details of Command are shown as follows. 1-byte command code RDID 1 0 0 1 1 1 1 1 IDENTIFICATION DEFINITION Manufacturer Identification AE[H] Device Identification Type 41[H] Capacity 15[H] 4/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM DEVICE OPERATION 1. Command “03h” or “0Bh” makes this LSI become and keep active mode until next #CS High. 2. Incorrect command makes this LSI become and keep standby mode until next #CS Low. In standby mode, SO pin is High-Z. COMMAND DESCRIPTION 1. Read Array This command consists of the 4-byte code. The 1st code is a command which decides if the device becomes standby or active mode. The 1st code “03h”activates the device. The 2nd code to the 4th code are address. 2. Fast-Read Array This command consists of the 5-byte code. The 1st code is a command which decides if the device becomes standby or active mode. The 1st code “0Bh”activates the device. The 2nd code to the 4th code are address. The 5th code is a dummy cycle. 3. Read Identification Array This command consists of the 1-byte code. The 1st code is a command which decides if the device becomes standby or active mode. The 1st code “9Fh”activates the device. 4. Standby When #CS is high , the device is put in standby mode at the next rising edge of SCLK. Maximum standby current is 50uA. When the above-mentioned 1st code is incorrect command , the device is put in standby mode at the next rising edge of SCLK. DATA SEQUENCE The data is serially sent out through SO pin, synchronized with the falling edge of SCLK. Meanwhile input data is also serially read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input and output data are bit7 (MSB) first, bit6, bit5, …, and bit0(LSB). ADDRESS SEQUENCE The address assignment is described at the COMMAND DEFINITION on page 2 or 3. 5/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Tstg — Storage temperature Value Unit –55 to 125 °C –0.5 to VCC+0.5 V –0.5 to VCC+0.5 V Input voltage VI Output voltage VO Power supply voltage VCC –0.5 to 5 V Power dissipation per package PD Ta = 25°C 1.0 W Output short circuit current IOS — 10 mA relative to VSS RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition (Ta = 0 to 70°C) Unit Min. Typ. Max. 0 — 70 °C 3.0 — 3.6 V Operating temperature under bias VCC power supply voltage VCC Input “H” level VIH 2.4 — VCC+0.5∗ V Input “L” level VIL –0.5∗∗ — 0.6 V Ta VCC = 3.0 to 3.6 V Voltage is relative to VSS. ∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns. PIN CAPACITANCE (VCC = 3.3 V, Ta = 25°C, f = 1 MHz) Typ. Max. Unit Parameter Symbol Condition Min. Input CIN1 VI = 0 V — — Output COUT VO = 0 V — — 10 DC CDC VI = 0 V — — 200 10 pF 6/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS Parameter (VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C) Typ. Max. Unit Symbol Condition Min. Input leakage current ILI VI = 0 to VCC — — 10 μA Output leakage current ILO VO = 0 to VCC — — 10 μA ICCSC #CS = VCC — — 50 μA ICCST #CS = VIH — — 1 mA — — 20 mA — — 30 mA — 2.4 — VCC+0.5∗ V VCC power supply current (Standby) VCC power supply current (Read) ICC1 VCC power supply current (Fast-Read) ICC1F Input “H” level VIH #CS = VIL f=20MHz #CS = VIL f=33MHz Input “L” level VIL — –0.5∗∗ — 0.6 V Output “H” level VOH IOH = –100 μA 2.4 — — V Output “L” level VOL IOL = 500 μA — — 0.4 V Voltage is relative to VSS. ∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns. 7/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM AC CHARACTERISTICS FAST-READ Parameter (VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C) Min. Max. Unit Symbol Condition Clock frequency tSCLK — — 33 MHz Clock high time tSKH — 12 — ns Clock low time tSKL — 12 — ns Clock rise time tR — — 3 ns Clock fall time tF — — 3 ns #CS lead clock time tCSA — 10 — ns #CS setup time tCS — 10 — ns #CS lag clock time tCSB — 5 — ns #CS hold time tCH — 5 — ns #CS high time tCSH — 80 — ns SI setup time tDS — 5 — ns SI hold time tDH — 10 — ns Access time tAA — — 15 ns SO hold time tDOH — 0 — ns SO floating time tDOZ — — 10 ns READ Parameter (VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C) Min. Max. Unit Symbol Condition Clock frequency tSCLK — — 20 MHz Clock high time tSKH — 20 — ns Clock low time tSKL — 20 — ns Clock rise time tR — — 5 ns Clock fall time tF — — 5 ns #CS lead clock time tCSA — 10 — ns #CS setup time tCS — 10 — ns #CS lag clock time tCSB — 5 — ns #CS hold time tCH — 5 — ns #CS high time tCSH — 80 — ns SI setup time tDS — 5 — ns SI hold time tDH — 10 — ns Access time tAA — — 15 ns SO hold time tDOH — 0 — ns SO floating time tDOZ — — 10 ns Measurement conditions Input signal level Input timing reference level Output load Output timing reference level Output load 0 V/Vcc Output 0.3Vcc/0.7Vcc 30 pF 0.5Vcc 30 pF (Including scope and jig) 8/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM TIMING CHART (READ CYCLE) Serial Data Input/Output Timing tCSH tCSB tCSA #CS tCS tF tR tCYC tCH SCLK tSKH BIT 7 SI tSKL BIT 6 BIT 0 tDS tDH BIT 6 BIT 7 SO tAA tDOH BIT 0 tDOZ Standby Timing #CS SCLK BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SI st 1 byte = incorrect code Hi-Z SO Standby Standby Incorrect command makes this LSI become and keep standby mode until next #CS rising edge. In standby mode, SO pin is High-Z. 9/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM Read Array Timing Waveform #CS SCLK *note1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 SI st 1 byte Command 2 nd byte AD1 SO Hi-Z #CS SCLK *note2 BIT 1 BIT 0 SI Don’t Care th 4 byte AD3 SO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 Hi-Z st 1 data output 2 nd data output #CS SCLK SI SO BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 Hi-Z th (N-1) data output th N data output th (N+1) data output Note: 1. Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 4th byte. 10/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM Fast Read Array Timing Waveform #CS SCLK *note1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 SI st 1 byte Command 2 nd byte AD1 SO Hi-Z #CS SCLK *note2 BIT 1 BIT 0 SI Don’t Care th 5 byte DUMMY SO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 Hi-Z st 1 data output 2 nd data output #CS SCLK SI SO BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 th (N-1) data output th N data output th Hi-Z (N+1) data output Note: 1. Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 5th byte. 11/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM Read Identification Timing Waveform #CS SCLK *note1 SI *note2 Don’t Care BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 st 1 byte Command SO BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 Hi-Z Manufacturer Identification tCSB #CS SCLK SI SO Don’t Care BIT 1 BIT 0 BIT15 BIT14 BIT13 BIT 2 BIT 1 BIT 0 Hi-Z Device Identification Note: 1. Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 1st byte. 12/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 13/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM REVISION HISTORY Document No. FEDR27V6441L-02-01 FEDR27V6441L-02-02 FEDR27V6441L-02-03 FEDR27V6441L-002-03 Page Date Previous Edition Current Edition Oct. 28, 2005 – – 1 1 6 6 8 8 2 2 3 3 13 13 – – Nov. 9, 2006 Mar. 16, 2007 Oct. 1, 2008 Description Final edition 1 PIN DESCRIPTIONS DC: Don’t care (H or L or Open) -- > Don’t care ( 0v - Vcc ) PIN CAPACITANCE CIN1 12 pF --- > 10 pF MAX COUT 12 pF --- > 10 pF MAX AC Characteristics FAST-READ & READ tCS 5 ns -- > 10 ns Min tDS 2 ns -- > 5 ns Min tDOZ 8 ns -- > 10 ns Max FAST-READ tR 0.1 V/ns Min -- > 3 ns Max tF 0.1 V/ns Min -- > 3 ns Max READ tR 0.1 V/ns Min -- > 5 ns Max tF 0.1 V/ns Min -- > 5 ns Max 3-byte address (0 to 3FFF[H]) --> 3-byte address 3-byte address (0 to 3FFF[H]) --> 3-byte address Replaced package diagram Changed company logo and name to OKI SEMICONDUCTOR 14/15 FEDR27V6441L-002-03 MR27V6441L / P2ROM NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Copyright 2008 - 2011 LAPIS Semiconductor Co., Ltd. 15/15