HP HCPL2631 High cmr, high speed ttl compatible optocoupler Datasheet

High CMR, High Speed TTL
Compatible Optocouplers
6N137
HCNW137
HCNW2601
HCNW2611
HCPL-0600
HCPL-0601
HCPL-0611
HCPL-0630
Technical Data
Features
• 5 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 50 V for HCPL-X601/
X631, HCNW2601 and
10 kV/µs Minimum CMR at
VCM = 1000 V for HCPLX611/X661, HCNW2611
• High Speed: 10 MBd Typical
• LSTTL/TTL Compatible
• Low Input Current
Capability: 5 mA
• Guaranteed ac and dc
Performance over Temperature: -40°C to +85°C
• Available in 8-Pin DIP,
SOIC-8, Widebody Packages
• Strobable Output (Single
Channel Products Only)
• Safety Approval
UL Recognized - 3750 V rms
for 1 minute and 5000 V rms*
for 1 minute per UL1577
CSA Approved
IEC/EN/DIN EN 60747-5-2
Approved with
VIORM = 630 V peak for
HCPL-2611 Option 060 and
VIORM = 1414 V peak for
HCNW137/26X1
• MIL-PRF-38534 Hermetic
Version Available (HCPL56XX/66XX)
Applications
• Isolated Line Receiver
• Computer-Peripheral
Interfaces
• Microprocessor System
Interfaces
• Digital Isolation for A/D,
D/A Conversion
• Switching Power Supply
• Instrument Input/Output
Isolation
• Ground Loop Elimination
• Pulse Transformer
Replacement
HCPL-0631
HCPL-0661
HCPL-2601
HCPL-2611
HCPL-2630
HCPL-2631
HCPL-4661
• Power Transistor Isolation
in Motor Drives
• Isolation of High Speed
Logic Systems
Description
The 6N137, HCPL-26XX/06XX/
4661, HCNW137/26X1 are
optically coupled gates that
combine a GaAsP light emitting
diode and an integrated high gain
photo detector. An enable input
allows the detector to be strobed.
The output of the detector IC is
Functional Diagram
6N137, HCPL-2601/2611
HCPL-0600/0601/0611
HCPL-2630/2631/4661
HCPL-0630/0631/0661
ANODE 1
1
8
VCC
VE
CATHODE 1
2
7
VO1
6
VO
CATHODE 2
3
6
VO2
5
GND
ANODE 2
4
5
GND
NC
1
8
VCC
ANODE
2
7
CATHODE
3
NC
4
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
ON
OFF
ON
OFF
ENABLE
H
H
L
L
NC
NC
OUTPUT
L
H
H
H
L
H
SHIELD
TRUTH TABLE
(POSITIVE LOGIC)
LED
ON
OFF
OUTPUT
L
H
*5000 V rms/1 Minute rating is for HCNW137/26X1 and Option 020 (6N137, HCPL-2601/11/30/31, HCPL-4661) products only.
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
2
an open collector Schottkyclamped transistor. The internal
shield provides a guaranteed
common mode transient
immunity specification of 5,000
V/µs for the HCPL-X601/X631
and HCNW2601, and 10,000 V/µs
for the HCPL-X611/X661 and
HCNW2611.
This unique design provides
maximum ac and dc circuit
isolation while achieving TTL
compatibility. The optocoupler ac
and dc operational parameters
are guaranteed from -40°C to
+85°C allowing troublefree
system performance.
The 6N137, HCPL-26XX, HCPL06XX, HCPL-4661, HCNW137,
and HCNW26X1 are suitable for
high speed logic interfacing,
input/output buffering, as line
receivers in environments that
conventional line receivers
cannot tolerate and are recommended for use in extremely high
ground or induced noise
environments.
Selection Guide
Minimum CMR
dV/dt
(V/µs)
VCM
(V)
NA
NA
8-Pin DIP (300 Mil)
Input
OnCurrent Output
(mA)
Enable
5
YES
Single
Channel
Package
6N137
NO
5,000
50
YES
10,000
1,000
YES
HCPL-2631
YES
HCPL-2602[1]
3, 500
300
YES
HCPL-2612[1]
1,000
50
YES
HCPL-261A[1]
1,000
1,000
50
YES
NO
12.5
HCNW2601
HCPL-0631
HCNW2611
HCPL-0661
HCPL-061A[1]
HCPL-263A[1]
NO
Single
Channel
Package
Hermetic
Single
and Dual
Channel
Packages
HCNW137
HCPL-0611
HCPL-4661
50
Widebody
(400 Mil)
HCPL-0630
HCPL-0601
HCPL-2611
1,000
Dual
Channel
Package
HCPL-0600
HCPL-2601
NO
1,000[2]
Single
Channel
Package
HCPL-2630
NO
3
Dual
Channel
Package
Small-Outline SO-8
HCPL-261N[1]
HCPL-063A[1]
HCPL-061N[1]
HCPL-263N[1]
[3]
Notes:
1. Technical data are on separate Agilent publications.
2. 15 kV/µs with VCM = 1 kV can be achieved using Agilent application circuit.
3. Enable is available for single channel products only, except for HCPL-193X devices.
HCPL-063N[1]
HCPL-193X[1]
HCPL-56XX[1]
HCPL-66XX[1]
3
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-2611#XXXX
020 = 5000 V rms/1 minute UL Rating Option*
060 = IEC/EN/DIN EN 60747-5-2 VIORM = 630 Vpeak Option**
300 = Gull Wing Surface Mount Option†
500 = Tape and Reel Packaging Option
XXXE = Lead Free Option
Option data sheets available. Contact Agilent sales representative or authorized distributor for information.
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July
2001 and lead free option will use “-”
*For 6N137, HCPL-2601/11/30/31 and HCPL-4661 (8-pin DIP products) only.
**For HCPL-2611 only. Combination of Option 020 and Option 060 is not available.
†Gull wing surface mount option applies to through hole parts only.
Schematic
HCPL-2630/2631/4661
HCPL-0630/0631/0661
IF
6N137, HCPL-2601/2611
HCPL-0600/0601/0611
HCNW137, HCNW2601/2611
ICC
1
ICC
8
2+
IO
6
VCC
VO
8
IF1
IO1
+
7
VCC
VO1
VF1
–
2
VF
SHIELD
–
3
SHIELD
IE
5
7
VE
USE OF A 0.1 µF BYPASS CAPACITOR CONNECTED
BETWEEN PINS 5 AND 8 IS RECOMMENDED (SEE NOTE 5).
GND
3
IO2
–
6
VO2
VF2
+
4
IF2
SHIELD
5
GND
4
Package Outline Drawings
8-pin DIP Package** (6N137, HCPL-2601/11/30/31, HCPL-4661)
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
A XXXXZ
YYWW RU
1
2
3
4
UL
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
5° TYP.
3.56 ± 0.13
(0.140 ± 0.005)
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
1.080 ± 0.320
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
**JEDEC Registered Data (for 6N137 only).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
8-pin DIP Package with Gull Wing Surface Mount Option 300
(6N137, HCPL-2601/11/30/31, HCPL-4661)
LAND PATTERN RECOMMENDATION
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
5
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
10.9 (0.430)
4
1.27 (0.050)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
3.56 ± 0.13
(0.140 ± 0.005)
1.080 ± 0.320
(0.043 ± 0.013)
2.0 (0.080)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
5
Small-Outline SO-8 Package (HCPL-0600/01/11/30/31/61)
LAND PATTERN RECOMMENDATION
8
7
6
5
5.994 ± 0.203
(0.236 ± 0.008)
XXX
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
PIN ONE 1
2
3
4
0.406 ± 0.076
(0.016 ± 0.003)
1.9 (0.075)
1.270 BSC
(0.050)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
3.175 ± 0.127
(0.125 ± 0.005)
7°
45° X
0.432
(0.017)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
0.305 MIN.
(0.012)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
8-Pin Widebody DIP Package (HCNW137, HCNW2601/11)
11.00 MAX.
(0.433)
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
9.00 ± 0.15
(0.354 ± 0.006)
5
TYPE NUMBER
A
HCNWXXXX
DATE CODE
YYWW
1
2
3
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
5.10 MAX.
(0.201)
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
0.40 (0.016)
0.56 (0.022)
DIMENSIONS IN MILLIMETERS (INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
6
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300
(HCNW137, HCNW2601/11)
11.15 ± 0.15
(0.442 ± 0.006)
8
7
6
LAND PATTERN RECOMMENDATION
5
9.00 ± 0.15
(0.354 ± 0.006)
1
2
3
13.56
(0.534)
4
2.29
(0.09)
1.3
(0.051)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00 MAX.
(0.433)
4.00 MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
2.54
(0.100)
BSC
1.00 ± 0.15
(0.039 ± 0.006)
0.75 ± 0.25
(0.030 ± 0.010)
+ 0.076
0.254 - 0.0051
+ 0.003)
(0.010 - 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
Solder Reflow Temperature Profile
300
TEMPERATURE (°C)
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
PEAK
TEMP.
230°C
200
2.5°C ± 0.5°C/SEC.
30
SEC.
160°C
150°C
140°C
SOLDERING
TIME
200°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
150
TIME (SECONDS)
200
250
7
Recommended Pb-free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
260 +0/-5 °C
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
tL
60 to 150 SEC.
25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Regulatory Information
The 6N137, HCPL-26XX/06XX/
46XX, and HCNW137/26XX have
been approved by the following
organizations:
UL
Recognized under UL 1577,
Component Recognition Program,
File E55361.
CSA
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
IEC/EN/DIN EN 60747-5-2
Approved under
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01
(Option 060 and HCNW only)
Insulation and Safety Related Specifications
Parameter
Minimum External
Air Gap (External
Clearance)
Minimum External
Tracking (External
Creepage)
Minimum Internal
Plastic Gap
(Internal Clearance)
Minimum Internal
Tracking (Internal
Creepage)
Tracking Resistance
(Comparative
Tracking Index)
Isolation Group
Symbol
L(101)
8-pin DIP
(300 Mil)
Value
7.1
SO-8
Value
4.9
L(102)
7.4
4.8
10.0
mm
0.08
0.08
1.0
mm
NA
NA
4.0
mm
200
200
200
Volts
IIIa
IIIa
IIIa
CTI
Widebody
(400 Mil)
Value
Units
9.6
mm
Conditions
Measured from input terminals
to output terminals, shortest
distance through air.
Measured from input terminals
to output terminals, shortest
distance path along body.
Through insulation distance,
conductor to conductor, usually
the direct distance between the
photoemitter and photodetector
inside the optocoupler cavity.
Measured from input terminals
to output terminals, along
internal cavity.
DIN IEC 112/VDE 0303 Part 1
Material Group
(DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
8
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics
(HCPL-2611 Option 060 Only)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Units
VIORM
I-IV
I-III
55/85/21
2
630
V peak
VPR
1181
V peak
VPR
945
V peak
VIOTM
6000
V peak
TS
IS,INPUT
PS,OUTPUT
RS
175
230
600
≥ 109
°C
mA
mW
Ω
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN
60747-5-2, for a detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics(HCNW137/2601/2611 Only)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms
for rated mains voltage ≤ 1000 V rms
Climatic Classification (DIN IEC 68 part 1)
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 16, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
Symbol
Characteristic
Units
VIORM
I-IV
I-III
55/100/21
2
1414
V peak
VPR
2651
V peak
VPR
2121
V peak
VIOTM
8000
V peak
TS
IS,INPUT
PS,OUTPUT
RS
150
400
700
≥ 109
°C
mA
mW
Ω
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN
60747-5-2, for a detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
9
Absolute Maximum Ratings* (No Derating Required up to 85°C)
Parameter
Storage Temperature
Operating Temperature†
Average Forward Input Current
Symbol
TS
TA
IF
Reverse Input Voltage
VR
Input Power Dissipation
Supply Voltage
(1 Minute Maximum)
Enable Input Voltage (Not to
Exceed VCC by more than
500 mV)
Enable Input Current
Output Collector Current
Output Collector Voltage
Output Collector Power
Dissipation
PI
VCC
Lead Solder Temperature
(Through Hole Parts Only)
VE
IE
IO
VO
PO
TLS
Package**
Single 8-Pin DIP
Single SO-8
Widebody
Dual 8-Pin DIP
Dual SO-8
8-Pin DIP, SO-8
Widebody
Widebody
Single 8-Pin DIP
Single SO-8
Widebody
Dual 8-Pin DIP
Dual SO-8
8-Pin DIP
SO-8 and
Option 300
Max.
125
85
20
Units
°C
°C
mA
15
Single 8-Pin DIP
Single SO-8
Widebody
Widebody
Solder Reflow Temperature
Profile (Surface Mount Parts Only)
Min.
-55
-40
Note
2
1, 3
5
3
40
7
V
mW
V
VCC + 0.5
V
5
50
7
85
mA
mA
V
mW
60
1
1
1
1, 4
260°C for 10 sec.,
1.6 mm below seating plane
260°C for 10 sec.,
up to seating plane
See Package Outline
Drawings section
*JEDEC Registered Data (for 6N137 only).
**Ratings apply to all devices except otherwise noted in the Package column.
†0°C to 70°C on JEDEC Registration.
Recommended Operating Conditions
Parameter
Input Current, Low Level
Input Current, High Level[1]
Power Supply Voltage
Low Level Enable Voltage†
High Level Enable Voltage†
Operating Temperature
Fan Out (at RL = 1 kΩ)[1]
Output Pull-up Resistor
Symbol
IFL*
IFH**
VCC
VEL
VEH
TA
N
RL
Min.
0
5
4.5
0
2.0
-40
330
Max.
250
15
5.5
0.8
VCC
85
5
4k
Units
µA
mA
V
V
V
°C
TTL Loads
Ω
*The off condition can also be guaranteed by ensuring that VFL ≤ 0.8 volts.
**The initial switching threshold is 5 mA or less. It is recommended that 6.3 mA to 10 mA be used for best performance and to permit
at least a 20% LED degradation guardband.
†For single channel products only.
10
Electrical Specifications
Over recommended temperature (TA = -40°C to +85°C) unless otherwise specified. All Typicals at VCC = 5 V,
TA = 25°C. All enable test conditions apply to single channel products only. See note 5.
Parameter
Sym.
Package
Typ.
Max.
Units
Test Conditions
Fig.
Note
High Level Output
Current
IOH*
All
5.5
100
µA
VCC = 5.5 V, VE = 2.0 V,
VO = 5.5 V, IF = 250 µA
1
1, 6,
19
Input Threshold
Current
ITH
Single Channel
Widebody
Dual Channel
2.0
5.0
mA
VCC = 5.5 V, VE = 2.0 V,
VO = 0.6 V,
IOL (Sinking) = 13 mA
2, 3
19
8-Pin DIP
SO-8
Widebody
0.35
0.6
V
VCC = 5.5 V, VE = 2.0 V,
IF = 5 mA,
IOL (Sinking) = 13 mA
2, 3,
4, 5
1, 19
Single Channel
7.0
6.5
10
10.0*
mA
VE = 0.5 V VCC = 5.5 V
VE = VCC
IF = 0 mA
Both
Channels
7
13.0*
mA
VE = 0.5 V VCC = 5.5 V
VE = VCC
IF = 10 mA
Both
Channels
8
Dual Channel
9.0
8.5
13
Single Channel
-0.7
-1.6
mA
VCC = 5.5 V, VE = 2.0 V
-0.9
-1.6
mA
VCC = 5.5 V, VE = 0.5 V
Low Level Output
Voltage
High Level Supply
Current
VOL*
ICCH
Min.
2.5
0.4
Dual Channel
Low Level Supply
Current
ICCL
High Level Enable
Current
IEH
Low Level Enable
Current
IEL*
High Level Enable
Voltage
VEH
Low Level Enable
Voltage
VEL
Input Forward
Voltage
VF
Input Reverse
Breakdown
Voltage
BVR*
Input Diode
Temperature
Coefficient
∆VF /
∆TA
Input Capacitance
CIN
Single Channel
15
21
2.0
8-Pin DIP
SO-8
Widebody
1.4
1.3
1.25
1.2
8-Pin DIP
SO-8
Widebody
5
9
V
1.5
1.64
0.8
V
1.75*
1.80
1.85
2.05
V
19
TA = 25°C IF = 10 mA
6, 7
1
TA = 25°C
V
IR = 10 µA
1
IR = 100 µA, TA = 25°C
3
8-Pin DIP
SO-8
Widebody
-1.6
8-Pin DIP
SO-8
Widebody
60
mV/°C
IF = 10 mA
7
1
-1.9
pF
f = 1 MHz, VF = 0 V
70
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to +70°C. HP specifies -40°C to +85°C.
1
11
Switching Specifications (AC)
Over Recommended Temperature (TA = -40°C to +85°C), VCC = 5 V, IF = 7.5 mA unless otherwise specified.
All Typicals at TA = 25°C, VCC = 5 V.
Parameter
Propagation Delay
Time to High
Output Level
Sym.
tPLH
Propagation Delay
Time to Low
Output Level
tPHL
Pulse Width
Distortion
|tPHL - tPLH|
Propagation Delay
Skew
Package**
Min. Typ.
20
48
25
8-Pin DIP
SO-8
Widebody
Max.
75*
100
Units
Test Conditions
Fig.
ns TA = 25°C RL = 350 Ω 8, 9,
CL = 15 pF 10
TA = 25°C
Note
1, 10,
19
50
75*
100
ns
3.5
35
ns
8, 9, 13, 19
10,
11
ns
12, 13,
19
40
tPSK
40
1, 11,
19
Output Rise
Time (10-90%)
tr
24
ns
12
1, 19
Output Fall
Time (90-10%)
tf
10
ns
12
1, 19
13,
14
14
Propagation Delay
Time of Enable
from VEH to VEL
tELH
Single Channel
30
ns
Propagation Delay
Time of Enable
from VEL to VEH
tEHL
Single Channel
20
ns
RL = 350 Ω,
CL = 15 pF,
VEL = 0 V, VEH = 3 V
15
*JEDEC registered data for the 6N137.
**Ratings apply to all devices except otherwise noted in the Package column.
Parameter
Logic High
Common
Mode
Transient
Immunity
Logic Low
Common
Mode
Transient
Immunity
Sym.
Device
|CMH| 6N137
HCPL-2630
HCPL-0600/0630
HCNW137
HCPL-2601/2631
HCPL-0601/0631
HCNW2601
HCPL-2611/4661
HCPL-0611/0661
HCNW2611
|CML| 6N137
HCPL-2630
HCPL-0600/0630
HCNW137
HCPL-2601/2631
HCPL-0601/0631
HCNW2601
HCPL-2611/4661
HCPL-0611/0661
HCNW2611
Min.
Typ. Units
10,000 V/µs
Test Conditions
|VCM| = 10 V VCC = 5 V, IF = 0 mA,
VO(MIN) = 2 V,
RL = 350 Ω, TA = 25°C
5,000
10,000
|VCM| = 50 V
10,000 15,000
|VCM| = 1 kV
10,000
V/µs
|VCM| = 10 V
10,000
|VCM| = 50 V
10,000 15,000
|VCM| = 1 kV
5,000
VCC = 5 V, IF = 7.5 mA,
VO(MAX) = 0.8 V,
RL = 350 Ω, TA = 25°C
Fig.
15
Note
1, 16,
18, 19
15
1, 17,
18, 19
12
Package Characteristics
All Typicals at TA = 25°C.
Parameter
Sym.
Package
Input-Output
Insulation
II-O*
Single 8-Pin DIP
Single SO-8
Input-Output
Momentary Withstand Voltage**
VISO
8-Pin DIP, SO-8
Widebody
OPT 020†
Input-Output
Resistance
RI-O
8-Pin DIP, SO-8
Widebody
Input-Output
Capacitance
CI-O
Min.
Typ.
Max.
Units
1
µA
3750
5000
5000
1012
1011
V rms
0.6
0.5
20, 21
20, 22
VI-O = 500 V dc
pF
f = 1 MHz, TA = 25°C
RH ≤ 45%, t = 5 s,
VI-I = 500 V
0.6
II-I
Dual Channel
0.005
µA
Resistance
(Input-Input)
RI-I
Dual Channel
1011
Ω
Capacitance
(Input-Input)
CI-I
Dual 8-Pin DIP
Dual SO-8
0.03
0.25
pF
Note
RH ≤ 50%, t = 1 min,
TA = 25°C
TA = 25°C
TA = 100°C
Input-Input
Insulation
Leakage Current
Fig.
20, 21
Ω
1012
1013
8-Pin DIP, SO-8
Widebody
Test Conditions
45% RH, t = 5 s,
VI-O = 3 kV dc, TA = 25°C
1, 20,
23
1, 20,
23
24
24
f = 1 MHz
24
*JEDEC registered data for the 6N137. The JEDEC Registration specifies 0°C to 70°C. Agilent specifies -40°C to 85°C.
**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table
(if applicable), your equipment level safety specification or Agilent Application Note 1074 entitled “Optocoupler Input-Output
Endurance Voltage.”
†For 6N137, HCPL-2601/2611/2630/2631/4661 only.
Notes:
1. Each channel.
2. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does
not exceed 20 mA.
3. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does
not exceed 15 mA.
4. Derate linearly above 80°C free-air temperature at a rate of 2.7 mW/°C for the SOIC-8 package.
5. Bypassing of the power supply line is required, with a 0.1 µF ceramic disc capacitor adjacent to each optocoupler as illustrated in
Figure 17. Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm.
6. The JEDEC registration for the 6N137 specifies a maximum IOH of 250 µA. Agilent guarantees a maximum IOH of 100 µA.
7. The JEDEC registration for the 6N137 specifies a maximum ICCH of 15 mA. Agilent guarantees a maximum ICCH of 10 mA.
8. The JEDEC registration for the 6N137 specifies a maximum ICCL of 18 mA. Agilent guarantees a maximum ICCL of 13 mA.
9. The JEDEC registration for the 6N137 specifies a maximum IEL of –2.0 mA. Agilent guarantees a maximum IEL of -1.6 mA.
10. The tPLH propagation delay is measured from the 3.75 mA point on the falling edge of the input pulse to the 1.5 V point on the
rising edge of the output pulse.
11. The tPHL propagation delay is measured from the 3.75 mA point on the rising edge of the input pulse to the 1.5 V point on the
falling edge of the output pulse.
12. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified
test conditions.
13. See application section titled “Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew” for more information.
14. The tELH enable propagation delay is measured from the 1.5 V point on the falling edge of the enable input pulse to the 1.5 V
point on the rising edge of the output pulse.
15. The tEHL enable propagation delay is measured from the 1.5 V point on the rising edge of the enable input pulse to the 1.5 V point
on the falling edge of the output pulse.
16. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state
(i.e., VO > 2.0 V).
17. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state
(i.e., VO < 0.8 V).
18. For sinusoidal voltages, (|dVCM | / dt)max = π fCMVCM(p-p).
13
8-PIN DIP, SO-8
6
VCC = 5.5 V
VO = 5.5 V
VE = 2.0 V*
IF = 250 µA
10
* FOR SINGLE
CHANNEL
PRODUCTS
ONLY
5
0
-60 -40 -20
0
20
40
60
5
4
RL = 1 KΩ
2
RL = 4 KΩ
1
0
TA – TEMPERATURE – °C
8-PIN DIP, SO-8
6
5
VCC = 5.0 V
VO = 0.6 V
4
RL = 350 Ω
3
RL = 1 KΩ
2
1
RL = 4 KΩ
0
-60 -40 -20
0
20
40
60
80 100
TA – TEMPERATURE – °C
1
2
3
4
6
5
IF – FORWARD INPUT CURRENT – mA
VCC = 5 V
TA = 25 °C
5
4
RL = 350 Ω
3
RL = 1 KΩ
2
RL = 4 KΩ
1
0
0
1
2
WIDEBODY
6
5
VCC = 5.0 V
VO = 0.6 V
4
3
RL = 1 KΩ
RL = 350 Ω
2
1
RL = 4 KΩ
0
-60 -40 -20
0
20
40
60
80 100
TA – TEMPERATURE – °C
Figure 3. Typical Input Threshold Current vs. Temperature.
3
4
5
6
IF – FORWARD INPUT CURRENT – mA
Figure 2. Typical Output Voltage vs. Forward Input Current.
ITH – INPUT THRESHOLD CURRENT – mA
ITH – INPUT THRESHOLD CURRENT – mA
Figure 1. Typical High Level Output
Current vs. Temperature.
RL = 350 Ω
3
0
80 100
WIDEBODY
6
VCC = 5 V
TA = 25 °C
VO – OUTPUT VOLTAGE – V
15
VO – OUTPUT VOLTAGE – V
IOH – HIGH LEVEL OUTPUT CURRENT – µA
19. No external pull up is required for a high logic state on the enable input. If the VE pin is not used, tying VE to VCC will result in
improved CMR performance. For single channel products only.
20. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.
21. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for one second
(leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge
(Method b) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
22. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for one second
(leakage detection current limit, II-O ≤ 5 µA). This test is performed before the 100% production test for partial discharge
(Method b) shown in the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table, if applicable.
23. Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products
only.
24. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. For dual channel products only.
0.7
VCC = 5.5 V
VE = 2.0 V*
IF = 5.0 mA
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
0.6
0.5
IO = 16 mA
IO = 12.8 mA
0.4
0.3
0.2
IO = 9.6 mA
IO = 6.4 mA
0.1
0
-60 -40 -20
20
0
40
60
80 100
WIDEBODY
0.8
VCC = 5.5 V
VE = 2.0 V
IF = 5.0 mA
0.7
0.6
IO = 16 mA
0.5
IO = 12.8 mA
0.4
0.3
IO = 9.6 mA
IO = 6.4 mA
0.2
0.1
0
-60 -40 -20
TA – TEMPERATURE – °C
0
20
40
60
80 100
8-PIN DIP, SO-8
10
IF – FORWARD CURRENT – mA
IF – FORWARD CURRENT – mA
TA = 25 °C
100
IF
+
VF
–
1.0
0.1
0.01
0.001
1.1
1.2
1.3
1.4
1.5
1.6
TA = 25 °C
100
IF
+
VF
–
10
1.0
0.1
0.01
0.001
1.2
1.3
1.4
1.5
1.6
1.7
VF – FORWARD VOLTAGE – V
VF – FORWARD VOLTAGE – V
8-PIN DIP, SO-8
dVF/dT – FORWARD VOLTAGE
TEMPERATURE COEFFICIENT – mV/°C
dVF/dT – FORWARD VOLTAGE
TEMPERATURE COEFFICIENT – mV/°C
Figure 6. Typical Input Diode Forward Characteristic.
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
0.1
1
10
100
IF – PULSE INPUT CURRENT – mA
WIDEBODY
-2.3
-2.2
-2.1
-2.0
-1.9
-1.8
0.1
1
VCC = 5.0 V
VE = 2.0 V*
VOL = 0.6 V
* FOR SINGLE
CHANNEL
PRODUCTS ONLY
60
IF = 10-15 mA
50
IF = 5.0 mA
40
20
-60 -40 -20
0
20
40
60
80 100
Figure 5. Typical Low Level Output
Current vs. Temperature.
WIDEBODY
1000
70
TA – TEMPERATURE – °C
TA – TEMPERATURE – °C
Figure 4. Typical Low Level Output Voltage vs. Temperature.
1000
IOL – LOW LEVEL OUTPUT CURRENT – mA
8-PIN DIP, SO-8
0.8
VOL – LOW LEVEL OUTPUT VOLTAGE – V
VOL – LOW LEVEL OUTPUT VOLTAGE – V
14
10
100
IF – PULSE INPUT CURRENT – mA
Figure 7. Typical Temperature Coefficient of Forward Voltage vs. Input Current.
15
PULSE GEN.
Z O = 50 Ω
t f = t r = 5 ns
SINGLE CHANNEL
PULSE GEN.
ZO = 50 Ω
t f = t r = 5 ns
IF
1
INPUT
MONITORING
NODE
DUAL CHANNEL
+5 V
2
7
3
6
4
5
0.1µF
BYPASS
OUTPUT VO
MONITORING
NODE
GND
1
VCC 8
2
7
3
6
4
5
RL
INPUT
MONITORING
NODE
RL
*CL
RM
RM
IF = 7.50 mA
INPUT
IF
IF = 3.75 mA
t PHL
t PLH
OUTPUT
VO
1.5 V
Figure 8. Test Circuit for tPHL and tPLH.
80
tPLH , RL = 4 KΩ
tPHL , RL = 350 Ω
1 KΩ
60
4 KΩ
tPLH , RL = 1 KΩ
40
20
tPLH , RL = 350 Ω
0
-60 -40 -20
tP – PROPAGATION DELAY – ns
tP – PROPAGATION DELAY – ns
105
VCC = 5.0 V
IF = 7.5 mA
40
60
30
VCC = 5.0 V
IF = 7.5 mA
20
RL = 350 Ω
0
RL = 1 kΩ
40
60
80 100
TA – TEMPERATURE – °C
Figure 11. Typical Pulse Width
Distortion vs. Temperature.
5
7
9
11
13
15
Figure 10. Typical Propagation Delay
vs. Pulse Input Current.
tr, tf – RISE, FALL TIME – ns
PWD – PULSE WIDTH DISTORTION – ns
RL = 4 kΩ
20
tPHL , RL = 350 Ω
1 KΩ
4 KΩ
IF – PULSE INPUT CURRENT – mA
40
0
tPLH , RL = 1 KΩ
45
80 100
Figure 9. Typical Propagation Delay
vs. Temperature.
-10
-60 -40 -20
tPLH , RL = 350 Ω
60
TA – TEMPERATURE – °C
10
tPLH , RL = 4 KΩ
75
30
20
0
VCC = 5.0 V
TA = 25°C
90
VCC = 5.0 V
IF = 7.5 mA
tRISE
tFALL
RL = 4 kΩ
300
290
60
RL = 1 kΩ
40
RL = 350 Ω
20
0
-60 -40 -20
0.1µF
BYPASS
CL*
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
100
+5 V
IF
VCC 8
RL = 350 Ω, 1 kΩ, 4 kΩ
0 20 40 60 80 100
TA – TEMPERATURE – °C
Figure 12. Typical Rise and Fall Time
vs. Temperature.
GND
OUTPUT VO
MONITORING
NODE
16
PULSE GEN.
Z O = 50 Ω
t f = t r = 5 ns
INPUT VE
MONITORING NODE
+5 V
7.5 mA
IF
3.0 V
VCC 8
1
2
0.1 µF
BYPASS
7
3
RL
*C L
GND
1.5 V
t EHL
OUTPUT VO
MONITORING
NODE
6
4
INPUT
VE
t ELH
OUTPUT
VO
1.5 V
5
*C L IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE.
tE – ENABLE PROPAGATION DELAY – ns
Figure 13. Test Circuit for tEHL and tELH.
120
VCC = 5.0 V
VEH = 3.0 V
VEL = 0 V
90 IF = 7.5 mA
tELH, RL = 4 kΩ
60
tELH, RL = 1 kΩ
30
tELH, RL = 350 Ω
tEHL, RL = 350 Ω, 1 kΩ, 4 kΩ
0
-60 -40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C
Figure 14. Typical Enable Propagation
Delay vs. Temperature.
IF
SINGLE CHANNEL
IF
1
VCC 8
B
A
VFF
2
7
3
6
4
GND
DUAL CHANNEL
B
+5 V
0.1 µF
BYPASS
1
A
VCC 8
RL
2
7
3
6
VFF
OUTPUT VO
MONITORING
NODE
5
4
VCM
GND
VCM
+
–
PULSE
GENERATOR
Z O = 50 Ω
+
–
PULSE
GENERATOR
Z O = 50 Ω
VCM (PEAK)
VCM
VO
VO
0V
5V
SWITCH AT A: IF = 0 mA
CMH
VO (MIN.)
SWITCH AT B: IF = 7.5 mA
VO (MAX.)
0.5 V
+5 V
RL
CML
Figure 15. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
5
0.1 µF
BYPASS
OUTPUT VO
MONITORING
NODE
HCPL-2611 OPTION 060
800
PS (mW)
700
IS (mA)
600
500
400
300
200
100
0
0
25
50
75 100 125 150 175 200
TS – CASE TEMPERATURE – °C
OUTPUT POWER – PS, INPUT CURRENT – IS
OUTPUT POWER – PS, INPUT CURRENT – IS
17
HCNWXXXX
PS (mW)
IS (mA)
800
700
600
500
400
300
200
100
0
0
25
50
75
100 125 150 175
TS – CASE TEMPERATURE – °C
Figure 16. Thermal Derating Curve, Dependence of Safety Limiting Value with
Case Temperature per IEC/EN/DIN EN 60747-5-2.
GND BUS (BACK)
VCC BUS (FRONT)
NC
ENABLE
0.1µF
NC
OUTPUT
10 mm MAX.
(SEE NOTE 5)
SINGLE CHANNEL
DEVICE ILLUSTRATED.
Figure 17. Recommended Printed Circuit Board Layout.
18
SINGLE CHANNEL DEVICE
VCC1
5V
5V
8
VCC2
390 Ω
470 Ω
IF
2
6
+
D1*
VF
–
GND 1
0.1 µF
BYPASS
3
5
SHIELD
GND 2
VE 7
1
2
*DIODE D1 (1N916 OR EQUIVALENT) IS NOT REQUIRED FOR UNITS WITH OPEN COLLECTOR OUTPUT.
DUAL CHANNEL DEVICE
CHANNEL 1 SHOWN
VCC1 5 V
5V
8
VCC2
390 Ω
470 Ω
IF
1
7
+
D1*
0.1 µF
BYPASS
VF
–
GND 1
2
5
GND 2
SHIELD
1
Figure 18. Recommended TTL/LSTTL to TTL/LSTTL Interface Circuit.
2
19
Propagation Delay, PulseWidth Distortion and
Propagation Delay Skew
Propagation delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propagation delay from low to high (tPLH)
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (tPHL) is the
amount of time required for the
input signal to propagate to the
output causing the output to
change from high to low (see
Figure 8).
Pulse-width distortion (PWD)
results when tPLH and tPHL differ in
value. PWD is defined as the
difference between tPLH and tPHL
and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being
transmitted. Typically, PWD on
the order of 20-30% of the
minimum pulse width is tolerable;
the exact figure depends on the
particular application (RS232,
RS422, T-l, etc.).
Propagation delay skew, tPSK, is
an important parameter to
consider in parallel data applica-
tions where synchronization of
signals on parallel data lines is a
concern. If the parallel data is
being sent through a group of
optocouplers, differences in
propagation delays will cause the
data to arrive at the outputs of the
optocouplers at different times. If
this difference in propagation
delays is large enough, it will
determine the maximum rate at
which parallel data can be sent
through the optocouplers.
signals at the inputs and outputs
of the optocouplers. To obtain the
maximum data transmission rate,
both edges of the clock signal are
being used to clock the data; if
only one edge were used, the
clock signal would need to be
twice as fast.
Propagation delay skew is defined
as the difference between the
minimum and maximum
propagation delays, either tPLH or
tPHL, for any given group of
optocouplers which are operating
under the same conditions (i.e.,
the same drive current, supply
voltage, output load, and
operating temperature). As
illustrated in Figure 19, if the
inputs of a group of optocouplers
are switched either ON or OFF at
the same time, tPSK is the
difference between the shortest
propagation delay, either tPLH or
tPHL, and the longest propagation
delay, either tPLH or tPHL.
Propagation delay skew represents the uncertainty of where an
edge might be after being sent
through an optocoupler. Figure
20 shows that there will be
uncertainty in both the data and
the clock lines. It is important
that these two areas of uncertainty
not overlap, otherwise the clock
signal might arrive before all of
the data outputs have settled, or
some of the data outputs may
start to change before the clock
signal has arrived. From these
considerations, the absolute
minimum pulse width that can be
sent through optocouplers in a
parallel application is twice tPSK. A
cautious design should use a
slightly longer pulse width to
ensure that any additional
uncertainty in the rest of the
circuit does not cause a problem.
As mentioned earlier, tPSK can
determine the maximum parallel
data transmission rate. Figure 20
is the timing diagram of a typical
parallel data application with both
the clock and the data lines being
sent through optocouplers. The
figure shows data and clock
The tPSK specified optocouplers
offer the advantages of
guaranteed specifications for
propagation delays, pulsewidth
distortion and propagation delay
skew over the recommended
temperature, input current, and
power supply ranges.
DATA
IF
INPUTS
50%
CLOCK
1.5 V
VO
IF
DATA
50%
OUTPUTS
VO
1.5 V
t PSK
CLOCK
t PSK
Figure 19. Illustration of Propagation
Delay Skew - tPSK.
t PSK
Figure 20. Parallel Data Transmission
Example.
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Copyright © 2004 Agilent Technologies, Inc.
Obsoletes 5989-0302EN
December 29, 2004
5989-2126EN