Cypress FM28V202A 2-mbit (128 k ã 16) f-ram memory Datasheet

FM28V202A
2-Mbit (128 K × 16) F-RAM Memory
2-Mbit (128 K × 16) F-RAM Memory
Features
■
2-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128 K × 16
❐ Configurable as 256 K × 8 using UB and LB
14
❐ High-endurance 100 trillion (10 ) read/writes
❐ 151-year data retention (see the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Page mode operation to 30-ns cycle time
❐ Advanced high-reliability ferroelectric process
■
SRAM compatible
❐ Industry-standard 128 K × 16 SRAM pinout
❐ 60-ns access time, 90-ns cycle time
■
Advanced features
❐ Software-programmable block write-protect
■
Superior to battery-backed SRAM modules
❐ No battery concerns
❐ Monolithic reliability
❐ True surface mount solution, no rework steps
❐ Superior for moisture, shock, and vibration
■
Low power consumption
❐ Active current 7 mA (typ)
❐ Standby current 120 A (typ)
■
Low-voltage operation: VDD = 2.0 V to 3.6 V
■
Industrial temperature: –40 C to +85 C
■
44-pin thin small outline package (TSOP) Type II
■
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM28V202A is a 128 K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM28V202A operation is similar to that of other RAM
devices and therefore, it can be used as a drop-in replacement
for a standard SRAM in a system. Read cycles may be triggered
by CE or simply by changing the address and write cycles may
be triggered by CE or WE. The F-RAM memory is nonvolatile
due to its unique ferroelectric memory process. These features
make the FM28V202A ideal for nonvolatile memory applications
requiring frequent or rapid writes.
The device is available in a 400-mil, 44-pin TSOP-II surface
mount package. Device specifications are guaranteed over the
industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
A 1-0
16 K x 16 block
16 K x 16 block
16 K x 16 block
16 K x 16 block
16 K x 16 block
16 K x 16 block
16 K x 16 block
16 K x 16 block
...
A 16-2
Block & Row Decoder
A16-0
Address Latch & Write Protect
Logic Block Diagram
...
CE
Column Decoder
WE
UB, LB
I/O Latch & Bus Driver
Control
Logic
DQ15-0
OE
ZZ
Cypress Semiconductor Corporation
Document Number: 001-90309 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 20, 2017
FM28V202A
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
Memory Operation ....................................................... 4
Read Operation ........................................................... 4
Write Operation ........................................................... 4
Page Mode Operation ................................................. 4
Pre-charge Operation .................................................. 4
Sleep Mode ................................................................. 4
Software Write Protect ................................................ 5
Software Write-Protect Timing .................................... 7
SRAM Drop-In Replacement ....................................... 8
Endurance ................................................................... 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
DC Electrical Characteristics .......................................... 9
Data Retention and Endurance ..................................... 10
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Conditions ........................................................ 10
Document Number: 001-90309 Rev. *G
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 12
Power Cycle and Sleep Mode Timing ........................... 16
Functional Truth Table ................................................... 17
Byte Select Truth Table .................................................. 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagram ............................................................ 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Page 2 of 22
FM28V202A
Pinout
Figure 1. 44-pin TSOP II pinout
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VDD
VSS
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44-pin TSOP II
(× 16)
Top View
(not to scale)
A5
A6
A7
OE
UB
44
43
42
41
40
39
38
37
36
35
34
33
32
31
LB
DQ15
DQ14
DQ13
DQ12
VSS
VDD
DQ11
DQ10
30
29
28
27
26
25
24
23
DQ9
DQ8
ZZ
A8
A9
A10
A11
NC
Pin Definitions
Pin Name
I/O Type
Description
A0–A16
Input
Address inputs: The 17 address lines select one of 128K words in the F-RAM array. The lowest two
address lines A1–A0 may be used for page mode read and write operations.
DQ0–DQ15 Input/Output Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array.
WE
Input
Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM28V202A to
write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address
for page mode write cycles.
CE
Input
Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A1–A0 address inputs allow
page mode operation.
OE
Input
Output Enable: When OE is LOW, the FM28V202A drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
UB
Input
Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 256K × 8, the UB and LB
pins may be tied to ground.
LB
Input
Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 256 K × 8, the UB and LB
pins may be tied to ground.
ZZ
Input
Sleep: When ZZ is LOW, the device enters a low-power sleep mode for the lowest supply current
condition. ZZ must be HIGH for a normal read/write operation. This pin must be tied to VDD if not used.
VSS
Ground
VDD
NC
Ground for the device. Must be connected to the ground of the system.
Power supply Power supply input to the device.
No connect
No connect. This pin is not connected to the die.
Document Number: 001-90309 Rev. *G
Page 3 of 22
FM28V202A
Device Operation
The FM28V202A is a word wide F-RAM memory logically
organized as 131,072 × 16 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers page
mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either CE transitions LOW or the upper address
(A16–A2) changes. See the Functional Truth Table on page 17
for a complete description of read and write modes.
Memory Operation
Users access 131,072 memory locations, each with 16 data bits
through a parallel interface. The F-RAM array is organized as
eight blocks, each having 4096 rows. Each row has four column
locations, which allow fast access in page mode operation.
When an initial address is latched by the falling edge of CE,
subsequent column locations may be accessed without the need
to toggle CE. When CE is deasserted HIGH, a pre-charge
operation begins. Writes occur immediately at the end of the
access with no delay. The WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile memory
array immediately, which is a feature unique to F-RAM called
NoDelay writes.
Read Operation
A read operation begins on the falling edge of CE. The falling
edge of CE causes the address to be latched and starts a
memory read cycle if WE is HIGH. Data becomes available on
the bus after the access time is met. When the address is latched
and the access completed, a new access to a random location
(different row) may begin while CE is still LOW. The minimum
cycle time for random addresses is tRC. Note that unlike SRAMs,
the FM28V202A's CE-initiated access time is faster than the
address access time.
The FM28V202A will drive the data bus when OE and at least
one of the byte enables (UB, LB) is asserted LOW. The upper
data byte is driven when UB is LOW, and the lower data byte is
driven when LB is LOW. If OE is asserted after the memory
access time is met, the data bus will be driven with valid data. If
OE is asserted before completing the memory access, the data
bus will not be driven until valid data is available. This feature
minimizes supply current in the system by eliminating transients
caused by invalid data being driven to the bus. When OE is
deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM28V202A, writes occur in the same interval as reads.
The FM28V202A supports both CE and WE controlled write
cycles. In both cases, the address A16–A2 is latched on the
falling edge of CE.
In a CE-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when CE falls.
In this case, the device begins the memory cycle as a write. The
FM28V202A will not drive the data bus regardless of the state of
OE as long as WE is LOW. Input data must be valid when CE is
Document Number: 001-90309 Rev. *G
deasserted HIGH. In a WE-controlled write, the memory cycle
begins on the falling edge of CE. The WE signal falls some time
later. Therefore, the memory cycle begins as a read. The data
bus will be driven if OE is LOW; however, it will be HI-Z when WE
is asserted LOW. The CE- and WE-controlled write timing cases
are shown in the Switching Waveforms on page 13.
Write access to the array begins on the falling edge of WE after
the memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access (rising edge of WE or CE).
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Page Mode Operation
The F-RAM array is organized as eight blocks, each having 4096
rows. Each row has four column-address locations. Address
inputs A1–A0 define the column address to be accessed. An
access can start on any column address, and other column
locations may be accessed without the need to toggle the CE pin.
For fast access reads, after the first data byte is driven to the bus,
the column address inputs A1–A0 may be changed to a new
value. A new data byte is then driven to the DQ pins no later than
tAAP, which is less than half the initial read access time. For fast
access writes, the first write pulse defines the first write access.
While CE is LOW, a subsequent write pulse along with a new
column address provides a page mode write access.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
Pre-charge is also activated by changing the upper addresses,
A16–A2. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a pre-charge operation. The new address
is latched and the new read data is valid within the tAA address
access time; see Figure 8 on page 13. A similar sequence occurs
for write cycles; see Figure 13 on page 14. The rate at which
random addresses can be issued is tRC and tWC, respectively.
Sleep Mode
The device incorporates a sleep mode of operation, which allows
the user to achieve the lowest power supply current condition. It
enters a low-power sleep mode by asserting the ZZ pin LOW.
Read and write operations must complete before the ZZ pin
going LOW. When ZZ is LOW, all pins are ignored except the ZZ
pin. When ZZ is deasserted HIGH, there is some time delay
(tZZEX) before the user can access the device. If sleep mode is
not used, the ZZ pin must be tied to VDD.
Page 4 of 22
FM28V202A
Figure 2. Sleep/Standby State Diagram
Power
Applied
CE HIGH,
ZZ HIGH
Standby
ZZ LOW
Table 1. Write Protect Sectors - 16K x 16 Blocks
Initialize
CE LOW,
ZZ HIGH
CE HIGH,
ZZ HIGH
Sleep
CE LOW,
ZZ HIGH
Normal
Operation
ZZ LOW
ZZ HIGH
Sectors
Blocks
Sector 7
1FFFFh–1C000h
Sector 6
1BFFFh–18000h
Sector 5
17FFFh–14000h
Sector 4
13FFFh–10000h
Sector 3
0FFFFh–0C000h
Sector 2
0BFFFh–08000h
Sector 1
07FFFh–04000h
Sector 0
03FFFh–00000h
The write-protect address sequence follows:
Software Write Protect
The 128 K × 16 address space is divided into eight sectors
(blocks) of 16 K × 16 each. Each sector can be individually
software write-protected and the settings are nonvolatile. A
unique address and command sequence invokes the
write-protect mode.
To modify write protection, the system host must issue six read
commands, three write commands, and a final read command.
The specific sequence of read addresses must be provided to
access the write-protect mode. Following the read address
sequence, the host must write a data byte that specifies the
desired protection state of each sector. For confirmation, the
system must then write the complement of the protection byte
immediately after the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a seventh
read address, or failing to complement the protection value will
leave the write protection unchanged.
The write-protect state machine monitors all addresses, taking
no action until this particular read/write sequence occurs. During
the address sequence, each read will occur as a valid operation
and data from the corresponding addresses will be driven to the
data bus. Any address that occurs out of sequence will cause the
software protection state machine to start over. After the address
sequence is completed, the next operation must be a write cycle.
The lower data byte contains the write-protect settings. This
value will not be written to the memory array, so the address is a
don't-care. Rather it will be held pending the next cycle, which
must be a write of the data complement to the protection settings.
If the complement is correct, the write-protect settings will be
adjusted. Otherwise, the process is aborted and the address
sequence starts over. The data value written after the correct six
addresses will not be entered into the memory.
The protection data byte consists of eight bits, each associated
with the write-protect state of a sector. The data byte must be
driven to the lower eight bits of the data bus, DQ7 - DQ0. Setting
a bit to ‘1’ write-protects the corresponding sector; a 0 enables
writes for that sector. The following table shows the write-protect
sectors with the corresponding bit that controls the write-protect
setting.
Document Number: 001-90309 Rev. *G
1. Read address 12555h
2. Read address 1DAAAh
3. Read address 01333h
4. Read address 0ECCCh
5. Read address 000FFh
6. Read address 1FF00h
7. Write address 1DAAAh
8. Write address 0ECCCh
9. Write address 0FF00h
10.Read address 00000h
The address sequence provides a secure way of modifying the
protection. The write-protect sequence has a one in 3 × 1032
chance of randomly accessing exactly the first six addresses.
The odds are further reduced by requiring three more write
cycles, one that requires an exact inversion of the data byte.
Figure 3 on page 6 shows a flow chart of the entire write-protect
operation. The write-protect settings are nonvolatile. The factory
default: all blocks are unprotected.
For example, the following sequence write-protects addresses
from 0C000h to 13FFFh (sectors 3 and 4):
Address
Data
Read
12555h
–
Read
1DAAAh
–
Read
01333h
–
Read
0ECCCh
–
Read
000FFh
–
Read
1FF00h
–
Write
1DAAAh
18h; bits 3 and 4 = 1
Write
0ECCCh
E7h; complement of 18h
Write
0FF00h
Don’t care
Read
00000h
Page 5 of 22
FM28V202A
Figure 3. Write-Protect State Machine
Normal Memory
Operation
Any other
operation
Write
1DAAAh?
n
y
Read 12555h?
Hold Data Byte
n
Write
0ECCCh?
n
y
Read 1AAAAh to
drive write protect
settings
y
n
Read
1DAAAh?
n
Write
0ECCCh?
Read 00000h
y
y
n
Read 01333h?
n
Data
Complement?
y
y
Read
0ECCCh?
n
n
y
Read 000FFh?
Write
0FF00h?
Read 00000h
To enter new
y write
protect settings
n
y
Read 1FF00h?
n
y
Sequence Detector
Document Number: 001-90309 Rev. *G
Change Write Protect
Settings
Read Write Protect
Settings
Page 6 of 22
FM28V202A
Software Write-Protect Timing
Figure 4. Sequence to Set Write-Protect Blocks [1]
CE
A16-0
12555
1DAAA
01333
0ECCC
000FF
1FF00
1DAAA
0ECCC
0FF00
00000
WE
OE
DQ
Data
7-0
Data
Figure 5. Sequence to Read Write-Protect Settings [1]
CE
A 16:0
12555
1DAAA
01333
0ECCC
000FF
1FF00
0ECCC
1AAAA
00000
WE
tCE (read access time)
OE
DQ 15-0
X
Data
Note
1. This sequence requires tAS > 10 ns and address must be stable while CE is LOW.
Document Number: 001-90309 Rev. *G
Page 7 of 22
FM28V202A
SRAM Drop-In Replacement
The FM28V202A is designed to be a drop-in replacement for
standard asynchronous SRAMs. The device does not require CE
to toggle for each new address. CE may remain LOW indefinitely.
While CE is LOW, the device automatically detects address
changes and a new access begins. This functionality allows CE
to be grounded, similar to an SRAM. It also allows page mode
operation at speeds up to 33 MHz. Note that if CE is tied to
ground, the user must be sure WE is not LOW at power-up or
power-down events. If CE and WE are both LOW during power
cycles, data will be corrupted. Figure 6 shows a pull-up resistor
on WE, which will keep the pin HIGH during power cycles,
assuming the MCU/MPU pin tristates during the reset
condition.The pull-up resistor value should be chosen to ensure
the WE pin tracks VDD to a high enough value, so that the current
drawn when WE is LOW is not an issue. A 10-k resistor draws
330 µA when WE is LOW and VDD = 3.3 V. Note that software
write-protect is not available if the chip enable pin is hard-wired.
Figure 6. Use of Pull-up Resistor on WE
VDD
FM28V202A
CE
WE
MCU / MPU
OE
A 16-0
DQ15-0
For applications that require the lowest power consumption, the
CE signal should be active (LOW) only during memory accesses.
The FM28V202A draws supply current while CE is LOW, even if
addresses and control signals are static. While CE is HIGH, the
device draws no more than the maximum standby current, ISB.
The FM28V202A is backward compatible with the 2-Mbit
FM21L16 device. There are some differences in the timing
specifications. Refer to the FM21L16 datasheet.
The UB and LB byte select pins are active for both read and write
cycles. They may be used to allow the device to be wired as a
256K × 8 memory. The upper and lower data bytes can be tied
together and controlled with the byte selects. Individual byte
enables or the next higher address line A17 may be available
from the system processor.
Document Number: 001-90309 Rev. *G
Figure 7. FM28V202A Wired as 256 K x 8
CE
WE
OE
ZZ
2-Mbit F-RAM
FM28V202A
DQ
15-8
UB
LB
A
17
A
16-0
D
DQ
7-0
A
16-0
7-0
Endurance
The FM28V202A is capable of being accessed at least 1014
times – reads or writes. An F-RAM memory operates with a read
and restore mechanism. Therefore, an endurance cycle is
applied on a row basis. The F-RAM architecture is based on an
array of rows and columns. Rows are defined by A16-2 and
column addresses by A1-0. The array is organized as 32K rows
of four words each. The entire row is internally accessed once
whether a single 16-bit word or all four words are read or written.
Each word in the row is counted only once in an endurance
calculation.
The user may choose to write CPU instructions and run them
from a certain address space. Table 2 shows endurance
calculations for a 256-byte repeating loop, which includes a
starting address, three-page mode accesses, and a CE
pre-charge. The number of bus clock cycles needed to complete
a four-word transaction is 4 + 1 at lower bus speeds, but 5 + 2 at
33 MHz due to initial read latency and an extra clock cycle to
satisfy the device’s pre-charge timing constraint tPC. The entire
loop causes each byte to experience only one endurance cycle.
The F-RAM read and write endurance is virtually unlimited even
at a 33-MHz system bus clock rate.
Table 2. Time to Reach 100 Trillion Cycles for Repeating
256-byte Loop
Bus
Freq
(MHz)
33
Bus
256-byte
Cycle
Endurance Endurance
Transaction
Time
Cycles/sec Cycles/year
Time (s)
(ns)
30
10.56
Years to
Reach
1014
Cycles
94,690
2.98 x 1012
33.5
12
40.6
25
40
12.8
78,125
2.46 x 10
10
100
28.8
34,720
1.09 x 1012
91.7
5
200
57.6
17,360
5.47 x 1011
182.8
Page 8 of 22
FM28V202A
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............... 2 kV
Charged Device Model (AEC-Q100-011 Rev. B) ......... 500 V
Latch-up current ................................................... > 140 mA
Operating Range
Range
Industrial
Ambient Temperature (TA)
VDD
–40 C to +85 C
2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min
Typ [2]
Max
Unit
2.0
3.3
3.6
V
VDD
Power supply voltage
IDD
VDD supply current
VDD = 3.6 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
–
7
12
mA
ISB
Standby current
TA = 25 C
VDD = 3.6 V, CE at VDD,
All other pins are static and at
TA = 85 C
CMOS levels
(0.2 V or VDD – 0.2 V), ZZ is HIGH
–
120
150
µA
–
–
250
µA
TA = 25 C
–
3
5
µA
TA = 85 C
–
–
8
µA
IZZ
Sleep mode current
VDD = 3.6 V, ZZ is LOW,
All other inputs VSS or VDD.
ILI
Input leakage current
VIN between VDD and VSS
–
–
+1
µA
ILO
Output leakage current
VOUT between VDD and VSS
–
–
+1
µA
VIH1
Input HIGH voltage
VDD = 2.7 V to 3.6 V
2.2
–
VDD + 0.3
V
VIH2
Input HIGH voltage
VDD = 2.0 V to 2.7 V
0.7 × VDD
–
–
V
VIL1
Input LOW voltage
VDD = 2.7 V to 3.6 V
– 0.3
–
0.8
V
VIL2
Input LOW voltage
VDD = 2.0 V to 2.7 V
– 0.3
–
0.3 × VDD
V
VOH1
Output HIGH voltage
IOH = –1 mA, VDD > 2.7 V
2.4
–
–
V
VOH2
Output HIGH voltage
IOH = –100 µA
VDD – 0.2
–
–
V
VOL1
Output LOW voltage
IOL = 2 mA, VDD > 2.7 V
–
–
0.4
V
VOL2
Output LOW voltage
IOL = 150 µA
–
–
0.2
V
Note
2. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Document Number: 001-90309 Rev. *G
Page 9 of 22
FM28V202A
Data Retention and Endurance
Parameter
TDR
NVC
Description
Data retention
Endurance
Test condition
TA = 85 C
Min
Max
Unit
10
–
Years
TA = 75 C
38
–
TA = 65 C
151
–
Over operating temperature
1014
–
Cycles
Max
Unit
8
pF
Capacitance
Parameter
Description
Test Conditions
TA = 25 C, f = 1 MHz, VDD = VDD(Typ)
CI/O
Input/Output capacitance (DQ)
CIN
Input capacitance
6
pF
CZZ
Input capacitance of ZZ pin
8
pF
Thermal Resistance
Parameter
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
44-pin TSOP II Unit
107
C/W
25
C/W
AC Test Conditions
Input pulse levels ...................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ....................... 1.5 V
Output load capacitance............................................... 30 pF
Document Number: 001-90309 Rev. *G
Page 10 of 22
FM28V202A
AC Switching Characteristics
Over the Operating Range
Parameters [3]
Cypress
Parameter
VDD = 2.0 V to 2.7 V
Description
Alt
Parameter
VDD = 2.7 V to 3.6 V
Min
Max
Min
Max
–
70
–
60
105
–
90
Unit
SRAM Read Cycle
tCE
tACE
Chip enable access time
ns
tRC
–
Read cycle time
tAA
–
Address access time, A16-2
–
105
–
90
ns
tOH
tOHA
Output hold time, A16-2
20
–
20
–
ns
tAAP
–
Page mode access time, A1-0
–
40
–
30
ns
tOHP
–
Page mode output hold time, A1-0
3
–
3
–
ns
tCA
–
Chip enable active time
70
–
60
–
ns
tPC
–
Pre-charge time
35
–
30
–
ns
tBA
tBW
UB, LB access time
–
25
–
15
ns
tAS
tSA
Address setup time (to CE LOW)
0
–
0
–
ns
tAH
tHA
Address hold time (CE Controlled)
70
–
60
–
ns
tOE
tDOE
Output enable access time
–
25
–
15
ns
tHZ[4, 5]
tHZCE
Chip Enable to output HI-Z
–
15
–
10
ns
tOHZ[4, 5]
tHZOE
Output enable HIGH to output HI-Z
–
15
–
10
ns
tBHZ[4, 5]
tHZBE
UB, LB HIGHHIGH to output HI-Z
–
15
–
10
ns
ns
Notes
3. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified
IOL/IOH and 30-pF load capacitance shown in AC Test Conditions on page 10.
4. tHZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
5. This parameter is characterized but not 100% tested.
Document Number: 001-90309 Rev. *G
Page 11 of 22
FM28V202A
AC Switching Characteristics (continued)
Over the Operating Range
Parameters [3]
Cypress
Parameter
VDD = 2.0 V to 2.7 V
Description
Alt
Parameter
VDD = 2.7 V to 3.6 V
Min
Max
Min
Max
Unit
SRAM Write Cycle
tWC
tWC
Write cycle time
105
–
90
–
ns
tCA
–
Chip enable active time
70
–
60
–
ns
tCW
tSCE
Chip enable to write enable HIGH
70
–
60
–
ns
tPC
–
Pre-charge time
35
–
30
–
ns
tPWC
–
Page mode write enable cycle time
40
–
30
–
ns
tWP
tPWE
Write enable pulse width
22
–
18
–
ns
tWP2
tBW
UB, LB pulse width
22
–
18
–
ns
tWP3
tPWE
WE LOW to UB, LB HIGH
22
–
18
–
ns
tAS
tSA
Address setup time (to CE LOW)
0
–
0
–
ns
tAH
tHA
Address hold time (CE Controlled)
70
–
60
–
ns
tASP
–
Page mode address setup time (to WE LOW)
8
–
5
–
ns
tAHP
–
Page mode address hold time (to WE LOW)
20
–
15
–
ns
tWLC
tPWE
Write enable LOW to chip disabled
30
–
25
–
ns
tBLC
tBW
UB, LB LOW to chip disabled
30
–
25
–
ns
tWLA
–
Write enable LOW to address change, A16-2
30
–
25
–
ns
tAWH
–
Address change to write enable HIGH, A16-2
105
–
90
–
ns
tDS
tSD
Data input setup time
20
–
15
–
ns
tHD
Data input hold time
0
–
0
–
ns
tHZWE
Write enable LOW to output HI-Z
–
10
–
10
ns
tWX[7]
–
Write enable HIGH to output driven
8
–
5
–
ns
tBDS
–
Byte disable setup time (to WE LOW)
8
–
5
–
ns
tBDH
–
Byte disable hold time (to WE HIGH)
8
–
5
–
ns
tDH
tWZ
[6, 7]
Notes
6. tWZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
7. This parameter is characterized but not 100% tested.
Document Number: 001-90309 Rev. *G
Page 12 of 22
FM28V202A
Figure 8. Read Cycle Timing 1 (CE LOW, OE LOW)
tRC
tRC
A16-2
tOH
tAA
tAA
tOH
Previous Data
DQ
15-0
Valid Data
Valid Data
Figure 9. Read Cycle Timing 2 (CE Controlled)
tCA
tPC
CE
tAH
tAS
A 16-0
tOE
OE
tHZ
tCE
tOHZ
tOH
DQ 15-0
tBA
tBHZ
UB / LB
Figure 10. Page Mode Read Cycle Timing [8]
tPC
tCA
CE
tAS
A 16-2
Col 0
A1-0
Col 1
tAAP
tOE
OE
tHZ
tOHZ
tOHP
tCE
DQ15-0
Col 2
Data 0
Data 1
Data 2
Note
8. Although sequential column addressing is shown, it is not required
Document Number: 001-90309 Rev. *G
Page 13 of 22
FM28V202A
Figure 11. Write Cycle Timing 1 (WE Controlled) [9]
tCA
tPC
tCW
CE
tAS
tWLC
A16-0
tWP
tWX
WE
DQ15-0
tWZ
tDH
tDS
D out
D in
tHZ
D out
Figure 12. Write Cycle Timing 2 (CE Controlled)
tCA
tPC
CE
tBLC
tAS
A16-0
WE
tDH
tDS
DQ
15-0
D in
UB/LB
Figure 13. Write Cycle Timing 3 (CE LOW) [9]
tWC
tAWH
A16-0
tWLA
tWX
WE
tWZ
tDS
DQ15-0
D out
D in
tDH
D out
D in
Note
9. OE (not shown) is LOW only to show the effect of WE on DQ pins.
Document Number: 001-90309 Rev. *G
Page 14 of 22
FM28V202A
Figure 14. Write Cycle Timing 4 (CE LOW) [10]
A16-0
tWP3
WE
tBDH
tBDS
tWP2
UB/LB
tDS
DQ15-0
tDH
tDS
D in
tDH
D in
Figure 15. Page Mode Write Cycle Timing
tCA
tPC
tCW
CE
tWLC
tAS
A16-2
tAHP
A 1-0
Col 0
tASP
Col 1
Col 2
tPWC
tWP
WE
OE
tDH
tDS
DQ15-0
Data 0
Data 1
Data 2
Note
10. UB and LB to show byte enable and byte masking cases.
Document Number: 001-90309 Rev. *G
Page 15 of 22
FM28V202A
Power Cycle and Sleep Mode Timing
Over the Operating Range
Parameter
tPU
tPD
tVR
[11]
Description
Min
Max
Unit
Power-up (after VDD min. is reached) to first access time
1
–
ms
Last write (WE HIGH) to power down time
0
–
ms
VDD power-up ramp rate
50
–
µs/V
tVF[11]
VDD power-down ramp rate
100
–
µs/V
tZZH
ZZ active to DQ HI-Z time
–
20
ns
tWEZZ
Last write to sleep mode entry time
0
–
µs
tZZL
ZZ active LOW time
1
–
µs
tZZEN
Sleep mode entry time (ZZ LOW to CE don’t care)
–
0
µs
–
450
µs
tZZEX
Sleep mode exit time (ZZ HIGH to
1st
access after wakeup)
Figure 16. Power Cycle and Sleep Mode Timing
VDD
t VR
t PU
CE
VDD min.
VDD min.
t ZZEN
t ZZEX
R/W
Allowed
t ZZEX
R/W
Allowed
t VF
R/W
Allowed
t ZZL
ZZ
t PD
t WEZZ
WE
t ZZH
DQ
D out
D in
Note
11. Slope measured at any point on the VDD waveform.
Document Number: 001-90309 Rev. *G
Page 16 of 22
FM28V202A
Functional Truth Table
Operation [12, 13]
CE
WE
A16-2
A1-0
ZZ
X
X
X
X
L
Sleep Mode
H
X
X
X
H
Standby/Idle
H
H
V
V
V
V
H
H
Read
L
L
H
No Change
Change
H
Page Mode Read
L
H
Change
V
H
Random Read
V
V
V
V
H
H
CE-Controlled Write[13]
L
L
L
L
V
V
H
WE-Controlled Write [13, 14]
L
No Change
V
H
Page Mode Write [15]
X
X
X
X
H
H
Starts pre-charge
L
X
X
Byte Select Truth Table
Operation [16]
WE
OE
LB
UB
H
H
X
X
X
H
H
L
H
L
Read upper byte; HI-Z lower byte
L
H
Read lower byte; HI-Z upper byte
L
L
Read both bytes
H
L
Write upper byte; Mask lower byte
L
H
Write lower byte; Mask upper byte
L
L
Write both bytes
H
L
X
Read; Outputs disabled
Notes
12. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, = toggle LOW, = toggle HIGH.
13. For write cycles, data-in is latched on the rising edge of CE or WE, whichever comes first.
14. WE-controlled write cycle begins as a Read cycle and then A16-2 is latched.
15. Addresses A1-0 must remain stable for at least 15 ns during page mode operation.
16. The UB and LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 256K x 8.
Document Number: 001-90309 Rev. *G
Page 17 of 22
FM28V202A
Ordering Information
Access
time
(ns)
60
Ordering Code
FM28V202A-TG
Package
Diagram
Package Type
51-85087 44-pin TSOP II with software WP, sleep mode
Operating
Range
Industrial
FM28V202A-TGTR
All the above parts are Pb-free.
Ordering Code Definitions
FM 28
V
202 A - TG TR
Option:
blank = Standard; TR = Tape and Reel
Package Type:
TG = 44-pin TSOP II
Die Revision: A
Density: 202 = 2-Mbit
Voltage: V = 2.0 V to 3.6 V
Parallel F-RAM
Cypress
Document Number: 001-90309 Rev. *G
Page 18 of 22
FM28V202A
Package Diagram
Figure 17. 44-pin TSOP Package Outline, 51-85087
51-85087 *E
Document Number: 001-90309 Rev. *G
Page 19 of 22
FM28V202A
Acronyms
Acronym
UB
Document Conventions
Description
Units of Measure
Symbol
Upper Byte
Unit of Measure
LB
Lower Byte
°C
CE
CMOS
Chip Enable
Hz
hertz
Complementary Metal Oxide Semiconductor
kHz
kilohertz
EIA
Electronic Industries Alliance
k
kilohm
F-RAM
Ferroelectric Random Access Memory
MHz
megahertz
I/O
Input/Output
A
microampere
OE
RoHS
Output Enable
F
microfarad
s
microsecond
RW
Read and Write
mA
milliampere
ms
millisecond
SRAM
Static Random Access Memory
M
megaohm
TSOP
Thin Small Outline Package
ns
nanosecond
WE
Write Enable

ohm
%
percent
pF
picofarad
V
volt
W
watt
Restriction of Hazardous Substances
Document Number: 001-90309 Rev. *G
degree Celsius
Page 20 of 22
FM28V202A
Document History Page
Document Title: FM28V202A, 2-Mbit (128 K × 16) F-RAM Memory
Document Number: 001-90309
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
4209369
GVCH
01/22/2014
New data sheet.
*A
4372700
GVCH
05/07/2014
Changed datasheet status from “Preliminary to Final”
Description of Change
Maximum Ratings: Static discharge voltage
Removed Machine Model
DC Electrical Characteristics:
Updated ISB and IZZ description
Updated IZZ test condition
Updated Figure 8 for more clarity
Removed FM28V202A-TGES part number
*B
4379377
GVCH
05/14/2014
No technical updates.
*C
4375244
GVCH
06/30/2014
Pin Definitions: ZZ pin
Added sentence: This pin must be tied to VDD if not used
Removed sentence: The ZZ pin is internally pulled up
DC Electrical Characteristics: Removed RIN spec
*D
4462029
ZSK
07/31/2014
No technical updates.
*E
4567856
ZSK
11/12/2014
Added related documentation hyperlink in page 1.
*F
4881722
ZSK / PSR
08/12/2015
Updated Maximum Ratings:
Removed “Maximum junction temperature”.
Added “Maximum accumulated storage time”.
Added “Ambient temperature with power applied”.
Updated to new template.
*G
5702283
AESATMP8
04/20/2017
Updated logo and Copyright.
Document Number: 001-90309 Rev. *G
Page 21 of 22
FM28V202A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
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closest to you, visit us at Cypress Locations.
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Forums | WICED IOT Forums | Projects | Video | Blogs |
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© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-90309 Rev. *G
Revised April 20, 2017
Page 22 of 22