MCP1725 500 mA, Low Voltage, Low Quiescent Current LDO Regulator Features Description • • • • The MCP1725 is a 500 mA Low Dropout (LDO) linear regulator that provides high current and low output voltages in a very small package. The MCP1725 comes in a fixed (or adjustable) output voltage version, with an output voltage range of 0.8V to 5.0V. The 500 mA output current capability, combined with the low output voltage capability, make the MCP1725 a good choice for new sub-1.8V output voltage LDO applications that have high current demands. • • • • • • • • • • 500 mA Output Current Capability Input Operating Voltage Range: 2.3V to 6.0V Adjustable Output Voltage Range: 0.8V to 5.0V Standard Fixed Output Voltages: - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V Other Fixed Output Voltage Options Available Upon Request Low Dropout Voltage: 210 mV typical at 500 mA Typical Output Voltage Tolerance: 0.5% Stable with 1.0 µF Ceramic Output Capacitor Fast response to Load Transients Low Supply Current: 120 µA (typical) Low Shutdown Supply Current: 0.1 µA (typical) Adjustable Delay on Power Good Output Short Circuit Current Limiting and Overtemperature Protection 2x3 DFN-8 and SOIC-8 Package Options Applications • • • • • • • The MCP1725 is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. Only 1 µF of output capacitance is needed to stabilize the LDO. Using CMOS construction, the quiescent current consumed by the MCP1725 is typically less than 120 µA over the entire input voltage range, making it attractive for portable computing applications that demand high output current. When shut down, the quiescent current is reduced to less than 0.1 µA. The scaled-down output voltage is internally monitored and a power good (PWRGD) output is provided when the output is within 92% of regulation (typical). An external capacitor can be used on the CDELAY pin to adjust the delay from 200 µs to 300 ms. High-Speed Driver Chipset Power Networking Backplane Cards Notebook Computers Network Interface Cards Palmtop Computers Video Graphics Adapters 2.5V to 1.XV Regulators The overtemperature and short circuit current-limiting provide additional protection for the LDO during system fault conditions. Package Types Adjustable (SOIC-8) VIN 1 VIN 2 SHDN 3 GND 4 8 VOUT 7 ADJ 6 CDELAY 5 PWRGD Fixed (SOIC-8) VIN 1 VIN 2 SHDN 3 GND 4 8 VOUT 7 Sense 6 CDELAY 5 PWRGD Adjustable (2x3 DFN) VIN 1 VIN 2 SHDN 3 GND 4 © 2007 Microchip Technology Inc. VOUT VIN 1 8 VOUT 7 ADJ VIN 2 7 Sense 6 CDELAY SHDN 3 6 CDELAY 5 PWRGD GND 4 5 PWRGD 8 Note: Fixed (2x3 DFN) DFN tab is at ground potential. DS22026B-page 1 MCP1725 Typical Application MCP1725 Fixed Output Voltage VIN = 2.3V to 2.8V C1 4.7 µF 1 VIN VOUT 8 2 VIN Sense 7 3 SHDN CDELAY 6 4 GND VOUT = 1.8V @ 500 mA C2 1 µF PWRGD 5 C3 1000 pF On R1 100 kΩ Off PWRGD MCP1725 Adjustable Output Voltage VIN = 2.3V to 2.8V C1 4.7 µF 1 VIN VOUT 8 2 VIN ADJ 7 3 SHDN CDELAY 6 4 GND VOUT = 1.2V @ 500 mA R1 40 kΩ R3 100 kΩ PWRGD 5 On Off C2 1 µF C3 1000 pF R2 20 kΩ PWRGD DS22026B-page 2 © 2007 Microchip Technology Inc. MCP1725 Functional Block Diagram - Adjustable Output PMOS VIN VOUT Undervoltage Lock Out (UVLO) ISNS Cf Rf SHDN ADJ Overtemperature Sensing + Driver w/limit and SHDN EA – SHDN VREF V IN SHDN Reference Soft-Start Comp TDELAY PWRGD GND 92% of VREF © 2007 Microchip Technology Inc. CDELAY DS22026B-page 3 MCP1725 Functional Block Diagram - Fixed Output PMOS VIN VOUT Undervoltage Lock Out (UVLO) ISNS Cf Rf SHDN Sense Overtemperature Sensing + Driver w/limit and SHDN EA – SHDN VREF V IN SHDN Reference Soft-Start Comp TDELAY PWRGD GND 92% of VREF DS22026B-page 4 CDELAY © 2007 Microchip Technology Inc. MCP1725 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VIN ......................................................................... 6.5V Maximum Voltage on Any Pin ........................................(GND – 0.3V) to (VIN + 0.3)V Maximum Power Dissipation............. Internally-Limited (Note 6) Output Short Circuit Duration ..................... Continuous Storage temperature .......................... -65°C to +150°C Maximum Junction Temperature, TJ ................ +150°C ESD protection on all pins (HBM/MM) .. ≥ 2 kV; ≥ 200V † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Sym Min Typ Max Input Operating Voltage VIN 2.3 Input Quiescent Current Iq Input Quiescent Current for SHDN Mode Maximum Output Current 6.0 V Note 1 — 120 220 µA IL = 0 mA, VIN = Note 1, VOUT = 0.8V to 5.0V ISHDN — 0.1 3 µA SHDN = GND IOUT 500 — — mA VIN = 2.3V to 6.0V VR = 0.8V to 5.0V, Note 1 Line Regulation ΔVOUT/ (VOUT x ΔVIN) — ±0.05 ±0.16 %/V (Note 1) ≤ VIN ≤ 6V Load Regulation ΔVOUT/VOUT -1.0 ±0.5 1.0 % IOUT = 1 mA to 500 mA, (Note 4) IOUT_SC — 1.2 — A RLOAD < 0.1Ω, Peak Current Output Short Circuit Current Units Conditions Adjust Pin Characteristics (Adjustable Output Only) Adjust Pin Reference Voltage VADJ 0.402 0.410 0.418 V VIN = 2.3V to VIN = 6.0V, IOUT = 1 mA Adjust Pin Leakage Current IADJ -10 ±0.01 +10 nA VIN = 6.0V, VADJ = 0V to 6V TCVOUT — 40 — ppm/°C Note 3 V Note 2 Adjust Temperature Coefficient Fixed-Output Characteristics (Fixed Output Only) Voltage Regulation Note 1: 2: 3: 4: 5: 6: 7: VOUT VR - 2.5% VR ±0.5% VR + 2.5% The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. © 2007 Microchip Technology Inc. DS22026B-page 5 MCP1725 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Sym Min Typ Max Units VIN-VOUT — 210 350 mV VPWRGD_VIN 1.0 — 6.0 V 1.2 — 6.0 Conditions Dropout Characteristics Dropout Voltage IOUT = 500 mA, (Note 5) VIN(MIN) = 2.3V Power Good Characteristics PWRGD Input Voltage Operating Range TA = +25°C TA = -40°C to +125°C For VIN < 2.3V, ISINK = 100 µA PWRGD Threshold Voltage (Referenced to VOUT) VPWRGD_TH — — — 89 92 95 %VOUT Falling Edge VOUT < 2.5V Fixed, VOUT = Adj. 90 92 94 VOUT >= 2.5V Fixed VPWRGD_HYS 1.0 2.0 3.0 %VOUT PWRGD Output Voltage Low VPWRGD_L — 0.2 0.4 V IPWRGD SINK = 1.2 mA, ADJ = 0V, SENSE = 0V PWRGD Leakage PWRGD_LK — 1 — nA VPWRGD = VIN = 6.0V PWRGD Threshold Hysteresis PWRGD Time Delay Rising Edge RPULLUP = 10 kΩ TPG — — 10 30 55 ms CDELAY = 0.01 µF — 300 — ms CDELAY = 0.1 µF TVDET-PWRGD — 200 — µs VADJ or VSENSE = VPWRGD_TH + 20 mV to VPWRGD_TH - 20 mV Logic High Input VSHDN-HIGH 45 — — %VIN VIN = 2.3V to 6.0V Logic Low Input VSHDN-LOW — — 15 %VIN VIN = 2.3V to 6.0V SHDNILK -0.1 ±0.001 +0.1 µA Detect Threshold to PWRGD Active Time Delay µs ICDELAY = 140 nA (Typ) CDELAY = OPEN 200 Shutdown Input SHDN Input Leakage Current Note 1: 2: 3: 4: 5: 6: 7: VIN = 6V, SHDN =VIN, SHDN = GND The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. DS22026B-page 6 © 2007 Microchip Technology Inc. MCP1725 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Sym Min Typ Max Units Conditions TOR — 100 — µs eN — 2.0 — µV/√Hz Power Supply Ripple Rejection Ratio PSRR — 60 — dB f = 100 Hz, COUT = 10 µF, IOUT = 10 mA, VINAC = 30 mV pk-pk, CIN = 0 µF Thermal Shutdown Temperature TSD — 150 — °C IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V Thermal Shutdown Hysteresis ΔTSD — 10 — °C IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V AC Performance Output Delay From SHDN Output Noise Note 1: 2: 3: 4: 5: 6: 7: SHDN = GND to VIN VOUT = GND to 95% VR IOUT = 200 mA, f = 1 kHz, COUT = 10 µF (X7R Ceramic), VOUT = 2.5V The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits apply for VIN = 2.3V to 6.0V. Parameters Sym Min Typ Max Operating Junction Temperature Range TJ Maximum Junction Temperature TJ Storage Temperature Range Units Conditions -40 — +125 °C Steady State — — +150 °C Transient TA -65 — +150 °C Temperature Ranges Thermal Package Resistances Thermal Resistance, 8LD 2x3 DFN Thermal Resistance, 8LD SOIC © 2007 Microchip Technology Inc. θJA — 76 — °C/W θJC — 26 — °C/W θJA — 163 — °C/W θJC — 38.8 — °C/W 4-Layer JC51-7 Standard Board with vias 4-Layer JC51-7 Standard Board DS22026B-page 7 MCP1725 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C. Note: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in Junction Temperature over the Ambient temperature is not significant. 0.12 IOUT = 0 mA 140 130 +90°C Line Regulation (%/V) Quiescent Current (µA) 150 +130°C 120 110 100 0°C 90 +25°C VIN = 2.3V to 6.0V 0.10 IOUT = 50 mA 0.06 IOUT = 100 mA 0.04 IOUT = 250 mA 0.02 -45°C 80 0.00 2 3 4 5 6 -45 -20 5 Input Voltage (V) VOUT = 1.2V Adj 200 190 180 170 160 VIN = 2.5V 150 140 VIN = 3.3V 130 VIN = 5.0V 120 0 100 200 300 400 500 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 VOUT = 5V IOUT = 1.0 mA to 500 mA -20 30 55 80 105 130 FIGURE 2-5: Load Regulation vs. Temperature (Adjustable Version). Adjust Pin Voltage (V) VIN = 6.0V 120 110 VIN = 3.3V VIN = 2.3V 90 5 0.412 VIN = 5.0V 100 130 VOUT = 0.8V VOUT = 1.8V -45 IOUT = 0 mA 130 105 Temperature (°C) FIGURE 2-2: Ground Current vs. Load Current (1.2V Adjustable). 140 80 VOUT = 3.3V Load Current (mA) 150 55 FIGURE 2-4: Line Regulation vs. Temperature (1.8V Adjustable). Load Regulation (%) Ground Current (µA) 210 30 Temperature (°C) FIGURE 2-1: Quiescent Current vs. Input Voltage (1.8V Adjustable). Quiescent Current (µA) IOUT = 500 mA IOUT = 1 mA 0.08 80 0.411 IOUT = 1 mA VIN = 6.0V VIN = 5.0V 0.410 0.409 VIN = 2.3V, 3.0V, 4.0V 0.408 -45 -20 5 30 55 80 105 130 -45 Temperature (°C) FIGURE 2-3: Quiescent Current vs. Junction Temperature (1.8V Adjustable). DS22026B-page 8 -20 5 30 55 80 105 130 Temperature (°C) FIGURE 2-6: Temperature. Adjust Pin Voltage vs. © 2007 Microchip Technology Inc. MCP1725 Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C. 150 VOUT = 5.0V 0.20 0.15 VOUT = 2.5V 0.10 0.05 Quiescent Current (µA) Dropout Voltage (V) 0.25 0.00 IOUT = 0 mA 140 +130°C 130 120 110 +90°C 100 0°C 90 -45°C 80 0 100 200 300 400 500 2 3 Load Current (mA) Quiescent Current (µA) Dropout Voltage (V) 150 0.26 0.24 VOUT = 5.0V VOUT = 3.3V 0.20 VOUT = 2.5V 0.18 0.16 IOUT = 0 mA 140 130 120 110 +135°C 100 -45°C +25°C 0°C -20 5 30 55 80 105 130 3 3.5 Temperature (°C) +90°C 4.5 5 5.5 6 FIGURE 2-11: Quiescent Current vs. Input Voltage (2.5V Fixed). VIN = 5.0V VIN = 3.0V 210 Ground Current (µA) CDELAY = 0.01 µF IOUT = 0 mA VIN = 2.3V 4 Input Voltage (V) FIGURE 2-8: Dropout Voltage vs. Temperature (Adjustable Version). Power Good Time Delay (ms) 6 90 -45 35 34 33 32 31 30 29 28 27 26 25 5 FIGURE 2-10: Quiescent Current vs. Input Voltage (0.8V Fixed). IOUT = 500 mA 0.22 4 Input Voltage (V) FIGURE 2-7: Dropout Voltage vs. Load Current (Adjustable Version). 0.28 +25°C 190 170 VOUT = 5.0V 150 VOUT = 2.5V 130 110 -45 -20 5 30 55 80 105 130 0 © 2007 Microchip Technology Inc. 200 300 400 500 Load Current (mA) Temperature (°C) FIGURE 2-9: Power Good (PWRGD) Time Delay vs. Temperature (Adjustable Version). 100 FIGURE 2-12: Current. Ground Current vs. Load DS22026B-page 9 MCP1725 Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C. 0.050 IOUT = 0 mA Line Regulation (%/V) Quiescent Current (µA) 140 130 120 VOUT = 2.5V 110 100 VOUT = 0.8V 90 80 0.045 0.040 0.035 IOUT = 50 mA 0.030 0.025 0.020 IOUT = 250 mA 0.015 IOUT = 100 mA -20 5 30 55 80 105 130 -45 -20 5 Junction Temperature (°C) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 30 80 105 130 FIGURE 2-16: Line Regulation vs. Temperature (2.5V Fixed). 0.20 VOUT = 0.8V IOUT = 1.0 mA to 500 mA Load Regulation (%) 0.18 VIN = 2.3V VIN = 6.0V 55 Temperature (°C) FIGURE 2-13: Quiescent Current vs. Junction Temperature. ISHDN (µA) IOUT = 500 mA 0.010 -45 VIN = 3.3V VOUT = 0.8V 0.16 0.14 VOUT = 1.2V 0.12 0.10 0.08 0.06 0.04 0.02 -45 -20 5 30 55 80 105 130 -45 -20 5 Temperature (°C) 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 ISHDN vs. Temperature. VIN = 2.3V to 6.0V VOUT = 0.8V IOUT = 1 mA 30 55 80 105 130 Temperature (°C) IOUT = 50 mA IOUT = 100 mA IOUT = 250 mA IOUT = 500 mA FIGURE 2-17: Load Regulation vs. Temperature (VOUT < 2.5V Fixed). 0.00 Load Regulation (%) FIGURE 2-14: Line Regulation (%/V) VOUT = 2.5V VIN = 3.0V to 6.0V IOUT = 1 mA IOUT = 1.0 mA to 500 mA -0.05 VOUT = 2.5V -0.10 -0.15 VOUT = 5.0V -0.20 -0.25 -0.30 -0.35 -45 -20 5 30 55 80 105 Temperature (°C) FIGURE 2-15: Line Regulation vs. Temperature (0.8V Fixed). DS22026B-page 10 130 -45 -20 5 30 55 80 105 130 Temperature (°C) FIGURE 2-18: Load Regulation vs. Temperature (VOUT ≥ 2.5V Fixed). © 2007 Microchip Technology Inc. MCP1725 Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C. 0.25 10 0.15 Noise (μV/¥Hz) Dropout Voltage (V) VOUT = 5.0V VIN = 3.3V VOUT = 2.5V 0.20 VOUT = 2.5V 0.10 0.05 0.00 0 100 200 300 400 500 1 0.1 VIN = 2.3V VOUT = 0.8V 0.01 0.001 0.01 0.1 Load Current (mA) FIGURE 2-19: Current. Dropout Voltage (V) 0.26 100 1000 0 ILOAD = 500 mA -10 0.24 VOUT = 5.0V 0.22 -20 0.20 VOUT = 2.5V 0.18 0.16 0.14 -30 -40 VR=1.2V Adj COUT=4.7 μF ceramic X7R VIN=2.5V CIN=0 μF IOUT=10 mA -50 -60 0.12 -70 0.10 -45 -20 5 30 55 80 105 -80 0.01 130 0.1 Temperature (°C) FIGURE 2-20: Temperature. Dropout Voltage vs. 1.20 100 1000 0 IPEAK 1.10 1 10 Frequency (kHz) FIGURE 2-23: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 1.2V Adj.). -10 VOUT = 2.5V Fixed CIN = 3000 µF 1.00 0.90 0.80 0.70 ISTEADY STATE 0.60 -20 PSRR (dB) Short Circuit Current (A) 1 10 Frequency (kHz) FIGURE 2-22: Output Noise Voltage Density vs. Frequency. PSRR (dB) 0.28 Dropout Voltage vs. Load ILOAD = 200 mA COUT = 1 μF CIN = 10 μF -30 -40 VR=1.2V Adj COUT=22 μF ceramic X7R VIN=2.5V CIN=0 μF IOUT=10 mA -50 -60 -70 0.50 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Voltage (V) FIGURE 2-21: Input Voltage. Short Circuit Current vs. © 2007 Microchip Technology Inc. -80 0.01 0.1 1 10 Frequency (kHz) 100 1000 FIGURE 2-24: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 1.2V Adj.). DS22026B-page 11 MCP1725 Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C. 0 -10 PSRR (dB) -20 -30 -40 VR=2.5V Fixed COUT=4.7 μF ceramic X7R VIN=3.3V CIN=0 μF IOUT=10 mA -50 -60 -70 -80 0.01 0.1 1 10 Frequency (KHz) 100 1000 FIGURE 2-25: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 2.5V Fixed). FIGURE 2-28: Shutdown. 2.5V (Adj.) Startup from 0 -10 PSRR (dB) -20 -30 -40 VR=2.5V Fixed COUT=22 μF ceramic X7R VIN=3.3V CIN=0 μF IOUT=10 mA -50 -60 -70 -80 0.01 0.1 1 10 Frequency (KHz) 100 1000 FIGURE 2-26: Power Supply Ripple Rejection (PSRR) vs. Frequency (VOUT = 2.5V Fixed). FIGURE 2-27: DS22026B-page 12 2.5V (Adj.) Startup from VIN. FIGURE 2-29: Power Good (PWRGD) Timing with Cdelay of 1000 pF (2.5V Fixed). FIGURE 2-30: Power Good (PWRGD) Timing with CDELAY of 0.01 µF (2.5V Fixed). © 2007 Microchip Technology Inc. MCP1725 Note: Unless otherwise indicated, VIN = VOUT + 0.5V or VIN = 2.3V (whichever is greater), IOUT = 1 mA, CIN = COUT = 4.7 µF Ceramic (X7R), SHDN = VIN, CDELAY = Open, Fixed Output Version, and TA = +25°C. FIGURE 2-31: (5.0V Fixed). Dynamic Line Response FIGURE 2-33: Dynamic Load Response (2.5V Fixed, 1 mA to 500 mA). FIGURE 2-32: (2.5V Fixed). Dynamic Line Response FIGURE 2-34: Dynamic Load Response (2.5V Fixed, 10 mA to 500 mA). © 2007 Microchip Technology Inc. DS22026B-page 13 MCP1725 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Fixed Output Adjustable Output Name 1 1 VIN Input Voltage Supply 2 2 VIN Input Voltage Supply 3 3 SHDN 4 4 GND 5 5 PWRGD Power Good Output (open-drain) 6 6 CDELAY Power Good Delay Set-Point Input — 7 ADJ 7 — Sense 8 8 VOUT Exposed Pad Exposed Pad EP 3.1 Input Voltage Supply (VIN) Connect the unregulated or regulated input voltage source to VIN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 1 µF to 10 µF should be sufficient for most applications. 3.2 Shutdown Control Input (SHDN) The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the PWRGD output also goes low and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.1 µA. 3.3 Ground (GND) Description Shutdown Control Input (active-low) Ground Voltage Sense Input (adjustable version) Voltage Sense Input (fixed voltage version) Regulated Output Voltage Exposed Pad of the DFN Package (ground potential) 3.4 Power Good Output (PWRGD) The PWRGD output is an open-drain output used to indicate when the LDO output voltage is within 92% (typically) of its nominal regulation value. The PWRGD threshold has a typical hysteresis value of 2%. The PWRGD output is typically delayed by 200 µs (typical, no capacitance on CDELAY pin) from the time the LDO output is within 92% + 3% (max hysteresis) of the regulated output value on power-up. This delay time is controlled by the CDELAY pin. 3.5 Power Good Delay Set-Point Input (CDELAY) The CDELAY input sets the power-up delay time for the PWRGD output. By connecting an external capacitor from the CDELAY pin to ground, the typical delay times for the PWRGD output can be adjusted from 200 µs (no capacitance) to 300 ms (0.1 µF capacitor). This allows for the optimal setting of the system reset time. Connect the GND pin of the LDO to a quiet circuit ground. This will help the LDO power supply rejection ratio and noise performance. The ground pin of the LDO only conducts the quiescent current of the LDO (typically 120 µA), so a heavy trace is not required. For applications that have switching or noisy inputs, tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. DS22026B-page 14 © 2007 Microchip Technology Inc. MCP1725 3.6 3.6.1 Output Voltage Sense/Adjust Input (ADJ/Sense) ADJ For adjustable applications, the output voltage is connected to the ADJ input through a resistor divider that sets the output voltage regulation value. This provides the user the capability to set the output voltage to any value they desire within the 0.8V to 5.0V range of the device. 3.6.2 Sense For fixed output voltage versions of the device, the SENSE input is used to provide output voltage feedback to the internal circuitry of the MCP1725. The SENSE pin typically improves load regulation by allowing the device to compensate for voltage drops due to packaging and circuit board layout. © 2007 Microchip Technology Inc. 3.7 Regulated Output Voltage (VOUT) The VOUT pin(s) is the regulated output voltage of the LDO. A minimum output capacitance of 1.0 µF is required for LDO stability. The MCP1725 is stable with ceramic, tantalum and aluminum-electrolytic capacitors. See Section 4.3 “Output Capacitor” for output capacitor selection guidance. 3.8 Exposed Pad (EP) The 2x3 DFN package has an exposed pad on the bottom of the package. This pad should be soldered to the Printed Circuit Board (PCB) to aid in the removal of heat from the package during operation. The exposed pad is at the ground potential of the LDO. DS22026B-page 15 MCP1725 4.0 DEVICE OVERVIEW EQUATION 4-2: The MCP1725 is a high output current, Low Dropout (LDO) voltage regulator with an adjustable delay power-good output and shutdown control input. The low dropout voltage of 210 mV typical at 0.5A of current makes it ideal for battery-powered applications. Unlike other high output current LDOs, the MCP1725 only draws a maximum of 220 µA of quiescent current. 4.1 The MCP1725 LDO is available with either a fixed output voltage or an adjustable output voltage. The output voltage range is 0.8V to 5.0V for both versions. 4.1.1 ADJUST INPUT The adjustable version of the MCP1725 uses the ADJ pin (pin 7) to get the output voltage feedback for output voltage regulation. This allows the user to set the output voltage of the device with two external resistors. The nominal voltage for ADJ is 0.41V. Figure 4-1 shows the adjustable version of the MCP1725. Resistors R1 and R2 form the resistor divider network necessary to set the output voltage. With this configuration, the equation for setting VOUT is: EQUATION 4-1: R1 + R2 V OUT = V ADJ ⎛ ------------------⎞ ⎝ R2 ⎠ Where: VOUT = LDO Output Voltage VADJ = ADJ Pin Voltage (typically 0.41V) Where: 4.2 LDO Output Voltage C1 4.7 µF VOUT 8 2 VIN ADJ 7 VOUT R1 3 SHDN CDELAY 6 On 4 GND Off C2 1 µF PWRGD 5 C3 1000 pF R2 FIGURE 4-1: Typical Adjustable Output Voltage Application Circuit. The allowable resistance value range for resistor R2 is from 10 kΩ to 200 kΩ. Solving the equation for R1 yields the following equation: DS22026B-page 16 = LDO Output Voltage VADJ = ADJ Pin Voltage (typically 0.41V) Output Current and Current Limiting The MCP1725 LDO is tested and ensured to supply a minimum of 0.5A of output current. The MCP1725 has no minimum output load, so the output load current can go to 0 mA and the LDO will continue to regulate the output voltage to within tolerance. The MCP1725 also incorporates an output current limit. If the output voltage falls below 0.7V due to an overload condition (usually represents a shorted load condition), the output current is limited to 1.2A (typical). If the overload condition is a soft overload, the MCP1725 will supply higher load currents of up to 1A. The MCP1725 should not be operated in this condition continuously as it may result in failure of the device. However, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 0.5A or less. 4.3 1 VIN VOUT Output overload conditions may also result in an overtemperature shutdown of the device. If the junction temperature rises above 150°C, the LDO will shut down the output voltage. See Section 4.9 “Overtemperature Protection” for more information on overtemperature shutdown. MCP1725-ADJ VIN V OUT – V ADJ R 1 = R 2 ⎛ --------------------------------⎞ ⎝ ⎠ V ADJ Output Capacitor The MCP1725 requires a minimum output capacitance of 1 µF for output voltage stability. Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series Resistance (ESR) of the electrolytic output capacitor must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 µF X7R 0805 capacitor has an ESR of 50 milli-ohms. Larger LDO output capacitors can be used with the MCP1725 to improve dynamic performance and power supply ripple rejection performance. A maximum of 22 µF is recommended. Aluminum-electrolytic capacitors are not recommended for low-temperature applications of < -25°C. © 2007 Microchip Technology Inc. MCP1725 4.4 Input Capacitor Low input source impedance is necessary for the LDO output to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 µF to 4.7 µF is recommended for most applications. For applications that have output step load requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO with a good local low-impedance source to pull the transient currents from in order to respond quickly to the output load step. For good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO. 4.5 Power Good Output (PWRGD) The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see Section 1.0 “Electrical Characteristics” for Minimum and Maximum specifications) of its nominal regulation value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as TPG in Section 1.0 “Electrical Characteristics”). The power good time delay is adjustable via the CDELAY pin of the LDO (see Section 4.6 “CDELAY Input”). By placing a capacitor from the CDELAY pin to ground, the power good time delay can be adjusted from 200 µs (no capacitance) to 300 ms (0.1 µF capacitor). After the time delay period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking 1.2 mA (VPWRGD < 0.4V maximum). VPWRGD_TH VOUT TPG VOH TVDET_PWRGD PWRGD VOL FIGURE 4-2: VIN Power Good Timing. TOR 30 µs SHDN 70 µs TPG VOUT PWRGD FIGURE 4-3: Shutdown. Power Good Timing from If the output voltage of the LDO falls below the power good threshold, the power good output will transition low. The power good circuitry has a 170 µs delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See Figure 4-2 for power good timing characteristics. When the LDO is put into Shutdown mode using the SHDN input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. The timing diagram for the power good output when using the shutdown input is shown in Figure 4-3. © 2007 Microchip Technology Inc. DS22026B-page 17 MCP1725 4.6 CDELAY Input 4.7 The CDELAY input is used to provide the power-up delay timing for the power good output, as discussed in the previous section. By adding a capacitor from the CDELAY pin to ground, the PWRGD power-up time delay can be adjusted from 200 µs (no capacitance on CDELAY) to 300 ms (0.1 µF of capacitance on CDELAY). See Section 1.0 “Electrical Characteristics” for CDELAY timing tolerances. Once the power good threshold (rising) has been reached, the CDELAY pin charges the external capacitor to VIN. The charging current is 140 nA (typical). The PWRGD output will transition high when the CDELAY pin voltage has charged to 0.42V. If the output falls below the power good threshold limit during the charging time between 0.0V and 0.42V on the CDELAY pin, the CDELAY pin voltage will be pulled to ground, thus resetting the timer. The CDELAY pin will be held low until the output voltage of the LDO has once again risen above the power good rising threshold. A timing diagram showing CDELAY, PWRGD and VOUT is shown in Figure 4-4. VOUT VPWRGD_TH TPG CDELAY 0V Shutdown Input (SHDN) The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a percentage of the input voltage. The typical value of this shutdown threshold is 30% of VIN, with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. The SHDN input will ignore low-going pulses (pulses meant to shut down the LDO) that are up to 400 ns in pulse width. If the shutdown input is pulled low for more than 400 ns, the LDO will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the shutdown input signal. On the rising edge of the SHDN input, the shutdown circuitry has a 30 µs delay before allowing the LDO output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the 30 µs delay, the LDO output enters its soft-start period as it rises from 0V to its final regulation value. If the SHDN input signal is pulled low during the 30 µs delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going high (turn-on) to the LDO output being in regulation is typically 100 µs. See Figure 4-5 for a timing diagram of the SHDN input. TOR VIN (typ) 400 ns (typ) CDELAY Threshold (0.42V) 30 µs 70 µs SHDN PWRGD VOUT FIGURE 4-4: Diagram. DS22026B-page 18 CDELAY and PWRGD Timing FIGURE 4-5: Diagram. Shutdown Input Timing © 2007 Microchip Technology Inc. MCP1725 4.8 Dropout Voltage and Undervoltage Lockout Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a VR + 0.6V differential applied. The MCP1725 LDO has a very low dropout voltage specification of 210 mV (typical) at 0.5A of output current. See Section 1.0 “Electrical Characteristics” for maximum dropout voltage specifications. The MCP1725 LDO operates across an input voltage range of 2.3V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the LDO output voltage off until the input voltage reaches a minimum of 2.18V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output will remain on until the input voltage level reaches 2.04V (typical). 4.9 Overtemperature Protection The MCP1725 LDO has temperature-sensing circuitry to prevent the junction temperature from exceeding approximately 150°C. If the LDO junction temperature does reach 150°C, the LDO output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section 5.0 “Application Circuits/Issues” for more information on LDO power dissipation and junction temperature. Since the MCP1725 LDO undervoltage lockout activates at 2.04V as the input voltage is falling, the dropout voltage specification does not apply for output voltages that are less than 1.9V. For high-current applications, voltage drops across the PCB traces must be taken into account. The trace resistances can cause significant voltage drops between the input voltage source and the LDO. For applications with input voltages near 2.3V, these PCB trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout. © 2007 Microchip Technology Inc. DS22026B-page 19 MCP1725 5.0 APPLICATION CIRCUITS/ ISSUES 5.1 Typical Application In addition to the LDO pass element power dissipation, there is power dissipation within the MCP1725 as a result of quiescent or ground current. The power dissipation as a result of the ground current can be calculated using the following equation: The MCP1725 is used for applications that require high LDO output current and a power good output. EQUATION 5-2: P I ( GND ) = V IN ( MAX ) × I VIN Where: MCP1725-2.5 VIN = 3.3V VOUT = 2.5V @ 0.5A C1 10 µF 1 VIN VOUT 8 2 VIN Sense 7 R1 10kΩ 3 SHDN CDELAY 6 C2 10 µF 4 GND PWRGD 5 On Off PI(GND = Power dissipation due to the quiescent current of the LDO VIN(MAX) = Maximum input voltage IVIN = Current flowing in the VIN pin with no LDO output current (LDO quiescent current) C3 1000 pF PWRGD FIGURE 5-1: 5.1.1 Typical Application Circuit. APPLICATION CONDITIONS Package Type = 2x3 DFN8 Input Voltage Range = 3.3V ± 5% 5.2 VIN maximum = 3.465V VIN minimum = 3.135V VDROPOUT (max) = 0.350V VOUT (typical) = 2.5V IOUT = 0.5A maximum PDISS (typical) = 0.4W Temperature Rise = 30.4°C Power Calculations 5.2.1 POWER DISSIPATION The internal power dissipation within the MCP1725 is a function of input voltage, output voltage, output current, and quiescent current. Equation 5-1 can be used to calculate the internal power dissipation for the LDO. The total power dissipated within the MCP1725 is the sum of the power dissipated in the LDO pass device and the P(IGND) term. Because of the CMOS construction, the typical IGND for the MCP1725 is 120 µA. Operating at 3.465V results in a power dissipation of 0.42 milli-Watts. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the MCP1725 is +125°C. To estimate the internal junction temperature of the MCP1725, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RθJA) of the device. The thermal resistance from junction to ambient for the 2x3 DFN package is estimated at 76° C/W. EQUATION 5-3: T J ( MAX ) = P TOTAL × Rθ JA + T AMAX TJ(MAX) = Maximum continuous junction temperature PTOTAL = Total device power dissipation RθJA = Thermal resistance from junction to ambient TAMAX = Maximum ambient temperature EQUATION 5-1: P LDO = ( V IN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) ) Where: PLDO = LDO Pass device internal power dissipation VIN(MAX) = Maximum input voltage VOUT(MIN) = LDO minimum output voltage DS22026B-page 20 © 2007 Microchip Technology Inc. MCP1725 The maximum power dissipation capability for a package can be calculated given the junction-toambient thermal resistance and the maximum ambient temperature for the application. Equation 5-4 can be used to determine the package maximum internal power dissipation. EQUATION 5-4: ( T J ( MAX ) – T A ( MAX ) ) P D ( MAX ) = --------------------------------------------------Rθ JA PD(MAX) = Maximum device power dissipation TJ(MAX) = maximum continuous junction temperature 5.3 Typical Application Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation is calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected. EXAMPLE 5-1: Package Package Type EQUATION 5-5: T J ( RISE ) = P D ( MAX ) × Rθ JA TJ(RISE) = Rise in device junction temperature over the ambient temperature VIN TJ = Junction temperature TJ(RISE) = Rise in device junction temperature over the ambient temperature TA = Ambient temperature © 2007 Microchip Technology Inc. = 3.3V ± 5% VOUT = 2.5V IOUT = 0.5A Maximum Ambient Temperature TA(MAX) = 60°C Internal Power Dissipation PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX) PLDO = ((3.3V x 1.05) – (2.5V x 0.975)) x 0.5A PLDO = 0.51 Watts RθJA = Thermal resistance from junction to ambient T J = T J ( RISE ) + T A 2x3 DFN LDO Output Voltage and Current PD(MAX) = Maximum device power dissipation EQUATION 5-6: = Input Voltage TA(MAX) = maximum ambient temperature RθJA = Thermal resistance from junction to ambient POWER DISSIPATION EXAMPLE 5.3.1 DEVICE JUNCTION TEMPERATURE RISE The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (RθJA) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface-mount packages. The EIA/JEDEC specification is JESD51-7 “High Effective Thermal Conductivity Test Board for Leaded Surface-Mount Packages”. The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this subject. TJ(RISE) = TJRISE = 0.51 W x 76.0° C/W TJRISE = 38.8°C PTOTAL x RθJA DS22026B-page 21 MCP1725 5.3.2 JUNCTION TEMPERATURE ESTIMATE To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: 5.4 CDELAY Calculations (typical) ΔT C = I • ------ΔV Where: C = CDELAY Capacitor I = CDELAY charging current, 140 nA typical. ΔT = time delay ΔV = CDELAY threshold voltage, 0.42V typical TJ = TJRISE + TA(MAX) TJ = 38.8°C + 60.0°C TJ = 98.8°C As you can see from the result, this application will be operating near around a junction temperature of 100°C. The PCB layout for this application is very important as it has a significant impact on the junctionto-ambient thermal resistance (RθJA) of the 2x3 DFN package, which is very important in this application. 5.3.3 MAXIMUM PACKAGE POWER DISSIPATION AT 60°C AMBIENT TEMPERATURE ΔT – 09 ( 140nA • Δ T ) C = I • ------- = ---------------------------------- = 333.3 ×10 • Δ T ΔV 0.42V For a delay of 300ms, C = 333.3E-09 *.300 C = 100E-09 µF (0.1 µF) 2x3 DFN (76°C/W RθJA): PD(MAX) = (125°C – 60°C) / 76°C/W PD(MAX) = 0.855W SOIC8 (163°C/Watt RθJA): PD(MAX) = (125°C – 60°C)/ 163°C/W PD(MAX) = 0.399W From this table, you can see the difference in maximum allowable power dissipation between the 2x3 DFN package and the 8-pin SOIC package. This difference is due to the exposed metal tab on the bottom of the DFN package. The exposed tab of the DFN package provides a very good thermal path from the die of the LDO to the PCB. The PCB then acts like a heatsink, providing more area to distribute the heat generated by the LDO. DS22026B-page 22 © 2007 Microchip Technology Inc. MCP1725 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN (2x3) Example: Standard Extended Temp XXX YWW NN Code Voltage Options * Code ABL 750 25 Voltage Options * ABL 0.8 ABR 3.0 ABM 1.2 ABS 3.3 ABP 1.8 ABT 5.0 ABQ 2.5 ABU ADJ * Custom output voltages available upon request. Contact your local Microchip sales office for more information. 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: Example: 250802E e3 SN^^0750 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. DS22026B-page 23 MCP1725 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH 0& ±[[PP%RG\>')1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D e b N N L K E2 E EXPOSED PAD NOTE 1 2 1 NOTE 1 1 2 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ 6WDQGRII $ &RQWDFW7KLFNQHVV $ 5() 2YHUDOO/HQJWK ' %6& 2YHUDOO:LGWK ( ([SRVHG3DG/HQJWK ' ± ([SRVHG3DG:LGWK ( ± E &RQWDFW/HQJWK / &RQWDFWWR([SRVHG3DG . ± ± &RQWDFW:LGWK %6& %6& 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS22026B-page 24 © 2007 Microchip Technology Inc. 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DS22026B-page 25 MCP1725 NOTES: DS22026B-page 26 © 2007 Microchip Technology Inc. MCP1725 APPENDIX A: REVISION HISTORY Revision B (December 2007) • Updated Temperature Specifications in Section 1.0 “Electrical Characteristics”. • Updated Section 6.0 “Packaging Information”. • Updated Templates. Revision A (December 2006) • Original Release of this Document. © 2007 Microchip Technology Inc. DS22026B-page 27 MCP1725 NOTES: DS22026B-page 28 © 2007 Microchip Technology Inc. MCP1725 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XX X X X/ XX Output Feature Tolerance Temp. Package Voltage Code Device: MCP1725: 500 mA Low Dropout Regulator MCP1725T: 500 mA Low Dropout Regulator Tape and Reel Output Voltage *: 08 12 18 25 30 33 50 = = = = = = = 0.8V “Standard” 1.2V “Standard” 1.8V “Standard” 2.5V “Standard” 3.0V “Standard” 3.3V “Standard” 5.0V “Standard” *Contact factory for other output voltage options Extra Feature Code: 0 = Fixed Tolerance: 2 = 2.0% (Standard) Temperature: E = -40°C to +125°C Package Type: MC = Plastic Dual Flat No Lead (DFN) (2x3 Body), 8-lead SN = Plastic Small Outline (150 mil Body), 8-lead © 2007 Microchip Technology Inc. Examples: a) MCP1725-0802E/MC: 0.8V Low Dropout Regulator, 8LD DFN pkg. b) MCP1725T-1202E/MC: Tape and Reel, 1.2V Low Dropout Regulator, 8LD DFN pkg. c) MCP1725-1802E/MC: d) MCP1725T-2502E/MC: Tape and Reel, 2.5V Low Dropout Voltage Regulator, 8LD DFN pkg. e) MCP1725-3002E/MC: 3.0V Low Dropout Voltage Regulator, 8LD DFN pkg. f) MCP1725-3302E/MC: 3.3V Low Dropout Voltage Regulator, 8LD DFN pkg. g) MCP1725T-5002E/MC: Tape and Reel, 5.0V Low Dropout Voltage Regulator, 8LD DFN pkg. h) MCP1725-ADJE/MC: i) MCP1725T-0802E/SN: Tape and Reel, 0.8V Low Dropout Voltage Regulator, 8LD SOIC pkg. j) MCP1725-1202E/SN: k) MCP1725T-1802E/SN: Tape and Reel, 1.8V Low Dropout Voltage Regulator, 8LD SOIC pkg. l) MCP1725-2502E/SN: 2.5V Low Dropout Voltage Regulator, 8LD SOIC pkg. m) MCP1725-3002E/SN: 3.0V Low Dropout Voltage Regulator, 8LD SOIC pkg. n) MCP1725-3302E/SN: 3.3V Low Dropout Voltage Regulator, 8LD SOIC pkg. o) MCP1725T-5002E/SN: Tape and Reel, 5.0V Low Dropout Voltage Regulator, 8LD SOIC pkg. p) MCP1725T-ADJE/SN: Tape and Reel, ADJ Low Dropout Voltage Regulator, 8LD SOIC pkg. 1.8V Low Dropout Voltage Regulator, 8LD DFN pkg. ADJ Low Dropout Voltage Regulator, 8LD DFN pkg. 1.2V Low Dropout Voltage Regulator, 8LD SOIC pkg. DS22026B-page 29 MCP1725 NOTES: DS22026B-page 30 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. 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