Product Folder Sample & Buy Support & Community Tools & Software Technical Documents bq40z50-R1 SLUSCB3 – JULY 2015 bq40z50-R1 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager 1 Features 3 Description • The bq40z50-R1 device, incorporating patented Impedance Track™ technology, is a fully integrated, single-chip, pack-based solution that provides a rich array of features for gas gauging, protection, and authentication for 1-series, 2-series, 3-series, and 4series cell Li-Ion and Li-Polymer battery packs. • • • • 2 Applications • • • PACKAGE BODY SIZE (NOM) VQFN (32) 4.00 mm × 4.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. Simplified Schematic VC4 DSG PACK BAT VCC PACK + CHG • • • PART NUMBER bq40z50-R1 PCHG • Device Information(1) PTC • Using its integrated high-performance analog peripherals, the bq40z50-R1 device measures and maintains an accurate record of available capacity, voltage, current, temperature, and other critical parameters in Li-Ion or Li-Polymer batteries, and reports this information to the system host controller over an SMBus v1.1 compatible interface. FUSE • • LEDCNTLA LEDCNTLB LEDCNTLC VC3 OUT VDD GND VC3 nd • Fully Integrated 1-Series, 2-Series, 3-Series, and 4-Series Li-Ion or Li-Polymer Cell Battery Pack Manager and Protection Next-Generation Patented Impedance Track™ Technology Accurately Measures Available Charge in Li-Ion and Li-Polymer Batteries High Side N-CH Protection FET Drive Integrated Cell Balancing While Charging or At Rest Full Array of Programmable Protection Features – Voltage – Current – Temperature – Charge Timeout – CHG/DSG FETs – AFE Sophisticated Charge Algorithms – JEITA – Enhanced Charging – Adaptive Charging – Cell Balancing Supports TURBO BOOST Mode Supports Battery Trip Point (BTP) Diagnostic Lifetime Data Monitor and Black Box Recorder LED Display Supports Two-Wire SMBus v1.1 Interface SHA-1 Authentication Compact Package: 32-Lead QFN (RSM) 2 level protector 1 VC2 Cell 3 Cell 2 VC2 DISP VC1 SMBD SMBC PBI VSS SRP SRN TS1 TS2 TS3 TS4 BTP PRES VC1 Cell 1 SMBD SMBC PRES BTP PACK– Notebook/Netbook PCs Medical and Test Equipment Portable Instrumentation 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Description (continued)......................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.24 Electrical Characteristics: Internal 1.8-V LDO ..... 14 7.25 Electrical Characteristics: High-Frequency Oscillator .................................................................. 14 7.26 Electrical Characteristics: Low-Frequency Oscillator .................................................................. 14 7.27 Electrical Characteristics: Voltage Reference 1.... 15 7.28 Electrical Characteristics: Voltage Reference 2.... 15 7.29 Electrical Characteristics: Instruction Flash .......... 15 7.30 Electrical Characteristics: Data Flash ................... 15 7.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2 Current Protection Thresholds ................................. 16 7.32 Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing ........................................ 16 7.33 Timing Requirements: SMBus .............................. 17 7.34 Timing Requirements: SMBus XL......................... 17 7.35 Typical Characteristics ......................................... 19 1 1 1 2 3 3 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 Absolute Maximum Ratings ...................................... 7 ESD Ratings.............................................................. 7 Recommended Operating Conditions....................... 8 Thermal Information .................................................. 8 Electrical Characteristics: Supply Current................. 8 Electrical Characteristics: Power Supply Control...... 8 Electrical Characteristics: AFE Power-On Reset ...... 9 Electrical Characteristics: AFE Watchdog Reset and Wake Timer................................................................ 9 7.9 Electrical Characteristics: Current Wake Comparator ................................................................ 9 7.10 Electrical Characteristics: VC1, VC2, VC3, VC4, BAT, PACK .............................................................. 10 7.11 Electrical Characteristics: SMBD, SMBC.............. 10 7.12 Electrical Characteristics: PRES, BTP_INT, DISP ................................................................................. 10 7.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB, LEDCNTLC ............................................................. 11 7.14 Electrical Characteristics: Coulomb Counter ........ 11 7.15 Electrical Characteristics: CC Digital Filter ........... 11 7.16 Electrical Characteristics: ADC ............................. 11 7.17 Electrical Characteristics: ADC Digital Filter ......... 12 7.18 Electrical Characteristics: CHG, DSG FET Drive . 12 7.19 Electrical Characteristics: PCHG FET Drive ......... 13 7.20 Electrical Characteristics: FUSE Drive.................. 13 7.21 Electrical Characteristics: Internal Temperature Sensor...................................................................... 13 7.22 Electrical Characteristics: TS1, TS2, TS3, TS4 .... 13 7.23 Electrical Characteristics: PTC, PTCEN ............... 14 8 Detailed Description ............................................ 22 8.1 8.2 8.3 8.4 9 Overview ................................................................. Functional Block Diagram ...................................... Feature Description................................................. Device Functional Modes........................................ 22 22 23 26 Applications and Implementation ...................... 27 9.1 Application Information .......................................... 27 9.2 Typical Applications ................................................ 28 10 Power Supply Recommendations ..................... 42 11 Layout................................................................... 43 11.1 Layout Guidelines ................................................. 43 11.2 Layout Example .................................................... 45 12 Device and Documentation Support ................. 47 12.1 12.2 12.3 12.4 12.5 Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 47 47 47 47 47 13 Mechanical, Packaging, and Orderable Information ........................................................... 47 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 2 DATE REVISION NOTES July 2015 * Initial Release Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 5 Description (continued) The bq40z50-R1 device supports TURBO BOOST mode by providing the available max power and max current to the host system. The device also supports Battery Trip Point to send a BTP interrupt signal to the host system at the pre-set state of charge thresholds. The bq40z50-R1 provides software-based 1st- and 2nd-level safety protection against overvoltage, undervoltage, overcurrent, short-circuit current, overload, and overtemperature conditions, as well as other pack- and cellrelated faults. SHA-1 authentication, with secure memory for authentication keys, enables identification of genuine battery packs. The compact 32-lead QFN package minimizes solution cost and size for smart batteries while providing maximum functionality and safety for battery gauging applications. 6 Pin Configuration and Functions PCHG NC DSG PACK VCC FUSE 29 28 27 26 25 CHG 31 30 BAT 32 RSM Package 32-Pin VQFN with Exposed Thermal Pad Top View PBI 1 24 PTCEN VC4 2 23 PTC VC3 3 22 LEDCNTLC VC2 4 21 LEDCNTLB VC1 5 20 LEDCNTLA SRN 6 19 SMBC NC 7 18 SMBD SRP 8 17 DISP 16 15 BTP_I NT PRES ¯¯¯¯ or SHUTDN ¯¯¯¯ 13 TS3 14 12 TS2 NC 11 TS1 TS4 9 10 VSS ¯¯¯¯ Pin Functions (1) TYPE (1) PIN NAME NUMBER PBI 1 P Power supply backup input pin DESCRIPTION VC4 2 IA Sense voltage input pin for most positive cell, and balance current input for most positive cell VC3 3 IA Sense voltage input pin for second most positive cell, balance current input for second most positive cell, and return balance current for most positive cell VC2 4 IA Sense voltage input pin for third most positive cell, balance current input for third most positive cell, and return balance current for second most positive cell VC1 5 IA Sense voltage input pin for least positive cell, balance current input for least positive cell, and return balance current for third most positive cell SRN 6 I NC 7 — SRP 8 I Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor. Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN where SRP is the top of the sense resistor. Not internally connected. Connect to VSS. VSS 9 P Device ground TS1 10 IA Temperature sensor 1 thermistor input pin TS2 11 IA Temperature sensor 2 thermistor input pin TS3 12 IA Temperature sensor 3 thermistor input pin TS4 13 IA Temperature sensor 4 thermistor input pin NC 14 — Not internally connected P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 3 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Pin Functions (continued) PIN NAME NUMBER BTP_INT 15 O Battery Trip Point (BTP) interrupt output PRES or SHUTDN 16 I Host system present input for removable battery pack or emergency system shutdown input for embedded pack DISP 17 — SMBD 18 I/OD SMBus data pin SMBC 19 I/OD SMBus clock pin LEDCNTLA 20 — LED display segment that drives the external LEDs depending on the firmware configuration LEDCNTLB 21 — LED display segment that drives the external LEDs depending on the firmware configuration LEDCNTLC 22 — LED display segment that drives the external LEDs depending on the firmware configuration PTC 23 IA Safety PTC thermistor input pin. To disable, connect both PTC and PTCEN to VSS. PTCEN 24 IA Safety PTC thermistor enable input pin. Connect to BAT. To disable, connect both PTC and PTCEN to VSS. FUSE 25 O Fuse drive output pin VCC 26 P Secondary power supply input PACK 27 IA Pack sense input pin DSG 28 O NMOS Discharge FET drive output pin NC 29 — Not internally connected PCHG 30 O PMOS Precharge FET drive output pin CHG 31 O NMOS Charge FET drive output pin BAT 32 P Primary power supply input pin 4 TYPE (1) DESCRIPTION Display control for LEDs Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 VC4 BAT VCC CDEN4 PACK VC3 + – 3.1 V BATDET ENVCC CDEN3 PACK Detector VC2 PACKDET PBI Reference System Shutdown Latch 1.8 V Domain VC1 BAT Control Power Supply Control ADC CDEN2 SHOUT ENBAT ADC Mux SHUTDOWN CDEN1 Cell Balancing VCC CHGEN BAT 2 kΩ CHG Pump CHG 8 kΩ 2 kΩ PCHG CHGOFF PCHGEN Pre-Charge Drive PACK BAT DSGEN BAT DSG Pump ZVCD 2 kΩ DSG CHGEN BAT DSGOFF CHG Pump VCC ZVCHGEN CHG, DSG Drive Zero-Volt Charge Figure 1. Pin Equivalent Diagram 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 5 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com 1.8 V ADTHx BAT FUSEWKPUP 18 kΩ 2 kΩ ADC Mux TS1,2,3,4 ADC FUSEEN 150 nA 2 kΩ FUSE 1.8 V 1.8 V 100 kΩ FUSEDIG RCWKPUP RCPUP FUSE Drive 1 kΩ RCIN RCOUT SMBCIN 100 kΩ SMBC Thermistor Inputs SMBCOUT SMBCEN 1 MΩ PBI 100 kΩ SMBDIN RHOEN SMBDOUT 10 kΩ PRES SMBD SMBDEN 1 MΩ SMBus Interface RHOUT 100 kΩ RHIN High-Voltage GPIO PTCEN BAT 30 kΩ PTC RLOEN PTC Comparator PTC Counter PTC Latch PTCDIG 290 nA 10 kΩ LED1, 2, 3 22.5 mA RLOUT 100 kΩ RLIN LED Drive PTC Detection Figure 2. Pin Equivalent Diagram 2 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 10 Ω VC4 CHANx Φ2 3.8 kΩ 1.9 MΩ SRP ADC Mux Φ1 ADC Φ2 3.8 kΩ 0.1 MΩ SRN Comparator Array Φ1 Φ2 10 Ω 100 Ω PACK Φ1 Coulomb Counter Φ2 CHANx 100 Ω Φ1 1.9 MΩ ADC Mux ADC 0.1 MΩ OCD, SCC, SCD Comparators and Coulomb Counter VC4 and PACK Dividers Figure 3. Pin Equivalent Diagram 3 7 Specifications 7.1 Absolute Maximum Ratings Over-operating free-air temperature range (unless otherwise noted) (1) Supply voltage range, VCC Input voltage range, VIN Output voltage range, VO MIN MAX UNIT BAT, VCC, PBI –0.3 30 V PACK, SMBC, SMBD, PRES or SHUTDN, BTP_INT, DISP –0.3 30 V TS1, TS2, TS3, TS4 –0.3 VREG + 0.3 V PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC –0.3 VBAT + 0.3 V SRP, SRN –0.3 0.3 V VC4 VC3 – 0.3 VC3 + 8.5, or VSS + 30 V VC3 VC2 – 0.3 VC2 + 8.5, or VSS + 30 V VC2 VC1 – 0.3 VC1 + 8.5, or VSS + 30 V VC1 VSS – 0.3 VSS + 8.5, or VSS + 30 V CHG, DSG –0.3 32 PCHG, FUSE –0.3 30 V 50 mA 150 °C 300 °C Maximum VSS current, ISS Storage temperature, TSTG –65 Lead temperature (soldering, 10 s), TSOLDER (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 7 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com 7.3 Recommended Operating Conditions Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) MIN VCC Supply voltage BAT, VCC, PBI VSHUTDOWN– Shutdown voltage VPACK < VSHUTDOWN– VSHUTDOWN+ Start-up voltage VPACK > VSHUTDOWN– + VHYS VHYS Shutdown voltage hysteresis VSHUTDOWN+ – VSHUTDOWN– NOM MAX 2.2 Input voltage range V 1.8 2.0 2.2 V 2.05 2.25 2.45 V 250 mV PACK, SMBC, SMBD, PRES, BTP_IN, DISP VIN UNIT 26 26 TS1, TS2, TS3, TS4 VREG PTC, PTCEN, LEDCNTLA, LEDCNTLB, LEDCNTLC VBAT SRP, SRN –0.2 0.2 VC4 VVC3 VVC3 + 5 VC3 VVC2 VVC2 + 5 VC2 VVC1 VVC1 + 5 VC1 VVSS VVSS + 5 VO Output voltage range CPBI External PBI capacitor 2.2 TOPR Operating temperature –40 CHG, DSG, PCHG, FUSE 26 V V µF 85 °C 7.4 Thermal Information RSM (QFN) THERMAL METRIC (1) RθJA, High K Junction-to-ambient thermal resistance 47.4 RθJC(top) Junction-to-case(top) thermal resistance 40.3 RθJB Junction-to-board thermal resistance 14.7 ψJT Junction-to-top characterization parameter 0.8 ψJB Junction-to-board characterization parameter 14.4 RθJC(bottom) Junction-to-case(bottom) thermal resistance 3.8 (1) UNIT 32 PINS °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics: Supply Current Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 20 V (unless otherwise noted) PARAMETER INORMAL NORMAL mode ISLEEP SLEEP mode ISHUTDOWN SHUTDOWN mode TEST CONDITIONS MIN CHG on. DSG on, no Flash write TYP MAX 336 CHG off, DSG on, no SBS communication 75 CHG off, DSG off, no SBS communication 52 UNIT µA µA 1.6 µA 7.6 Electrical Characteristics: Power Supply Control Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER VSWITCHOVER– 8 BAT to VCC switchover voltage TEST CONDITIONS VBAT < VSWITCHOVER– Submit Documentation Feedback MIN TYP MAX 1.95 2.1 2.2 UNIT V Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Electrical Characteristics: Power Supply Control (continued) Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS VSWITCHOVER+ VCC to BAT switchover voltage VHYS Switchover VSWITCHOVER+ – VSWITCHOVER– voltage hysteresis ILKG Input Leakage current Internal pulldown resistance RPD VBAT > VSWITCHOVER– + VHYS MIN TYP MAX UNIT 2.9 3.1 3.25 V 1000 mV BAT pin, BAT = 0 V, VCC = 25 V, PACK = 25 V 1 PACK pin, BAT = 25 V, VCC = 0 V, PACK = 0 V 1 BAT and PACK terminals, BAT = 0 V, VCC = 0 V, PACK = 0 V, PBI = 25 V 1 PACK 30 40 50 µA kΩ 7.7 Electrical Characteristics: AFE Power-On Reset Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS VREGIT– Negative-going voltage input VREG VHYS Power-on reset hysteresis VREGIT+ – VREGIT– tRST Power-on reset time MIN TYP MAX UNIT 1.51 1.55 1.59 V 70 100 130 mV 200 300 400 µs 7.8 Electrical Characteristics: AFE Watchdog Reset and Wake Timer Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER AFE watchdog timeout tWDT tWAKE AFE wake timer tFETOFF FET off delay after reset TEST CONDITIONS MIN TYP MAX tWDT = 500 372 500 628 tWDT = 1000 744 1000 1256 tWDT = 2000 1488 2000 2512 tWDT = 4000 2976 4000 5024 tWAKE = 250 186 250 314 tWAKE = 500 372 500 628 tWAKE = 1000 744 1000 1256 tWAKE = 512 1488 2000 2512 409 512 614 tFETOFF = 512 UNIT ms ms ms 7.9 Electrical Characteristics: Current Wake Comparator Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER VWAKE Wake voltage threshold VWAKE(DRIFT) Temperature drift of VWAKE accuracy MIN TYP MAX VWAKE = ±0.625 mV TEST CONDITIONS ±0.3 ±0.625 ±0.9 VWAKE = ±1.25 mV ±0.6 ±1.25 ±1.8 VWAKE = ±2.5 mV ±1.2 ±2.5 ±3.6 VWAKE = ±5 mV ±2.4 ±5.0 ±7.2 0.5% Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 UNIT mV °C 9 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Electrical Characteristics: Current Wake Comparator (continued) Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER tWAKE Time from application of current to wake interrupt tWAKE(SU) Wake comparator startup time TEST CONDITIONS MIN TYP 500 MAX UNIT 700 µs 1000 µs 7.10 Electrical Characteristics: VC1, VC2, VC3, VC4, BAT, PACK Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.1980 0.2000 0.2020 BAT–VSS, PACK–VSS 0.049 0.050 0.051 VREF2 0.490 0.500 0.510 VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3 K Scaling factor VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3 –0.2 5 BAT–VSS, PACK–VSS –0.2 20 VIN Input voltage range ILKG Input leakage current VC1, VC2, VC3, VC4, cell balancing off, cell detach detection off, ADC multiplexer off RCB Internal cell balance resistance RDS(ON) for internal FET switch at 2 V < VDS < 4 V ICD Internal cell detach check current VCx > VSS + 0.8 V 30 50 UNIT — V 1 µA 200 Ω 70 µA 7.11 Electrical Characteristics: SMBD, SMBC Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1.3 UNIT VIH Input voltage high SMBC, SMBD, VREG = 1.8 V VIL Input voltage low SMBC, SMBD, VREG = 1.8 V 0.8 V V VOL Output low voltage SMBC, SMBD, VREG = 1.8 V, IOL = 1.5 mA 0.4 V CIN Input capacitance ILKG Input leakage current 1 µA RPD Pulldown resistance 1.3 MΩ 5 0.7 1.0 pF 7.12 Electrical Characteristics: PRES, BTP_INT, DISP Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER VIH High-level input VIL Low-level input VOH Output voltage high VOL Output voltage low CIN Input capacitance ILKG Input leakage current RO Output reverse resistance 10 TEST CONDITIONS MIN TYP MAX 1.3 V 0.55 VBAT > 5.5 V, IOH = –0 µA 3.5 VBAT > 5.5 V, IOH = –10 µA 1.8 0.4 5 Submit Documentation Feedback V pF 1 8 V V IOL = 1.5 mA Between PRES or BTP_INT or DISP and PBI UNIT µA kΩ Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 7.13 Electrical Characteristics: LEDCNTLA, LEDCNTLB, LEDCNTLC Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS VIH High-level input VIL Low-level input MIN TYP MAX UNIT 1.45 V 0.55 VOH Output voltage high VBAT > 3.0 V, IOH = –22.5 mA VOL Output voltage low IOL = 1.5 mA ISC High level output current protection IOL Low level output current VBAT > 3.0 V, VOH = 0.4 V ILEDCNTLx Current matching between LEDCNTLx VBAT = VLEDCNTLx + 2.5 V CIN Input capacitance ILKG Input leakage current fLEDCNTLx Frequency of LED pattern V VBAT – 1.6 V 0.4 V –30 –45 –6 0 mA 15.75 22.5 29.25 mA ±1% 20 pF 1 µA 124 Hz 7.14 Electrical Characteristics: Coulomb Counter Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS Input voltage range Full scale range Integral nonlinearity (1) 16-bit, best fit over input voltage range Offset error Offset error drift Gain error 15-bit + sign, over input voltage range Gain error drift 15-bit + sign, over input voltage range TYP MAX 0.1 –VREF1/10 VREF1/10 UNIT V V ±5.2 ±22.3 16-bit, Post-calibration ±5 ±10 µV 15-bit + sign, Post-calibration 0.2 0.3 µV/°C ±0.2% ±0.8% Effective input resistance (1) MIN –0.1 150 LSB FSR PPM/°C 2.5 N MΩ 15 1 LSB = VREF1/(10 × 2 ) = 1.215/(10 × 2 ) = 3.71 µV 7.15 Electrical Characteristics: CC Digital Filter Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS Conversion time Single conversion Effective resolution Single conversion MIN TYP MAX UNIT 250 ms 15 Bits 7.16 Electrical Characteristics: ADC Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER Input voltage range Full scale range Integral nonlinearity (1) (1) TEST CONDITIONS MIN TYP MAX Internal reference (VREF1) –0.2 1 External reference (VREG) –0.2 0.8 x VREG VFS = VREF1 or VREG –VFS VFS 16-bit, best fit, –0.1 V to 0.8 x VREF1 16-bit, best fit, –0.2 V to –0.1 V ±6.6 ±13.1 UNIT V V LSB 1 LSB = VREF1/(2N) = 1.225/(215) = 37.4 µV (when tCONV = 31.25 ms) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 11 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Electrical Characteristics: ADC (continued) Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS Offset error (2) 16-bit, Post-calibration, VFS = VREF1 Offset error drift 16-bit, Post-calibration, VFS = VREF1 Gain error 16-bit, –0.1 V to 0.8 x VFS Gain error drift 16-bit, –0.1 V to 0.8 x VFS Effective input resistance (2) MIN TYP MAX UNIT ±67 ±157 µV 0.6 3 ±0.2% ±0.8% 150 8 µV/°C FSR PPM/°C MΩ For VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC4–VSS, PACK–VSS, and VREF1/2, the offset error is multiplied by (1/ADC multiplexer scaling factor (K)). 7.17 Electrical Characteristics: ADC Digital Filter Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER Conversion time TEST CONDITIONS MIN Single conversion 31.25 Single conversion 15.63 Single conversion 7.81 Single conversion Resolution Effective resolution TYP MAX UNIT ms 1.95 No missing codes 16 With sign, tCONV = 31.25 ms 14 15 Bits With sign, tCONV = 15.63 ms 13 14 With sign, tCONV = 7.81 ms 11 12 With sign, tCONV = 1.95 ms 9 10 Bits 7.18 Electrical Characteristics: CHG, DSG FET Drive Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER Output voltage ratio V(FETON) V(FETOFF) tR tF 12 TEST CONDITIONS MIN TYP MAX RatioDSG = (VDSG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 10 MΩ between PACK and DSG 2.133 2.333 2.433 RatioCHG = (VCHG – VBAT)/VBAT, 2.2 V < VBAT < 4.92 V, 10 MΩ between BAT and CHG 2.133 2.333 2.433 10.5 11.5 12 10.5 11.5 12 VDSG(ON) = VDSG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between PACK and DSG, VBAT = 18 V Output voltage, CHG and DSG on VCHG(ON) = VCHG – VBAT, VBAT ≥ 4.92 V, 10 MΩ between BAT and CHG, VBAT = 18 V VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and Output voltage, DSG CHG and DSG off VCHG(OFF) = VCHG – VBAT, 10 MΩ between BAT and CHG Rise time Fall time — V –0.4 0.4 –0.4 0.4 VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG 200 VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥ 2.2 V, CL = 4.7 nF between CHG and BAT, 5.1 kΩ between CHG and CL, 10 MΩ between BAT and CHG 200 500 VDSG from VDSG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF between DSG and PACK, 5.1 kΩ between DSG and CL, 10 MΩ between PACK and DSG 40 300 VCHG from VCHG(ON)(TYP) to 1 V, VBAT ≥ 2.2 V, CL = 4.7 nF between CHG and BAT, 5.1 kΩ between CHG and CL, 10 MΩ between BAT and CHG 40 200 Submit Documentation Feedback UNIT V 500 µs µs Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 7.19 Electrical Characteristics: PCHG FET Drive Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS V(FETON) Output voltage, PCHG on VPCHG(ON) = VVCC – VPCHG, 10 MΩ between VCC and PCHG V(FETOFF) Output voltage, PCHG off VPCHG(OFF) = VVCC – VPCHG, 10 MΩ between VCC and PCHG tR Rise time VPCHG from 10% to 90% VPCHG(ON)(TYP), VVCC ≥ 8 V, CL = 4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG and CL, 10 MΩ between VCC and CHG tF Fall time VPCHG from 90% to 10% VPCHG(ON)(TYP), VCC ≥ 8 V, CL = 4.7 nF between PCHG and VCC, 5.1 kΩ between PCHG and CL, 10 MΩ between VCC and CHG MIN TYP MAX 6 7 8 V 0.4 V 40 200 µs 40 200 µs –0.4 UNIT 7.20 Electrical Characteristics: FUSE Drive Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS VOH Output voltage high VIH High-level input IAFEFUSE(PU) Internal pullup current RAFEFUSE Output impedance CIN Input capacitance tDELAY Fuse trip detection delay tRISE Fuse output rise time MIN TYP MAX VBAT ≥ 8 V, CL = 1 nF, IAFEFUSE = 0 µA 6 7 8.65 VBAT < 8 V, CL = 1 nF, IAFEFUSE = 0 µA VBAT – 0.1 1.5 VBAT ≥ 8 V, VAFEFUSE = VSS 2 UNIT V VBAT 2.0 2.5 V 150 330 nA 2.6 3.2 kΩ 5 128 VBAT ≥ 8 V, CL = 1 nF, VOH = 0 V to 5 V 5 pF 256 µs 20 µs 7.21 Electrical Characteristics: Internal Temperature Sensor Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER Internal temperature sensor voltage drift VTEMP TEST CONDITIONS VTEMPP VTEMPP – VTEMPN, assured by design MIN TYP MAX –1.9 –2.0 –2.1 0.177 0.178 0.179 UNIT mV/°C 7.22 Electrical Characteristics: TS1, TS2, TS3, TS4 Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX TS1, TS2, TS3, TS4, VBIAS = VREF1 –0.2 0.8 x VREF1 TS1, TS2, TS3, TS4, VBIAS = VREG –0.2 0.8 x VREG UNIT VIN Input voltage range RNTC(PU) Internal pullup resistance TS1, TS2, TS3, TS4 14.4 18 21.6 kΩ RNTC(DRIFT) Resistance drift over temperature TS1, TS2, TS3, TS4 –360 –280 –200 PPM/°C V Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 13 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com 7.23 Electrical Characteristics: PTC, PTCEN Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.2 2.5 3.95 MΩ RPTC(TRIP) PTC trip resistance VPTC(TRIP) PTC trip voltage VPTC(TRIP) = VPTCEN – VPTC 200 500 890 mV IPTC Internal PTC current bias TA = –40°C to 110°C 200 290 350 nA tPTC(DELAY) PTC delay time TA = –40°C to 110°C 40 80 145 ms 7.24 Electrical Characteristics: Internal 1.8-V LDO Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 1.6 1.8 2.0 VREG Regulator voltage ΔVO(TEMP) Regulator output over temperature ΔVREG/ΔTA, IREG = 10 mA ΔVO(LINE) Line regulation ΔVREG/ΔVBAT, VBAT = 10 mA –0 .6% 0.5% ΔVO(LOAD) Load regulation ΔVREG/ΔIREG, IREG = 0 mA to 10 mA –1.5% 1.5% IREG Regulator output current limit VREG = 0.9 x VREG(NOM), VIN > 2.2 V 20 ISC Regulator shortcircuit current limit VREG = 0 x VREG(NOM) 25 PSRRREG Power supply rejection ratio ΔVBAT/ΔVREG, IREG = 10 mA ,VIN > 2.5 V, f = 10 Hz VSLEW Slew rate enhancement voltage threshold VREG UNIT V ±0.25% 1.58 mA 40 55 mA 40 dB 1.65 V 7.25 Electrical Characteristics: High-Frequency Oscillator Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER fHFO TEST CONDITIONS MIN TYP TA = –20°C to 70°C, includes frequency drift –2.5% ±0.25% 2.5% TA = –40°C to 85°C, includes frequency drift –3.5% ±0.25% 3.5% Operating frequency fHFO(ERR) tHFO(SU) Frequency error Start-up time MAX 16.78 TA = –20°C to 85°C, oscillator frequency within +/–3% of nominal oscillator frequency within +/–3% of nominal UNIT MHz 4 ms 100 µs 7.26 Electrical Characteristics: Low-Frequency Oscillator Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER fLFO MIN Operating frequency fLFO(ERR) Frequency error fLFO(FAIL) Failure detection frequency 14 TEST CONDITIONS TYP MAX 262.144 kHz TA = –20°C to 70°C, includes frequency drift –1.5% ±0.25% 1.5% TA = –40°C to 85°C, includes frequency drift –2.5 ±0.25 2.5 30 80 100 Submit Documentation Feedback UNIT kHz Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 7.27 Electrical Characteristics: Voltage Reference 1 Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER VREF1 Internal reference voltage VREF1(DRIFT) Internal reference voltage drift TEST CONDITIONS TA = 25°C, after trim MIN TYP MAX UNIT 1.21 1.215 1.22 V TA = 0°C to 60°C, after trim ±50 TA = –40°C to 85°C, after trim ±80 PPM/°C 7.28 Electrical Characteristics: Voltage Reference 2 Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER VREF2 Internal reference voltage VREF2(DRIFT) Internal reference voltage drift TEST CONDITIONS TA = 25°C, after trim MIN TYP MAX UNIT 1.22 1.225 1.23 V TA = 0°C to 60°C, after trim ±50 TA = –40°C to 85°C, after trim ±80 PPM/°C 7.29 Electrical Characteristics: Instruction Flash Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS Data retention Flash programming write cycles MIN TYP MAX UNIT 10 Years 1000 Cycles tPROGWORD Word programming time TA = –40°C to 85°C 40 µs tMASSERASE Mass-erase time TA = –40°C to 85°C 40 ms tPAGEERASE Page-erase time TA = –40°C to 85°C 40 ms IFLASHREAD Flash-read current TA = –40°C to 85°C 2 mA IFLASHWRITE Flash-write current TA = –40°C to 85°C 5 mA IFLASHERASE Flash-erase current TA = –40°C to 85°C 15 mA 7.30 Electrical Characteristics: Data Flash Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS Data retention Flash programming write cycles MIN TYP MAX UNIT 10 Years 20000 Cycles tPROGWORD Word programming time TA = –40°C to 85°C 40 µs tMASSERASE Mass-erase time TA = –40°C to 85°C 40 ms tPAGEERASE Page-erase time TA = –40°C to 85°C 40 ms IFLASHREAD Flash-read current TA = –40°C to 85°C 1 mA IFLASHWRITE Flash-write current TA = –40°C to 85°C 5 mA IFLASHERASE Flash-erase current TA = –40°C to 85°C 15 mA Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 15 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com 7.31 Electrical Characteristics: OCD, SCC, SCD1, SCD2 Current Protection Thresholds Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) PARAMETER TEST CONDITIONS VOCD = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 OCD detection threshold voltage range VOCD = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 VOCD OCD detection threshold voltage program step ΔVOCD SCC detection threshold voltage program step ΔVSCC SCD1 detection threshold voltage program step ΔVSCD1 VSCD2 SCD2 detection threshold voltage program step ΔVSCD2 VOFFSET OCD, SCC, and SCDx offset error VSCALE OCD, SCC, and SCDx scale error –100 –8.3 –50 –2.78 mV 44.4 200 22.2 100 mV VSCC = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 22.2 VSCC = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 11.1 mV –44.4 –200 –22.2 –100 mV VSCD1 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 –22.2 VSCD1 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 –11.1 mV –44.4 –200 –22.2 –100 mV VSCD2 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 –22.2 VSCD2 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 –11.1 Post-trim No trim Post-trim UNIT mV VOCD = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 VSCD2 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 SCD2 detection threshold voltage range VSCD2 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 MAX –16.6 –5.56 VSCD1 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 SCD1 detection threshold voltage range VSCD1 = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 VSCD1 TYP VOCD = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 VSCC = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 1 SCC detection threshold voltage range VSCC = VSRP – VSRN, AFE PROTECTION CONTROL[RSNS] = 0 VSCC MIN mV –2.5 2.5 –10% 10% –5% 5% mV — 7.32 Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) MIN tOCD OCD detection delay time ΔtOCD OCD detection delay time program step tSCC SCC detection delay time ΔtSCC SCC detection delay time program step tSCD1 SCD1 detection delay time 16 NOM 1 MAX 31 2 0 ms ms 915 61 µs µs AFE PROTECTION CONTROL[SCDDx2] = 0 0 915 AFE PROTECTION CONTROL[SCDDx2] = 1 0 1850 Submit Documentation Feedback UNIT µs Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Timing Requirements: OCD, SCC, SCD1, SCD2 Current Protection Timing (continued) Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) MIN NOM MAX AFE PROTECTION CONTROL[SCDDx2] = 0 61 ΔtSCD1 SCD1 detection delay time program step AFE PROTECTION CONTROL[SCDDx2] = 1 121 tSCD2 SCD2 detection delay time AFE PROTECTION CONTROL[SCDDx2] = 0 0 458 AFE PROTECTION CONTROL[SCDDx2] = 1 0 915 SCD2 detection delay time program step AFE PROTECTION CONTROL[SCDDx2] = 0 30.5 ΔtSCD2 AFE PROTECTION CONTROL[SCDDx2] = 1 61 tDETECT Current fault detect time VSRP – VSRN = VT – 3 mV for OCD, SCD1, and SC2, VSRP – VSRN = VT + 3 mV for SCC tACC Current fault delay time accuracy Max delay setting UNIT µs µs µs 160 –10% µs 10% 7.33 Timing Requirements: SMBus Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) MIN NOM MAX UNIT 100 kHz fSMB SMBus operating frequency SLAVE mode, SMBC 50% duty cycle fMAS SMBus master clock frequency MASTER mode, no clock low slave extend tBUF Bus free time between start and stop 4.7 µs tHD(START) Hold time after (repeated) start 4.0 µs tSU(START) Repeated start setup time 4.7 µs tSU(STOP) Stop setup time 4.0 µs tHD(DATA) Data hold time 300 ns tSU(DATA) Data setup time 250 ns tTIMEOUT Error signal detect time 25 tLOW Clock low period 4.7 tHIGH Clock high period 4.0 tR Clock rise time tF Clock fall time 10 51.2 kHz 35 ms µs 50 µs 10% to 90% 1000 ns 90% to 10% 300 ns tLOW(SEXT) Cumulative clock low slave extend time 25 ms tLOW(MEXT) Cumulative clock low master extend time 10 ms 7.34 Timing Requirements: SMBus XL Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) MIN SLAVE mode NOM MAX UNIT 400 kHz fSMBXL SMBus XL operating frequency tBUF Bus free time between start and stop 4.7 µs tHD(START) Hold time after (repeated) start 4.0 µs 40 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 17 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Timing Requirements: SMBus XL (continued) Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2 V to 26 V (unless otherwise noted) MIN tSU(START) Repeated start setup time 4.7 tSU(STOP) Stop setup time 4.0 tTIMEOUT Error signal detect time tLOW tHIGH NOM MAX UNIT µs µs 5 20 ms Clock low period 20 µs Clock high period 20 µs TtR tSU(STOP)p TtF TtF TtBUFT SMBC SMBC SMBD SMBD P TtR TtHIGHT tHD(START) TtLOWT S tHD(DATA)T Start and Stop Condition TtSU(DATA) Wait and Hold Condition tSU(START)T TtTIMEOUT SMBC SMBC SMBD SMBD S Timeout Condition Repeated Start Condition Figure 4. SMBus Timing Diagram 18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 7.35 Typical Characteristics 0.15 8.0 Max CC Offset Error Min CC Offset Error 6.0 ADC Offset Error (V/C) CC Offset Error (V/C) 0.10 0.05 0.00 ±0.05 ±0.10 4.0 2.0 0.0 ±2.0 ±4.0 ±6.0 ±0.15 ±40 ±20 0 20 40 60 80 100 Temperature (C) ±8.0 120 ±40 0 20 40 60 80 100 Temperature (C) Figure 5. CC Offset Error vs. Temperature 120 C003 Figure 6. ADC Offset Error vs. Temperature 264 Low-Frequency Oscillator (kHz) Reference Voltage (V) ±20 C001 1.24 1.23 1.22 1.21 1.20 262 260 258 256 254 252 250 ±40 0 ±20 20 40 60 80 Temperature (C) 100 ±40 0 ±20 20 40 60 80 Temperature (C) C006 Figure 7. Reference Voltage vs. Temperature 100 C007 Figure 8. Low-Frequency Oscillator vs. Temperature 16.9 ±24.6 OCD Protection Threshold (mV) High-Frequency Oscillator (MHz) Max ADC Offset Error Min ADC Offset Error 16.8 16.7 16.6 ±24.8 ±25.0 ±25.2 ±25.4 ±25.6 ±25.8 ±40 ±20 0 20 40 60 Temperature (C) 80 100 120 ±40 ±20 0 20 40 60 80 100 Temperature (C) C008 120 C009 Threshold setting is 25 mV. Figure 9. High-Frequency Oscillator vs. Temperature Figure 10. Overcurrent Discharge Protection Threshold vs. Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 19 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Typical Characteristics (continued) ±86.0 SCD 1 Protection Threshold (mV) SCC Protection Threshold (mV) 87.4 87.2 87.0 86.8 86.6 86.4 86.2 ±86.2 ±86.4 ±86.6 ±86.8 ±87.0 ±87.2 ±40 ±20 0 20 40 60 80 100 Temperature (C) 120 ±40 ±20 0 C010 Threshold setting is 25 mV. 20 40 60 80 100 Temperature (C) 120 C011 Threshold setting is –88.85 mV. Figure 11. Short Circuit Charge Protection Threshold vs. Temperature Figure 12. Short Circuit Discharge 1 Protection Threshold vs. Temperature ±172.9 Over-Current Delay Time (mS) SCD 2 Protection Threshold (mV) 11.00 ±173.0 ±173.1 ±173.2 ±173.3 ±173.4 ±173.5 10.95 10.90 10.85 10.80 10.75 10.70 ±173.6 ±40 ±20 0 20 40 60 80 100 Temperature (C) 120 ±40 Threshold setting is –177.7 mV. 20 40 60 80 100 120 C013 Threshold setting is 11 ms. Figure 14. Overcurrent Delay Time vs. Temperature 480 452 450 SC Discharge 1 Delay Time (S) SC Charge Current Delay Time (S) 0 Temperature (C) Figure 13. Short Circuit Discharge 2 Protection Threshold vs. Temperature 448 446 444 442 440 438 436 434 432 460 440 420 400 ±40 ±20 0 20 40 60 Temperature (C) 80 100 120 ±40 ±20 0 20 40 60 80 Temperature (C) C014 Threshold setting is 465 µs. 100 120 C015 Threshold setting is 465 µs (including internal delay). Figure 15. Short Circuit Charge Current Delay Time vs. Temperature 20 ±20 C012 Figure 16. Short Circuit Discharge 1 Delay Time vs. Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Typical Characteristics (continued) 3.49825 2.4984 2.49835 3.4982 Cell Voltage (V) Cell Voltage (V) 2.4983 2.49825 2.4982 2.49815 2.4981 3.49815 3.4981 3.49805 2.49805 3.498 2.498 ±40 ±20 0 20 40 60 80 100 Temperature (C) 120 ±40 ±20 0 20 40 60 80 100 Temperature (C) C016 120 C017 This is the VCELL average for single cell. Figure 17. VCELL Measurement at 2.5-V vs. Temperature Figure 18. VCELL Measurement at 3.5-V vs. Temperature 4.24805 Measurement Current (mA) 99.25 Cell Voltage (V) 4.248 4.24795 4.2479 4.24785 4.2478 99.20 99.15 99.10 99.05 99.00 ±40 ±20 0 20 40 60 Temperature (C) 80 100 120 ±40 0 20 40 60 80 100 Temperature (C) C018 This is the VCELL average for single cell. ±20 120 C019 ISET = 100 mA Figure 19. VCELL Measurement at 4.25-V vs. Temperature Figure 20. I measured vs. Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 21 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com 8 Detailed Description 8.1 Overview The bq40z50-R1 device, incorporating patented Impedance Track™ technology, provides cell balancing while charging or at rest. This fully integrated, single-chip, pack-based solution provides a rich array of features for gas gauging, protection, and authentication for 1-series, 2-series, 3-series, and 4-series cell Li-Ion and Li-Polymer battery packs, including a diagnostic lifetime data monitor and black box recorder. Cell Detach Detection Wake Comparator PCHG DSG CHG PBI VCC BAT VSS Cell, Stack, Pack Voltage PACK VC2 VC1 VC4 Cell Balancing VC3 8.2 Functional Block Diagram Power Mode Control High Side N-CH FET Drive P-CH FET Drive Power On Reset Zero Volt Charge Control PTC Overtemp Short Circuit Comparator FUSE Control PTCEN PTC FUSE SRP SRN Over Current Comparator Voltage Reference2 High Voltage I/O NTC Bias Random Number Generator Watchdog Timer Internal Temp Sensor LED Display Drive I/O TS1 TS2 TS3 ADC/CC FRONTEND ADC MUX /PRES or /SHUTDN /DISP LEDCNTLC LEDCNTLB LEDCNTLA TS4 Voltage Reference1 BTP_INT AFE Control Low Frequency Oscillator 1.8V LDO Regulator AFE COM Engine SBS High Voltage Translation I/O & Interrupt Controller AFE COM Engine SBS COM Engine SMBD SMBC High Frequency Oscillator Low Voltage I/O I/O ADC/CC Digital Filter Data (8bit) bqBMP CPU PMInstr (8bit) DMAddr (16bit) PMAddr (16bit) Program Flash EEPROM 22 Timers & PWM Data Flash EEPROM Data SRAM Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 8.3 Feature Description 8.3.1 Primary (1st Level) Safety Features The bq40z50-R1 supports a wide range of battery and system protection features that can easily be configured. See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for detailed descriptions of each protection function. The primary safety features include: • • • • • • • • • • • • • • • • • • • • Cell Overvoltage Protection Cell Undervoltage Protection Cell Undervoltage Protection Compensated Overcurrent in Charge Protection Overcurrent in Discharge Protection Overload in Discharge Protection Short Circuit in Charge Protection Short Circuit in Discharge Protection Overtemperature in Charge Protection Overtemperature in Discharge Protection Undertemperature in Charge Protection Undertemperature in Discharge Protection Overtemperature FET protection Precharge Timeout Protection Host Watchdog Timeout Protection Fast Charge Timeout Protection Overcharge Protection Overcharging Voltage Protection Overcharging Current Protection Over Precharge Current Protection 8.3.2 Secondary (2nd Level) Safety Features The secondary safety features of the bq40z50-R1 can be used to indicate more serious faults via the FUSE pin. This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or discharging. See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for detailed descriptions of each protection function. The secondary safety features provide protection against: • Safety Overvoltage Permanent Failure • Safety Undervoltage Permanent Failure • Safety Overtemperature Permanent Failure • Safety FET Overtemperature Permanent Failure • Qmax Imbalance Permanent Failure • Impedance Imbalance Permanent Failure • Capacity Degradation Permanent Failure • Cell Balancing Permanent Failure • Fuse Failure Permanent Failure • PTC Permanent Failure • Voltage Imbalance at Rest Permanent Failure • Voltage Imbalance Active Permanent Failure • Charge FET Permanent Failure • Discharge FET Permanent Failure • AFE Register Permanent Failure • AFE Communication Permanent Failure Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 23 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Feature Description (continued) • • • • • Second Level Protector Permanent Failure Instruction Flash Checksum Permanent Failure Open Cell Connection Permanent Failure Data Flash Permanent Failure Open Thermistor Permanent Failure 8.3.3 Charge Control Features The bq40z50-R1 charge control features include: • • • • • • • Supports JEITA temperature ranges. Reports charging voltage and charging current according to the active temperature range Handles more complex charging profiles. Allows for splitting the standard temperature range into two subranges and allows for varying the charging current according to the cell voltage Reports the appropriate charging current needed for constant current charging and the appropriate charging voltage needed for constant voltage charging to a smart charger using SMBus broadcasts Reduces the charge difference of the battery cells in fully charged state of the battery pack gradually using a voltage-based cell balancing algorithm during charging. A voltage threshold can be set up for cell balancing to be active. This prevents fully charged cells from overcharging and causing excessive degradation and also increases the usable pack energy by preventing premature charge termination. Supports pre-charging/zero-volt charging Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range Reports charging fault and also indicates charge status via charge and discharge alarms 8.3.4 Gas Gauging The bq40z50-R1 uses the Impedance Track algorithm to measure and calculate the available capacity in battery cells. The bq40z50-R1 accumulates a measure of charge and discharge currents and compensates the charge current measurement for the temperature and state-of-charge of the battery. The bq40z50-R1 estimates selfdischarge of the battery and also adjusts the self-discharge estimation based on temperature. The device also has TURBO BOOST mode support, which enables the bq40z50-R1 to provide the necessary data for the MCU to determine what level of peak power consumption can be applied without causing a system reset or transient battery voltage level spike to trigger termination flags. See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for further details. 8.3.5 Configuration 8.3.5.1 Oscillator Function The bq40z50-R1 fully integrates the system oscillators and does not require any external components to support this feature. 8.3.5.2 System Present Operation The bq40z50-R1 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external system, the bq40z50-R1 detects this as system present. 8.3.5.3 Emergency Shutdown For battery maintenance, the emergency shutdown feature enables a push button action connecting the SHUTDN pin to shutdown an embedded battery pack system before removing the battery. A high-to-low transition of the SHUTDN pin signals the bq40z50-R1 to turn off both CHG and DSG FETs, disconnecting the power from the system to safely remove the battery pack. The CHG and DSG FETs can be turned on again by another high-to-low transition detected by the SHUTDN pin or when a data flash configurable timeout is reached. 8.3.5.4 1-Series, 2-Series, 3-Series, or 4-Series Cell Configuration In a 1-series cell configuration, VC4 is shorted to VC, VC2 and VC1. In a 2-series cell configuration, VC4 is shorted to VC3 and VC2. In a 3-series cell configuration, VC4 is shorted to VC3. 24 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Feature Description (continued) 8.3.5.5 Cell Balancing The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device's internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time. Higher cell balance current can be achieved by using an external cell balancing circuit. In external cell balancing mode, only one cell at a time can be balanced. The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of all cells. 8.3.6 Battery Parameter Measurements 8.3.6.1 Charge and Discharge Counting The bq40z50-R1 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a second delta-sigma ADC for individual cell and battery voltage and temperature measurement. The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage drop across a small-value sense resistor between the SRP and SRN terminals. The integrating ADC measures bipolar signals from –0.1 V to 0.1 V. The bq40z50-R1 detects charge activity when VSR = V(SRP) – V(SRN) is positive, and discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq40z50-R1 continuously integrates the signal over time, using an internal counter. The fundamental rate of the counter is 0.26 nVh. 8.3.7 Battery Trip Point (BTP) Required for WIN8 OS, the battery trip point (BTP) feature indicates when the RSOC of a battery pack has depleted to a certain value set in a DF register. This feature allows a host to program two capacity-based thresholds that govern the triggering of a BTP interrupt on the BTP_INT pin and the setting or clearing of the OperationStatus[BTP_INT] on the basis of RemainingCapacity(). An internal weak pull-up is applied when the BTP feature is active. Depending on the system design, an external pull-up may be required to put on the BTP_INT pin. See Electrical Characteristics: PRES, BTP_INT, DISP for details. 8.3.8 Lifetime Data Logging Features The bq40z50-R1 offers lifetime data logging for several critical battery parameters. The following parameters are updated every 10 hours if a difference is detected between values in RAM and data flash: • Maximum and Minimum Cell Voltages • Maximum Delta Cell Voltage • Maximum Charge Current • Maximum Discharge Current • Maximum Average Discharge Current • Maximum Average Discharge Power • Maximum and Minimum Cell Temperature • Maximum Delta Cell Temperature • Maximum and Minimum Internal Sensor Temperature • Maximum FET Temperature • Number of Safety Events Occurrences and the Last Cycle of the Occurrence • Number of Valid Charge Termination and the Last Cycle of the Valid Charge Termination • Number of Qmax and Ra Updates and the Last Cycle of the Qmax and Ra Updates • Number of Shutdown Events • Cell Balancing Time for Each Cell (This data is updated every 2 hours if a difference is detected.) • Total FW Runtime and Time Spent in Each Temperature Range (This data is updated every 2 hours if a difference is detected.) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 25 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Feature Description (continued) 8.3.9 Authentication The bq40z50-R1 supports authentication by the host using SHA-1. 8.3.10 LED Display The bq40z50-R1 can drive a 3-, 4-, or 5- segment LED display for remaining capacity indication and/or a permanent fail (PF) error code indication. 8.3.11 Voltage The bq40z50-R1 updates the individual series cell voltages at 0.25-second intervals. The internal ADC of the bq40z50-R1 measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the impedance of the cell for the Impedance Track gas gauging. 8.3.12 Current The bq40z50-R1 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current using a 1-mΩ to 3-mΩ typ. sense resistor. 8.3.13 Temperature The bq40z50-R1 has an internal temperature sensor and inputs for four external temperature sensors. All five temperature sensor options can be individually enabled and configured for cell or FET temperature usage. Two configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET temperature, which use a different thermistor profile. 8.3.14 Communications The bq40z50-R1 uses SMBus v1.1 with MASTER mode and packet error checking (PEC) options per the SBS specification. 8.3.14.1 SMBus On and Off State The bq40z50-R1 detects an SMBus off state when SMBC and SMBD are low for two or more seconds. Clearing this state requires that either SMBC or SMBD transition high. The communication bus will resume activity within 1 ms. 8.3.14.2 SBS Commands See the bq40z50-R1 Technical Reference Manual (SLUUBC1) for further details. 8.4 Device Functional Modes The bq40z50-R1 supports three power modes to reduce power consumption: • In NORMAL mode, the bq40z50-R1 performs measurements, calculations, protection decisions, and data updates in 250-ms intervals. Between these intervals, the bq40z50-R1 is in a reduced power stage. • In SLEEP mode, the bq40z50-R1 performs measurements, calculations, protection decisions, and data updates in adjustable time intervals. Between these intervals, the bq40z50-R1 is in a reduced power stage. The bq40z50-R1 has a wake function that enables exit from SLEEP mode when current flow or failure is detected. • In SHUTDOWN mode, the bq40z50-R1 is completely disabled. 26 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The bq40z50-R1 is a gas gauge with primary protection support, and that can be used with a 1-series to 4-series Li-Ion/Li Polymer battery pack. To implement and design a comprehensive set of parameters for a specific battery pack, users need the Battery Management Studio (bqSTUDIO) graphical user-interface tool installed on a PC during development. The firmware installed on the bqSTUDIO tool has default values for this product, which are summarized in the bq40z50-R1 Technical Reference Manual (SLUUBC1). Using the bqSTUDIO tool, these default values can be changed to cater to specific application requirements during development once the system parameters, such as fault trigger thresholds for protection, enable/disable of certain features for operation, configuration of cells, chemistry that best matches the cell used, and more are known. This data is referred to as the "golden image." Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 27 bq40z50-R1 4P J1 1 2 3 1 1 U2 BQ2947xyDSG VDD CD OUT 8 6 7 5 1 C7 F1 3 2 4P 10M R2 300 R1 FUSEPIN 51K 0.1uF C3 5.1K R16 R6 Q5 Si1406DH SFDxxxx AGND FUSE 0.1uF BAT D1 BAT54HT1 C13 R17 5.1K R7 3 CHG Q2 Si7116DN 5.1K 2.2uF 1 2 3 4 5 6 7 8 PBI VC4 VC3 VC2 VC1 SRN NC SRP C1 0.1uF C2 R9 2 0.1uF Q1 FDN358P R5 10M R8 3 DSG 100 10K RT3 GND 5.1K RT2 10K GND GND GND RT4 10K GND 4 RT5 10K PTCEN PTC DISP SMBD SMBC LEDCNTLA LEDCNTLB LEDCNTLC Q3 Si7116DN R10 5.1K TP12 R3 10M R12 10K 24 21 22 23 20 19 17 18 LED DISPLAY A A' S2 B B' SHUTDOWN A A' S3 Q4 2N7002K 1 10K R4 CHGND BAT C12 RT1 D6 D8 LED4 LED2 D5 D7 0.1uF 2 10K LED5 D9 4P BAT 10K R32 1K R29 SMBD SMBC A A' PACK+ Wake S1 5 4 3 2 1 For Thumbus-SMB CHGND I2C_VOUT R27 100 R26 100 200 GND B B' 200 1 2 R25 D4 200 D3 R24 J7 LED1 LED3 D2 MM3ZxxVyC R28 CHGND 6 7 R11 1 V4 VSS V1 V3 V2 0.1uF C6 BAT 3 C17 0.1uF 1 GND CHGND SMBD 100 C4 0.1uF 2 3 4 GND C15 0.1uF C16 SRN DNP C20 MM3ZxxVyC 5 1 1 2 3 GND 1 R13 1K C5 0.1uF C14 0.1uF 0.1uF GND 0.1uF C18 R31 C21 DNP B B' J6 SMBC 4 SMBD 3 2 PACK+ J2 1 CHGND SMBD GND SIDE VSS SMBC C8 0.1uF C10 0.1uF 2 1 3 2 1 J4 J3 CHGND PACK+ PACK- PACK- Sys Pres PACK+ PACK+ Product Folder Links: bq40z50-R1 R14 1K R15 C9 0.1uF C11 0.1uF R23 R30 4 100 GND SIDE 1 GND SIDE 1K 100 R22 C19 100 GND 1 2 1 2 R18 100 R21 TP3 SRP DNP 0.001 R19 MM3ZxxVyC CHGND 1 1 1K R20 100 100 GND GND 1 1 3P 2P 2 NT1 Net-Tie GND IC ground should be connected to the 1N cell tab. Place RT1 close to Q2 and Q3. Replace D1 and R9 with a 10 ohm resistor for single cell applications SMBC PRESorSHUTDN 1 31 1 1 5 1 1 1 2 3 1 1 3 6 4 3 2 1 FUSE 25 16 1 27 PACK 28 NC 26 VCC BTP_INT 15 30 CHG PCHG 29 NC DSG 14 TS4 13 TS3 12 TS2 11 TS1 10 33 PWPD 32 BAT VSS 9 1P J5 1N 4P AGND 1 3 2 1 1 SMBC SMBD 1 2 1 GND SIDE 2 1 1 1 1 1 EP 9 5 2 1 1 Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 28 www.ti.com SLUSCB3 – JULY 2015 9.2 Typical Applications Figure 21. Application Schematic bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Typical Applications (continued) 9.2.1 Design Requirements Table 1 shows the default settings for the main parameters. Use the bqSTUDIO tool to update the settings to meet the specific application or battery pack configuration requirements. The device should be calibrated before any gauging test. Follow the bqSTUDIO Calibration page to calibrate the device, and use the bqSTUDIO Chemistry page to update the match chemistry profile to the device. Table 1. Design Parameters (1) DESIGN PARAMETER EXAMPLE Cell Configuration 3s1p (3-series with 1 Parallel) (1) Design Capacity 4400 mAh Device Chemistry 1210 (LiCoO2/graphitized carbon) Cell Overvoltage at Standard Temperature 4300 mV Cell Undervoltage 2500 mV Shutdown Voltage 2300 mV Overcurrent in CHARGE Mode 6000 mA Overcurrent in DISCHARGE Mode –6000 mA Short Circuit in CHARGE Mode 0.1 V/Rsense across SRP, SRN Short Circuit in DISCHARGE Mode 0.1 V/Rsense across SRP, SRN Safety Overvoltage 4500 mV Cell Balancing Disabled Internal and External Temperature Sensor External Temperature Sensor is used. Undertemperature Charging 0°C Undertemperature Discharging 0°C BROADCAST Mode Disabled Battery Trip Point (BTP) with active high interrupt Disabled When using the device the first time, if the a 1-s or 2-s battery pack is used, then a charger or power supply should be connected to the PACK+ terminal to prevent device shutdown. Then update the cell configuration (see the bq40z50-R1 Technical Reference Manual [SLUUBC1] for details) before removing the charger connection. 9.2.2 Detailed Design Procedure 9.2.2.1 High-Current Path The high-current path begins at the PACK+ terminal of the battery pack. As charge current travels through the pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the sense resistor, and then returns to the PACK– terminal (see Figure 22). In addition, some components are placed across the PACK+ and PACK– terminals to reduce effects from electrostatic discharge. 9.2.2.1.1 Protection FETs Select the N-channel charge and discharge FETs for a given application. Most portable battery applications are a good match for the CSD17308Q3. The TI CSD17308Q3 is a 47A, 30-V device with Rds(on) of 8.2 mΩ when the gate drive voltage is 8 V. If a precharge FET is used, R1 is calculated to limit the precharge current to the desired rate. Be sure to account for the power dissipation of the series resistor. The precharge current is limited to (VCHARGER – VBAT)/R1 and maximum power dissipation is (Vcharger – Vbat)2/R1. The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source to ensure they are turned off if the gate drive is open. Capacitors C1 and C2 help protect the FETs during an ESD event. Using two devices ensures normal operation if one becomes shorted. To have good ESD protection, the copper trace inductance of the capacitor leads must be designed to be as short and wide as possible. Ensure that the voltage rating of both C1 and C2 are adequate to hold off the applied voltage if one of the capacitors becomes shorted. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 29 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Figure 22. bq40z50-R1 Protection FETs 9.2.2.1.2 Chemical Fuse The chemical fuse (Dexerials, Uchihashi, and so forth) is ignited under command from either the bq294700 secondary voltage protection IC or from the FUSE pin of the gas gauge. Either of these events applies a positive voltage to the gate of Q5, shown in Figure 23, which then sinks current from the third terminal of the fuse, causing it to ignite and open permanently. It is important to carefully review the fuse specifications and match the required ignition current to that available from the N-channel FET. Ensure that the proper voltage, current, and Rds(on) ratings are used for this device. The fuse control circuit is discussed in detail in FUSE Circuitry. 30 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Figure 23. FUSE Circuit 9.2.2.1.3 Lithium-Ion Cell Connections The important part to remember about the cell connections is that high current flows through the top and bottom connections; therefore, the voltage sense leads at these points must be made with a Kelvin connection to avoid any errors due to a drop in the high-current copper trace. The location marked 4P in Figure 24 indicates the Kelvin connection of the most positive battery node. The connection marked 1N is equally important. The VC5 pin (a ground reference for cell voltage measurement), which is in the older generation devices, is not in the bq40z50-R1 device. Therefore, the single-point connection at 1N to the low-current ground is needed to avoid an undesired voltage drop through long traces while the gas gauge is measuring the bottom cell voltage. Figure 24. Lithium-Ion Cell Connections Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 31 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com 9.2.2.1.4 Sense Resistor As with the cell connections, the quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short-circuit ranges of the bq40z50-R1. Select the smallest value possible to minimize the negative voltage generated on the bq40z50-R1 VSS node(s) during a short circuit. This pin has an absolute minimum of –0.3 V. Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a 1mΩ to 3-mΩ sense resistor. The ground scheme of bq40z50-R1 is different from the older generation devices. In previous devices, the device ground (or low current ground) is connected to the SRN side of the Rsense resistor pad. The bq40z50-R1, however, connects the low-current ground on the SRP side of the Rsense resistor pad, close to the battery 1N terminal (see Lithium-Ion Cell Connections). This is because the bq40z50-R1 has one less VC pin (a ground reference pin VC5) compared to the previous devices. The pin was removed and was internally combined to SRP. Figure 25. Sense Resistor 9.2.2.1.5 ESD Mitigation A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– terminals to help in the mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack if one of the capacitors becomes shorted. Optionally, a tranzorb such as the SMBJ2A can be placed across the terminals to further improve ESD immunity. 9.2.2.2 Gas Gauge Circuit The Gas Gauge Circuit includes the bq40z50-R1 and its peripheral components. These components are divided into the following groups: Differential Low-Pass Filter, PBI, System Present, SMBus Communication, FUSE circuit, and LED. 9.2.2.2.1 Coulomb-Counting Interface The bq40z50-R1 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-µF (C18) filter capacitor across the SRP and SRN inputs. Optional 0.1-µF filter capacitors (C19 and C20) can be added for additional noise filtering, if required for your circuit. 32 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Figure 26. Differential Filter 9.2.2.2.2 Power Supply Decoupling and PBI The bq40z50-R1 has an internal LDO that is internally compensated and does not require an external decoupling capacitor. The PBI pin is used as a power supply backup input pin providing power during brief transient power outages. A standard 2.2-µF ceramic capacitor is connected from the PBI pin to ground as shown in Figure 27. Figure 27. Power Supply Decoupling 9.2.2.2.3 System Present The System Present signal is used to inform the gas gauge whether the pack is installed into or removed from the system. In the host system, this pin is grounded. The PRES pin of the bq40z50-R1 is occasionally sampled to test for system present. To save power, an internal pullup is provided by the gas gauge during a brief 4-μs sampling pulse once per second. A resistor can be used to pull the signal low and the resistance must be 20 kΩ or lower to insure that the test pulse is lower than the VIL limit. The pull-up current source is typically 10 µA to 20 µA. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 33 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Figure 28. System Present Pull-Down Resistor Because the System Present signal is part of the pack connector interface to the outside world, it must be protected from external electrostatic discharge events. An integrated ESD protection on the PRES device pin reduces the external protection requirement to just R29 for an 8-kV ESD contact rating. However, if it is possible that the System Present signal may short to PACK+, then R28 and D4 must be included for high-voltage protection. Figure 29. System Present ESD and Short Protection 9.2.2.2.4 SMBus Communication The SMBus clock and data pins have integrated high-voltage ESD protection circuits, however, adding a Zener diode (D2 and D3) and series resistor (R24 and R26) provides more robust ESD performance. 34 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 The SMBus clock and data lines have internal pulldown. When the gas gauge senses that both lines are low (such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP mode to conserve power. Figure 30. ESD Protection for SMB Communication 9.2.2.2.5 FUSE Circuitry The FUSE pin of the bq40z50-R1 is designed to ignite the chemical fuse if one of the various safety criteria is violated. The FUSE pin also monitors the state of the secondary-voltage protection IC. Q5 ignites the chemical fuse when its gate is high. The 7-V output of the bq294700 is divided by R16 and R6, which provides adequate gate drive for Q5 while guarding against excessive back current into the bq294700 if the FUSE signal is high. Using C3 is generally a good practice, especially for RFI immunity. C3 may be removed, if desired, because the chemical fuse is a comparatively slow device and is not affected by any sub-microsecond glitches that come from the FUSE output during the cell connection process. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 35 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Figure 31. FUSE Circuit When the bq40z50-R1 is commanded to ignite the chemical fuse, the FUSE pin activates to give a typical 8-V output. The new design makes it possible to use a higher Vgs FET for Q5. This improves the robustness of the system, as well as widens the choices for Q5. 9.2.2.3 Secondary-Current Protection The bq40z50-R1 provides secondary overcurrent and short-circuit protection, cell balancing, cell voltage multiplexing, and voltage translation. The following discussion examines Cell and Battery Inputs, Pack and FET Control, Temperature Output, and Cell Balancing. 9.2.2.3.1 Cell and Battery Inputs Each cell input is conditioned with a simple RC filter, which provides ESD protection during cell connect and acts to filter unwanted voltage transients. The resistor value allows some trade-off for cell balancing versus safety protection. The integrated cell balancing FETs allow the AFE to bypass cell current around a given cell or numerous cells, effectively balancing the entire battery stack. External series resistors placed between the cell connections and the VCx I/O pins set the balancing current magnitude. The internal FETs provide a 200-Ω resistance (2 V < VDS < 4 V). Series input resistors between 100 Ω and 1 kΩ are recommended for effective cell balancing. The BAT input uses a diode (D1) to isolate and decouple it from the cells in the event of a transient dip in voltage caused by a short-circuit event. Also, as described in High-Current Path, the top and bottom nodes of the cells must be sensed at the battery connections with a Kelvin connection to prevent voltage sensing errors caused by a drop in the high-current PCB copper. 36 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Figure 32. Cell and BAT Inputs 9.2.2.3.2 External Cell Balancing Internal cell balancing can only support up to 10 mA. External cell balancing provide as another option for faster cell balancing. For details, refer to the application note, Fast Cell Balancing Using External MOSFET (SLUA420). 9.2.2.3.3 PACK and FET Control The PACK and VCC inputs provide power to the bq40z50-R1 from the charger. The PACK input also provides a method to measure and detect the presence of a charger. The PACK input uses a 100-Ω resistor; whereas, the VCC input uses a diode to guard against input transients and prevents mis-operation of the date driver during short-circuit events. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 37 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Figure 33. bq40z50-R1 PACK and FET Control The N-channel charge and discharge FETs are controlled with 5.1-kΩ series gate resistors, which provide a switching time constant of a few microseconds. The 10-MΩ resistors ensure that the FETs are off in the event of an open connection to the FET drivers. Q4 is provided to protect the discharge FET (Q3) in the event of a reverse-connected charger. Without Q4, Q3 can be driven into its linear region and suffer severe damage if the PACK+ input becomes slightly negative. Q4 turns on in that case to protect Q3 by shorting its gate to source. To use the simple ground gate circuit, the FET must have a low gate turn-on threshold. If it is desired to use a more standard device, such as the 2N7002 as the reference schematic, the gate should be biased up to 3.3 V with a high-value resistor. The bq40z50-R1 device has the capability to provide a current-limited charging path typically used for low battery voltage or low temperature charging. The bq40z50-R1 device uses an external P-channel, pre-charge FET controlled by PCHG. 9.2.2.3.4 Temperature Output For the bq40z50-R1 device, TS1, TS2, TS3, and TS4 provide thermistor drive-under program control. Each pin can be enabled with an integrated 18-kΩ (typical) linearization pullup resistor to support the use of a 10-kΩ at 25°C (103) NTC external thermistor such as a Mitsubishi BN35-3H103. The reference design includes four 10-kΩ thermistors: RT1, RT2, RT3, and RT4. The bq40z50-R1 device supports up to four external thermistors. Connect unused thermistor pins to VSS. 38 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Figure 34. Thermistor Drive 9.2.2.3.5 LEDs Three LED control outputs provide constant current sinks for the driving external LEDs. These outputs are configured to provide voltage and control for up to 5 LEDs. No external bias voltage is required. Unused LEDCNTL pins can remain open or they can be connected to VSS. The DISP pin should be connected to VSS, if the LED feature is not used. Figure 35. LEDs 9.2.2.3.6 Safety PTC Thermistor The bq40z50-R1 device provides support for a safety PTC thermistor. The PTC thermistor is connected between the PTC pin and VSS. It can be placed close to the CHG/DSG FETs to monitor the temperature. The PTC pin outputs a very small current, typical ~370 nA, and the PTC fault will be triggered at ~0.7 V typical. A PTC fault is one of the permanent failure modes. It can only be cleared by a POR. To disable this feature, connect a 10-kΩ resistor between PTC and VSS. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 39 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Figure 36. PTC Thermistor 40 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 9.2.3 Application Curves 87.4 SCC Protection Threshold (mV) OCD Protection Threshold (mV) ±24.6 ±24.8 ±25.0 ±25.2 ±25.4 ±25.6 87.2 87.0 86.8 86.6 86.4 86.2 ±25.8 ±40 ±20 0 20 40 60 80 100 Temperature (C) 120 ±40 ±20 0 20 40 60 80 100 Temperature (C) C009 Threshold setting is 25 mV. 120 C010 Threshold setting is 25 mV. Figure 37. Overcurrent Discharge Protection Threshold Vs. Temperature Figure 38. Short Circuit Charge Protection Threshold Vs. Temperature SCD 2 Protection Threshold (mV) SCD 1 Protection Threshold (mV) ±86.0 ±86.2 ±86.4 ±86.6 ±86.8 ±87.0 ±172.9 ±173.0 ±173.1 ±173.2 ±173.3 ±173.4 ±173.5 ±173.6 ±87.2 ±40 ±20 0 20 40 60 80 100 Temperature (C) ±40 120 0 20 40 60 80 100 Temperature (C) C011 120 C012 Threshold setting is –177.7 mV. Threshold setting is –88.85 mV. Figure 39. Short Circuit Discharge 1 Protection Threshold Vs. Temperature Figure 40. Short Circuit Discharge 2 Protection Threshold Vs. Temperature 452 SC Charge Current Delay Time (S) 11.00 Over-Current Delay Time (mS) ±20 10.95 10.90 10.85 10.80 10.75 10.70 450 448 446 444 442 440 438 436 434 432 ±40 ±20 0 20 40 60 Temperature (C) 80 100 120 ±40 Threshold setting is 11 ms. ±20 0 20 40 60 80 100 Temperature (C) C013 120 C014 Threshold setting is 465 µs. Figure 41. Overcurrent Delay Time Vs. Temperature Figure 42. Short Circuit Charge Current Delay Time Vs. Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 41 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com 10 Power Supply Recommendations The device manages its supply voltage dynamically according to the operation conditions. Normally, the BAT input is the primary power source to the device. The BAT pin should be connected to the positive termination of the battery stack. The input voltage for the BAT pin ranges from 2.2 V to 26 V. The VCC pin is the secondary power input, which activates when the BAT voltage falls below minimum Vcc. This allows the device to source power from a charger (if present) connected to the PACK pin. The VCC pin should be connected to the common drain of the CHG and DSG FETs. The charger input should be connected to the PACK pin. 42 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 11 Layout 11.1 Layout Guidelines A battery fuel gauge circuit board is a challenging environment due to the fundamental incompatibility of highcurrent traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-totrace coupling is with a component placement, such as that shown in Figure 43, where the high-current section is on the opposite side of the board from the electronic devices. Clearly this is not possible in many situations due to mechanical constraints. Still, every attempt should be made to route high-current traces away from signal traces, which enter the bq40z50-R1 directly. IC references and registers can be disturbed and in rare cases damaged due to magnetic and capacitive coupling from the high-current path. Note that during surge current and ESD events, the high-current traces appear inductive and can couple unwanted noise into sensitive nodes of the gas gauge electronics, as illustrated in Figure 44. Figure 43. Separating High- and Low-Current Sections Provides an Advantage in Noise Immunity Figure 44. Avoid Close Spacing Between High-Current and Low-Level Signal Lines Kelvin voltage sensing is extremely important in order to accurately measure current and top and bottom cell voltages. Place all filter components as close as possible to the device. Route the traces from the sense resistor in parallel to the filter circuit. Adding a ground plane around the filter network can add additional noise immunity. Figure 45 and Figure 46 demonstrates correct kelvin current sensing. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 43 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Layout Guidelines (continued) Current Direction R SNS Current Sensing Direction To SRP – SRN pin or HSRP – HSRN pin Figure 45. Sensing Resistor PCB Layout Figure 46. Sense Resistor, Ground Shield, and Filter Circuit Layout 11.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors The general principle is to use wide copper traces to lower the inductance of the bypass capacitor circuit. In Figure 47, an example layout demonstrates this technique. Figure 47. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3 44 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 Layout Guidelines (continued) 11.1.2 ESD Spark Gap Protect SMBus Clock, Data, and other communication lines from ESD with a spark gap at the connector. The pattern in Figure 48 recommended, with 0.2-mm spacing between the points. Figure 48. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD 11.2 Layout Example THERMISTORS CHARGE AND DISCHARGE PATH 2ND LEVEL PROTECTOR CURRENT FILTER LEDS SENSE RESISTOR Figure 49. Top Layer Figure 50. Internal Layer 1 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 45 bq40z50-R1 SLUSCB3 – JULY 2015 www.ti.com Layout Example (continued) Figure 51. Internal Layer 2 CHARGE AND DISCHARGE PATH FILTER COMPONENTS Figure 52. Bottom Layer 46 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 bq40z50-R1 www.ti.com SLUSCB3 – JULY 2015 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the bq40z50-R1 Technical Reference Manual (SLUUBC1). 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.3 Trademarks Impedance Track, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: bq40z50-R1 47 PACKAGE OPTION ADDENDUM www.ti.com 16-Jul-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) BQ40Z50RSMR-R1 ACTIVE VQFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ40Z50 BQ40Z50RSMT-R1 ACTIVE VQFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ40Z50 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 16-Jul-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ40Z50RSMR-R1 VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ40Z50RSMT-R1 VQFN RSM 32 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ40Z50RSMR-R1 VQFN RSM 32 3000 367.0 367.0 35.0 BQ40Z50RSMT-R1 VQFN RSM 32 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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