Hitachi HD66100D Lcd driver with 80-channel output Datasheet

HD66100F
(LCD Driver with 80-Channel Outputs)
Description
The HD66100F description segment driver with 80 LCD drive circuits is the improved version of the no
longer current HD44100H LCD driver with 40 circuits.
It is composed of a shift register, an 80-bit latch circuit, and 80 LCD drive circuits. Its interface is
compatible with the HD44100H. It reduces the number of LSI’s and lowers the cost of an LCD module.
Features
• LCD driver with serial/parallel converting function
• Interface compatible with the HD44100H; connectable with HD43160AH, HD61830, HD61830B,
LCD-II (HD44780), LCD-III (HD44790)
• Internal output circuits for LCD drive: 80
• Internal serial/parallel converting circuits
 80-bit bidirectional shift register
 80-bit latch circuit
• Power supply
 Internal logic circuit: +5V ±10%
 LCD drive circuit: 3.0V to 6.0V
• CMOS process
109
HD66100F
Comparison with HD44100H
Table 1 shows the main differences between HD66100F and HD44100H.
Table 1
Difference between Products HD66100F and HD44100H
HD66100F
HD44100H
LCD drive outputs
80 × 1 channel
20 × 2 channels
Supply voltage for LCD drive circuits
3 to 6V
4.5 to 11V
Multiplexing duty ratio
Static to 1/16 duty
Static to 1/32 duty
Package
100-pin plastic QFP
60-pin plastic QFP
Ordering Information
Type No.
Package
HD66100F
100-pin plastic QFP (FP-100)
HD66100FH
100-pin plastic QFP (FP-100B)
HD66100D
Chip
110
HD66100F
Pad Coordinate
1 100
TYPE CODE
Chip size (X × Y)
Coordinate
Origin
Pad size (X × Y)
Y
:
:
:
:
4.50mm × 4.50mm
Pad Center
Chip Center
100µm × 100µm
Unit : µ m
30
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
VEE
V1
V2
V3
37 39
Coordinate
X
Y
–1725
2100
–1925
2100
–2100
2060
–2100
1865
–2100
1690
–2100
1520
–2100
1360
–2100
1200
–2100
1040
–2100
880
–2100
720
–2100
560
–2100
400
–2100
240
–2100
80
–2100
–80
–2100
–240
–2100
–400
–2100
–560
–2100
–720
–2100
–880
–2100 –1040
–2100 –1200
–2100 –1360
–2100 –1520
–2100 –1690
–2100 –1865
–2100 –2060
–1925 –2100
–1725 –2100
–1520 –2100
–1360 –2100
–1200 –2100
–1040 –2100
42 44 46 51
Pad
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Coordinate
Function X
Y
V4
–880 –2100
GND
–720 –2100
CL1
–470 –2100
SHL
CL2
DI
DO
–270
–70
130
350
–2100
–2100
–2100
–2100
M
620
–2100
VCC
980
–2100
Y80
Y79
Y78
Y77
Y76
Y75
Y74
Y73
Y72
Y71
Y70
Y69
Y68
Y67
Y66
Y65
Y64
Y63
1725
1925
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
–2100
–2100
–2060
–1865
–1690
–1520
–1360
–1200
–1040
–880
–720
–560
–400
–240
–80
80
240
400
Pad
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Function
Y62
Y61
Y60
Y59
Y58
Y57
Y56
Y55
Y54
Y53
Y52
Y51
Y50
Y49
Y48
Y47
Y46
Y45
Y44
Y43
Y42
Y41
Y40
Y39
Y38
Y37
Y36
Y35
Y34
Y33
Y32
Y31
Coordinate
X
Y
2100
560
2100
720
2100
880
2100 1040
2100 1200
2100 1360
2100 1520
2100 1690
2100 1865
2100 2060
1925 2100
1725 2100
1520 2100
1360 2100
1200 2100
1040 2100
880 2100
720 2100
560 2100
400 2100
240 2100
80 2100
–80 2100
–240 2100
–400 2100
–560 2100
–720 2100
–880 2100
–1040 2100
–1200 2100
–1360 2100
–1520 2100
111
HD66100F
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
HD66100F
(FP-100)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Y51
Y52
Y53
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Y77
Y78
Y79
Y80
VEE
V1
V2
V3
V4
GND
CL1
NC
SHL
CL2
DI
DO
NC
M
NC
VCC
NC
NC
NC
NC
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y40
Y41
Y42
Y43
Y44
Y45
Y46
Y47
Y48
Y49
Y50
Y51
Y52
Y53
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
HD66100FH
(FP-100B)
Y3
Y2
Y1
VEE
V1
V2
V3
V4
GND
CL1
NC
SHL
CL2
DI
DO
NC
M
NC
VCC
NC
NC
NC
NC
Y80
Y79
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Y28
Y27
Y26
Y25
Y24
Y23
Y22
Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y5
Y4
(Top view)
112
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Y54
Y55
Y56
Y57
Y58
Y59
Y60
Y61
Y62
Y63
Y64
Y65
Y66
Y67
Y68
Y69
Y70
Y71
Y72
Y73
Y74
Y75
Y76
Y77
Y78
HD66100F
Pin Description
VCC, GND, VEE: VCC supplies power to the internal logic circuit. GND is the logic and drive ground. VEE
supplies power to the LCD drive circuit.
V1, V2, V3, and V4: V1 to V4 supply power for driving an LCD (Figure 2).
CL1: HD66100F latches data at the negative edge of CL1.
CL2: HD66100F receives shift data at the negative edge of CL2.
M: Changes LCD drive outputs to AC.
DI: Inputs data to the shift register.
DO: Output data from the shift register.
SHL: Selects a shift direction of serial data. When the serial data is input in order of D1, D2, ..., D79,
D80, the relation between the data and the output Y is shown in Table 3.
Y1–Y80: Each Y outputs one of the four voltage levels—V1, V2, V3, or V4—according to the
combination of M and display data (Figure 2).
NC: Do not connect any wire to these terminals.
Table 2
Pin Function
Symbol
Pin No.
Pin Name
I/O
VCC
46
VCC
—
GND
36
Ground
—
VEE
31
VEE
—
V1
32
V1
—
V2
33
V2
—
V3
34
V3
—
V4
35
V4
—
CL1
37
Clock 1
I
CL2
40
Clock 2
I
M
44
M
I
DI
41
Data in
I
DO
42
Data out
O
SHL
39
Shift left
I
Y1–Y80
1–30, 51–100
Y1–Y80
O
NC
38, 43, 45, 47–50
No connection
—
113
HD66100F
Table 3
Relation between SHL and Data Output
SHL
Y1
Y2
Y3.......
Y79
Y80
High
D1
D2
D3.......
D79
D80
Low
D80
D79
D78.....
D2
D1
1
M
1
0
1
0
V1
V3
V2
V4
D
Y output
level
0
When used as a common driver
Figure 1 Selection of LCD Drive Output
V1
V3
V4
V2
V1, V2: Selected level
V3, V4: Non-selected level
Figure 2 Power Supply for Driving an LCD
114
HD66100F
Block Functions
LCD Drive Circuits
Select one of four levels of voltage V1, V2, V3, and V4 for driving a LCD and transfer it to the output
terminals according to the combination of M and the data in the latch circuit.
Latch Circuit
Latches the data input from the bidirectional shift register at the fall of CL1 and transfer its outputs to the
LCD drive circuits.
Bidirectional Shift Register
Shifts the serial data at the fall of CL2 and transfers the output of each bit of the register to the latch
circuit. When SHL = GND, the data input from DI shifts from bit 1 to bit 80 in order of entry. On the
other hand, when SHL = VCC, the data shifts from bit 80 to bit-1. In both cases, the data of the last bit of
the register is latched to be output from DO at the rise of CL2.
SHL = GND
LCD drive outputs
Y1 Y2
Y79 Y80
CL1
1 2
Latch circuit
79 80
CL2
1 2
Shift register
79 80
DI
DO
SHL = VCC
LCD drive outputs
Y1 Y2
Y79 Y80
CL1
1 2
Latch circuit
79 80
CL2
1 2
Shift register
79 80
DI
DO
Figure 3 Relation between SHL and the Shift Direction
115
HD66100F
M
(alternating
signal)
Y1 Y2
LCD drive outputs
Y79 Y80
1 2
LCD drive circuit
79 80
1 2
Level shifter
79 80
V1, V2, V3, V4
(power supply for
LCD drive circuit)
VCC
1 2
Latch circuit
79 80
1 2
Bidirectional shift register
79 80
GND
VEE
Logic circuit
DI
(input data)
Logic circuit
CL1
(latch clock)
SHL
(selects a shift
direction)
CL2
(shift clock)
Figure 4 Block Diagram
116
DO
(output data)
HD66100F
Primary Operations
Shifting Data
The input data DI shifts at the fall of CL2 and the data delayed 80 bits by the shift register is output from
the DO terminal. The output of DO changes synchronously with the rise of CL2. This operation is
completely unaffected by the latch clock CL1.
Latching Data
The data of the shift register is latched at the negative edge of the latch clock CL1. Thus, the outputs Y1–
Y80 change synchronously with the fall of CL1.
Switching Data Shift Direction
When the shift direction switching signal SHL is connected with GND, the data D80, immediately before
the negative edge of CL1, is output from the output terminal Y1. When SHL is connected with VCC, it is
output from Y80.
Shift clock
CL2
Input data
DI
Output data
DO
Figure 5 Timing of Receiving and Outputting Data
Shift clock
CL2
Latch clock CL1
Outputs
Y1–Y80
Figure 6 Timing of Latching Data
117
HD66100F
SHL = GND
Shift clock
CL2
Input data
DI
D1
D2
D79 D80
Latch clock CL1
Outputs
Y1
to
Y80
D80
Y1
to
D1
Y80
D80
D1
SHL = VCC
Outputs
Figure 7 SHL and Waveforms of Data Shift
118
HD66100F
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Note
Logic circuits
VCC
–0.3 to +7.0
V
1
LCD drive circuits
VCC–VEE
–0.3 to +7.0
V
Input voltage (1)
VT1
–0.3 to VCC + 0.3
V
1
Input voltage (2)
VT2
VCC + 0.3 to VEE – 0.3
V
2
Operation temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Supply voltage
Notes: 1. A reference point is GND (= 0V)
2. Applies to V1–V4.
Note: If used beyond the absolute maximum ratings, LSIs may be permanently destroyed. It is best to
use them at the electrical characteristics for normal operations. If they are not used at these
conditions, it may affect the reliability of the device.
119
HD66100F
Electrical Characteristics
DC Characteristics (VCC = 5V ± 10%, VCC – VEE = 3.0 to 6.0V, GND = 0V, Ta = –20 to +75°C)
Item
Symbol Terminals
Input high voltage
VIH
Input low voltage
VIL
Output high voltage VOH
Output low voltage
Typ
Max
Unit
CL1, CL2, 0.8 × VCC
M, DI, SHL 0
—
VCC
V
—
0.2 × VCC
V
DO
VCC – 0.4
—
—
V
IOH = –0.4 mA
—
—
0.4
V
IOL = +0.4 mA
—
—
11
kΩ
ION = 0.1 mA to
one Y terminal
—
—
30
kΩ
ION = 0.05 mA to
each Y terminal
VOL
On resistance Vi–Vj RON1
Y1–Y80
V1–V4
RON2
Min
Test Condition
Input leakage
current
IIL
CL1, CL2, –5.0
M, DI, SHL
—
5.0
µA
Vin = 0V to VCC
Vi leakage current
IVL
V1–V4
–5.0
—
5.0
µA
Output Y1–Y80
open
Vin = VCC to VEE
Current dissipation
IGND
—
—
2.0
mA
IEE
—
—
0.1
mA
fCL2 = 1.0 MHz
fCL1 = 2.5 kHz
Note:
120
1. Input/output currents are excluded; when an input is at the intermediate level in CMOS,
excessive current flows from the power supply through the input circuit.
To avoid this, VIH and VIL must be fixed at VCC and GND level respectively.
Note
1
HD66100F
AC Characteristics (VCC = 5V ± 10%, VCC – VEE = 3.0 to 6.0V, GND = 0V, Ta = –20 to +75°C)
Item
Symbol
Terminals Min
Typ
Max
Unit
Note
Data shift frequency
fCL
CL2
—
—
1
MHz
Clock high level width
tCWH
CL1, CL2
450
—
—
ns
Clock low level width
tCWL
CL2
450
—
—
ns
Data set–up time
fSU
DI
100
—
—
ns
Clock set–up time (1)
tSL
CL2
200
—
—
ns
1
Clock set–up time (2)
tLS
CL1
200
—
—
ns
2
Output delay time
tpd
DO
—
—
250
ns
3
Data hold time
tDH
DI
100
—
—
ns
Clock rise/fall time
fCT
CL1, CL2
—
—
50
ns
Notes: 1. Set-up time from the fall of CL2 to that of CL1.
2. Set-up time from the fall CL1 to that of CL2.
3. Test terminal
CL (Load capacitance on outputs) = 30 pF
(Including jig capacitance)
CL2
VIH
VIL
tct
DI
tct
VIH
VIH
tCWL
tCWH
tSU
tDH
tSL
VIL
tpd
DO
CL1
VOH
VOL
VIH
VIL
tLS
tCWH
tct
tct
Figure 8 Timing Chart of HD66100F
121
HD66100F
Typical Applications
Connection with the LCD Controller HD44780
16
SEG1–
SEG40
D
LCD
80
40
Y1–Y80
DI
Y1–Y80
DI
SHL
HD66100F
CL1
CL2
M
VCC
GND
VEE
V1
V2
V3
V4
SHL
80
DO
DO
VCC
HD66100F
R
CL1
CL2
M
VCC
GND
VEE
V1
V2
V3
V4
COM1–
COM16
R
R
CL1
CL2
M
VCC
V1
V2
HD44780 V3
V4
V5
GND
R
R
Contrast
GND
–V
(Power supply
for LCD dribe)
Figure 9 Example of Connection (1/16 Duty Cycle, 1/5 Bias)
SEG1–
SEG40
D
8
LCD
80
40
DI
80
DO
HD66100F
CL1
CL2
M
VCC
GND
VEE
V1
V2
V3
V4
SHL
Y1–Y80
DI
SHL
Y1–Y80
DO
HD66100F
CL1
CL2
M
VCC
GND
VEE
V1
V2
V3
V4
COM1–
COM8
VCC
R
R
CL1
CL2
M
VCC
V1
V2
HD44780 V3
V4
V5
GND
R
R
Contrast
–V
GND
(Power supply
for LCD drive)
Figure 10 Example of Connection (1/8 Duty Cycle, 1/4 Bias)
122
HD66100F
Connection with LCD III (HD44790)
3
SEG1–
SEG32
R13
LCD
80
32
Y1–Y80
DI
SHL
HD66100F
CL1
CL2
M
VCC
GND
VEE
V1
V2
V3
V4
SHL
80
Y1–Y80
DI
DO
DO
HD66100F
CL1
CL2
M
VCC
GND
VEE
V1
V2
V3
V4
COM1–
COM3
VCC
R
R12
R11
R10
GND
V1
V2
HD44790 VV3
CC
R
R
–V
GND (Power supply
for LCD drive)
Figure 11 Example of Connection (1/3 Duty Cycle, 1/3 Bias)
Static Drive
First
figure
Second
figure
Tenth
figure
COM signal
CMOS
inberter
SEG1–SEG80
80
DI
Y1–Y80
SHL
HD66100F
DO
CL1
CL2
M
VCC
GND
VEE
V1
V2
V3
V4
D
CL1
CL2
M
VCC
GND
Figure 12 Example of Connection (80–Segment Display)
123
HD66100F
Timing Chart of Input Waveforms
1
Shift clock
CL2
Input data
DI
2
3
78
79
80
SEG2
SEG1
......
SEG80 SEG79 SEG78 . . . . . . . . SEG3
Latch clock CL1
Figure 13 Timing Chart of Input Waveforms
Notes: 1. Input square waves of 50% duty cycle (about 30–500 Hz) to M. The frequency depends on the
specifications of LCD panels.
2. The drive waveforms corresponding to the new displayed data are output at the fall of CL1.
Therefore, when the alternating signal M and CL1 do not fall synchronously, DC elements are
produced on the LCD drive waveforms. These DC elements may shorten the life span of the
LCD, if the displayed data frequently changes (e.g. display of hours, minutes, and seconds of a
clock). To avoid this, make CL1 fall synchronously with the one edge of M.
3. In this example, the CMOS inverter is used as a COM signal driver in consideration of the
large display area. (The load capacitance on COM is large because it is common to all the
displayed segments.)
Usually, one of the HD66100F outputs can be used as a COM signal. The displayed data
corresponding to the terminal should be 0 in that case.
COM
LCD
Y2–Y80
Y1
SHL
HD66100F
Figure 14 Example of Connection
124
HD66100F
79
80
CL2
DI
Y3
Data transferred
to Y2–Y80
Y2
0
Data 0 corresponding
to Y1 (COM signal)
CL1
Figure 15 Timing Chart (when Y1 is Used as a COM Signal)
125
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