Altera ET4040QI 40a power stage high speed mosfet with integrated current and temperature sense Datasheet

Enpirion® Power Datasheet
ET4040QI 40A Power Stage
High Speed MOSFET with Integrated
Current and Temperature Sense
Description
Features
The ET4040QI is a 40A, high speed, high density,
monolithic power stage IC with integrated sensing
features in a 5.5mm x 7.5mm x 0.95mm, 46 pin QFN
package. It is targeted for low duty cycle operation,
supplying low voltages for processor, DDR memory,
and GPU core applications. The ET4040QI maintains
very high efficiency at operating frequencies of 1MHz
or greater. The ET4040QI enables 35% higher power
density by utilizing 50-75% less inductance and
significantly less output capacitance than current
generation multi-phase power supply solutions. It
integrates a current sense and temperature
measurement function.
The device has a pin-selectable diode emulation
mode to improve efficiency under PS2 and PS3 low
power modes.
The ET4040QI is designed to interface with multiphase PWM controllers and enables high efficiency
delivery of up to 240 Amps for next generation CPU,
DDR memory, and GPU core memory applications.
All Altera Enpirion products are RoHS compliant,
halogen free and are compatible with lead-free
manufacturing environments.
• 40A continuous Operating Current
• 96.4% Peak Efficiency at 500KHz (3.3V at 12A)
• 3MHz Maximum Operating Frequency
•
•
•
•
•
•
•
•
•
•
•
1.8°C/W Junction-to-Top Thermal Resistance
35% Higher Power Density
No POSCAP or Electrolytic Capacitors Needed
Thermally Enhanced Low Inductance Package
Integrated Gate Drive Independent of Drive Voltage
Integrated Inductor-less Current Sense
Integrated Die Temperature Sense
Tri-state Control Option
Diode Emulation Mode for Light Load Efficiency
Top-side Cooling for Heat-sink Attachment
RoHS Compliant, MSL Level 3, 260oC Reflow
Applications
• High Density Power Stage in Conjunction with
Multi-phase Controllers
• CPU Core, Non-core, Peripheral and DDR Memory
Core Power Supplies
• GPU Core Regulation
• Servers, Desktops, Telecommunications,
Equipment, Industrial and Embedded computing
CONTROLLER
PGND
VCC_GD
1.8V
ET4040 40A
VIN
CIN
ISEN
4.5V – 14V
TSEN/FAULT
OFF#
REFIN
PWM
PWM
INDUCTOR
VOUT
SW
COUT
PGND
PGND
3.3V
VCC
VCC_GND
PHASE
BOOT
Figure 1. Simplified Applications Circuit
Figure 2. Highest Efficiency
www.altera.com/enpirion, Page 1
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March 19, 2014
Rev A
ET4040QI
Ordering Information
Part Number
ET4040QI
ET4040QI-E
Package Markings
ET4040QI
TAMBIENT Rating (°C)
Package Description
-40 to +85
46-pin (5.5mm x 7.5mm x 0.95mm) QFN T&R
Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
VCC
VIN
PGND
PGND
PGND
VCC_GD
VCC_GD
NC
46
44
43
42
41
40
39
38
Pin Assignments (Top View)
NC
1
37
SW
AGND
2
36
SW
35
SW
34
SW
PWM
3
OFF#
4
ISEN
5
33
SW
REFIN
6
32
SW
VCC1
7
31
SW
TSEN
8
30
SW
BGND
9
29
SW
BGND
10
28
SW
VCC2
11
27
SW
NC
12
26
SW
PHASE
13
25
SW
BOOT
14
24
SW
47
VIN
49
SW
48
PGND
15
16
17
18
19
20
21
22
23
VIN
VIN
VIN
PGND
PGND
PGND
VCC_GD
VCC_GD
NC
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. All pins
including NC pins must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: The dotted outlines in the center of the package represent the exposed pads on the bottom of the package for
VIN, PGND, and SW which are required to be soldered to the PCB.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
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ET4040QI
Pin Description
I/O Legend:
PIN
P=Power
G=Ground
NAME
I/O
1,12,
23,38
NC
NC
2
AGND
G
3
PWM
I
4
OFF#
5
ISEN
6
REFIN
7
VCC1
8
TSEN
9, 10
11
BGND
VCC2
13
PHASE
14
BOOT
15-17,
44
18-20,
41-43
21, 22,
39, 40
24-37
46
I
VIN
I
PGND
G
VCC_GD
I
SW
VCC
I
47
VIN
I
48
PGND
G
49
SW
NC=No Connect
I=Input O=Output
I/O=Input/Output
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them to each
other or to any other electrical signal. Failure to follow this guideline may result in device
damage.
Analog ground. This is the ground return for the controller. All AGND pins need to be
connected to a quiet ground.
PWM control signal. Logic LOW = Low-side FET enabled. Logic HIGH = high-side FET
enabled. FLOAT = Tri-state, both LS and HS FETs disabled. See PWM Pin
Characteristics table for additional details.
Low-side OFF signal. Logic LOW = low-side FET disabled. Logic HIGH = normal PWM
operation, LS FET enabled. OFF# is used to turn off the low-side driver during PS2 and
PS3 low-power modes, where diode emulation is used to improve efficiency.
Current Monitor Output. Provides a bandwidth limited (nominally 3.6 MHz) replica of the
current waveform at the SW node. See Current Monitor Characteristics section for more
details. Use 5 kΩ low TC resistor between ISEN and REFIN.
Reference level shift voltage for the ISEN pin. Provided by the controller. See Current
Monitor Characteristics section for more details.
Connect VCC1 to VCC pin.
Temperature monitor output. See Electrical Characteristics table and Functionality and
Features section for description.
Connect to AGND.
Connect VCC2 to VCC pin.
Bottom plate of High-Side FET boot capacitor. Use X5R ceramic on top-side of PCB only
and critically located very close to device pins (PHASE and BOOT).
Top plate of High-Side FET boot capacitor. Use X5R ceramic on top-side of PCB only
and critically located very close to device pins (PHASE and BOOT).
Power input supply for drivers.
Input/output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
1.8V supply for gate drivers.
Driver drain/switch node pins. Connect an external inductor from SW to the output.
3.3V supply for analog control circuits.
Not a perimeter pin. Power input supply for drivers. This VIN is exposed on the package
underside. Tie to VIN plane on EVB with buried vias. High-quality connection to VIN plane
critical for thermal and electrical performance.
Not a perimeter pin. Input/output power ground. This PGND is exposed on package
underside. Tie to PGND plane on EVB with buried VIAs. High-quality connection to
PGND plane critical for thermal and electrical performance.
Not a perimeter pin. Driver drain/switch node. This SW is exposed on package underside.
Tie to SW node/plane on EVB with wide copper on top layer. High-quality connection to
inductor is critical.
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ET4040QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on Power MOSFET Input Supply VIN
VIN
-0.3
16
V
VINSLEW
0.3
10
V/ms
VCC_GD
-0.3
2.1
V
Voltages on logic input supply VCC
VCC
-0.3
5.5
V
Voltages on control pin OFF#,
OFF#
-0.3
5.5
V
-0.3
5.5
V
V
VIN Slew Rate (Note 1)
Voltages on gate drive input supply VCC_GD
Voltages on ISEN, TSEN
Voltages on BOOT
BOOT
-0.3
16
Voltages on PHASE
PHASE
-0.3
2.1
Voltages on REFIN
REFIN
-0.3
5.5
V
Voltages on PWM input signal
PWM
-0.3
5.5
V
Voltages on PGND
PGND
-0.3
0.3
V
Voltages on logic ground AGND
AGND
-0.3
0.3
V
Voltages on switch (common drain) node
SW
-2.0
VIN+0.3
V
Storage Temperature Range
TSTG
-65
150
°C
150
°C
260
°C
Maximum Operating Junction temperature
TJ-ABS Max
Reflow Temperature, 10 sec,
MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CDM)
500
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
VIN
4.5
12
14.5
V
VCC_GD
1.6
1.8
2.0
V
VCC
3.0
3.3
3.6
Supply Voltage to Power MOSFETs
Supply voltage to the MOSFETs gate driver
Supply voltage to logic circuits
Operating junction temperature
0
Continuous load current
+125
ILOAD
40
Operating ambient temperature
-40
+85
V
o
C
A
o
C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Top-side (0 LFM)
θJT
1.8
°C/W
Thermal Resistance: Junction to Bottom-side (0 LFM)
θJB
2.0
°C/W
Note 1: PVIN rising and falling slew rates cannot be outside of specification. For accurate power up sequencing, use a
fast ENABLE logic after both AVIN and PVIN is high.
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ET4040QI
Electrical Characteristics
NOTE: VIN=12V, Minimum and Maximum values are over operating ambient temperature range (-40°C ≤ TA ≤ +85°C)
unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
14.5
V
DEVICE LEVEL CHARACTERISTICS
Operating VIN Voltage
Range
VVIN
4.5
Operating VCC Voltage
Range
VPVCC
3.0
3.3
3.6
V
VPVCC_GD
1.5
1.8
2.0
V
Operating VCC_GD
Voltage Range
VCC Quiescent Current
IQVCC
PWM = Low
1.4
1.8
2.3
mA
VIN Quiescent Current –
No Switching
IQVIN_NS
PWM = Low
2.5
3.3
4.2
mA
VIN Quiescent Current –
Switching
IQVIN
Freq(PWM) = 600 kHz, Duty Cycle =
20%
45
60
75
mA
PWM = Low, VCC_GD = 1.8V
340
450
Freq(PWM) = 600 kHz
VCC_GD = 1.8V
22
30
50
mA
Low-Side Rds_on
1.4
1.6
mΩ
High-Side Rds_on
6.6
8
mΩ
VCC_GD Quiescent
Current – No Switching
VCC_GD Quiescent
Current – Switching
IQVCC_GD_NS
IQVCC_GD
µA
CURRENT MONITORING (ISEN) CHARACTERISTICS
Trans-impedance Gain
ISEN Output Resistor
R_ISEN
ISEN Output Resistor –
Temperature Coefficient
TC_RISEN
ISEN External Parasitic
or LOAD Capacitance
C_ISEN
ISEN – Zero-current DC
Output Voltage
R_ISEN = 5KΩ
5.5
mV/A
External Resistor between ISEN and
REFIN pins. 0.1% tolerance
recommended.
1.5
kΩ
0
mΩ/°C
Use 0TC Resistor
External parasitic capacitance
reduces ISEN replica bandwidth
ILOAD = 0A, REFIN=1.8V,
R_ISEN=5KΩ
Referenced to AGND
ISEN – Maximum Output
Voltage
5
1.785
V
1.8
2.5
ISEN – Output Current
(into REFIN)
REFIN = 1.8V
REFIN must be capable of sinking or
sourcing this current.
REFIN Allowable
Voltage Range
Referenced to AGND
-200
pF
V
0
0.8
200
µA
2.1
V
THERMAL MONITORING (TSEN)
Thermal Gain
7.8
8
8.2
mV/C
0C Output Voltage
Temp = 0C
0.582
0.6
0.618
V
150C Output Voltage
Temp = 150C
1.746
1.8
1.854
V
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March 19, 2014
Rev A
ET4040QI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
Input Capacitance
Output Resistance,
Sourcing
Source Current
Sink Current
MAX
UNITS
10
pF
100
Ω
1
mA
100
µA
Maximum Number of
ORed Phases
Maximum Load
Capacitance
7
Phases
1000
pF
PWM PIN CHARACTERISTICS
Equivalent Input
Resistance
Input Capacitance
kΩ
6
10
pF
330
µA
Input Current
VPWM = VCC = 3.3V
Logic Low Level
VCC = 3.3V, Relative to AGND
-0.3
+0.8
V
Logic High Level
VCC = 3.3V
2.4V
3.6
V
Logic Low Hysteresis
VCC = 3.3V
110
mV
Logic High Hysteresis
VCC = 3.3V
180
mV
Tri-State Thresholds
VCC = 3.3V
Floating Tri-State
Voltage
PWM floated/driven with high
impedance (>10 MΩ)
250
1.2
2
VCC/
2
V
V
Input Rise Time (note 2)
5
ns
Input Fall Time (note 2)
5
ns
Turn-off Propagation
Delay (note 2)
Delay from PWM input HIGH to LOW
to beginning of SW transition
24
ns
Turn-on Propagation
Delay (note 2)
Delay from PWM input LOW to HIGH
to beginning of SW transition
22
ns
Tri-state Hold-Off Time
(note 2)
Delay from Tri-State active level
transition on PWM to beginning of
transition to tri-state on SW
50
ns
Delay - PWM transition high from tristate mode to start of high-side
assertion
22
ns
Delay - PWM transitions to low state
from tri-state mode to start of low-side
assertion
22
ns
Tri-state to Active High SW Rising Propagation
Delay (note 2)
Tri-state to Active Low –
SW Assertion Low
Propagation Delay (note
2)
OFF# PIN CHARACTERISTICS
Logic Low
Relative to AGND
-0.3
0.8
V
Logic High
VCC=3.3V
2.3
VCC +
0.3
V
Hysteresis
800
mV
450
kΩ
Input Capacitance
10
pF
Input Rise Time
5
ns
Input Fall Time
5
ns
Input Resistance
(pull-up to VCC)
Delay – Logic LOW to
150
300
30
ns
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09588
March 19, 2014
Rev A
ET4040QI
PARAMETER
SYMBOL
NFET OFF
Delay – Logic HIGH to
NFET ON
TEST CONDITIONS
MIN
PWM=0
TYP
MAX
30
UNITS
ns
VCC_GD UVLO CHARACTERISTICS
Operating VCC_GD
Voltage Range
VPVCC_GD
1.6
UVLO Falling Threshold
UVLO_FAL
L
0.9
UVLO Rising Threshold
UVLO_RIS
E
2.0
V
1.55
UVLO Hysteresis
V
150
V
mV
Note 2: Parameter not production tested but is guaranteed by design.
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ET4040QI
Typical Performance Curves
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ET4040QI
Functional Block Diagram
VIN
BOOT
PHASE
DT Adjust
Voltage
Level
Shifter
HS
Logic
SW
PWM
PWM
Signal
Clamp
PWM
Logic
Tri-State
Detect
LS
Logic
System
Logic
DT Adjust
VCC
OFF#
PGND
VDDG
UVLO
VCC_GD
Current
Monitor
Circuits
ISEN
TSEN
VCC_GND
Temp
Sensor
Figure 4: Functional Block Diagram
Functional Description
emulation mode for improved efficiency under
light load conditions.
ET4040QI Power Train
The ET4040QI is a monolithic 40A driver stage
that integrates P-Channel high side power
MOSFET, N-Channel low side power MOSFET
and an optimized high speed gate driver. The
device also includes die temperature
monitoring, current sensing, and high side
MOSFET short circuit detection circuitry. The
ET4040QI also has a pin-selectable diode
The ET4040QI utilizes Enpirion’s advanced
high frequency LDMOS process to enable high
switching frequency and high efficiency. The
ET4040QI has industry leading figure of merit
(FOM) providing for very low switching loss
hence enabling high switching frequency for
small external inductor and capacitors.
www.altera.com/enpirion, Page 9
09588
March 19, 2014
Rev A
ET4040QI
Table 1. PWM Logic state table.
Configured properly, the ET4040QI does not
require any bulk electrolytic or POSCAPs.
Only low cost Ceramic MLCC capacitors are
required.
PWM
Low
High
Float
ET4040QIQI Power Train
Pulse Width Modulator (PWM) pin is a Tri-state
input signal. Floating or “tri-stating” this pin will
turn off both high side and low side MOSFETs.
When PWM is placed in tri-state mode, the
PWM signal is internally pulled to 1.6V. This
simplifies the tri-state operation and prevents
indeterminate states from occurring.
High Side
MOSFET
OFF
ON
OFF
Low Side
MOSFET
ON
OFF
OFF
Shoot Through Protection
The ET4040QIQI employs an advanced shoot
through protection scheme. Feedback is used
from each gate to ensure that both MOSFETs
are never on simultaneously.
PWM_HIGH
PWM_TRI
PWM_LOW
PWM
T_PD_OFF_HSG
HSG
T_PD_ON_HSG
T_TRI_HOLDOFF
HSG_T_PD_TRI_RISE
T_TRI_HOLDOFF
LSG
T_PD_OFF_LSG
LSG_T_PD_TRI_RISE
T_PD_ON_LSG
Figure 1. PWM, LSG (Low Side Gate) and HSG (High Side Gate) timing. Note: HSG is active low,
LSG is active high.
ISEN Current Sense Output
The current monitoring function provides a
voltage based replica of the dynamic inductor
current waveform, including both static output
current
and
dynamic
ripple
current
contributions.
The nominal replication
bandwidth is 3.6 MHz – given the nominal
output resistance of 5kΩ, parasitic loading on
this pin should be minimized. The voltage on
ISEN is the sum of the current monitoring
output voltage and the REFIN pin, allowing
ISEN to be summed with REFIN. The ISEN
control and sensing circuits are internally
temperature compensated, allowing the ISEN
indication to correctly track output current even
as internal junction temperature changes due
to self-heating and due to changes in ambient
temperature.
TSEN Temperature Monitor
The ET4040QI provides a thermal monitor that
indicates the internal junction temperature of
the device with a conversion factor of ~8 mV/C
– this indication occurs on the TSEN pin.
Additional specifications relative to TSEN are
provided in the corresponding Electrical
Characteristics section.
The TSEN pin of
multiple devices/phases can be wired-ORed
together, allowing the hottest phase with the
highest temperature to control the temperature
indication. The maximum number of phases
that can be ORed together is seven.
www.altera.com/enpirion, Page 10
09588
March 19, 2014
Rev A
ET4040QI
Application Information
Under Voltage Lock Out
The gate driver supply rail, VCC_GD, is
monitored to ensure a valid supply voltage is
present that allows the gate driver control and
driver circuitry to properly function.
If the
VCC_GD supply drops below UVLO_FALL or
fails to rise above UVLO_RISE, the UVLO
monitor counts 3 PWM pulses or a nominal
maximum persistence of 15 uSec, at which
point switching is disabled at the next
immediate ON cycle.
When the UVLO
condition clears, the driver allows switching to
continue.
An UVLO event is NOT and
indicated fault and therefore does not toggle
the TSEN/FAULT pin or latch into the FAULT
latch
Diode Emulation Mode
The ET4040QI diode emulation mode enables
increased light load efficiency by preventing
negative inductor current from flowing through
the low-side (synchronous) MOSFET. Diode
emulation mode is controlled with the active
low OFF# signal. When the OFF# pin is
asserted low, the low side MOSFET will be
turned off. The high side MOSFET will be
continue to follow the PWM signal commands.
www.altera.com/enpirion, Page 11
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March 19, 2014
Rev A
ET4040QI
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
The Altera Enpirion ET4040QI Power Train is
packaged in an 5.5x7.5mm 46-pin QFN package.
The exposed ground pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability.
The ET4040QI is guaranteed to support the full 40A
output current up to 85°C ambient temperature.
The following example and calculations illustrate
the thermal performance of the ET4040QI.
PIN ≈ 40W / 0.869 ≈ 46W
The power dissipation (PD) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 46W – 40W ≈ 6.0W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JPCB value (θJPCB). The θJPCB parameter
estimates how much the temperature will rise in the
device for every watt of power dissipation. The
ET4040QI Evaluation Board has a θJPCB value of 6
ºC/W without airflow and heatsink (the PCB board
temperature is measured 3cm from the device).
Determine the change in temperature (ΔT) based
on PD and θJPCB.
ΔT = PD x θJPCB
ΔT ≈ 6.0W x 6°C/W = 36°C
The junction temperature (TJ) of the device is
approximately the PCB board temperature (TB) plus
the change in temperature.
Example:
VIN = 12V
VOUT = 1.0V
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the maximum
board temperature (TBMAX) allowed can be
calculated.
IOUT = 40A
First calculate the output power.
POUT = 1.0V x 40A = 40W
Next, determine the input power based on the
efficiency (η) shown in Figure 11.
TBMAX = TJMAX – PD x θJPCB
≈ 125°C – 36°C ≈ 89°C
The maximum board temperature the device can
reach is 89°C given the input and output voltage at
no airflow and no heatsink conditions. Note that
larger size PCB board, heatsink and airflow will
greatly improve the thermal performance.
Figure 11: Efficiency vs. Output Current
For VIN = 12V, VOUT = 1.0V at 40A, η ≈ 86.9%
η = POUT / PIN = 86.9% = 0.869
PIN = POUT / η
www.altera.com/enpirion, Page 12
09588
March 19, 2014
Rev A
ET4040QI
Engineering Schematic
+1.8V
VIN (+4.5V – 14.5V)
+3.3V
10uF
10uF
VCC_GD
1.0uF
NC
AGND
PWM
OFF#
ISEN
REFIN
VCC1
VCC
TSEN
TMON
BGND
BGND
VCC2
NC
VCC
PHASE
BOOT
39
38
40
41
NC
PGND
42
36
3
35
34
49
SW
48
PGND
47
VIN
5
33
6
32
7
31
8
30
9
29
SW
10
28
11
27
12
26
13
25
14
24
NC
PGND
VCC_GD
VIN
1.0uF
VOUT
23
22
20
21
19
18
17
16
VIN
0.1uF
37
2
15
0.1uF
1
4
ISEN
43
46
44
VIN
VCC
1.0uF
PGND
AGND
10uF
10uF
VIN (+4.5V – 14.5V)
+1.8V
Figure12. Pin interconnection diagram.
www.altera.com/enpirion, Page 13
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March 19, 2014
Rev A
ET4040QI
Recommended PCB Footprint
Figure 14: ET4040QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad (shown in blue) is based on Altera’s manufacturing recommendations
www.altera.com/enpirion, Page 14
09588
March 19, 2014
Rev A
ET4040QI
Package and Mechanical
Figure 15: ET4040QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
www.altera.com/enpirion, Page 15
09588
March 19, 2014
Rev A