SLAS504A − JULY 2006 − REVISED DECEMBER 2006 D Low Supply Voltage Range 1.8 V to 3.6 V D Ultralow-Power Consumption D D D D D D D − Active Mode: 270 µA at 1 MHz, 2.2 V − Standby Mode: 0.7 µA − Off Mode (RAM Retention): 0.1 µA Ultrafast Wake-Up From Standby Mode in Less Than 1 µs 16-Bit RISC Architecture, 62.5 ns Instruction Cycle Time Basic Clock Module Configurations: − Internal Frequencies up to 16MHz With Four Calibrated Frequencies to ±1% − Internal Very Low Power LF Oscillator − 32-kHz Crystal − High-Frequency Crystal up to 16 MHz − Resonator − External Digital Clock Source − External resistor 16-Bit Timer_A With Three Capture/Compare Registers 16-Bit Timer_B With Three Capture/Compare Registers Universal Serial Communication Interface − Enhanced UART supporting Auto-Baudrate Detection (LIN) − IrDA Encoder and Decoder − Synchronous SPI − I2Ct 10-Bit, 200-ksps A/D Converter With Internal Reference, Sample-and-Hold, Autoscan, and Data Transfer Controller D Two Configurable Operational Amplifiers D D D D D D (MSP430x22x4 only) Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse Bootstrap Loader On Chip Emulation Module Family Members Include: MSP430F2232: 8KB + 256B Flash Memory 512B RAM MSP430F2252: 16KB + 256B Flash Memory 512B RAM MSP430F2272: 32KB + 256B Flash Memory 1KB RAM MSP430F2234: 8KB + 256B Flash Memory 512B RAM MSP430F2254: 16KB + 256B Flash Memory 512B RAM MSP430F2274: 32KB + 256B Flash Memory 1KB RAM Available in a 38-Pin Plastic Small-Outline Thin (TSSOP) Package and 40-Pin QFN Package For Complete Module Descriptions, Refer to the MSP430x2xx Family User’s Guide description The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs. The MSP430x22xx series is an ultralow-power mixed signal microcontroller with two built-in 16-bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer controller (DTC), two general purpose operational amplifiers in the MSP430x22x4 devices, and 32 I/O pins. Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand alone RF sensor front end is another area of application. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2006 Texas Instruments Incorporated !"# $"%&! '#( '"! ! $#!! $# )# # # "# '' *+( '"! $!#, '# #!#&+ !&"'# #, && $##( POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 AVAILABLE OPTIONS PACKAGED DEVICES PLASTIC 38-PIN TSSOP (DA) PLASTIC 40-PIN QFN (RHA) −40°C to 85°C MSP430F2232IDA MSP430F2252IDA MSP430F2272IDA MSP430F2234IDA MSP430F2254IDA MSP430F2274IDA MSP430F2232IRHA MSP430F2252IRHA MSP430F2272IRHA MSP430F2234IRHA MSP430F2254IRHA MSP430F2274IRHA −40°C to 105°C MSP430F2232TDA† MSP430F2252TDA† MSP430F2272TDA† MSP430F2234TDA MSP430F2254TDA MSP430F2274TDA MSP430F2232TRHA† MSP430F2252TRHA† MSP430F2272TRHA† MSP430F2234TRHA MSP430F2254TRHA MSP430F2274TRHA TA † Product Preview 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 MSP430x22x2 device pinout, DA package TEST/SBWTCK 1 38 P1.7/TA 2/TDO /TDI DVCC 2 37 P1.6/TA 1/TDI P2.5/Rosc 3 36 P1.5/TA 0/TMS DVSS 4 35 P1.4/SMCLK /TCK XOUT /P2.7 5 34 P1.3/TA 2 XIN /P2.6 6 33 P1.2/TA 1 7 32 P1.1/TA 0 P2.0/ACLK /A0 8 31 P1.0/TACLK /ADC 10 CLK P2.1/TAINCLK /SMCLK /A1 9 30 P2.4/TA 2/A4/VREF +/VeREF + RST /NMI /SBWTDIO P2.2/TA 0/A2 10 29 P2.3/TA 1/A3/VREF −/VeREF − P3.0/UCB 0STE /UCA 0CLK /A5 11 28 P3.7/A7 P3.1/UCB 0SIMO /UCB 0SDA 12 27 P3.6/A6 P3.2/UCB 0SOMI /UCB 0SCL 13 26 P3.5/UCA 0RXD /UCA 0SOMI P3.3/UCB 0CLK /UCA 0STE 14 25 P3.4/UCA 0TXD /UCA 0SIMO AVSS 15 24 P4.7/TBCLK AVCC 16 23 P4.6/TBOUTH /A15 P4.0/TB 0 17 22 P4.5/TB 2/A14 P4.1/TB 1 18 21 P4.4/TB 1/A13 P4.2/TB 2 19 20 P4.3/TB 0/A12 MSP430x22x4 device pinout, DA package TEST /SBWTCK 1 38 P1.7/TA 2/TDO /TDI DVCC 2 37 P1.6/TA 1/TDI P2.5/Rosc 3 36 P1.5/TA 0/TMS DVSS 4 35 P1.4/SMCLK /TCK XOUT /P2.7 5 34 P1.3/TA 2 XIN /P2.6 6 33 P1.2/TA 1 RST /NMI /SBWTDIO 7 32 P1.1/TA 0 P2.0/ACLK /A0/OA 0I0 8 31 P1.0/TACLK /ADC 10 CLK P2.1/TAINCLK /SMCLK /A1/OA 0O 9 30 P2.4/TA 2/A4/VREF +/VeREF +/OA 1I0 P2.2/TA 0/A2/OA 0I1 10 29 P2.3/TA 1/A3/VREF −/VeREF −/OA 1I1/OA 1O P3.0/UCB 0STE /UCA 0CLK /A5 11 28 P3.7/A7/OA 1I2 P3.1/UCB 0SIMO /UCB 0SDA 12 27 P3.6/A6/OA 0I2 P3.2/UCB 0SOMI /UCB 0SCL 13 26 P3.5/UCA 0RXD /UCA 0SOMI P3.3/UCB 0CLK /UCA 0STE 14 25 P3.4/UCA 0TXD /UCA 0SIMO AVSS 15 24 P4.7/TBCLK AVCC 16 23 P4.6/TBOUTH /A15 /OA 1I3 P4.0/TB 0 17 22 P4.5/TB 2/A14 /OA 0I3 P4.1/TB 1 18 21 P4.4/TB 1/A13 /OA 1O P4.2/TB 2 19 20 P4.3/TB 0/A12 /OA 0O POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 39 38 37 36 35 34 33 32 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI TEST/SBWTCK DVCC DVCC P2.5/Rosc MSP430x22x2 device pinout, RHA package DVSS 1 XOUT /P2.7 2 29 P1.0/TACLK /ADC 10 CLK XIN /P2.6 3 28 P2.4/TA 2/A4/VREF +/VeREF + DVSS 4 27 P2.3/TA 1/A3/VREF −/VeREF − RST /NMI /SBWTDIO 5 26 P3.7/A7 P2.0/ACLK /A0 6 25 P3.6/A6 P2.1/TAINCLK /SMCLK /A1 7 24 P3.5/UCA 0RXD /UCA 0SOMI P2.2/TA 0/A2 8 23 P3.4/UCA 0TXD /UCA 0SIMO P3.0/UCB 0STE /UCA 0CLK /A5 9 22 P4.7/TBCLK 21 P4.6/TBOUTH /A15 P3.1/UCB 0SIMO /UCB 0SDA 10 30 4 POST OFFICE BOX 655303 P4.5/TB2/A14 P4.4/TB1/A13 P4.3/TB0/A12 P4.2/TB2 P4.1/TB1 P4.0/TB0 AVCC AVSS P3.3/UCB0CLK/UCA0STE P3.2/UCB0SOMI/UCB0SCL 12 13 14 15 16 17 18 19 • DALLAS, TEXAS 75265 P1.1/TA 0 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 39 38 37 36 35 34 33 32 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI/TCLK TEST/SBWTCK P1.7/TA2/TDO/TDI DVCC DVCC P2.5/Rosc MSP430x22x4 device pinout, RHA package DVSS 1 XOUT /P2.7 2 29 P1.0/TACLK /ADC 10 CLK XIN /P2.6 3 28 P2.4/TA 2/A4/VREF +/VeREF +/OA 1I0 30 P1.1/TA 0 DVSS 4 27 P2.3/TA 1/A3/VREF −/VeREF −/OA 1I1/OA 1O RST /NMI /SBWTDIO 5 26 P3.7/A7/OA 1I2 P2.0/ACLK /A0/OA 0I0 6 25 P3.6/A6/OA 0I2 P2.1/TAINCLK /SMCLK /A1/OA 0O 7 24 P3.5/UCA 0RXD /UCA 0SOMI P2.2/TA 0/A2/OA 0I1 8 23 P3.4/UCA 0TXD /UCA 0SIMO P3.0/UCB 0STE /UCA 0CLK /A5 9 22 P4.7/TBCLK 21 P4.6/TBOUTH /A15 /OA 1I3 10 POST OFFICE BOX 655303 P4.5/TB2/A14/OA0I3 P4.4/TB1/A13/OA1O P4.3/TB0/A12/OA0O P4.2/TB2 P4.1/TB1 P4.0/TB0 AVSS AVCC P3.3/UCB0CLK/UCA0STE 12 13 14 15 16 17 18 19 P3.2/UCB0SOMI/UCB0SCL P3.1/UCB 0SIMO /UCB 0SDA • DALLAS, TEXAS 75265 5 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 MSP430x22x2 functional block diagram VCC VSS P1.x/P2.x 2x8 P3.x/P4.x 2x8 XOUT XIN Basic Clock System+ ACLK SMCLK MCLK Flash RAM 32kB 16kB 8kB 1kB 512B 512B ADC10 10−Bit Ports P1/P2 Ports P3/P4 2x8 I/O Interrupt capability, pull−up/down resistors 12 Channels, Autoscan, DTC 2x8 I/O pull−up/down resistors MAB 16MHz CPU incl. 16 Registers MDB Emulation (2BP) Timer_B3 JTAG Interface Watchdog WDT+ Brownout Protection 15/16−Bit Timer_A3 3 CC Registers Spy−Bi Wire 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C RST/NMI NOTE: See port schematics section for detailed I/O information. MSP430x22x4 functional block diagram VCC VSS P1.x/P2.x 2x8 2x8 XOUT XIN Basic Clock System+ ACLK 16MHz CPU incl. 16 Registers Flash RAM 32kB 16kB 8kB 1kB 512B 512B ADC10 10−Bit Ports P1/P2 Ports P3/P4 OA0, OA1 SMCLK MCLK 12 Channels, Autoscan, DTC 2 Op Amps JTAG Interface 2x8 I/O Interrupt capability, pull−up/down resistors 2x8 I/O pull−up/down resistors MAB MDB Emulation (2BP) Timer_B3 Brownout Protection Watchdog WDT+ 15/16−Bit Timer_A3 3 CC Registers Spy−Bi Wire RST/NMI NOTE: See port schematics section for detailed I/O information. 6 P3.x/P4.x POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Terminal Functions, MSP430x22x2 TERMINAL DA RHA NO. NO. P1.0/TACLK/ ADC10CLK 31 29 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ADC10, conversion clock P1.1/TA0 32 30 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit P1.2/TA1 33 31 I/O General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output P1.3/TA2 34 32 I/O General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output P1.4/SMCLK/ TCK 35 33 I/O General-purpose digital I/O pin / SMCLK signal output Test Clock input for device programming and test P1.5/TA0/ TMS 36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output Test Mode Select input for device programming and test P1.6/TA1/ TDI/TCLK 37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output Test Data Input or Test Clock Input for programming and test P1.7/TA2/ TDO/TDI† 38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output Test Data Output or Test Data Input for programming and test P2.0/ACLK/A0 8 6 I/O General-purpose digital I/O pin / ACLK output ADC10, analog input A0 P2.1/TAINCLK/SMCLK/A1 9 7 I/O General-purpose digital I/O pin Timer_A, clock signal at INCLK, SMCLK signal output ADC10, analog input A1 P2.2/TA0/A2 10 8 I/O General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 P2.3/TA1/ A3/VREF−/VeREF− 29 27 I/O General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input P2.4/TA2/ A4/VREF+/VeREF+ 30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output ADC10, analog input A4 / positive reference voltage output/input P2.5/ ROSC 3 40 I/O General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency XIN/P2.6 6 3 I/O Input terminal of crystal oscillator General-purpose digital I/O pin XOUT/P2.7 5 2 I/O Output terminal of crystal oscillator General-purpose digital I/O pin P3.0/ UCB0STE/UCA0CLK/ A5 11 9 I/O General-purpose digital I/O pin USCI_B0 slave transmit enable / USCI_A0 clock input/output ADC10, analog input A5 P3.1/ UCB0SIMO/UCB0SDA 12 10 I/O General-purpose digital I/O pin USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/ UCB0SOMI/UCB0SCL 13 11 I/O General-purpose digital I/O pin USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/ UCB0CLK/UCA0STE 14 12 I/O General-purpose digital I/O pin USCI_B0 clock input/output / USCI_A0 slave transmit enable P3.4/ UCA0TXD/UCA0SIMO 25 23 I/O General-purpose digital I/O pin USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode NAME DESCRIPTION I/O POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Terminal Functions, MSP430x22x2 (Continued) TERMINAL DA RHA NO. NO. P3.5/ UCA0RXD/UCA0SOMI 26 24 I/O General-purpose digital I/O pin USCI_A0 receive data input in UART mode, slave out/master in in SPI mode P3.6/A6 27 25 I/O General-purpose digital I/O pin ADC10 analog input A6 P3.7/A7 28 26 I/O General-purpose digital I/O pin ADC10 analog input A7 P4.0/TB0 17 15 I/O General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output P4.1/TB1 18 16 I/O General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output P4.2/TB2 19 17 I/O General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output P4.3/TB0/ A12 20 18 I/O General-purpose digital I/O pin Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 P4.4/TB1 A13 21 19 I/O General-purpose digital I/O pin Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13 P4.5/TB2 A14 22 20 I/O General-purpose digital I/O pin Timer_B, compare: OUT2 output ADC10 analog input A14 P4.6/TBOUTH A15 23 21 I/O General-purpose digital I/O pin Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 P4.7/TBCLK 24 22 I/O General-purpose digital I/O pin Timer_B, clock signal TBCLK input RST/NMI/SBWTDIO 7 5 I Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test TEST/SBWTCK 1 37 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test DVCC 2 38, 39 Digital supply voltage AVCC DVSS 16 14 Analog supply voltage 4 1, 4 Digital ground reference AVSS QFN Pad 15 13 Analog ground reference NA Package Pad NAME DESCRIPTION I/O NA QFN package pad; connection to DVSS recommended. † TDO or TDI is selected via JTAG instruction. NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Terminal Functions, MSP430x22x4 TERMINAL DA RHA NO. NO. P1.0/TACLK/ ADC10CLK 31 29 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ADC10, conversion clock P1.1/TA0 32 30 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit P1.2/TA1 33 31 I/O General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output P1.3/TA2 34 32 I/O General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output P1.4/SMCLK/ TCK 35 33 I/O General-purpose digital I/O pin / SMCLK signal output Test Clock input for device programming and test P1.5/TA0/ TMS 36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output Test Mode Select input for device programming and test P1.6/TA1/ TDI/TCLK 37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output Test Data Input or Test Clock Input for programming and test P1.7/TA2/ TDO/TDI† 38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output Test Data Output or Test Data Input for programming and test P2.0/ACLK/A0/OA0I0 8 6 I/O General-purpose digital I/O pin / ACLK output ADC10, analog input A0 / OA0, analog input I0 P2.1/TAINCLK/SMCLK/ A1/OA0O 9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK SMCLK signal output ADC10, analog input A1 / OA0, analog output P2.2/TA0/ A2/OA0I1 10 8 I/O General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 / OA0, analog input I1 P2.3/TA1/ A3/VREF−/VeREF− /OA1I1/OA1O 29 27 I/O General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input OA1, analog input I1 / OA1, analog output P2.4/TA2/ A4/VREF+/VeREF+ /OA1I0 30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output ADC10, analog input A4 / positive reference voltage output/input OA1, analog input I0 P2.5/ ROSC 3 40 I/O General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency XIN/P2.6 6 3 I/O Input terminal of crystal oscillator General-purpose digital I/O pin XOUT/P2.7 5 2 I/O Output terminal of crystal oscillator General-purpose digital I/O pin P3.0/ UCB0STE/UCA0CLK/ A5 11 9 I/O General-purpose digital I/O pin USCI_B0 slave transmit enable / USCI_A0 clock input/output ADC10, analog input A5 P3.1/ UCB0SIMO/UCB0SDA 12 10 I/O General-purpose digital I/O pin USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode P3.2/ UCB01SOMI/UCB0SCL 13 11 I/O General-purpose digital I/O pin USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode P3.3/ UCB0CLK/UCA0STE 14 12 I/O General-purpose digital I/O pin USCI_B0 clock input/output / USCI_A0 slave transmit enable P3.4/ UCA0TXD/UCA0SIMO 25 23 I/O General-purpose digital I/O pin USCI_A0 transmit data output in UART mode, slave in/master out in SPI mode NAME DESCRIPTION I/O POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Terminal Functions, MSP430x22x4 (Continued) TERMINAL DA RHA NO. NO. P3.5/ UCA0RXD/UCA0SOMI 26 24 I/O General-purpose digital I/O pin USCI_A0 receive data input in UART mode, slave out/master in in SPI mode P3.6/A6/OA0I2 27 25 I/O General-purpose digital I/O pin ADC10 analog input A6 / OA0 analog input I2 P3.7/A7/OA1I2 28 26 I/O General-purpose digital I/O pin ADC10 analog input A7 / OA1 analog input I2 P4.0/TB0 17 15 I/O General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output P4.1/TB1 18 16 I/O General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output P4.2/TB2 19 17 I/O General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output P4.3/TB0/ A12/OA0O 20 18 I/O General-purpose digital I/O pin Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 / OA0 analog output P4.4/TB1 A13/OA1O 21 19 I/O General-purpose digital I/O pin Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13 / OA1 analog output P4.5/TB2 A14/OA0I3 22 20 I/O General-purpose digital I/O pin Timer_B, compare: OUT2 output ADC10 analog input A14 / OA0 analog input I3 P4.6/TBOUTH A15/OA1I3 23 21 I/O General-purpose digital I/O pin Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 / OA1 analog input I3 P4.7/TBCLK 24 22 I/O General-purpose digital I/O pin Timer_B, clock signal TBCLK input RST/NMI/SBWTDIO 7 5 I Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test TEST/SBWTCK 1 37 I Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST. Spy-Bi-Wire test clock input during programming and test DVCC 2 38, 39 Digital supply voltage AVCC DVSS 16 14 Analog supply voltage 4 1, 4 Digital ground reference AVSS QFN Pad 15 13 Analog ground reference NA Package Pad NAME DESCRIPTION I/O NA QFN package pad connection to DVSS recommended. † TDO or TDI is selected via JTAG instruction. NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 short-form description CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 SR/CG1/R2 Status Register Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. instruction set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats; the address modes are listed in Table 2. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 1. Instruction Word Formats Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 −−−> R5 Single operands, destination only e.g., CALL PC −−> (TOS), R8−−> PC Relative jump, un/conditional e.g., JNE R8 Jump-on-equal bit = 0 Table 2. Address Mode Descriptions ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register F F MOV Rs,Rd MOV R10,R11 Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) Symbolic (PC relative) F F MOV EDE,TONI M(EDE) −−> M(TONI) Absolute F F MOV &MEM,&TCDAT M(MEM) −−> M(TCDAT) R10 −−> R11 M(2+R5)−−> M(6+R6) Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) −−> M(Tab+R6) Indirect autoincrement F MOV @Rn+,Rm MOV @R10+,R11 M(R10) −−> R11 R10 + 2−−> R10 F MOV #X,TONI MOV #45,TONI Immediate NOTE: S = source #45 −−> M(TONI) D = destination POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 operating modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: D Active mode AM; − All clocks are active D Low-power mode 0 (LPM0); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled D Low-power mode 1 (LPM1); − CPU is disabled ACLK and SMCLK remain active. MCLK is disabled DCO’s dc-generator is disabled if DCO not used in active mode D Low-power mode 2 (LPM2); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator remains enabled ACLK remains active D Low-power mode 3 (LPM3); − CPU is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled ACLK remains active D Low-power mode 4 (LPM4); − 12 CPU is disabled ACLK is disabled MCLK and SMCLK are disabled DCO’s dc-generator is disabled Crystal oscillator is stopped POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 interrupt vector addresses The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will go into LPM4 immediately after power-up. INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY Power-up External reset Watchdog Flash key violation PC out-of-range (see Note 1) PORIFG RSTIFG WDTIFG KEYV (see Note 2) Reset 0FFFEh 31, highest NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (see Notes 2 & 4) (non)-maskable, (non)-maskable, (non)-maskable 0FFFCh 30 Timer_B3 TBCCR0 CCIFG (see Note 3) maskable 0FFFAh 29 Timer_B3 TBCCR1 and TBCCR2 CCIFGs, TBIFG (see Notes 2 & 3) maskable 0FFF8h 28 0FFF6h 27 Watchdog Timer WDTIFG maskable 0FFF4h 26 Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25 Timer_A3 TACCR1 CCIFG. TACCR2 CCIFG TAIFG (see Notes 2 & 3) maskable 0FFF0h 24 USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG (see Notes 2) maskable 0FFEEh 23 USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG (see Notes 2) maskable 0FFECh 22 ADC10 ADC10IFG (see Note 3) maskable 0FFEAh 21 0FFE8h 20 I/O Port P2 (eight flags) P2IFG.0 to P2IFG.7 (see Notes 2 & 3) maskable 0FFE6h 19 I/O Port P1 (eight flags) P1IFG.0 to P1IFG.7 (see Notes 2 & 3) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 (see Note 5) 0FFDEh 15 (see Note 6) 0FFDCh ... 0FFC0h 14 ... 0, lowest NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh) or from within unused address ranges. 2. Multiple source flags 3. Interrupt flags are located in the module 4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. 5. This location is used as bootstrap loader security key (BSLSKEY). A 0AA55h at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied. 6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if necessary. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 special function registers Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. interrupt enable 1 and 2 Address 7 6 00h WDTIE 5 4 ACCVIE rw−0 1 0 NMIIE OFIE WDTIE rw−0 rw−0 rw−0 Oscillator fault enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable 7 6 5 01h 14 2 Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. OFIE Address 3 UCA0RXIE USCI_A0 receive-interrupt enable UCA0TXIE USCI_A0 transmit-interrupt enable UCB0RXIE USCI_B0 receive-interrupt enable UCB0TXIE USCI_B0 transmit-interrupt enable POST OFFICE BOX 655303 4 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw−0 rw−0 rw−0 rw−0 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 interrupt flag register 1 and 2 Address 7 6 5 02h WDTIFG 4 3 2 1 0 NMIIFG RSTIFG PORIFG OFIFG WDTIFG rw−0 rw−(0) rw−(1) rw−1 rw−(0) Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode. OFIFG Flag set on oscillator fault RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up PORIFG Power-On interrupt flag. Set on VCC power-up. NMIIFG Set via RST/NMI-pin Address 7 6 5 4 03h UCA0RXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag rw: rw-0,1: rw-(0,1): 2 1 0 UCB0 TXIFG UCB0 RXIFG UCA0 TXIFG UCA0 RXIFG rw−1 rw−0 rw−1 rw−0 USCI_A0 receive-interrupt flag UCA0TXIFG Legend 3 Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR. SFR bit is not present in device POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 memory organization MSP430F223x MSP430F225x MSP430F227x Memory Main: interrupt vector Main: code memory Size Flash Flash 8KB Flash 0FFFFh−0FFC0h 0FFFFh−0E000h 16KB Flash 0FFFFh−0FFC0h 0FFFFh−0C000h 32KB Flash 0FFFFh−0FFC0h 0FFFFh−08000h Information memory Size Flash 256 Byte 010FFh−01000h 256 Byte 010FFh−01000h 256 Byte 010FFh−01000h Boot memory Size ROM 1KB 0FFFh−0C00h 1KB 0FFFh−0C00h 1KB 0FFFh−0C00h Size 512 Byte 03FFh−0200h 512 Byte 03FFh−0200h 1KB 05FFh−0200h 16-bit 8-bit 8-bit SFR 01FFh−0100h 0FFh−010h 0Fh−00h 01FFh−0100h 0FFh−010h 0Fh−00h 01FFh−0100h 0FFh−010h 0Fh−00h RAM Peripherals bootstrap loader (BSL) The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report, Features of the MSP430 Bootstrap Loader, TI literature number SLAA089. BSL Function DA Package Pins RHA Package Pins Data Transmit 32 − P1.1 30 − P1.1 Data Receive 10 − P2.2 8 − P2.2 flash memory The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. D Segments 0 to n may be erased in one step, or each segment may be individually erased. D Segments A to D can be erased individually, or as a group with segments 0−n. Segments A to D are also called information memory. D Segment A contains calibration data. After reset, segment A is protected against programming or erasing. It can be unlocked, but care should be taken not to erase this segment if the calibration data is required. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 peripherals Peripherals are connected to the CPU through data, address, and control busses and can be handled using all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide. oscillator and system clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very low power, low frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals: D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal, or the internal very D D low power LF oscillator. Main clock (MCLK), the system clock used by the CPU. Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. DCO Calibration Data (provided from factory in flash info memory segment A, see Note) DCO Frequency Calibration Register Size 1 MHz CALBC1_1MHZ byte 010FFh CALDCO_1MHZ byte 010FEh 8 MHz 12 MHz 16 MHz Address CALBC1_8MHZ byte 010FDh CALDCO_8MHZ byte 010FCh CALBC1_12MHZ byte 010FBh CALDCO_12MHZ byte 010FAh CALBC1_16MHZ byte 010F9h CALDCO_16MHZ byte 010F8h brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. digital I/O There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4: D D D D D All individual I/O bits are independently programmable. Any combination of input, output, and interrupt conditions is possible. Edge-selectable interrupt input capability for all the eight bits of port P1 and P2. Read/write access to port-control registers is supported by all instructions. Each I/O has an individually programmable pullup/pulldown resistor. WDT+ watchdog timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 timer_A3 Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_A3 Signal Connections Input Pin Number DA RHA 31 - P1.0 29 - P1.0 Device Input Signal Module Input Name TACLK TACLK ACLK ACLK SMCLK SMCLK Timer Module Output Signal Output Pin Number DA RHA NA 9 - P2.1 7 - P2.1 TAINCLK INCLK 32 - P1.1 30 - P1.1 TA0 CCI0A 32 - P1.1 30 - P1.1 10 - P2.2 8 - P2.2 TA0 CCI0B 10 - P2.2 8 - P2.2 36 - P1.5 34 - P1.5 33 - P1.2 31 - P1.2 29 - P2.3 27 - P2.3 37 - P1.6 35 - P1.6 TA2 VCC CCI2A 34 - P1.3 32 - P1.3 ACLK (internal) CCI2B 30 - P2.4 28 - P2.4 38 - P1.7 36 - P1.7 33 - P1.2 31 - P1.2 29 - P2.3 27 - P2.3 34 - P1.3 32 - P1.3 VSS VCC TA1 VCC CCI1A TA1 CCI1B VSS VCC GND VSS VCC 18 Module Block GND GND CCR0 CCR1 CCR2 VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TA0 TA1 TA2 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 timer_B3 Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Timer_B3 Signal Connections Input Pin Number DA RHA 24 - P4.7 22 - P4.7 Device Input Signal Module Input Name TBCLK TBCLK ACLK ACLK SMCLK SMCLK Module Block Timer Module Output Signal Output Pin Number DA RHA NA 24 - P4.7 22 - P4.7 TBCLK INCLK 17 - P4.0 15 - P4.0 TB0 CCI0A 17 - P4.0 15 - P4.0 20 - P4.3 18 - P4.3 TB0 CCI0B 20 - P4.3 18 - P4.3 18 - P4.1 16 - P4.1 21 - P4.4 19 - P4.4 TB2 VCC CCI2A 19 - P4.2 17 - P4.2 ACLK (internal) CCI2B 22 - P4.5 20 - P4.5 18 - P4.1 16 - P4.1 21 - P4.4 19 - P4.4 19 - P4.2 17 - P4.2 VSS VCC TB1 VCC CCI1A TB1 CCI1B VSS VCC GND VSS VCC CCR0 GND CCR1 CCR2 GND TB0 TB1 TB2 VCC USCI The universal serial communication interface (USCI) module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols like UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 ADC10 The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention. operational amplifier OA (MSP430x22x4 only) The MSP430x22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion. OA0 Signal Connections Analog Input Pin Number DA RHA Device Input Signal Module Input Name 8 - A0 6 - A0 OA0I0 OAxI0 10 - A2 8 - A2 OA0I1 OA0I1 10 - A2 8 - A2 OA0I1 OAxI1 27 - A6 25 - A6 OA0I2 OAxIA 22 - A14 20 - A14 OA0I3 OAxIB OA1 Signal Connections Analog Input Pin Number 20 Device Input Signal Module Input Name DA RHA 30 - A4 28 - A4 OA1I0 OAxI0 10 - A2 8 - A2 OA0I1 OA0I1 29 - A3 27 - A3 OA1I1 OAxI1 28 - A7 26 - A7 OA1I2 OAxIA 23 - A15 21 - A15 OA1I3 OAxIB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 peripheral file map PERIPHERALS WITH WORD ACCESS ADC10 ADC data transfer start address ADC memory ADC control register 1 ADC control register 0 ADC analog enable 0 ADC analog enable 1 ADC data transfer control register 1 ADC data transfer control register 0 ADC10SA ADC10MEM ADC10CTL1 ADC10CTL0 ADC10AE0 ADC10AE1 ADC10DTC1 ADC10DTC0 1BCh 1B4h 1B2h 1B0h 04Ah 04Bh 049h 048h Timer_B Capture/compare register Capture/compare register Capture/compare register Timer_B register Capture/compare control Capture/compare control Capture/compare control Timer_B control Timer_B interrupt vector TBCCR2 TBCCR1 TBCCR0 TBR TBCCTL2 TBCCTL1 TBCCTL0 TBCTL TBIV 0196h 0194h 0192h 0190h 0186h 0184h 0182h 0180h 011Eh Timer_A Capture/compare register Capture/compare register Capture/compare register Timer_A register Capture/compare control Capture/compare control Capture/compare control Timer_A control Timer_A interrupt vector TACCR2 TACCR1 TACCR0 TAR TACCTL2 TACCTL1 TACCTL0 TACTL TAIV 0176h 0174h 0172h 0170h 0166h 0164h 0162h 0160h 012Eh Flash Memory Flash control 3 Flash control 2 Flash control 1 FCTL3 FCTL2 FCTL1 012Ch 012Ah 0128h Watchdog Timer+ Watchdog/timer control WDTCTL 0120h OA1 (MSP430x22x4 only) Operational Amplifier 1 control register 1 Operational Amplifier 1 control register 1 OA1CTL1 OA1CTL0 0C3h 0C2h OA0 (MSP430x22x4 only) Operational Amplifier 0 control register 1 Operational Amplifier 0 control register 1 OA0CTL1 OA0CTL0 0C1h 0C0h USCI_B0 USCI_B0 transmit buffer USCI_B0 receive buffer USCI_B0 status USCI_B0 bit rate control 1 USCI_B0 bit rate control 0 USCI_B0 control 1 USCI_B0 control 0 USCI_B0 I2C slave address USCI_B0 I2C own address UCB0TXBUF UCB0RXBUF UCB0STAT UCB0BR1 UCB0BR0 UCB0CTL1 UCB0CTL0 UCB0SA UCB0OA 06Fh 06Eh 06Dh 06Bh 06Ah 069h 068h 011Ah 0118h USCI_A0 USCI_A0 transmit buffer USCI_A0 receive buffer USCI_A0 status USCI_A0 modulation control USCI_A0 baud rate control 1 USCI_A0 baud rate control 0 USCI_A0 control 1 USCI_A0 control 0 USCI_A0 IrDA receive control USCI_A0 IrDA transmit control USCI_A0 auto baud rate control UCA0TXBUF UCA0RXBUF UCA0STAT UCA0MCTL UCA0BR1 UCA0BR0 UCA0CTL1 UCA0CTL0 UCA0IRRCTL UCA0IRTCTL UCA0ABCTL 067h 066h 065h 064h 063h 062h 061h 060h 05Fh 05Eh 05Dh PERIPHERALS WITH BYTE ACCESS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 PERIPHERALS WITH BYTE ACCESS (continued) 22 Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL 053h 058h 057h 056h Port P4 Port P4 resistor enable Port P4 selection Port P4 direction Port P4 output Port P4 input P4REN P4SEL P4DIR P4OUT P4IN 011h 01Fh 01Eh 01Dh 01Ch Port P3 Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input P3REN P3SEL P3DIR P3OUT P3IN 010h 01Bh 01Ah 019h 018h Port P2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 027h 026h 025h 024h 023h 022h 021h 020h Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 IFG2 IFG1 IE2 IE1 003h 002h 001h 000h POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 absolute maximum ratings (see Note 1) Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA Storage temperature, Tstg (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C Storage temperature, Tstg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. 3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. recommended operating conditions MIN NOM MAX UNIT Supply voltage during program execution, VCC 1.8 3.6 V Supply voltage during program/erase flash memory, VCC 2.2 3.6 V Supply voltage, VSS 0 Operating free-air temperature range, TA Processor frequency fSYSTEM (Maximum MCLK frequency) (see Notes 1, 2 and Figure 1) V I Version −40 85 °C T Version −40 105 °C VCC = 1.8 V, Duty Cycle = 50% ±10% dc 4.15 VCC = 2.7 V, Duty Cycle = 50% ±10% dc 12 VCC ≥ 3.3 V, Duty Cycle = 50% ±10% dc 16 MHz NOTES: 1. The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. 2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this data sheet. System Frequency −MHz 16 MHz 12 MHz 7.5 MHz 4.15 MHz 1.8 V ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏ 2.2 V 2.7 V 3.3 V ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ Legend: Supply voltage range, during flash memory programming Supply voltage range, during program execution 3.6 V Supply Voltage −V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Operating Area POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) active mode supply current (into DVCC + AVCC) excluding external current (see Notes 1 and 2) PARAMETER IAM, 1MHz IAM, 1MHz IAM, 4kHz IAM,100kHz Active mode (AM) current (1MHz) Active mode (AM) current (1MHz) Active mode (AM) current (4kHz) Active mode (AM) current (100kHz) TEST CONDITIONS TA fDCO = fMCLK = fSMCLK = 1MHz, fACLK = 32,768Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 VCC 2.2 V MIN TYP MAX 270 390 µA fDCO = fMCLK = fSMCLK = 1MHz, fACLK = 32,768Hz, Program executes in RAM, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 3V 390 2.2 V 240 3V fMCLK = fSMCLK = fACLK = 32,768Hz/8 = 4,096Hz, fDCO = 0Hz, Program executes in flash, SELMx = 11, SELS = 1, DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0 -40−85°C 2.2 V 105°C 2.2 V -40−85°C 3V 105°C 3V fMCLK = fSMCLK = fDCO(0, 0) ≈ 100kHz, DCO(0,0) fACLK = 0Hz, Program executes in flash, RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1 -40−85°C 2.2 V 105°C 2.2 V -40−85°C 3V 105°C 3V POST OFFICE BOX 655303 550 µA 340 5 9 18 µA 6 • DALLAS, TEXAS 75265 10 20 60 85 95 72 NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. 2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9pF. 24 UNIT 95 105 µA SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − active mode supply current (into DVCC + AVCC) 5.0 8.0 fDCO = 16 MHz 6.0 fDCO = 12 MHz 5.0 4.0 fDCO = 8 MHz 3.0 2.0 TA = 85 °C Active Mode Current − mA Active Mode Current − mA 7.0 4.0 TA = 25 °C 3.0 VCC = 3 V TA = 85 °C 2.0 TA = 25 °C 1.0 1.0 0.0 1.5 VCC = 2.2 V fDCO = 1 MHz 2.0 2.5 3.0 3.5 4.0 0.0 0.0 VCC − Supply Voltage − V Figure 2. Active mode current vs VCC, TA = 25°C POST OFFICE BOX 655303 4.0 8.0 12.0 16.0 fDCO − DCO Frequency − MHz Figure 3. Active mode current vs DCO frequency • DALLAS, TEXAS 75265 25 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) low power mode supply currents (into DVCC + AVCC) excluding external current (see Notes 1 and 2) PARAMETER ILPM0, 1MHz Low-power mode 0 (LPM0) current, see Note 3 Low-power mode ILPM0,100kHz 0 (LPM0) current, see Note 3 ILPM2 Low-power mode 2 (LPM2) current, see Note 4 TEST CONDITIONS TA fMCLK = 0MHz, fSMCLK = fDCO = 1MHz, fACLK = 32,768Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 2.2 V ILPM3,VLO ILPM4 fDCO = fMCLK = fSMCLK = 0MHz, fACLK = 0Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 2.2 V 37 48 41 65 22 29 105°C 35 -40−85°C 25 32 0.7 1.4 0.7 1.4 2.8 4.5 105°C 6 18 -40°C 0.9 1.5 25°C 0.9 1.5 3.0 5.0 POST OFFICE BOX 655303 µA 3V 105°C 40 85°C 2.2 V 3V 105°C 6.5 19 -40°C 0.4 1.0 0.5 1.0 2.2 4.2 105°C 5.7 16.5 -40°C 0.5 1.2 25°C 0.6 1.2 2.5 4.5 85°C 2.2 V 3V 105°C 6.0 17 -40°C 0.1 0.5 0.1 0.5 1.9 4.0 5.5 16 25°C 85°C 105°C 2.2 V/3 V NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. 2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9pF. 3. Current for brownout and WDT clocked by SMCLK included. 4. Current for brownout and WDT clocked by ACLK included. 5. Current for brownout included. 26 UNIT 2.2 V 85°C Low-power mode 4 (LPM4) current, see Note 5 90 120 -40−85°C 25°C fDCO = fMCLK = fSMCLK = 0MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 75 90 3V 85°C Low-power mode 3 current, (LPM3) see Note 4 MAX µA 25°C fDCO = fMCLK = fSMCLK = 0MHz, fACLK = 32,768Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 TYP 3V -40°C Low-power mode 3 (LPM3) current, ILPM3,LFXT1 see Note 4 MIN µA fMCLK = 0MHz, fSMCLK = fDCO(0, 0) ≈ 100kHz, fACLK = 0Hz, RSELx = 0, DCOx = 0, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1 fMCLK = fSMCLK = 0MHz, fDCO = 1MHz, fACLK = 32,768Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 VCC • DALLAS, TEXAS 75265 µA µA µA µA A µA SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Schmitt-trigger inputs − Ports P1, P2, P3, P4, and RST/NMI PARAMETER VIT+ VIT− TEST CONDITIONS Positive-going input threshold voltage Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ − VIT−) RPull Pullup/pulldown resistor For pullup: VIN = VSS; For pulldown: VIN = VCC CI Input Capacitance VIN = VSS or VCC VCC MIN MAX UNIT 0.45 0.75 VCC 2.2 V 1.00 1.65 3V 1.35 2.25 0.25 0.55 2.2 V 0.55 1.20 3V 0.75 1.65 2.2 V 0.2 1.0 3V 0.3 1.0 20 TYP 35 50 5 V VCC V V kW pF inputs − Ports P1 and P2 PARAMETER t(int) TEST CONDITIONS Port P1, P2: P1.x to P2.x, External trigger puls width to set interrupt flag, (see Note 1) External interrupt timing VCC 2.2 V/3 V MIN TYP MAX 20 UNIT ns NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals shorter than t(int). leakage current − Ports P1, P2, P3 and P4 PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Ilkg(Px.x) High-impedance leakage current see Notes 1 and 2 2.2 V/3 V ±50 nA NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. 2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs − Ports P1, P2, P3 and P4 PARAMETER VOH VOL High-level output voltage Low-level output voltage VCC MIN I(OHmax) = −1.5 mA (see Notes 1) I(OHmax) = −6 mA (see Notes 2) TEST CONDITIONS 2.2 V VCC−0.25 VCC−0.6 VCC VCC I(OHmax) = −1.5 mA (see Notes 1) I(OHmax) = −6 mA (see Notes 2) 3V VCC−0.25 VCC−0.6 VCC VCC 2.2 V 3V TYP MAX UNIT I(OLmax) = 1.5 mA (see Notes 1) I(OLmax) = 6 mA (see Notes 2) 2.2 V 2.2 V VSS VSS VSS+0.25 VSS+0.6 I(OLmax) = 1.5 mA (see Notes 1) 3V VSS VSS+0.25 V V I(OLmax) = 6 mA (see Notes 2) 3V VSS VSS+0.6 NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage drop specified. 2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified. output frequency − Ports P1, P2, P3 and P4 PARAMETER fPx.y fPort_CLK Port output frequency (with load) Clock output frequency TEST CONDITIONS VCC MAX UNIT 2.2 V 10 MHz 3V 12 MHz 2.2 V 12 MHz 16 MHz P1.4/SMCLK, CL = 20 pF, RL = 1 kW against VCC/2 (see Note 1 and 2) P2.0/ACLK, P1.4/SMCLK, CL = 20 pF (see Note 2) 3V MIN TYP NOTES: 1. Alternatively a resistive divider with 2 times 2 kW between VCC and VSS is used as load. The output is connected to the center tap of the divider. 2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − outputs TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50.0 I OL − Typical Low-Level Output Current − mA I OL − Typical Low-Level Output Current − mA 25.0 TA = 25°C VCC = 2.2 V P4.5 20.0 TA = 85°C 15.0 10.0 5.0 0.0 0.0 0.5 1.0 1.5 2.0 VCC = 3 V P4.5 40.0 TA = 85°C 30.0 20.0 10.0 0.0 0.0 2.5 0.5 VOL − Low-Level Output Voltage − V 1.0 3.0 3.5 0.0 VCC = 2.2 V P4.5 I OH − Typical High-Level Output Current − mA I OH − Typical High-Level Output Current − mA 2.5 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0.0 −5.0 −10.0 −15.0 TA = 85°C TA = 25°C 0.5 2.0 Figure 5 TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE −25.0 0.0 1.5 VOL − Low-Level Output Voltage − V Figure 4 −20.0 TA = 25°C 1.0 1.5 2.0 2.5 VOH − High-Level Output Voltage − V VCC = 3 V P4.5 −10.0 −20.0 −30.0 −40.0 −50.0 0.0 TA = 85°C TA = 25°C 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOH − High-Level Output Voltage − V Figure 7 Figure 6 NOTE: One output loaded at a time. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) POR/brownout reset (BOR) (see Notes 1 and 2) PARAMETER TEST CONDITIONS VCC(start) (see Figure 8) dVCC/dt ≤ 3 V/s V(B_IT−) Vhys(B_IT−) (see Figure 8 through Figure 10) dVCC/dt ≤ 3 V/s dVCC/dt ≤ 3 V/s td(BOR) (see Figure 8) t(reset) Pulse length needed at RST/NMI pin to accepted reset internally (see Figure 8) VCC MIN TYP MAX 0.7 × V(B_IT−) 70 2.2 V/3 V 2 130 UNIT V 1.71 V 210 mV 2000 µs µs NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−) + Vhys(B_IT−) is ≤ 1.8V. 2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. VCC Vhys(B_IT−) V(B_IT−) VCC(start) 1 0 t d(BOR) Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage 30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − POR/brownout reset (BOR) VCC 3V 2 VCC(drop) − V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns tpw − Pulse Width − µs 1 ns tpw − Pulse Width − µs Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC VCC(drop) − V 2 1.5 t pw 3V VCC = 3 V Typical Conditions 1 VCC(drop) 0.5 0 0.001 tf = tr 1 1000 tf tr tpw − Pulse Width − µs tpw − Pulse Width − µs Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main DCO characteristics D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. D DCO control bits DCOx have a step size as defined by parameter SDCO. D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: f average + MOD 32 f DCO(RSEL,DCO) f DCO(RSEL,DCO)1) f DCO(RSEL,DCO))(32*MOD) f DCO(RSEL,DCO)1) DCO frequency PARAMETER Vcc Supply voltage range TEST CONDITIONS VCC MIN TYP MAX UNIT RSELx < 14 1.8 3.6 V RSELx = 14 2.2 3.6 V RSELx = 15 3.0 3.6 V fDCO(0,0) fDCO(0,3) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 2.2 V/3 V 0.06 0.14 MHz DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 2.2 V/3 V 0.07 0.17 MHz fDCO(1,3) fDCO(2,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 2.2 V/3 V 0.10 0.20 MHz DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 2.2 V/3 V 0.14 0.28 MHz fDCO(3,3) fDCO(4,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 2.2 V/3 V 0.20 0.40 MHz DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 2.2 V/3 V 0.28 0.54 MHz fDCO(5,3) fDCO(6,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 2.2 V/3 V 0.39 0.77 MHz DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 2.2 V/3 V 0.54 1.06 MHz fDCO(7,3) fDCO(8,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 2.2 V/3 V 0.80 1.50 MHz DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 2.2 V/3 V 1.10 2.10 MHz fDCO(9,3) fDCO(10,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 2.2 V/3 V 1.60 3.00 MHz DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 2.2 V/3 V 2.50 4.30 MHz fDCO(11,3) fDCO(12,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 2.2 V/3 V 3.00 5.50 MHz DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 2.2 V/3 V 4.30 7.30 MHz fDCO(13,3) fDCO(14,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 2.2 V/3 V 6.00 9.60 MHz DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 2.2 V/3 V 8.60 13.9 MHz fDCO(15,3) fDCO(15,7) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 12.0 18.5 MHz DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 16.0 26.0 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL f = /fDCO(RSEL,DCO) DCO(RSEL+1,DCO) 2.2 V/3 V SDCO Frequency step between tap DCO and DCO+1 SDCO f= /fDCO(RSEL,DCO) DCO(RSEL,DCO+1) 2.2 V/3 V 1.05 1.08 1.12 Measured at P1.4/SMCLK 2.2 V/3 V 40 50 60 Duty Cycle 32 1.55 ratio POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 % SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies − tolerance at calibration PARAMETER TEST CONDITIONS Frequency tolerance at calibration TA 25°C VCC MIN TYP MAX UNIT 3V −1 ±0.2 +1 25°C 3V 0.990 1 1.010 MHz % fCAL(1MHz) 1MHz calibration value BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ Gating time: 5ms fCAL(8MHz) 8MHz calibration value BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ Gating time: 5ms 25°C 3V 7.920 8 8.080 MHz fCAL(12MHz) 12MHz calibration value BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ Gating time: 5ms 25°C 3V 11.88 12 12.12 MHz fCAL(16MHz) 16MHz calibration value BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ Gating time: 2ms 25°C 3V 15.84 16 16.16 MHz VCC MIN MAX UNIT calibrated DCO frequencies − tolerance over temperature 0°C to +85°C PARAMETER 1 MHz tolerance over temperature TA 0−85°C 3.0 V −2.5 ±0.5 +2.5 % 8 MHz tolerance over temperature 0−85°C 3.0 V −2.5 ±1.0 +2.5 % 12 MHz tolerance over temperature 0−85°C 3.0 V −2.5 ±1.0 +2.5 % 16 MHz tolerance over temperature 0−85°C 3.0 V −3.0 ±2.0 +3.0 % 2.2 V 0.970 1 1.030 MHz 3.0 V 0.975 1 1.025 MHz 3.6 V 0.970 1 1.030 MHz 2.2 V 7.760 8 8.400 MHz 3.0 V 7.800 8 8.200 MHz 3.6 V 7.600 8 8.240 MHz 2.2 V 11.70 12 12.30 MHz 3.0 V 11.70 12 12.30 MHz 3.6 V 11.70 12 12.30 MHz 3.0 V 15.52 16 16.48 MHz 3.6 V 15.00 16 16.48 MHz fCAL(1MHz) fCAL(8MHz) fCAL(12MHz) fCAL(16MHz) 1MHz calibration value 8MHz calibration value 12MHz calibration value 16MHz calibration value TEST CONDITIONS BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ Gating time: 5ms BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ Gating time: 5ms 0−85°C 0−85 C 0−85°C 0−85 C BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ Gating time: 5ms 0−85°C 0−85 C BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ Gating time: 2ms 0−85°C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 33 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) calibrated DCO frequencies − tolerance over supply voltage VCC PARAMETER TEST CONDITIONS 1 MHz tolerance over VCC TA 25°C VCC MIN TYP MAX UNIT 1.8 V − 3.6 V −3 ±2 +3 % 8 MHz tolerance over VCC 25°C 1.8 V − 3.6 V −3 ±2 +3 % 12 MHz tolerance over VCC 25°C 2.2 V − 3.6 V −3 ±2 +3 % 16 MHz tolerance over VCC 25°C 3.0 V − 3.6 V −6 ±2 +3 % 25°C 1.8 V − 3.6 V 0.970 1 1.030 MHz fCAL(1MHz) 1MHz calibration value BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ Gating time: 5ms fCAL(8MHz) 8MHz calibration value BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ Gating time: 5ms 25°C 1.8 V − 3.6 V 7.760 8 8.240 MHz fCAL(12MHz) 12MHz calibration value BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ Gating time: 5ms 25°C 2.2 V − 3.6 V 11.64 12 12.36 MHz fCAL(16MHz) 16MHz calibration value BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ Gating time: 2ms 25°C 3.0 V − 3.6 V 15.00 16 16.48 MHz TA I: -40−85°C T: -40−105°C VCC MIN MAX UNIT calibrated DCO frequencies − overall tolerance PARAMETER TEST CONDITIONS 1 MHz tolerance overall TYP 1.8 V − 3.6 V −5 ±2 +5 % 8 MHz tolerance overall I: -40−85°C T: -40−105°C 1.8 V − 3.6 V −5 ±2 +5 % 12 MHz tolerance overall I: -40−85°C T: -40−105°C 2.2 V − 3.6 V −5 ±2 +5 % 16 MHz tolerance overall I: -40−85°C T: -40−105°C 3.0 V − 3.6 V −6 ±3 +6 % fCAL(1MHz) 1MHz calibration value BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ Gating time: 5ms I: -40−85°C T: -40−105°C 1.8 V − 3.6 V 0.950 1 1.050 MHz fCAL(8MHz) 8MHz calibration value BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ Gating time: 5ms I: -40−85°C T: -40−105°C 1.8 V − 3.6 V 7.600 8 8.400 MHz fCAL(12MHz) 12MHz calibration value BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ Gating time: 5ms I: -40−85°C T: -40−105°C 2.2 V − 3.6 V 11.40 12 12.60 MHz fCAL(16MHz) 16MHz calibration value BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ Gating time: 2ms I: -40−85°C T: -40−105°C 3.0 V − 3.6 V 15.00 16 17.00 MHz 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 typical characteristics − calibrated 1MHz DCO frequency 1.03 1.02 VCC = 1.8 V Frequency − MHz 1.01 VCC = 2.2 V 1.00 VCC = 3.0 V 0.99 VCC = 3.6 V 0.98 0.97 −50.0 −25.0 0.0 25.0 50.0 75.0 100.0 TA − Temperature − °C Figure 11. Calibrated 1 MHz Frequency vs. Temperature 1.03 Frequency − MHz 1.02 1.01 TA = 105 °C 1.00 TA = 85 °C TA = 25 °C 0.99 TA = −40 °C 0.98 0.97 1.5 2.0 2.5 3.0 3.5 4.0 VCC − Supply Voltage − V Figure 12. Calibrated 1 MHz Frequency vs. VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) wake-up from lower power modes (LPM3/4) PARAMETER TEST CONDITIONS DCO clock wake-up time from tDCO,LPM3/4 LPM3/4 (see Note 1) VCC MIN TYP MAX BCSCTL1= CALBC1_1MHZ DCOCTL = CALDCO_1MHZ 2.2 V/3 V 2 BCSCTL1= CALBC1_8MHZ DCOCTL = CALDCO_8MHZ 2.2 V/3 V 1.5 BCSCTL1= CALBC1_12MHZ DCOCTL = CALDCO_12MHZ 2.2 V/3 V 1 BCSCTL1= CALBC1_16MHZ DCOCTL = CALDCO_16MHZ 3V 1 UNIT µss 1/fMCLK + tClock,LPM3/4 NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). 2. Parameter applicable only if DCOCLK is used for MCLK. tCPU,LPM3/4 CPU wake-up time from LPM3/4 (see Note 2) typical characteristics − DCO clock wake-up time from LPM3/4 DCO Wake Time − us 10.00 RSELx = 0...11 RSELx = 12...15 1.00 0.10 0.10 1.00 10.00 DCO Frequency − MHz Figure 13. Clock wake-up time from LPM3 vs DCO frequency 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) DCO with external resistor ROSC (see Note 1) PARAMETER TEST CONDITIONS fDCO,ROSC DCO output frequency with ROSC Dt Temperature drift DV Drift with VCC VCC DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0, TA = 25°C DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 MIN TYP MAX UNIT 2.2 V 1.8 3V 1.95 2.2 V/3 V ±0.1 %/°C 2.2 V/3 V 10 %/V MHz DCOR = 1, RSELx = 4, DCOx = 3, MODx = 0 NOTES: 1. ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C. typical characteristics − DCO with external resistor ROSC 10.00 DCO Frequency − MHz DCO Frequency − MHz 10.00 1.00 0.10 RSELx = 4 0.01 10.00 100.00 1000.00 1.00 0.10 RSELx = 4 0.01 10.00 10000.00 ROSC − External Resistor − kOhm 10000.00 Figure 15. DCO Frequency vs ROSC, VCC = 3.0 V, TA = 255C 2.50 2.50 2.25 ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 DCO Frequency − MHz 2.25 DCO Frequency − MHz 1000.00 ROSC − External Resistor − kOhm Figure 14. DCO Frequency vs ROSC, VCC = 2.2 V, TA = 255C ROSC = 100k 2.00 1.75 1.50 1.25 1.00 ROSC = 270k 0.75 0.50 ROSC = 1M 0.25 0.00 −50.0 100.00 −25.0 0.0 25.0 50.0 75.0 ROSC = 1M 0.25 100.0 0.00 2.0 TA − Temperature − 5C Figure 16. DCO Frequency vs Temperature, VCC = 3.0 V POST OFFICE BOX 655303 2.5 3.0 3.5 4.0 VCC − Supply Voltage − V Figure 17. DCO Frequency vs VCC, TA = 255C • DALLAS, TEXAS 75265 37 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, low frequency modes (see Note 4) PARAMETER fLFXT1,LF TEST CONDITIONS LFXT1 oscillator crystal frequency, LF mode 0, 1 LFXT1 oscillator logic level fLFXT1,LF,logic square wave input frequency, LF mode OALF CL,eff Oscillation Allowance for LF crystals Integrated effective Load Capacitance, LF mode (see Note 1) VCC XTS = 0, LFXT1Sx = 0 or 1 1.8 V − 3.6 V XTS = 0, LFXT1Sx = 3 1.8 V − 3.6 V MIN TYP MAX 32,768 10,000 XTS = 0, LFXT1Sx = 0; fLFXT1,LF = 32,768 kHz, CL,eff = 6 pF XTS = 0, LFXT1Sx = 0; fLFXT1,LF = 32,768 kHz, CL,eff = 12 pF 32,768 UNIT Hz 50,000 Hz 500 kW 200 kW XTS = 0, XCAPx = 0 1 pF XTS = 0, XCAPx = 1 5.5 pF XTS = 0, XCAPx = 2 8.5 pF XTS = 0, XCAPx = 3 11 pF Duty Cycle LF mode XTS = 0, Measured at P1.4/ACLK, fLFXT1,LF = 32,768 Hz 2.2 V/3 V 30 fFault,LF Oscillator fault frequency, LF mode (see Note 3) XTS = 0, LFXT1Sx = 3 (see Notes 2) 2.2 V/3 V 10 50 70 % 10,000 Hz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Measured with logic level input frequency but also applies to operation with crystals. 3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. − Keep as short a trace as possible between the device and the crystal. − Design a good ground plane around the oscillator pins. − Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. − Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. − Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. − If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. − Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. internal very low power, low frequency oscillator (VLO) PARAMETER TEST CONDITIONS TA -40−85°C VCC 2.2 V/3 V 105°C 2.2 V/3 V fVLO VLO frequency dfVLO/dT VLO frequency temperature drift (see Note 1) I: -40−85°C T: -40−105°C 2.2 V/3 V dfVLO/dVCC VLO frequency supply voltage drift (see Note 2) 25°C 1.8V − 3.6V MIN TYP MAX 4 12 20 NOTES: 1. Calculated using the box method: I Version: (MAX(−40...85_C) − MIN(−40...85_C))/MIN(−40...85_C)/(85_C − (−40_C)) T Version: (MAX(−40...105_C) − MIN(−40...105_C))/MIN(−40...105_C)/(105_C − (−40_C)) 2. Calculated using the box method: (MAX(1.8...3.6V) − MIN(1.8...3.6V))/MIN(1.8...3.6V)/(3.6V − 1.8V) 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 22 UNIT kHz 0.5 %/°C 4 %/V SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator, LFXT1, high frequency modes (see Note 5) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fLFXT1,HF0 LFXT1 oscillator crystal frequency, HF mode 0 XTS = 1, LFXT1Sx = 0 1.8 V − 3.6 V 0.4 1 MHz fLFXT1,HF1 LFXT1 oscillator crystal frequency, HF mode 1 XTS = 1, LFXT1Sx = 1 1.8 V − 3.6 V 1 4 MHz 1.8 V − 3.6 V 2 10 MHz fLFXT1,HF2 LFXT1 oscillator crystal frequency, HF mode 2 XTS = 1, LFXT1Sx = 2 2.2 V − 3.6 V 2 12 MHz 3.0 V − 3.6 V 2 16 MHz 1.8 V − 3.6 V 0.4 10 MHz 2.2 V − 3.6 V 0.4 12 MHz 3.0 V − 3.6 V 0.4 16 MHz LFXT1 oscillator logic level square fLFXT1,HF,logic wave input frequency, HF mode XTS = 1, LFXT1Sx = 3 XTS = 0, LFXT1Sx = 0, fLFXT1,HF = 1 MHz, CL,eff = 15 pF OAHF CL,eff Duty Cycle fFault,HF Oscillation Allowance for HF crystals (refer to Figure 18 and Figure 19) Integrated effective Load Capacitance, HF mode (see Note 1) XTS = 0, LFXT1Sx = 1 fLFXT1,HF = 4 MHz, CL,eff = 15 pF XTS = 0, LFXT1Sx = 2 fLFXT1,HF = 16 MHz, CL,eff = 15 pF XTS = 1 (see Note 2) HF mode Oscillator fault frequency, HF mode (see Note 4) 2700 W 800 W 300 W 1 pF XTS = 1, Measured at P1.4/ACLK, fLFXT1,HF = 10 MHz 2.2 V/3 V 40 50 60 % XTS = 1, Measured at P1.4/ACLK, fLFXT1,HF = 16 MHz 2.2 V/3 V 40 50 60 % XTS = 1, LFXT1Sx = 3 (see Notes 3) 2.2 V/3 V 30 300 kHz NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin). Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal. 2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers. 3. Measured with logic level input frequency but also applies to operation with crystals. 4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag. Frequencies in between might set the flag. 5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed. − Keep as short a trace as possible between the device and the crystal. − Design a good ground plane around the oscillator pins. − Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. − Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. − Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. − If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. − Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 39 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) typical characteristics − LFXT1 oscillator in HF mode (XTS = 1) Oscillation Allowance − Ohms 100000.00 10000.00 1000.00 LFXT1Sx = 3 100.00 LFXT1Sx = 2 LFXT1Sx = 1 10.00 0.10 1.00 10.00 100.00 Crystal Frequency − MHz Figure 18. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C 800.0 XT Oscillator Supply Current − uA LFXT1Sx = 3 700.0 600.0 500.0 400.0 300.0 LFXT1Sx = 2 200.0 100.0 LFXT1Sx = 1 0.0 0.0 4.0 8.0 12.0 16.0 20.0 Crystal Frequency − MHz Figure 19. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C 40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Timer_A PARAMETER fTA Timer_A clock frequency tTA,cap Timer_A, capture timing TEST CONDITIONS Internal: SMCLK, ACLK; External: TACLK, INCLK; Duty Cycle = 50% ±10% TA0, TA1, TA2 VCC MIN TYP MAX 2.2 V 10 3V 16 UNIT MHz 2.2 V/3 V 20 ns Timer_B PARAMETER fTB Timer_B clock frequency tTB,cap Timer_B, capture timing TEST CONDITIONS Internal: SMCLK, ACLK; External: TBCLK; Duty Cycle = 50% ±10% TB0, TB1, TB2 POST OFFICE BOX 655303 VCC TYP MAX 10 3V 16 UNIT MHz 2.2 V/3 V • DALLAS, TEXAS 75265 MIN 2.2 V 20 ns 41 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (UART Mode) PARAMETER fUSCI USCI input clock frequency fBITCLK BITCLK clock frequency (equals Baudrate in MBaud) tτ UART receive deglitch time (see Note 1) TEST CONDITIONS VCC MIN Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% ± 10% TYP MAX UNIT fSYSTEM MHz 1 MHz 2.2V /3 V 2.2 V 50 150 600 ns 3V 50 100 600 ns NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. USCI (SPI Master Mode, see Figure 20 and Figure 21) PARAMETER fUSCI USCI input clock frequency tSU,MI SOMI input data setup time tHD,MI tVALID,MO TEST CONDITIONS VCC MIN SMCLK, ACLK Duty Cycle = 50% ± 10% SOMI input data hold time UCLK edge to SIMO valid; CL = 20 pF SIMO output data valid time TYP MAX UNIT fSYSTEM MHz 2.2 V 110 ns 3V 75 ns 2.2 V 0 ns 3V 0 ns 2.2 V 30 ns 3V 20 ns USCI (SPI Slave Mode, see Figure 22 and Figure 23) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT tSTE,LEAD STE lead time STE low to clock 2.2 V/3 V tSTE,LAG STE lag time Last clock to STE high 2.2 V/3 V tSTE,ACC STE access time STE low to SOMI data out 2.2 V/3 V 50 ns tSTE,DIS STE disable time STE high to SOMI high impedance 2.2 V/3 V 50 ns tSU,SI SIMO input data setup time tHD,SI SIMO input data hold time tVALID,SO 42 SOMI output data valid time UCLK edge to SOMI valid; CL = 20 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 50 ns 10 ns 2.2 V 20 ns 3V 15 ns 2.2 V 10 ns 3V 10 ns 2.2 V 75 110 ns 3V 50 75 ns SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 1/fUCxCLK CKPL =0 CKPL =1 UCLK tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID ,MO SIMO Figure 20. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL =0 CKPL =1 UCLK tLOW/HIGH tLOW/HIGH tSU,MI tHD,MI SOMI tVALID ,MO SIMO Figure 21. SPI Master Mode, CKPH = 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 43 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL =0 CKPL =1 UCLK tLOW/HIGH tLOW/HIGH tSU,SIMO tHD,SIMO SIMO tACC tVALID ,SOMI tDIS SOMI Figure 22. SPI Slave Mode, CKPH = 0 tSTE,LEAD tSTE,LAG STE 1/fUCxCLK CKPL=0 UCLK CKPL=1 tLOW/HIGH tLOW/HIGH tSU,SI tHD,SI SIMO tACC tVALID ,SO SOMI Figure 23. SPI Slave Mode, CKPH = 1 44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tDIS SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) USCI (I2C Mode, see Figure 24) PARAMETER TEST CONDITIONS fUSCI USCI input clock frequency fSCL SCL clock frequency VCC MIN TYP Internal: SMCLK, ACLK External: UCLK Duty Cycle = 50% ± 10% MAX UNIT fSYSTEM MHz 400 kHz 2.2 V/3 V 0 2.2 V/3 V 4.0 us 2.2 V/3 V 0.6 us 2.2 V/3 V 4.7 us 2.2 V/3 V 0.6 us tHD,STA Hold time (repeated) START fSCL ≤ 100kHz fSCL > 100kHz tSU,STA Set-up time for a repeated START fSCL ≤ 100kHz fSCL > 100kHz tHD,DAT tSU,DAT Data hold time 2.2 V/3 V 0 ns Data set-up time 2.2 V/3 V 250 ns tSU,STO Set-up time for STOP 2.2 V/3 V 4.0 us Pulse width of spikes suppressed by input filter 2.2 V 50 150 600 ns tSP 3V 50 100 600 ns tHD , STA tSU , STA tHD , STA tBUF SDA t LOW tHIGH tSP SCL tSU ,DAT tSU , STO tHD ,DAT Figure 24. I2C Mode Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 45 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, power supply and input range conditions (see Note 1) PARAMETER TEST CONDITIONS TA VCC VCC Analog supply voltage range VSS = 0 V VAx Analog input voltage range (see Note 2) All Ax terminals. Analog inputs selected in ADC10AE register. ADC10 supply current (see Note 3) fADC10CLK = 5.0 MHz ADC10ON = 1, REFON = 0 ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV =0 -40−85°C I: -40−85 C T: -40−105°C fADC10CLK = 5.0 MHz ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0 I: -40−85°C T: -40−105°C fADC10CLK = 5.0 MHz ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0 I: -40−85°C T: -40−105°C 3V -40−85°C 2.2 V/3 V 105°C 2.2 V/3 V -40−85°C 2.2 V/3 V 105°C 2.2 V/3 V IADC10 IREF+ Reference supply current, reference buffer disabled (see Note 4) fADC10CLK = 5.0 MHz ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR=0 Reference buffer supply current with ADC10SR=1 (see Note 4) fADC10CLK = 5.0 MHz ADC10ON = 0, REFON = 1, REF2_5V = 0, REFOUT = 1, ADC10SR=1 CI Input capacitance Only one terminal Ax selected at a time I: -40−85°C T: -40−105°C RI Input MUX ON resistance 0V ≤ VAx ≤ VCC I: -40−85°C T: -40−105°C IREFB,1 NOTES: 1. 2. 3. 4. 46 TYP MAX UNIT 2.2 3.6 V 0 VCC V 2.2 V 0.52 1.05 3V 0.6 1.2 mA 2.2 V/3 V mA 0.25 Reference buffer supply current with ADC10SR=0 (see Note 4) IREFB,0 MIN 2.2 V/3 V 0.4 mA 1.1 0.5 1.4 mA 1.8 mA 0.7 mA 0.8 mA 27 pF 2000 Ω The leakage current is defined in the leakage current table with Px.x/Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results. The internal reference supply current is not included in current consumption parameter IADC10. The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, built-in voltage reference PARAMETER VCC,REF+ TEST CONDITIONS Positive built-in reference analog supply voltage range VREF+ Positive built-in reference voltage ILD,VREF+ Maximum VREF+ load current VCC IVREF+ ≤ 1mA, REF2_5V=0 IVREF+ ≤ 0.5mA, REF2_5V=1 VREF+ load regulation response time UNIT V IVREF+ ≤ 1mA, REF2_5V=1 IVREF+ ≤ IVREF+max, REF2_5V=0 2.2 V/3 V 1.41 1.5 1.59 V IVREF+ ≤ IVREF+max, REF2_5V=1 3V 2.35 2.5 2.65 V 2.9 ±0.5 3V ±1 mA IVREF+ = 500 µA ± 100 µA Analog input voltage VAx ≈ 0.75 V; REF2_5V=0 2.2 V/3 V ±2 LSB IVREF+ = 500 µA ± 100 µA Analog input voltage VAx ≈ 1.25 V; REF2_5V=1 3V ±2 LSB 3V 400 IVREF+ = 100µA→900µA, VAx ≈ 0.5 x VREF+ Error of conversion result ≤ 1 LSB ADC10SR=0 ns ADC10SR=1 3V 2000 100 Max. capacitance at pin VREF+ (see Note 1) IVREF+ ≤ ±1mA, REFON=1, REFOUT=1 2.2 V/3 V TCREF+ Temperature coefficient IVREF+ = const. with 0 mA ≤ IVREF+ ≤ 1 mA 2.2 V/3 V tREFON Settling time of internal reference voltage (see Note 2) IVREF+ = 0.5 mA, REF2_5V=0 REFON = 0 → 1 Settling time of reference buffer (see Note 2) MAX 2.8 CVREF+ tREFBURST TYP 2.2 2.2 V VREF+ load regulation MIN pF ±100 ppm/°C 3.6 V 30 IVREF+ = 0.5 mA, REF2_5V=0, REFON = 1, REFBURST = 1 ADC10SR=0 2.2 V 1 ADC10SR=1 2.2 V 2.5 IVREF+ = 0.5 mA, REF2_5V=1, REFON = 1, REFBURST = 1 ADC10SR=0 3V 2 ADC10SR=1 3V 4.5 µs µss µss NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+ (REFOUT=1), must be limited; the reference buffer may become unstable otherwise. 2. The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 47 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, external reference (see Note 1) PARAMETER VeREF+ TEST CONDITIONS Positive external reference input voltage range (see Note 2) TYP MAX UNIT 1.4 VCC V VeREF− ≤ VeREF+ ≤ VCC − 0.15V SREF1 = 1, SREF0 = 1 (see Note 3) 1.4 3.0 V 0 1.2 V 1.4 VCC V Negative external reference input voltage range (see Note 4) VeREF+ > VeREF− ∆VeREF Differential external reference input voltage range ∆VeREF = VeREF+ − VeREF− VeREF+ > VeREF− (see Note 5) Static input current into VeREF+ MIN VeREF+ > VeREF− SREF1 = 1, SREF0 = 0 VeREF− IVeREF+ VCC 0V ≤ VeREF+ ≤ VCC, SREF1 = 1, SREF0 = 0 2.2 V/3 V ±1 µA 0V ≤VeREF+ ≤ VCC − 0.15V ≤ 3V SREF1 = 1, SREF0 = 1 (see Note 3) 2.2 V/3 V 0 µA IVeREF− Static input current into VeREF− 0V ≤ VeREF− ≤ VCC 2.2 V/3 V ±1 µA NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. 2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. 3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1. 4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. 5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. 48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, timing parameters PARAMETER fADC10CLK fADC10OSC tCONVERT TEST CONDITIONS For specified performance of ADC10 linearity parameters ADC10 input clock frequency ADC10 built-in oscillator frequency Conversion time VCC MIN TYP MAX UNIT ADC10SR=0 2.2 V/3 V 0.45 6.3 ADC10SR=1 2.2 V/3 V 0.45 1.5 ADC10DIVx=0, ADC10SSELx = 0 fADC10CLK = fADC10OSC 2.2 V/3 V 3.7 6.3 MHz ADC10 built-in oscillator, ADC10SSELx = 0 fADC10CLK = fADC10OSC 2.2 V/3 V 2.06 3.51 µs MHz 13× ADC10DIV× 1/fADC10CLK fADC10CLK from ACLK, MCLK or SMCLK: ADC10SSELx ≠ 0 µs tADC10ON Turn on settling time of the ADC (see Note 1) 100 ns NOTES: 1. The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already settled. 10-bit ADC, linearity parameters PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT EI ED Integral linearity error 2.2 V/3 V ±1 LSB Differential linearity error 2.2 V/3 V ±1 LSB EO Offset error 2.2 V/3 V ±1 LSB EG Gain error Source impedance RS < 100 Ω, SREFx = 010; un-buffered external reference; VeREF+ = 1.5V 2.2 V ±1.1 ±2 LSB SREFx = 010; un-buffered external reference; VeREF+ = 2.5V 3V ±1.1 ±2 LSB 2.2 V ±1.1 ±4 LSB 3V ±1.1 ±3 LSB 2.2 V ±2 ±5 LSB 3V ±2 ±5 LSB SREFx = 011; buffered external reference (see Note 1); VeREF+ = 1.5V 2.2 V ±2 ±7 LSB SREFx = 011; buffered external reference (see Note 1); VeREF+ = 2.5V 3V ±2 ±6 LSB SREFx = 011; buffered external reference (see Note 1); VeREF+ = 1.5V SREFx = 011; buffered external reference (see Note 1); VeREF+ = 2.5V SREFx = 010; un-buffered external reference; VeREF+ = 1.5V SREFx = 010; un-buffered external reference; VeREF+ = 2.5V ET Total unadjusted error NOTES: 1. The reference buffer’s offset adds to the gain and total unadjusted error. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 49 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 10-bit ADC, temperature sensor and built-in VMID PARAMETER ISENSOR Temperature sensor supply current (see Note 1) TEST CONDITIONS REFON = 0, INCHx = 0Ah, TA = 25_C TCSENSOR† ADC10ON = 1, INCHx = 0Ah (see Note 2) VOffset,Sensor Sensor offset voltage ADC10ON = 1, INCHx = 0Ah (see Note 2) VSensor Sensor output voltage (see Note 3) Sample time required if tSensor(sample) channel 10 is selected (see Note 4) VCC MIN TYP MAX 2.2 V 40 120 3V 60 160 3.55 3.66 mV/°C 100 mV 2.2 V/3 V 3.44 −100 µA A Temperature sensor voltage at TA = 105°C (T Version only) 2.2 V/3 V 1265 1365 1465 mV Temperature sensor voltage at TA = 85°C 2.2 V/3 V 1195 1295 1395 mV Temperature sensor voltage at TA = 25°C 2.2 V/3 V 985 1085 1185 Temperature sensor voltage at TA = 0°C 2.2 V/3 V 895 995 1095 ADC10ON = 1, INCHx = 0Ah, Error of conversion result ≤ 1 LSB 2.2 V/3 V 30 mV µs 2.2 V NA 3V NA IVMID Current into divider at channel 11 (see Note 5) ADC10ON = 1, INCHx = 0Bh, 1.06 1.1 1.14 VCC divider at channel 11 ADC10ON = 1, INCHx = 0Bh, VMID is ≈0.5 x VCC 2.2 V VMID 3V 1.46 1.5 1.54 ADC10ON = 1, INCHx = 0Bh, Error of conversion result ≤ 1 LSB 2.2 V 1400 3V 1220 Sample time required if tVMID(sample) channel 11 is selected (see Note 6) UNIT A µA V ns NOTES: 1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor input (INCH = 0Ah). 2. The following formula can be used to calculate the temperature sensor output voltage: VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV] 3. Results based on characterization and/or production test, not TCSensor or VOffset,sensor. 4. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on). 5. No additional current is needed. The VMID is used during sampling. 6. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) operational amplifier OA, supply specifications (MSP430x22x4 only) PARAMETER VCC ICC PSRR TEST CONDITIONS VCC Supply voltage range Supply current (see Note 1) Power supply rejection ratio MIN TYP 2.2 MAX UNIT 3.6 Fast Mode 2.2 V/3 V 180 290 Medium Mode 2.2 V/3 V 110 190 Slow Mode 2.2 V/3 V 50 80 Non-inverting 2.2 V/3 V 70 V µA dB NOTES: 1. Corresponding pins configured as OA inputs and outputs respectively. operational amplifier OA, input/output specifications (MSP430x22x4 only) PARAMETER VI/P IIkg TEST CONDITIONS Input voltage range Input leakage current (see Notes 1 and 2) Voltage noise density, I/P MIN −0.1 ±0.5 VCC−1.2 5 nA 2.2 V/3 V −20 ±5 20 nA TA = +85 to +105_C Fast Mode 2.2 V/3 V −50 50 nA 80 fV(I/P) = 1 kHz 140 Fast Mode 30 50 fV(I/P) = 10 kHz 65 ±10 2.2 V/3 V ±10 2.2 V/3 V 0.3V ≤ VIN ≤ VCC−1.0V ∆VCC≤ ± 10%, TA = 25°C 2.2 V/3 V Fast Mode, ISOURCE ≤ −500µA 2.2 V/3 V Slow Mode,ISOURCE ≤ −150µA 2.2 V/3 V Fast Mode, ISOURCE ≤ +500µA 2.2 V/3 V Slow Mode,ISOURCE ≤ +150µA 2.2 V/3 V RLoad= 3 kΩ, CLoad = 50pF, VO/P(OAx) < 0.2 V 2.2 V/3 V 150 250 RLoad= 3 kΩ, CLoad = 50pF, VO/P(OAx) > VCC − 1.2 V 2.2 V/3 V 150 250 RLoad= 3 kΩ, CLoad = 50pF, 0.2 V ≤ VO/P(OAx) ≤ VCC − 0.2 V 2.2 V/3 V 0.1 4 Non-inverting 2.2 V/3 V 70 Low-level output voltage, O/P Output Resistance (see Figure 25 and Note 4) Common-mode rejection ratio VCC−0.2 VCC−0.1 VSS VSS mV µV/°C see Note 3 Offset voltage drift with supply, I/P VOL CMRR nV/√Hz Offset temperature drift, I/P High-level output voltage, O/P V 50 Slow Mode Offset voltage, I/P VOH NOTES: 1. 2. 3. 4. UNIT −5 Slow Mode RO/P(OAx) MAX 2.2 V/3 V Medium Mode VIO TYP TA = −40 to +55_C TA = +55 to +85_C Medium Mode Vn VCC ±1.5 mV/V VCC VCC V 0.2 0.1 V Ω dB ESD damage can degrade input current leakage. The input bias current is overridden by the input leakage current. Calculated using the box method. Specification valid for voltage-follower OAx configuration. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 51 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) RO/P(OAx) Max RLoad ILoad AV CC OAx 2 CLoad O/P(OAx) Min 0.2V AV CC −0.2VAV V CC OUT Figure 25. OAx Output Resistance Tests operational amplifier OA, dynamic specifications (MSP430x22x4 only) PARAMETER SR TEST CONDITIONS Slew rate VCC MIN TYP Fast Mode 1.2 Medium Mode 0.8 Slow Mode 0.3 Open-loop voltage gain φm ten(on) ten(off) UNIT V/µs 100 dB Phase margin CL = 50 pF 60 deg Gain margin CL = 50 pF 20 dB Gain-Bandwidth Product (see Figure 26 and Figure 27) GBW MAX Enable time on Non-inverting, Fast Mode, RL = 47kΩ, CL = 50pF 2.2 V/3 V 2.2 Non-inverting, Medium Mode, RL =300kΩ, CL = 50pF 2.2 V/3 V 1.4 Non-inverting, Slow Mode, RL =300kΩ, CL = 50pF 2.2 V/3 V 0.5 ton, non-inverting, Gain = 1 2.2 V/3 V 10 Enable time off 2.2 V/3 V MHz 20 µs 1 µs TYPICAL PHASE vs FREQUENCY TYPICAL OPEN-LOOP GAIN vs FREQUENCY 0 140 120 100 −50 Fast Mode 80 Phase − degrees Gain − dB Fast Mode 60 40 Medium Mode 20 0 Slow Mode −100 Medium Mode −150 −20 Slow Mode −40 −200 −60 −80 1 10 100 1000 10000 100000 −250 1 Input Frequency − kHz 100 Figure 27 POST OFFICE BOX 655303 1000 Input Frequency − kHz Figure 26 52 10 • DALLAS, TEXAS 75265 10000 100000 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) operational amplifier OA feedback network, resistor network (see Note 1. MSP430x22x4 only) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Rtotal Total resistance of resistor string 76 96 128 kΩ Runit Unit resistor of resistor string (see Note 2) 4.8 6 8 kΩ NOTES: 1. A single resistor string is composed of 4 Runit + 4 Runit + 2 Runit + 2 Runit + 1 Runit + 1 Runit + 1 Runit + 1 Runit = 16 Runit = Rtotal. 2. For the matching (i.e. the relative accuracy) of the unit resistors on a device refer to the gain and level specifications of the respective configurations. operational amplifier OA feedback network, comparator mode (OAFCx = 3. MSP430x22x4 only) PARAMETER VLevel tPLH, tPHL Comparator level Propagation delay (low−high and high−low) TEST CONDITIONS VCC MIN TYP MAX OAFBRx = 1, OARRIP = 0 2.2 V/ 3V 0.245 1/4 0.255 OAFBRx = 2, OARRIP = 0 2.2 V/ 3V 0.495 1/2 0.505 OAFBRx = 3, OARRIP = 0 2.2 V/ 3V 0.619 5/8 0.631 OAFBRx = 4, OARRIP = 0 2.2 V/ 3V N/A (see Note 1) OAFBRx = 5, OARRIP = 0 2.2 V/ 3V N/A (see Note 1) OAFBRx = 6, OARRIP = 0 2.2 V/ 3V N/A (see Note 1) OAFBRx = 7, OARRIP = 0 2.2 V/ 3V OAFBRx = 1, OARRIP = 1 2.2 V/ 3V 0.061 OAFBRx = 2, OARRIP = 1 2.2 V/ 3V OAFBRx = 3, OARRIP = 1 2.2 V/ 3V OAFBRx = 4, OARRIP = 1 UNIT N/A (see Note 1) 1/16 0.065 0.122 1/8 0.128 0.184 3/16 0.192 2.2 V/ 3V 0.245 1/4 0.255 OAFBRx = 5, OARRIP = 1 2.2 V/ 3V 0.367 3/8 0.383 OAFBRx = 6, OARRIP = 1 2.2 V/ 3V 0.495 1/2 0.505 OAFBRx = 7, OARRIP = 1 2.2 V/ 3V Fast Mode, Overdrive 10mV 2.2 V/ 3V 40 Fast Mode, Overdrive 100mV 2.2 V/3 V 4 Fast Mode, Overdrive 500mV 2.2 V/3 V 3 Medium Mode, Overdrive 10mV 2.2 V/3 V 60 Medium Mode, Overdrive 100mV 2.2 V/3 V 6 Medium Mode, Overdrive 500mV 2.2 V/3 V 5 Slow Mode, Overdrive 10mV 2.2 V/3 V 160 Slow Mode, Overdrive 100mV 2.2 V/3 V 20 Slow Mode, Overdrive 500mV 2.2 V/3 V 15 VCC N/A (see Note 1) µs NOTES: 1. The level is not available due to the analog input voltage range of the operational amplifier. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 53 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) operational amplifier OA feedback network, non-inverting amplifier mode (OAFCx = 4. MSP430x22x4 only) PARAMETER G THD Gain Total Harmonic Distortion/ Nonlinearity TEST CONDITIONS VCC MIN TYP MAX OAFBRx = 0 2.2 V/ 3V 0.998 1.00 1.002 OAFBRx = 1 2.2 V/ 3V 1.328 1.334 1.340 OAFBRx = 2 2.2 V/ 3V 1.985 2.001 2.017 OAFBRx = 3 2.2 V/ 3V 2.638 2.667 2.696 OAFBRx = 4 2.2 V/ 3V 3.94 4.00 4.06 OAFBRx = 5 2.2 V/ 3V 5.22 5.33 5.44 OAFBRx = 6 2.2 V/ 3V 7.76 7.97 8.18 OAFBRx = 7 2.2 V/ 3V 15.0 15.8 16.6 2.2 V −60 3V −70 all gains UNIT dB tSettle Settling time (see Note 1) all power modes 2.2 V/3 V 7 12 µs NOTES: 1. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster. operational amplifier OA feedback network, inverting amplifier mode (OAFCx = 6, see Note 1, MSP430x22x4 only) PARAMETER G THD Gain Total Harmonic Distortion/ Nonlinearity VCC MIN TYP MAX OAFBRx = 1 TEST CONDITIONS 2.2 V/ 3V −0.345 −0.335 −0.325 OAFBRx = 2 2.2 V/ 3V −1.023 −1.002 −0.979 OAFBRx = 3 2.2 V/ 3V −1.712 −1.668 −1.624 OAFBRx = 4 2.2 V/ 3V −3.10 −3.00 −2.90 OAFBRx = 5 2.2 V/ 3V −4.51 −4.33 −4.15 OAFBRx = 6 2.2 V/ 3V −7.37 −6.97 −6.57 OAFBRx = 7 2.2 V/ 3V −16.3 −14.8 −13.1 all gains 2.2 V −60 3V −70 UNIT dB tSettle Settling time (see Note 2) all power modes 2.2 V/3 V 7 12 µs NOTES: 1. This includes the 2 OA configuration “inverting amplifier with input buffer”. Both OA needs to be set to the same power mode OAPMx. 2. The settling time specifies the time until an ADC result is stable. This includes the minimum required sampling time of the ADC. The settling time of the amplifier itself might be faster. 54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) Flash Memory PARAMETER VCC(PGM/ ERASE) TEST CONDITIONS VCC Program and Erase supply voltage MIN TYP 2.2 fFTG IPGM Flash Timing Generator frequency Supply current from VCC during program 2.2 V/3.6 V 257 1 IERASE tCPT Supply current from VCC during erase 2.2 V/3.6 V 1 Cumulative program time (see Note 1) 2.2 V/3.6 V tCMErase Cumulative mass erase time 2.2 V/3.6 V Program/Erase endurance tRetention Data retention duration TJ = 25°C tWord tBlock, 0 Word or byte program time Block program time for 1st byte or word tBlock, 1-63 tBlock, End Block program time for each additional byte or word tMass Erase tSeg Erase Mass erase time Block program end-sequence wait time 20 104 MAX UNIT 3.6 V 476 kHz 5 mA 7 mA 10 ms ms 105 cycles 100 years 30 25 18 see Note 2 tFTG 6 10593 Segment erase time 4819 NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. 2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG). RAM PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(RAMh) RAM retention supply voltage (see Note 1) CPU halted 1.6 V NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 55 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) JTAG and Spy-Bi-Wire Interface TEST CONDITIONS PARAMETER fSBW tSBW,Low VCC MIN TYP MAX UNIT Spy-Bi-Wire input frequency 2.2 V / 3 V 0 20 MHz Spy-Bi-Wire low clock pulse length 2.2 V / 3 V 0.025 15 us tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge, see Note 1) 2.2 V/ 3 V 1 us tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V/ 3 V 15 100 2.2 V 0 5 MHz 3V 0 10 MHz fTCK TCK input frequency (see Note 2) us RInternal Internal pull-down resistance on TEST 2.2 V/ 3 V 25 60 90 kΩ NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. 2. fTCK may be restricted to meet the timing requirements of the module selected. JTAG Fuse (see Note 1) TEST CONDITIONS PARAMETER VCC(FB) VFB Supply voltage during fuse-blow condition IFB tFB Supply current into TEST during fuse blow TA = 25°C Voltage level on TEST for fuse-blow VCC MIN MAX 2.5 6 Time to blow fuse TYP UNIT V 7 V 100 mA 1 ms NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible and is switched to bypass mode. 56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 APPLICATION INFORMATION Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt-trigger Pad Logic P1REN.x P1DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P1OUT.x DVSS DVCC P1.0/TACLK/ADC10CLK P1.1/TA0 P1.2/TA1 P1.3/TA2 P1SEL.x P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select Port P1 (P1.0 to P1.3) pin functions CONTROL BITS / SIGNALS PIN NAME (P1.X) X P1.0/ TACLK/ADC10CLk 0 P1.1/TA0 P1.2/TA1 P1.3/TA2 1 2 3 FUNCTION P1DIR.x P1SEL.x I: 0; O: 1 0 Timer_A3.TACLK 0 1 ADC10CLK 1 1 P1.1† (I/O) P1.0† (I/O) I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.2† (I/O) I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 P1.3† (I/O) I: 0; O: 1 0 Timer_A3.CCI0A 0 1 Timer_A3.TA0 1 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 57 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P1 pin schematic: P1.4 to P1.6, input/output with Schmitt-trigger and in-system access features Pad Logic P1REN.x P1DIR.x 0 P1OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q Set P1IFG.x P1SEL.x P1IES.x Interrupt Edge Select To JTAG From JTAG Port P1 (P1.4 to P1.6) pin functions PIN NAME (P1.X) P1.4/SMCLK/TCK P1.5/TA0/TMS P1.6/TA1/TDI/TCLK CONTROL BITS / SIGNALS X 4 5 6 FUNCTION P1.4† (I/O) P1SEL.x 4-Wire JTAG I: 0; O: 1 0 0 SMCLK 1 1 0 TCK X X 1 I: 0; O: 1 0 0 P1.5† (I/O) Timer_A3.TA0 1 1 0 TMS X X 1 P1.6† (I/O) I: 0; O: 1 0 0 Timer_A3.TA1 1 1 0 TDI/TCLK (see Note 3) X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Function controlled by JTAG. 58 P1DIR.x POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P1 pin schematic: P1.7, input/output with Schmitt-trigger and in-system access features Pad Logic P1REN.7 P1DIR.7 0 P1OUT.7 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P1.7/TA2/TDO/TDI Bus Keeper P1SEL.7 EN P1IN.7 EN Module X IN D P1IE.7 P1IRQ.7 EN Q Set P1IFG.7 Interrupt Edge Select P1SEL.7 P1IES.7 To JTAG From JTAG From JTAG From JTAG (TDO) Port P1 (P1.7) pin functions PIN NAME (P1.X) P1.7/TA2/TDO/TDI CONTROL BITS / SIGNALS X 7 FUNCTION P1.7† (I/O) P1DIR.x P1SEL.x 4-Wire JTAG I: 0; O: 1 0 0 Timer_A3.TA2 1 1 0 TDO/TDI (see Note 3) X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Function controlled by JTAG. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 59 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P2 pin schematic: P2.0, P2.2, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = y ADC10AE0.y P2REN.x P2DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.x DVSS DVCC P2.0/ACLK/A0/OA0I0 P2.2/TA0/A2/OA0I1 Bus Keeper P2SEL.x EN P2IN.x EN Module X IN D P2IE.x P2IRQ.x EN Q P2IFG.x P2SEL.x P2IES.x Set Interrupt Edge Select + OA0 − Port P2 (P2.0, P2.2) pin functions CONTROL BITS / SIGNALS PIN NAME (P2.X) X Y P2.0/ACLK/A0/OA0I0 0 0 P2.2/TA0/A2/OA0I1 2 2 FUNCTION P2.0† (I/O) P2DIR.x P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 ACLK 1 1 0 A0/OA0I0 (see Note 3) X X 1 I: 0; O: 1 0 0 Timer_A3.CCI0B 0 1 0 Timer_A3.TA0 1 1 0 A2/OA0I1 (see Note 3) X X P2.2† (I/O) 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P2 pin schematic: P2.1, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = 1 ADC10AE0.1 P2REN.1 P2DIR.1 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.1 DVSS DVCC P2.1/TAINCLK/SMCLK/ A1/OA0O Bus Keeper P2SEL.1 EN P2IN.1 EN Module X IN D P2IE.1 P2IRQ.1 EN Q P2IFG.1 Set + OA0 P2SEL.1 P2IES.1 OAADCx OAFCx OAPMx Interrupt Edge Select 1 − (OAADCx = 10 or OAFCx = 000) and OAPMx > 00 To OA0 Feedback Network POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 61 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P2 pin schematic: P2.3, input/output with Schmitt-trigger SREF2 Pad Logic VSS 0 To ADC 10 VR− 1 To ADC 10 INCHx = 3 ADC10AE0.3 P2REN.3 P2DIR.3 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P2OUT.3 DVSS DVCC P2.3/TA1/ A3/VREF−/VeREF−/ OA1I1/OA1O Bus Keeper P2SEL.3 EN P2IN.3 EN Module X IN D P2IE.3 P2IRQ.3 P2IFG.3 P2SEL.3 P2IES.3 OAADCx OAFCx OAPMx EN Q Set Interrupt Edge Select + OA1 − (OAADCx = 10 or OAFCx = 000) and OAPMx > 00 To OA1 Feedback Network 62 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P2 (P2.1) pin functions CONTROL BITS / SIGNALS PIN NAME (P2.X) X Y P2.1/TAINCLK/SMCLK /A1/OA0O 1 1 FUNCTION P2DIR.x P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 Timer_A3.INCLK 0 1 0 SMCLK 1 1 0 A1/OA0O (see Note 3) X X P2.1† (I/O) 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. Port P2 (P2.3) pin functions CONTROL BITS / SIGNALS PIN NAME (P2.X) X Y P2.3/TA1/ A3/VREF−/VeREF−/ OA1I1/OA1O 3 3 FUNCTION P2.3† (I/O) Timer_A3.CCI1B P2DIR.x P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 0 1 0 0 Timer_A3.TA1 1 1 A3/VREF−/VeREF−/OA1I1/OA1O (see Note 3) X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 63 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P2 pin schematic: P2.4, input/output with Schmitt-trigger Pad Logic To/from ADC10 positive reference To ADC10 INCHx = 4 ADC10AE0.4 P2REN.4 P2DIR.4 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P2OUT.4 DVSS P2.4/TA2/ A4/VREF+/VeREF+/ OA1I0 Bus Keeper P2SEL.4 EN P2IN.4 EN Module X IN D P2IE.4 P2IRQ.4 EN Q Set P2IFG.4 P2SEL.4 P2IES.4 Interrupt Edge Select + OA1 − Port P2 (P2.4) pin functions CONTROL BITS / SIGNALS PIN NAME (P2.X) X Y P2.4/TA2/ A4/VREF+/VeREF+/ OA1I0 4 4 FUNCTION P2.4† (I/O) Timer_A3.TA2 P2DIR.x P2SEL.x ADC10AE0.y I: 0; O: 1 0 0 1 1 0 A4/VREF+/VeREF+/OA1I0 (see Note 3) X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P2 pin schematic: P2.5, input/output with Schmitt-trigger and external ROSC for DCO Pad Logic To DCO DCOR P1REN.x P1DIR.x 0 P1OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.5/ROSC Bus Keeper P1SEL.x EN P1IN.x EN Module X IN D P1IE.x P1IRQ.x EN Q P1IFG.x P1SEL.x P1IES.x Set Interrupt Edge Select Port P2 (P2.5) pin functions PIN NAME (P2.X) P2.5/ROSC CONTROL BITS / SIGNALS X 5 FUNCTION P2.5† (I/O) P2DIR.x P2SEL.x DCOR I: 0; O: 1 0 0 N/A 0 1 0 DVSS ROSC 1 1 0 X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 65 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P2 pin schematic: P2.6, input/output with Schmitt-trigger and crystal oscillator input BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator P2.7/XOUT LFXT1 off 0 LFXT1CLK 1 Pad Logic P2SEL.7 P2REN.6 P2DIR.6 0 P2OUT.6 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.6/XIN Bus Keeper P2SEL.6 EN P2IN.6 EN Module X IN D P2IE.6 P2IRQ.6 EN Q Set P2IFG.6 Interrupt Edge Select P2SEL.6 P2IES.6 Port P2 (P2.6) pin functions PIN NAME (P2.X) P2.6/XIN CONTROL BITS / SIGNALS X 6 FUNCTION P2.6 (I/O) XIN† † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 P2DIR.x P2SEL.x I: 0; O: 1 0 X 1 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P2 pin schematic: P2.7, input/output with Schmitt-trigger and crystal oscillator output BCSCTL3.LFXT1Sx = 11 LFXT1 Oscillator LFXT1 off 0 LFXT1CLK From P2.6/XIN 1 P2.6/XIN Pad Logic P2SEL.6 P2REN.7 P2DIR.7 0 P2OUT.7 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P2.7/XOUT Bus Keeper P2SEL.7 EN P2IN.7 EN Module X IN D P2IE.7 P2IRQ.7 EN Q P2IFG.7 P2SEL.7 P2IES.7 Set Interrupt Edge Select Port P2 (P2.7) pin functions PIN NAME (P2.X) XOUT/P2.7 CONTROL BITS / SIGNALS X 6 FUNCTION P2.7 (I/O) XOUT† (see Note 3) P2DIR.x P2SEL.x I: 0; O: 1 0 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. If the pin XOUT/P2.7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection to this pin after reset. POST OFFICE BOX 655303 X • DALLAS, TEXAS 75265 67 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P3 pin schematic: P3.0, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = 5 ADC10AE0.5 P3REN.0 P3DIR.0 USCI Direction Control 0 P3OUT.0 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 P3.0/UC1STE/UC0CLK/A5 Bus Keeper P3SEL.0 EN P3IN.0 EN Module X IN D Port P3 (P3.0) pin functions CONTROL BITS / SIGNALS PIN NAME (P3.X) X Y P3.0/ UC1STE/UC0CLK/A5 0 5 FUNCTION P3.0† (I/O) UC1STE/UC0CLK (see Notes 3, 4) P3DIR.x P3SEL.x ADC10AE0.y I: 0; O: 1 0 0 X 1 0 A5 (see Note 5) X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. The pin direction is controlled by the USCI module. 4. UC0CLK function takes precedence over UC1STE function. If the pin is required as UC0CLK input or output USCI1 will be forced to 3-wire SPI mode if 4-wire SPI mode is selected. 5. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P3 pin schematic: P3.1 to P3.5, input/output with Schmitt-trigger Pad Logic DVSS P3REN.x P3DIR.x USCI Direction Control 0 P3OUT.x 0 Module X OUT 1 DVSS 0 DVCC 1 1 Direction 0: Input 1: Output 1 Bus Keeper P3SEL.x EN P3IN.x P3.1/UC1SIMO/UC1SCL P3.2/UC1SOMI/UC1SDA P3.3/UC1CLK/UC0STE P3.4/UC0TXD/UC0SIMO P3.5/UC0RXD/UC0SOMI EN Module X IN D Port P3 (P3.1 to P3.5) pin functions CONTROL BITS / SIGNALS PIN NAME (P3.X) X P3.1/ UC1SIMO/UC1SDA 1 P3.2/ UC1SOMI/UC1SCL 1 P3.3/ UC1CLK/UC0STE 1 P3.4/ UC0TXD/UC0SIMO 1 P3.5/ UC0RXD/UC0SOMI 1 FUNCTION P3.1† (I/O) UC1SIMO/UC1SDA (see Note 3) P3.2† (I/O) UC1SOMI/UC1SCL (see Note 3) P3.3† (I/O) UC1CLK/UC0STE (see Notes 3, 4) P3.4† (I/O) UC0TXD/UC0SIMO (see Note 3) P3.5† (I/O) UC0RXD/UC0SOMI (see Note 3) P3DIR.x P3SEL.x I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 X 1 I: 0; O: 1 0 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. The pin direction is controlled by the USCI module. 4. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output USCI0 will be forced to 3-wire SPI mode even if 4-wire SPI mode is selected. POST OFFICE BOX 655303 X • DALLAS, TEXAS 75265 69 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P3 pin schematic: P3.6 to P3.7, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = y ADC10AE0.y P3REN.x P3DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P3OUT.x DVSS DVCC P3.6/A6/OA0I2 P3.7/A7/OA1I2 Bus Keeper P3SEL.x EN P3IN.x EN Module X IN D + OA0/1 − Port P3 (P3.6, P3.7) pin functions PIN NAME (P3.X) P3.6/A6/OA0I2 CONTROL BITS / SIGNALS X Y 6 6 FUNCTION P3DIR.x P3.6† (I/O) A6/OA0I2 (see Note 5) P3.7/A7/OA1I2 7 7 P3.7† (I/O) A7/OA1I2 (see Note 5) P3SEL.x ADC10AE0.y I: 0; O: 1 0 0 X X 1 I: 0; O: 1 0 0 X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. The pin direction is controlled by the USCI module. 4. UC1CLK function takes precedence over UC0STE function. If the pin is required as UC1CLK input or output USCI0 will be forced to 3-wire SPI mode if 4-wire SPI mode is selected. 5. Setting the ADC10AE0.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P4 pin schematic: P4.0 to P4.2, input/output with Schmitt-trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic P4REN.x P4DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS DVCC Bus Keeper P4SEL.x P4.0/TB0 P4.1/TB1 P4.2/TB2 EN P4IN.x EN Module X IN D Port P4 (P4.0 to P4.2) pin functions PIN NAME (P4.X) P4.0/TB0 CONTROL BITS / SIGNALS X 0 FUNCTION P4.0† (I/O) Timer_B3.CCI0A Timer_B3.TB0 P4.1/TB1 P4.2/TB2 1 2 P4DIR.x P4SEL.x I: 0; O: 1 0 0 1 1 1 I: 0; O: 1 0 Timer_B3.CCI1A 0 1 Timer_B3.TB1 1 1 I: 0; O: 1 0 Timer_B3.CCI2A 0 1 Timer_B3.TB2 1 1 P4.1† (I/O) P4.2† (I/O) † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 71 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P4 pin schematic: P4.3 to P4.4, input/output with Schmitt-trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic To ADC 10 † INCHx = 8+y ADC10AE1.y P4REN.x P4DIR.x 0 0 Module X OUT 1 0 1 1 Direction 0: Input 1: Output 1 P4OUT.x DVSS DVCC P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D + OA0/1 − OAADCx OAPMx 1 OAADCx = 01 and OAPMx > 00 To OA0/1 Feedback Network 1 † If OAADCx = 11 and not OAFCx = 000 the ADC input A12 or A13 is internally connected to the OA0 or OA1 output respectively and the connections from the ADC and the operational amplifiers to the pad are disabled. 72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P4 (P4.3 to P4.4) pin functions CONTROL BITS / SIGNALS PIN NAME (P4.X) X Y P4.3/TB0/A12/OA0O 3 4 P4.4/TB1/A13/OA1O 4 5 FUNCTION P4DIR.x P4SEL.x ADC10AE1.y I: 0; O: 1 0 0 Timer_B3.CCI0B 0 1 0 Timer_B3.TB0 1 1 0 A12/OA0O (see Note 3) X X 1 P4.3† (I/O) P4.4† (I/O) I: 0; O: 1 0 0 Timer_B3.CCI1B 0 1 0 Timer_B3.TB1 1 1 0 A13/OA1O (see Note 3) X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 73 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P4 pin schematic: P4.5, input/output with Schmitt-trigger Timer_B Output Tristate Logic P4.6/TBOUTH/A15/OA1I3 P4SEL.6 P4DIR.6 ADC10AE1.7 Pad Logic To ADC 10 INCHx = 14 ADC10AE1.6 P4REN.5 P4DIR.5 0 0 Module X OUT 1 0 1 P4.5/TB3/A14/OA0I3 Bus Keeper P4SEL.5 EN P4IN.5 EN Module X IN D + OA0 − 74 1 Direction 0: Input 1: Output 1 P4OUT.5 DVSS DVCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P4 (P4.5) pin functions CONTROL BITS / SIGNALS PIN NAME (P4.X) X Y P4.5/TB3/A14/OA0I3 5 6 FUNCTION P4.5† (I/O) P4DIR.x P4SEL.x ADC10AE1.y I: 0; O: 1 0 0 0 Timer_B3.TB2 1 1 A14/OA0I3 (see Note 3) X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 75 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P4 pin schematic: P4.6, input/output with Schmitt-trigger Pad Logic To ADC 10 INCHx = 15 ADC10AE1.7 P4REN.6 P4DIR.6 0 0 Module X OUT 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 P4OUT.6 DVSS P4.6/TBOUTH/ A15/OA1I3 Bus Keeper P4SEL.6 EN P4IN.6 EN Module X IN D + OA1 − Port P4 (P4.6) pin functions PIN NAME (P4.X) P4.6/TBOUTH/ A15/OA1I3 CONTROL BITS / SIGNALS X Y 6 7 FUNCTION P4.6† (I/O) P4DIR.x P4SEL.x ADC10AE1.y I: 0; O: 1 0 0 TBOUTH 0 1 0 DVSS A15/OA1I3 (see Note 3) 1 1 0 X X 1 † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 3. Setting the ADC10AE1.y bit disables the output driver as well as the input schmitt trigger to prevent parasitic cross currents when applying analog signals. 76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Port P4 pin schematic: P4.7, input/output with Schmitt-trigger Pad Logic DVSS P4REN.x P4DIR.x 0 P4OUT.x 0 1 0 DVCC 1 1 Direction 0: Input 1: Output 1 Module X OUT DVSS P4.7/TBCLK Bus Keeper P4SEL.x EN P4IN.x EN Module X IN D Port P4 (P4.7) pin functions PIN NAME (P4.X) CONTROL BITS / SIGNALS X FUNCTION P4DIR.x P4SEL.x I: 0; O: 1 0 Timer_B3.TBCLK 0 1 DVSS † Default after reset (PUC/POR) NOTES: 1. N/A: Not available or not applicable. 2. X: Don’t care. 1 1 P4.7/TBCLK 7 P4.7† (I/O) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 77 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 JTAG fuse check mode MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense currents are terminated. Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse check mode has the potential to be activated. The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see Figure 28). Therefore, the additional current flow can be prevented by holding the TMS pin high (default condition). Time TMS Goes Low After POR TMS ITEST ITF Figure 28. Fuse Check Mode Current, MSP430F22xx NOTE: The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the bootstrap loader section for more information. 78 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SLAS504A − JULY 2006 − REVISED DECEMBER 2006 Data Sheet Revision History Literature Number SLAS504 SLAS504A Summary Preliminary data sheet release. Production data sheet release. Updated specification and added characterization graphs. Updated/corrected port pin schematics. NOTE: The referring page and figure numbers are referred to the respective document revision. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 79 PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty MSP430F2232IDA ACTIVE TSSOP DA 38 MSP430F2232IDAR ACTIVE TSSOP DA MSP430F2232IRHAR ACTIVE QFN MSP430F2232IRHAT ACTIVE MSP430F2232TDA 40 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2232TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2232TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2232TRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2234IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2234IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2234IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2234IRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2234TDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2234TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2234TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2234TRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2252IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2252IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2252IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2252IRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2252TDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2252TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2252TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2252TRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2254IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty MSP430F2254IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2254IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2254IRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2254TDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2254TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2254TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2254TRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2272IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2272IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2272IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2272IRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2272TDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2272TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2272TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2272TRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2274IDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2274IDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2274IRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2274IRHAT ACTIVE QFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2274TDA ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2274TDAR ACTIVE TSSOP DA 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430F2274TRHAR ACTIVE QFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR MSP430F2274TRHAT ACTIVE QFN RHA 40 250 CU NIPDAU Level-3-260C-168 HR (1) Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2007 OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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