NSC CD4023C Triple 3-input nand(nor) gate Datasheet

CD4023M/CD4023C Triple 3-Input NAND Gate
CD4025M/CD4025C Triple 3-Input NOR Gate
General Description
Features
These triple gates are monolithic complementary MOS
(CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. All inputs are protected
against static discharge with diodes to VDD and VSS.
Y
Y
Y
Y
Wide supply voltage range
High noise immunity
5V – 10V parametric ratings
Low power
3.0V to 15V
0.45 VDD (typ.)
Connection Diagrams
Dual-In-Line Packages
CD4025M/CD4025C
CD4023M/CD4023C
TL/F/5955 – 1
Top View
TL/F/5955 – 2
Top View
Order Number CD4023 or CD4025
C1995 National Semiconductor Corporation
TL/F/5955
RRD-B30M105/Printed in U. S. A.
CD4023M/CD4023C Triple 3-Input NAND Gate
CD4025M/CD4025C Triple 3-Input NOR Gate
February 1988
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
Operating Temperature Range
CD4023M, CD4025M
CD4023C, CD4025C
Storage Temperature Range
b 65§ C to a 150§ C
Power Dissipation (PD)
Dual-In-Line
Small Outline
Operating VDD Range
VSSb to VDD a 0.3V
b 55§ C to a 125§ C
b 40§ C to a 85§ C
700 mW
500 mW
VSS a 3.0V to VSS a 15V
Lead Temperature
(Soldering, 10 seconds)
260§ C
DC Electrical Characteristics CD4023M, CD4025M
Limits
Symbol
Parameter
b 55§ C
Conditions
Min
Max
a 25§ C
Min
Typ
a 125§ C
Max
Min
Units
Max
IL
Quiescent Device
Current
VDD e 5.0V
VDD e 10V
0.05
0.1
0.001 0.05
0.001 0.1
3.0
6.0
mA
mA
PD
Quiescent Device
Dissipation/Package
VDD e 5.0V
VDD e 10V
0.25
1.0
0.005 0.25
0.01 1.0
15
60
mW
mW
VOL
Output Voltage
Low Level
VDD e 5.0V, VI e VDD, IO e 0A
VDD e 10V, VI e VDD, IO e 0A
0.05
0.05
0.05
0.05
V
V
VOH
Output Voltage
High Level
VDD e 5.0V, VI e VSS, IO e 0A
VDD e 10V, VI e VSS, IO e 0A
4.95
9.95
4.95
9.95
5.0
10
4.95
9.95
V
V
VNL
Noise Immunity
(All Inputs)
VDD e 5.0V, VO e 3.6V, IO e 0A
VDD e 10V, VO e 7.2V, IO e 0A
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH
Noise Immunity
(All Inputs)
VDD e 5.0V, VO e 0.95V, IO e 0A
VDD e 10V, VO e 2.9V, IO e 0A
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
IDN
Output Drive Current
VDD e 5.0V, VO e 0.4V, VI e VDD
N-Channel (4025) (Note 2) VDD e 10V, VO e 0.5V, VI e VDD
0.5
1.1
0.40
0.9
1.0
2.5
0.28
0.65
mA
mA
IDP
Output Drive Current
VDD e 5.0V, VO e 2.5V, VI e VSS b0.62
P-Channel (4025) (Note 2) VDD e 10V, VO e 9.5V, VI e VSS b0.62
b 0.5
b 0.5
b 2.0
b 1.0
b 0.35
b 0.35
mA
mA
IDN
Output Drive Current
VDD e 5.0V, VO e 0.4V, VI e VDD
N-Channel (4023) (Note 2) VDD e 10V, VO e 0.5V, VI e VDD
0.25
0.5
0.5
0.6
0.175
0.35
mA
mA
IDP
Output Drive Current
VDD e 5.0V, VO e 2.5V, VI e VSS b0.31
P-Channel (4023) (Note 2) VDD e 10V, VO e 9.5V, VI e VSS b0.75
b 0.175
b 0.4
mA
mA
II
Input Current
0.31
0.63
0
0
b 0.25 b 0.5
b 0.6 b 1.2
10
0.05
0.05
pA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: IDN and IDP are tested one output at a time.
2
DC Electrical Characteristics CD4023C, CD4025C
Limits
Symbol
Parameter
b 40§ C
Conditions
Min
Max
a 25§ C
Min
Typ
a 85§ C
Max
Min
Units
Max
IL
Quiescent Device
Current
VDD e 5.0V
VDD e 10V
0.05
5.0
0.005 0.5
0.005 5.0
15
30
mA
mA
PD
Quiescent Device
Dissipation/Package
VDD e 5.0V
VDD e 10V
2.5
50
0.025 2.5
0.05 50
75
300
mW
mW
VOL
Output Voltage
Low Level
VDD e 5.0V, VI e VDD, IO e 0A
VDD e 10V, VI e VDD, IO e 0A
0.01
0.01
0.05
0.05
V
V
VOH
Output Voltage
High Level
VDD e 5.0V, VI e VSS, IO e 0A
VDD e 10V, VI e VSS, IO e 0A
4.99
9.99
4.99
9.99
5.0
10
II
Input Current
VNL
Noise Immunity
(All Inputs)
VDD e 5.0V, VO e 3.6V, IO e 0A
VDD e 10V, VO e 7.2V, IO e 0A
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH
Noise Immunity
(All Inputs)
VDD e 5.0V, VO e 0.95V, IO e 0A
VDD e 10V, VO e 2.9V, IO e 0A
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
IDN
Output Drive Current
VDD e 5.0V, VO e 0.4V, VI e VDD
N-Channel (4025) (Note 2) VDD e 10V, VO e 0.5V, VI e VDD
0.35
0.72
0.3
0.6
1.0
2.5
0.24
0.48
mA
mA
IDP
Output Drive Current
VDD e 5.0V, VO e 2.5V, VI e VSS
P-Channel (4025) (Note 2) VDD e 10V, VO e 9.5V, VI e VSS
b 0.35
b 0.3
b 0.24
b 0.2
mA
mA
IDN
Output Drive Current
VDD e 5.0V, VO e 0.4V, VI e VDD
N-Channel (4023) (Note 2) VDD e 10V, VO e 0.5V, VI e VDD
0.145
0.3
0.095
0.2
mA
mA
IDP
Output Drive Current
VDD e 5.0V, VO e 2.5V, VI e VSS b0.145
P-Channel (4023) (Note 2) VDD e 10V, VO e 9.5V, VI e VSS b0.35
b 0.095
b 0.24
mA
mA
II
Input Current
0
0
0.01
0.01
4.95
9.95
10
b 0.3 b 2.0
b 0.25 b 1.0
0.12
0.25
0.5
0.6
b 0.12 b 0.5
b 0.3 b 1.2
10
V
V
pA
pA
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device
operation.
Note 2: IDN and IDP are tested one output at a time.
3
AC Electrical Characteristics* TA e 25§ C, CL e 15 pF, and input rise and fall times e 20 ns. Typical
temperature coefficient for all values of VDD e 0.3%/§ C
Symbol
Parameter
Conditions
tPHL
Propagation Delay Time
High to Low Level
tPLH
Min
Typ
Max
Units
VDD e 5.0V
VDD e 10V
35
25
50
40
ns
ns
Propagation Delay Time
Low to High Level
VDD e 5.0V
VDD e 10V
35
25
40
70
ns
ns
tTHL
Transition Time
High to Low Level
VDD e 5.0V
VDD e 10V
65
35
125
70
ns
ns
tTLH
Transition Time
Low to High Level
VDD e 5.0V
VDD e 10V
65
35
175
75
ns
ns
CI
Input Capacitance
Any Input
5.0
tPHL
Propagation Delay Time
High to Low Level
VDD e 5.0V
VDD e 10V
35
25
80
55
ns
ns
tPLH
Propagation Delay Time
Low to High Level
VDD e 5.0V
VDD e 10V
35
25
120
65
ns
ns
tTHL
Transition Time
High to Low Level
VDD e 5.0V
VDD e 10V
65
35
200
115
ns
ns
tTLH
Transition Time
Low to High Level
VDD e 5.0V
VDD e 10V
65
35
300
125
ns
ns
CI
Input Capacitance
Any Input
5.0
tPHL
Propagation Delay Time
High to Low Level
VDD e 5.0V
VDD e 10V
50
25
75
40
ns
ns
tPLH
Propagation Delay Time
Low to High Level
VDD e 5.0V
VDD e 10V
50
25
75
40
ns
ns
tTHL
Transition Time
High to Low Level
VDD e 5.0V
VDD e 10V
75
50
125
75
ns
ns
tTLH
Transition Time
Low to High Level
VDD e 5.0V
VDD e 10V
75
40
100
60
ns
ns
CI
Input Capacitance
Any Input
5.0
tPHL
Propagation Delay Time
High to Low Level
VDD e 5.0V
VDD e 10V
50
25
100
50
ns
ns
tPLH
Propagation Delay Time
Low to High Level
VDD e 5.0V
VDD e 10V
50
25
100
50
ns
ns
tTHL
Transition Time
High to Low Level
VDD e 5.0V
VDD e 10V
75
50
150
100
ns
ns
tTLH
Transition Time
Low to High Level
VDD e 5.0V
VDD e 10V
75
40
125
75
ns
ns
CI
Input Capacitance
Any Input
5.0
CD4025M
pF
CD4025C
pF
CD4023M
pF
CD4023C
*AC Parameters are guaranteed by DC correlated testing.
4
pF
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4023MJ, CD4023CJ, CD4025MJ or CD4025CJ
NS Package Number J14A
5
CD4023M/CD4023C Triple 3-Input NAND Gate
CD4025M/CD4025C Triple 3-Input NOR Gate
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number CD4023MN, CD4023CN, CD4025MN or CD4025CN
NS Package Number N14A
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