Catalyst CAT93C76SITE13 8k-bit microwire serial eeprom Datasheet

H
EE
GEN FR
ALO
CAT93C76 (Rev. A)
8K-Bit Microwire Serial EEPROM
LE
A D F R E ETM
FEATURES
■ High speed operation: 3MHz @ VCC
≥ 2.5V
■ Power-up inadvertant write protection
■ Low power CMOS technology
■ 1,000,000 Program/erase cycles
■ 1.8 to 5.5 volt operation
■ 100 year data retention
■ Selectable x8 or x16 memory organization
■ Industrial and extended temperature ranges
■ Self-timed write cycle with auto-clear
■ Sequential read
■ Software write protection
■ “Green” package option available
DESCRIPTION
The CAT93C76 is an 8K-bit Serial EEPROM memory
device which is configured as either registers of 16 bits
(ORG pin at VCC or Not Connected) or 8 bits (ORG pin
at GND). Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT93C76 is
manufactured using Catalyst’s advanced CMOS
EEPROM floating gate technology. The device is
designed to endure 1,000,000 program/erase cycles
and has a data retention of 100 years. The device is
available in 8-pin DIP, SOIC, TSSOP and 8-pad TDFN
packages.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
CS
SK
1
DI
DO
3
8
7
6
5
2
4
VCC
SOIC Package (S, V)
DIP Package (P, L)
VCC
NC
ORG
GND
1
2
3
4
CS
SK
DI
DO
8
7
6
5
VCC
NC
ORG
GND
ORG
DI
CS
DO
SK
TSSOP Package (U,Y)
CS
SK
DI
DO
1
2
8
7
3
4
6
5
TDFN Package (RD4, ZD4)
CS 1
8 VCC
SK 2
7 NC
DI 3
6 ORG
DO 4
5 GND
Top View
VCC
NC
ORG
GND
GND
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
SK
Serial Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
+1.8 to 5.5V Power Supply
GND
Ground
ORG
Memory Organization
NC
No Connection
Note: When the ORG pin is connected to VCC, x16 organization is
selected. When it is connected to ground, x8 organization is selected.
If the ORG pin is left unconnected, then an internal
pull-up device will select x16 organization.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
Doc. No. 1090, Rev. A
CAT93C76
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Stresses exceeding those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other conditions
outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute
maximum rating for extended periods may affect device
performance and reliability.
Storage Temperature ........................ -65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............. -2.0V to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
NEND(3)
Endurance
MIL-STD-883, Test Method 1033
1,000,000
Typ
Max
Cycles/Byte
Units
TDR(3)
Data Retention
MIL-STD-883, Test Method 1008
100
Years
VZAP(3)
ESD Susceptibility
MIL-STD-883, Test Method 3015
2000
Volts
ILTH(3)(4)
Latch-Up
JEDEC Standard 17
100
mA
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +5.5V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC1
Power Supply Current
(Write)
ICC2
Min
Typ
Max
Units
fSK = 1MHz
VCC = 5.0V
1
3
mA
Power Supply Current
(Read)
fSK = 1MHz
VCC = 5.0V
300
500
µA
ISB1
Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG=GND
2
10
µA
ISB2
Power Supply Current
(Standby) (x16Mode)
CS=0V
ORG=Float or VCC
0(5)
10
µA
ILI
Input Leakage Current
VIN = 0V to VCC
0(5)
10
µA
10
µA
10
µA
ILO
Output Leakage Current
VOUT = 0V to VCC, CS = 0V
0(5)
ILORG
ORG Pin Leakage Current
ORG = GND or ORG = VCC
1
VIL1
Input Low Voltage
4.5V ≤ VCC ≤ 5.5V
-0.1
0.8
V
VIH1
Input High Voltage
4.5V ≤ VCC ≤ 5.5V
2
VCC + 1
V
VIL2
Input Low Voltage
1.8V ≤ VCC < 4.5V
0
VCC x 0.2
V
VIH2
Input High Voltage
1.8V ≤ VCC < 4.5V
VCC x 0.7
VCC+1
V
VOL1
Output Low Voltage
4.5V ≤ VCC ≤ 5.5V
IOL = 2.1mA
0.4
V
VOH1
Output High Voltage
4.5V ≤ VCC ≤ 5.5V
IOH = -400µA
VOL2
Output Low Voltage
1.8V ≤ VCC < 4.5V
IOL = 100µA
VOH2
Output High Voltage
1.8V ≤ VCC < 4.5V
IOH = -100µA
2.4
V
0.1
VCC - 0.2
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second.
(3) These parameters are tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on I/O pins from –1V to VCC +1V.
(5) 0 µA is defined as less than 900 nA.
Doc. No. 1090, Rev. A
2
CAT93C76
PIN CAPACITANCE
Symbol
Test
Conditions
COUT
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
(1)
CIN(1)
Min
Typ
Max
Units
VOUT=0V
5
pF
VIN=0V
5
pF
INSTRUCTION SET(2)
Address
Data
Instruction
Start Bit
Opcode
x8
x16
x8
READ
1
10
A10-A0
A9-A0
Read Address AN– A0
ERASE
1
11
A10-A0
A9-A0
Clear Address AN– A0
WRITE
1
01
A10-A0
A9-A0
EWEN
1
00
11XXXXXXXXX 11XXXXXXXX
Write Enable
EWDS
1
00
00XXXXXXXXX 00XXXXXXXX
Write Disable
ERAL
1
00
10XXXXXXXXX 10XXXXXXXX
Clear All Addresses
WRAL
1
00
01XXXXXXXXX 01XXXXXXXX
D7-D0
D7-D0
x16
Comments
D15-D0 Write Address AN– A0
D15-D0 Write All Addresses
A.C. CHARACTERISTICS
Limits
VCC =
1.8V-2.5V
Symbol
Parameter
Test
Conditions
Min
Max
VCC =
2.5V-5.5V
Min
Max
Units
tCSS
CS Setup Time
100
50
ns
tCSH
CS Hold Time
0
0
ns
tDIS
DI Setup Time
100
50
ns
tDIH
DI Hold Time
100
50
ns
tPD1
Output Delay to 1
tPD0
Output Delay to 0
tHZ(1)
Output Delay to High-Z
tEW
250
150
ns
CL = 100pF
250
150
ns
(3)
150
100
ns
5
5
ms
Program/Erase Pulse Width
tCSMIN
Minimum CS Low Time
200
150
ns
tSKHI
Minimum SK High Time
250
150
ns
tSKLOW
Minimum SK Low Time
250
150
ns
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
250
DC
1000
DC
100
ns
3000
kHz
NOTE:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) Address bit A10 for the 1,024x8 org. and A9 for the 512x16 org. are “don’t care” bits, but must be kept at either a “1” or
“0” for READ, WRITE and ERASE commands.
(3) The input levels and timing reference points are shown in the “AC Test Conditions” table.
3
Doc. No. 1090, Rev. A
CAT93C76
POWER-UP TIMING (1)(2)
Symbol
tPUR
tPUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Max
1
1
≤ 50ns
0.4V to 2.4V
0.8V, 2.0V
0.2VCC to 0.7VCC
0.5VCC
Units
ms
ms
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
NOTE:
(1) These parameters are tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
DEVICE OPERATION
Read
The CAT93C76 is a 8192-bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C76 can be organized as either registers of
16 bits or 8 bits. When organized as X16, seven 13-bit
instructions control the read, write and erase operations
of the device. When organized as X8, seven 14-bit
instructions control the read, write and erase
operations of the device. The CAT93C76 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C76 will
come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
For the CAT93C76, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data
word in a sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit. All subsequent data words will follow
without a dummy zero bit.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
The ready/busy status can be determined after the start
of a write operation by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DI pin. The DO pin will enter the high impedance state on
the falling edge of the clock (SK). Placing the DO pin into
the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied
together to form a common DI/O pin.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C76 can be determined by selecting the device
and polling the DO pin. Since this device features AutoClear before write, it is NOT necessary to erase a
memory location before it is written into.
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 10-bit
address (an additional bit when organized X8) and for
write operations a 16-bit data field (8-bit for X8
organizations). The most significant bit of the address is
“don’t care” but it must be present.
Doc. No. 1090, Rev. A
4
CAT93C76
Figure 1. Sychronous Data Timing
tSKHI
tSKLOW
tCSH
SK
tDIS
tDIH
VALID
DI
VALID
tCSS
CS
tDIS
tPD0,tPD1
DO
tCSMIN
DATA VALID
Figure 2. Read Instruction Timing
SK
CS
Don't Care
AN
DI
1
1
AN–1
A0
0
HIGH-Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D 7 . . . D0
Address + 2
D15 . . . D0
or
D 7 . . . D0
Address + n
D15 . . .
or
D7 . . .
Figure 3. Write Instruction Timing
SK
tCSMIN
AN
DI
1
0
AN-1
A0
DN
D0
1
tSV
DO
STANDBY
STATUS
VERIFY
CS
tHZ
BUSY
HIGH-Z
READY
HIGH-Z
tEW
5
Doc. No. 1090, Rev. A
CAT93C76
Erase
Write All
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clocking
of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93C76 can be determined by selecting the
device and polling the DO pin. Once cleared, the content
of a cleared location returns to a logical “1” state.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
status of the CAT93C76 can be determined by selecting
the device and polling the DO pin. It is not necessary for
all memory locations to be cleared before the WRAL
command is executed.
Erase/Write Enable and Disable
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edge of the clock (SK) in order to start the self-timed high
voltage cycle. This is important because if CS is brought
low before or after this specific frame window, the
addressed location will not be programmed or erased.
The CAT93C76 powers up in the write disable state. Any
writing after power-up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled,
it will remain enabled until power to the device is removed,
or the EWDS instruction is sent. The EWDS instruction
can be used to disable all CAT93C76 write and clear
instructions, and will prevent any accidental writing or
clearing of the device. Data can be read normally from
the device regardless of the write enable/disable status.
Power-On Reset (POR)
The CAT93C76 incorporates Power-On Reset (POR)
circuitry which protects the device against malfunctioning
while VCC is lower than the recommended operating
voltage.
Erase All
The device will power up into a read-only state and will
power-down into a reset state when VCC crosses the
POR level of ~1.3 V.
Upon receiving an ERAL command, the CS (Chip Select)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C76 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Figure 4. Erase Instruction Timing
SK
STATUS VERIFY
CS
AN
DI
1
1
tCS
A0
AN-1
STANDBY
1
tSV
tHZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
tEW
Doc. No. 1090, Rev. A
6
CAT93C76
Figure 5. EWEN/EWDS Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCS
DI
1
0
0
0
1
tSV
tHZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
tEW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCSMIN
DI
1
0
0
0
DN
1
D0
tSV
tHZ
DO
BUSY
READY
HIGH-Z
tEW
7
Doc. No. 1090, Rev. A
CAT93C76
ORDERING INFORMATION
Prefix
CAT
Optional
Company ID
Device #
93C76
Product
Number
Suffix
S
I
Temperature Range
I = Industrial (-40°C to +85°C)
E = Extended (-40°C to +125°C)
TE13
Rev A
(2)
Tape & Reel
Die Revision
Package
P = PDIP
S = SOIC (JEDEC)
U = TSSOP
RD4 = TDFN (3x3mm)
L = PDIP (Lead free, Halogen free)
V = SOIC, JEDEC (Lead free, Halogen free)
Y = TSSOP (Lead free, Halogen free)
ZD4 = TDFN (3x3mm, Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 93C76SI-TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage,
Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA.) For additional
information, please contact your Catalyst sales office.
Doc. No. 1090, Rev. A
8
CAT93C76
REVISION HISTORY
Date
08/11/04
Revision Comments
A
Initial Issue
9
Doc. No. 1090, Rev. A
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Publication #:
Revison:
Issue date:
1090
A
08/11/04