NSC LMC662 Cmos dual operational amplifier Datasheet

LMC662
CMOS Dual Operational Amplifier
General Description
The LMC662 CMOS Dual operational amplifier is ideal for
operation from a single supply. It operates from +5V to +15V
and features rail-to-rail output swing in addition to an input
common-mode range that includes ground. Performance
limitations that have plagued CMOS amplifiers in the past
are not a problem with this design. Input VOS, drift, and
broadband noise as well as voltage gain into realistic loads
(2 kΩ and 600Ω) are all equal to or better than widely accepted bipolar equivalents.
This chip is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
See the LMC660 datasheet for a Quad CMOS operational
amplifier with these same features.
Features
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Rail-to-rail output swing
Specified for 2 kΩ and 600Ω loads
High voltage gain: 126 dB
Low input offset voltage: 3 mV
Low offset voltage drift: 1.3 µV/˚C
Ultra low input bias current: 2 fA
Input common-mode range includes V−
Operating range from +5V to +15V supply
ISS = 400 µA/amplifier; independent of V+
Low distortion: 0.01% at 10 kHz
Slew rate: 1.1 V/µs
Available in extended temperature range (−40˚C to
+125˚C); ideal for automotive applications
n Available to a Standard Military Drawing specification
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Applications
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High-impedance buffer or preamplifier
Precision current-to-voltage converter
Long-term integrator
Sample-and-hold circuit
Peak detector
Medical instrumentation
Industrial controls
Automotive sensors
Connection Diagram
8-Pin DIP/SO
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Ordering Information
Package
Temperature Range
Military
8-Pin
Extended
Industrial
Commercial
LMC662AMJ/883
NSC
Drawing
Transport
Media
J08A
Rail
Ceramic DIP
8-Pin
LMC662EM
LMC662AIM
LMC662CM
M08A
Small Outline
Rail,
Tape and Reel
8-Pin
LMC662EN
LMC662AIN
LMC662CN
N08E
Rail
D08C
Rail
Molded DIP
8-Pin
Side Brazed
LMC662AMD
Ceramic DIP
© 1999 National Semiconductor Corporation
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www.national.com
LMC662 CMOS Dual Operational Amplifier
April 1998
Absolute Maximum Ratings (Note 3)
ESD Tolerance (Note 8)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings(Note 3)
Temperature Range
LMC662AMJ/883,
LMC662AMD
LMC662AI
LMC662C
LMC662E
Supply Voltage Range
Power Dissipation
Thermal Resistance (θJA) (Note 11)
8-Pin Ceramic DIP
8-Pin Molded DIP
8-Pin SO
8-Pin Side Brazed Ceramic DIP
± Supply Voltage
Differential Input Voltage
Supply Voltage (V+ − V−)
Output Short Circuit to V+
Output Short Circuit to V−
Lead Temperature
(Soldering, 10 sec.)
Storage Temp. Range
Voltage at Input/Output Pins
Current at Output Pin
Current at Input Pin
Current at Power Supply Pin
Power Dissipation
Junction Temperature
1000V
16V
(Note 12)
(Note 1)
260˚C
−65˚C to +150˚C
(V+) +0.3V, (V−) −0.3V
± 18 mA
± 5 mA
35 mA
(Note 2)
150˚C
−55˚C ≤ TJ ≤ +125˚C
−40˚C ≤ TJ ≤ +85˚C
0˚C ≤ TJ ≤ +70˚C
−40˚C ≤ TJ ≤ +125˚C
4.75V to 15.5V
(Note 10)
100˚C/W
101˚C/W
165˚C/W
100˚C/W
DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V,
V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
Parameter
Conditions
Input Offset Voltage
Typ
(Note 4)
LMC662AMJ/883
1
Input Offset Voltage
LMC662AI
LMC662C
LMC662E
Units
LMC662AMD
Limit
Limit
Limit
Limit
(Notes 4, 9)
(Note 4)
(Note 4)
(Note 4)
3
3
6
6
mV
3.5
3.3
6.3
6.5
max
1.3
µV/˚C
Average Drift
Input Bias Current
0.002
20
100
Input Offset Current
0.001
0V ≤ VCM ≤ 12.0V
V+ = 15V
83
83
Rejection Ratio
5V ≤ V+ ≤ 15V
VO = 2.5V
Negative Power Supply
0V ≤ V− ≤ −10V
94
Rejection Ratio
Positive Power Supply
60
max
100
2
1
60
max
70
70
63
63
dB
68
68
62
60
min
70
70
63
63
dB
68
68
62
60
min
84
84
74
74
dB
82
83
73
70
min
−0.1
−0.1
−0.1
−0.1
V
0
0
0
0
max
V+ − 2.3
V+ − 2.3
V+ − 2.3
V+ − 2.3
V
V+ − 2.6
V+ − 2.5
V+ − 2.4
V+ − 2.6
min
V/mV
20
pA
TeraΩ
Rejection Ratio
Input Common-Mode
V+ = 5V & 15V
Voltage Range
For CMRR ≥ 50 dB
−0.4
V+ − 1.9
Large Signal
RL = 2 kΩ (Note 5)
Voltage Gain
Sourcing
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2
>1
Input Resistance
Common Mode
pA
4
2000
400
440
300
200
300
400
200
100
min
180
90
90
V/mV
Sinking
500
180
70
120
80
40
min
RL = 600Ω (Note 5)
1000
200
220
150
100
V/mV
Sourcing
150
200
100
75
min
Sinking
100
100
50
50
V/mV
35
60
40
20
min
250
2
DC Electrical Characteristics
(Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V,
V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
Parameter
Output Swing
Conditions
V+ = 5V
RL = 2 kΩ to V+/2
Typ
(Note 4)
LMC662AMJ/883
4.87
0.10
V+ = 5V
RL = 600Ω to V+/2
4.61
0.30
V+ = 15V
RL = 2 kΩ to V+/2
14.63
0.26
V+ = 15V
RL = 600Ω to V+/2
13.90
0.79
Output Current
V+ = 5V
Sourcing, VO = 0V
Sinking, VO = 5V
Output Current
V+ = 15V
Sourcing, VO = 0V
Sinking, VO = 13V
22
21
40
39
(Note 12)
Supply Current
Both Amplifiers
VO = 1.5V
LMC662AI
LMC662C
LMC662E
Units
LMC662AMD
0.75
Limit
Limit
Limit
Limit
(Notes 4, 9)
(Note 4)
(Note 4)
(Note 4)
4.82
4.82
4.78
4.78
V
4.77
4.79
4.76
4.70
min
0.15
0.15
0.19
0.19
V
0.19
0.17
0.21
0.25
max
4.41
4.41
4.27
4.27
V
4.24
4.31
4.21
4.10
min
0.50
0.50
0.63
0.63
V
0.63
0.56
0.69
0.75
max
14.50
14.50
14.37
14.37
V
14.40
14.44
14.32
14.25
min
0.35
0.35
0.44
0.44
V
0.43
0.40
0.48
0.55
max
13.35
13.35
12.92
12.92
V
13.02
13.15
12.76
12.60
min
1.16
1.16
1.45
1.45
V
1.42
1.32
1.58
1.75
max
16
16
13
13
mA
12
14
11
9
min
16
16
13
13
mA
12
14
11
9
min
19
28
23
23
mA
19
25
21
15
min
19
28
23
23
mA
19
24
20
15
min
1.3
1.3
1.6
1.6
mA
1.8
1.5
1.8
1.9
max
AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for TJ = 25˚C. Boldface limits apply at the temperature extremes. V+ = 5V,
V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
Parameter
Slew Rate
Conditions
(Note 6)
Typ
(Note
4)
LMC662AMJ/883
LMC662AI
LMC662C
LMC662E
Units
LMC662AMD
1.1
Limit
Limit
Limit
Limit
(Notes 4, 9)
(Note 4)
(Note 4)
(Note 4)
0.8
0.8
0.8
0.8
0.5
0.6
0.7
0.4
V/µs
min
Gain-Bandwidth Product
1.4
MHz
Phase Margin
50
Deg
Gain Margin
17
dB
dB
Amp-to-Amp Isolation
(Note 7)
130
Input-Referred Voltage Noise
F = 1 kHz
22
Input-Referred Current Noise
F = 1 kHz
0.0002
Total Harmonic Distortion
F = 10 kHz, AV = −10
RL = 2 kΩ, VO = 8 VPP
%
0.01
V+ = 15V
3
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AC Electrical Characteristics
(Continued)
Note 1: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts
can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of ± 30 mA over long term may adversely affect reliability.
Note 2: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD =
(TJ(max)–TA)/θJA.
Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 4: Typical values represent the most likely parametric norm. Limits are guaranteed by testing or correlation.
Note 5: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.
Note 6: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.
Note 7: Input referred. V+ = 15V and RL = 10 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP.
Note 8: Human body model, 1.5 kΩ in series with 100 pF.
Note 9: A military RETS electrical test specification is available on request. At the time of printing, the LMC662AMJ/883 RETS spec complied fully with the boldface
limits in this column. The LMC662AMJ/883 may also be procured to a Standard Military Drawing specification.
Note 10: For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA.
Note 11: All numbers apply for packages soldered directly into a PC board.
Note 12: Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected.
Typical Performance Characteristics
Supply Current vs
Supply Voltage
VS = ± 7.5V, TA = 25˚C unless otherwise specified
Input Bias Current
Offset Voltage
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Output Characteristics
Current Sinking
Output Characteristics
Current Sourcing
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Input Voltage Noise
vs Frequency
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4
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Typical Performance Characteristics
CMRR vs Frequency
VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued)
Open-Loop Frequency
Response
Frequency Response vs
Capacitive Load
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Non-Inverting Large Signal
Pulse Response
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Stability vs
Capacitive Load
Stability vs
Capacitive Load
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Note: Avoid resistive loads of less than 500Ω,
as they may cause instability.
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Note: Avoid resistive loads of less than 500Ω,
as they may cause instability.
Application Hints
AMPLIFIER TOPOLOGY
The topology chosen for the LMC662, shown in Figure 1, is
unconventional (compared to general-purpose op amps) in
that the traditional unity-gain buffer output stage is not used;
instead, the output is taken directly from the output of the integrator, to allow rail-to-rail output swing. Since the buffer
traditionally delivers the power to the load, while maintaining
high op amp gain and stability, and must withstand shorts to
either rail, these tasks now fall to the integrator.
As a result of these demands, the integrator is a compound
affair with an embedded gain stage that is doubly fed forward
(via Cf and Cff) by a dedicated unity-gain compensation
driver. In addition, the output portion of the integrator is a
push-pull configuration for delivering heavy loads. While
sinking current the whole amplifier path consists of three
gain stages with one stage fed forward, whereas while
sourcing the path contains four gain stages with two fed
forward.
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FIGURE 1. LMC662 Circuit Topology (Each Amplifier)
The large signal voltage gain while sourcing is comparable
to traditional bipolar op amps, even with a 600Ω load. The
gain while sinking is higher than most CMOS op amps, due
to the additional gain stage; however, under heavy load
(600Ω) the gain will be reduced as indicated in the Electrical
Characteristics.
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Application Hints
the following value of feedback capacitor is recommended:
(Continued)
COMPENSATING INPUT CAPACITANCE
The high input resistance of the LMC662 op amps allows the
use of large feedback and source resistor values without losing gain accuracy due to loading. However, the circuit will be
especially sensitive to its layout when these large-value resistors are used.
Every amplifier has some capacitance between each input
and AC ground, and also some differential capacitance between the inputs. When the feedback network around an
amplifier is resistive, this input capacitance (along with any
additional capacitance due to circuit board traces, the
socket, etc.) and the feedback resistors create a pole in the
feedback path. In the following General Operational Amplifier
Circuit, Figure 2, the frequency of this pole is
If
the feedback capacitor should be:
Note that these capacitor values are usually significantly
smaller than those given by the older, more conservative formula:
where CS is the total capacitance at the inverting input, including amplifier input capacitance and any stray capacitance from the IC socket (if one is used), circuit board traces,
etc., and RP is the parallel combination of RF and RIN. This
formula, as well as all formulae derived below, apply to inverting and non-inverting op-amp configurations.
When the feedback resistors are smaller than a few kΩ, the
frequency of the feedback pole will be quite high, since CS is
generally less than 10 pF. If the frequency of the feedback
pole is much higher than the “ideal” closed-loop bandwidth
(the nominal closed-loop bandwidth in the absence of CS),
the pole will have a negligible effect on stability, as it will add
only a small amount of phase shift.
However, if the feedback pole is less than approximately 6 to
10 times the “ideal” −3 dB frequency, a feedback capacitor,
CF, should be connected between the output and the inverting input of the op amp. This condition can also be stated in
terms of the amplifier’s low-frequency noise gain: To maintain stability, a feedback capacitor will probably be needed if
DS009763-6
CS consists of the amplifier’s input capacitance plus any stray capacitance
from the circuit board and socket. CF compensates for the pole caused by
CS and the feedback resistor.
FIGURE 2. General Operational Amplifier Circuit
Using the smaller capacitors will give much higher bandwidth with little degradation of transient response. It may be
necessary in any of the above cases to use a somewhat
larger feedback capacitor to allow for unexpected stray capacitance, or to tolerate additional phase shifts in the loop, or
excessive capacitive load, or to decrease the noise or bandwidth, or simply because the particular circuit implementation needs more feedback capacitance to be sufficiently
stable. For example, a printed circuit board’s stray capacitance may be larger or smaller than the breadboard’s, so the
actual optimum value for CF may be different from the one
estimated using the breadboard. In most cases, the value of
CF should be checked on the actual circuit, starting with the
computed value.
where
is the amplifier’s low-frequency noise gain and GBW is the
amplifier’s gain bandwidth product. An amplifier’s
low-frequency noise gain is represented by the formula
CAPACITIVE LOAD TOLERANCE
Like many other op amps, the LMC662 may oscillate when
its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration
most sensitive to oscillation is a unity-gain follower. See the
Typical Performance Characteristics.
regardless of whether the amplifier is being used in an inverting or non-inverting mode. Note that a feedback capacitor is
more likely to be needed when the noise gain is low and/or
the feedback resistor is large.
If the above condition is met (indicating a feedback capacitor
will probably be needed), and the noise gain is large enough
that:
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The load capacitance interacts with the op amp’s output resistance to create an additional pole. If this pole frequency is
sufficiently low, it will degrade the op amp’s phase margin so
that the amplifier is no longer stable at low gains. As shown
in Figure 3, the addition of a small resistor (50Ω to 100Ω) in
series with the op amp’s output, and a capacitor (5 pF to 10
pF) from inverting input to output pins, returns the phase
6
Application Hints
ures 6, 7, 8 for typical connections of guard rings for standard op-amp configurations. If both inputs are active and at
high impedance, the guard can be tied to ground and still
provide some protection; see Figure 9.
(Continued)
margin to a safe value without interfering with
lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all
cases, the output will ring heavily when the load capacitance
is near the threshold for oscillation.
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FIGURE 3. Rx, Cx Improve Capacitive Load Tolerance
Capacitive load driving capability is enhanced by using a pull
up resistor to V+ Figure 4. Typically a pull up resistor conducting 500 µA or more will significantly improve capacitive
load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain
of the amplifier can also be affected by the pull up resistor
(see Electrical Characteristics).
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FIGURE 5. Example, using the LMC660,
of Guard Ring in P.C. Board Layout
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FIGURE 4. Compensating for Large Capacitive Loads
with a Pull Up Resistor
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PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC662, typically less
than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC662’s inputs and the
terminals of capacitors, diodes, conductors, resistors, relay
terminals, etc. connected to the op-amp’s inputs. See Figure
5. To have a significant effect, guard rings should be placed
on both the top and bottom of the PC board. This PC foil
must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of an input. This
would cause a 100 times degradation from the LMC662’s actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 1011Ω would
cause only 0.05 pA of leakage current, or perhaps a minor
(2:1) degradation of the amplifier’s performance. See Fig-
FIGURE 6. Guard Ring Connections: Inverting
Amplifier
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FIGURE 7. Guard Ring Connections: Non-Inverting
Amplifier
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FIGURE 8. Guard Ring Connections: Follower
7
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Application Hints
BIAS CURRENT TESTING
(Continued)
The test method of Figure 11 is appropriate for bench-testing
bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is
opened, then
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FIGURE 9. Guard Ring Connections: Howland Current
Pump
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring. See Figure
10.
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FIGURE 11. Simple Input Bias Current Test Circuit
A suitable capacitor for C2 would be a 5 pF or 10 pF silver
mica, NPO ceramic, or air-dielectric. When determining the
magnitude of Ib−, the leakage of the capacitor and socket
must be taken into account. Switch S2 should be left shorted
most of the time, or else the dielectric absorption of the capacitor C2 could cause errors.
Similarly, if S1 is shorted momentarily (while leaving S2
shorted)
where Cx is the stray capacitance at the + input.
DS009763-21
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board.)
FIGURE 10. Air Wiring
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8
Typical Single-Supply Applications
(V+ = 5.0 VDC)
Additional single-supply applications ideas can be found in
the LM358 datasheet. The LMC662 is pin-for-pin compatible
with the LM358 and offers greater bandwidth and input resistance over the LM358. These features will improve the performance of many existing single-supply applications. Note,
however, that the supply voltage range of the LM662 is
smaller than that of the LM358.
Sine-Wave Oscillator
Low-Leakage Sample-and-Hold
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Instrumentation Amplifier
Oscillator frequency is determined by R1, R2, C1, and C2:
fOSC = 1/2πRC
where R = R1 = R2 and C = C1 = C2.
This circuit, as shown, oscillates at 2.0 kHz with a
peak-to-peak output swing of 4.5V
1 Hz Square-Wave Oscillator
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Power Amplifier
For good CMRR over temperature, low drift resistors should
be used. Matching of R3 to R6 and R4 to R7 affects CMRR.
Gain may be adjusted through R2. CMRR may be adjusted
through R7.
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Typical Single-Supply Applications
(V+ = 5.0 VDC) (Continued)
10 Hz High-Pass Filter
10 Hz Bandpass Filter
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fO = 10 Hz
Q = 2.1
Gain = −8.8
fc = 10 Hz
d = 0.895
Gain = 1
2 dB passband ripple
1 Hz Low-Pass Filter
(Maximally Flat, Dual Supply Only)
High Gain Amplifier with
Offset Voltage Reduction
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Gain = −46.8
Output offset voltage reduced to the level of the input offset voltage of the
bottom amplifier (typically 1 mV).
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10
Physical Dimensions
inches (millimeters) unless otherwise noted
Hermatic Dual-In-Line Pkg. (D)
Order Number LMC662AMD
NS Package Number D08C
Ceramic Dual-In-Line Pkg. (J)
Order Number LMC662AMJ/883
NS Package Number J08A
11
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Small Outline Dual-In-Line Pkg. (M)
Order Number LMC662AIM, LMC662CM or LMC662EM
NS Package Number M08A
Molded Dual-In-Line Pkg. (N)
Order Number LMC662AIN, LMC662CN or LMC662EN
NS Package Number N08E
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12
LMC662 CMOS Dual Operational Amplifier
Notes
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