Cypress CY7C1370BV25-200AC 512k x 36/1m x 18 pipelined sram with nobl architecture Datasheet

CY7C1372BV25
CY7C1370BV25
512K x 36/1M x 18 Pipelined SRAM
with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between Write and
Read cycles
• Fast clock speed: 200,167, 150, and 133 MHz
• Fast access time: 3.0, 3.4, 3.8, 4.2 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 2.5V +5%
• Single WE (Read/Write) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte Write (BWSa–BWSd) control (may be
tied LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA and 100-pin TQFP
packages
• Automatic power-down available using zz mode or CE
deselect
Functional Description
The CY7C1370BV25 and CY7C1372BV25 SRAMs are
designed to eliminate dead cycles when transitions from
READ to WRITE or vice versa. These SRAMs are optimized
for 100 percent bus utilization and achieves Zero Bus Latency.
They integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells,
respectively, with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. The Cypress
Synchronous Burst SRAM family employs high-speed,
low-power CMOS designs using advanced single layer
polysilicon, threelayer metal technology. Each memory cell
consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE1, CE2 and CE3), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Selects (BWSa, BWSb, BWSc
and BWSd), and Read-Write control (WE). BWSc and BWSd
apply to CY7C1370BV25 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A Clock Enable (CEN) pin allows operation of the
CY7C1370BV25/CY7C1372BV25 to be suspended as long as
necessary. All synchronous inputs are ignored when (CEN) is
HIGH and the internal device registers will hold their previous
values.
There are three Chip Enable (CE1, CE2, CE3) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(Read or Write) will be completed. The data bus will be in
high-impedance state two cycles after chip is deselected or a
Write cycle is initiated.
The CY7C1370BV25 and CY7C1372BV25 have an on-chip
two-bit burst counter. In the burst mode, the CY7C1370BV25
and CY7C1372BV25 provide four cycles of data for a single
address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Logic Block Diagram
CLK
CE
D
Data-In REG.
Q
OUTOUT
REGISTERS
and LOGIC
ADV/LD
Ax
CY7C1370
CY7C1372
AX
X = 18:0
X = 19:0
DQX
X = a, b, c, d
X = a, b
DPX
X = a, b, c, d
X = a, b
BWSX
X = a, b, c, d
X = a, b
CEN
CE1
CE2
CE3
WE
BWSx
256K × 36/
512K × 18
MEMORY
ARRAY
CONTROL
and WRITE
LOGIC
DQx
DPx
Mode
OE
Cypress Semiconductor Corporation
Document #: 38-05252 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
Revised April 8, 2002
CY7C1372BV25
CY7C1370BV25
Selection Guide
200 MHz
167 MHz
150 MHz
133 MHz
Unit
Maximum Access Time
3.0
3.4
3.8
4.2
ns
Maximum Operating Current
280
230
190
160
mA
Maximum CMOS Standby Current
30
30
30
30
mA
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DPb
DQb
DQb
VDDQ
VSS
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DPb
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1372BV25
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document #: 38-05252 Rev. **
A
DNU
DNU
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DPa
NC
NC
NC
MODE
A
A
A
A
A1
A0
DNU
DNU
VS
VDD
DNU
DNU
A
A
A
A
A
A
A
CY7C1370BV25
(512K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DNU
DNU
VSS
VDD
DPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWSb
BWSa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWSd
BWSc
BWSb
BWSa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
100-pin TQFP Packages
A
NC
NC
VDDQ
VSS
NC
DPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
Page 2 of 26
CY7C1372BV25
CY7C1370BV25
Pin Configurations (continued)
119-ball Bump BGA
CY7C1370BV25
(512K × 36)–7 × 17 BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
A
VDDQ
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
DQc
DPc
VSS
NC
VSS
DPb
DQb
DQc
DQc
VSS
CE1
VSS
DQb
DQb
R
T
U
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
DQc
DQc
BWSc
A
BWSb
DQb
DQb
DQc
VDDQ
DQc
VDD
VSS
NC
WE
VDD
VSS
NC
DQb
VDD
DQb
VDDQ
DQd
DQd
DQd
DQd
VSS
BWSd
CLK
NC
VSS
BWSa
DQa
DQa
DQa
DQa
VDDQ
VDDQ
DQd
VSS
CEN
VSS
DQa
DQd
DQd
VSS
A1
VSS
DQa
DQa
DQd
DPd
VSS
A0
VSS
DPa
DQa
NC
A
MODE
VDD
NC
A
NC
NC
64M
A
A
A
32M
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
CY7C1372BV25
(1M × 18)–7 × 17 BGA
1
2
3
4
5
6
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
VDDQ
A
A
A
A
A
VDDQ
NC
CE2
A
ADV/LD
A
CE3
NC
NC
R
T
U
Document #: 38-05252 Rev. **
NC
A
A
VDD
A
A
DQb
NC
VSS
NC
VSS
DPa
NC
NC
DQb
VSS
CE1
VSS
NC
DQa
VDDQ
NC
VSS
OE
VSS
DQa
VDDQ
NC
DQb
VDDQ
DQb
NC
VDD
BWSb
VSS
NC
A
WE
VDD
VSS
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
NC
DQb
VSS
CLK
VSS
NC
DQa
DQb
NC
VSS
NC
BWSa
DQa
NC
VDDQ
DQb
VSS
CEN
VSS
NC
VDDQ
DQb
NC
VSS
A1
VSS
DQa
NC
NC
DPb
VSS
A0
VSS
NC
DQa
NC
A
MODE
VDD
NC
A
NC
64M
A
A
32M
A
A
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Page 3 of 26
CY7C1372BV25
CY7C1370BV25
Pin Configurations (continued)
165-ball Bump FBGA
CY7C1370BV25
(512K × 36)–11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE1
BWSc
BWSb
CE3
CEN
ADV/LD
A
A
NC
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
DPc
A
NC
CE2
VDDQ
BWSd
VSS
BWSa
VSS
CLK
VSS
WE
VSS
OE
VSS
A
VDDQ
A
NC
128M
DPb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
R
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
NC
DQd
VDD
DQd
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
DQa
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DPd
NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
DPa
NC
64M
A
A
DNU
A1
DNU
A
A
A
NC
MODE
32M
A
A
DNU
A0
DNU
A
A
A
A
CY7C1372BV25
(1M × 18)–11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE1
BWSb
NC
CE3
CEN
ADV/LD
A
A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC
NC
A
NC
CE2
VDDQ
NC
VSS
BWSa
VSS
CLK
VSS
WE
VSS
OE
VSS
A
VDDQ
A
NC
128M
DPa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDD
NC
NC
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
NC
VDDQ
NC
DQa
ZZ
NC
DQb
DQb
NC
NC
VDDQ
VDDQ
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDDQ
VDDQ
DQa
DQa
NC
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DPb
NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
NC
NC
64M
A
A
DNU
A1
DNU
A
A
A
NC
MODE
32M
A
A
DNU
A0
DNU
A
A
A
A
R
Document #: 38-05252 Rev. **
Page 4 of 26
CY7C1372BV25
CY7C1370BV25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
InputSynchronous
Address Inputs used to select one of the 524,288/1048576 address locations. Sampled at
the rising edge of CLK.
BWSa
BWSb
BWSc
BWSd
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb controls DQb and
DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a Write sequence.
ADV/LD
InputSynchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2 and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the device
to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE
is masked during the data portion of a Write sequence, during the first clock when emerging
from a deselected state and when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does
not deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
I/OSynchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
location specified by AX during the previous clock rise of the Read cycle. The direction of
the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the
pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state condition.
The outputs are automatically three-stated during the data portion of a Write sequence,
during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE. DQ a,b,c and d are eight bits wide
DPa
DPb
DPc
DPd
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ[31:0].
During Write sequences, DPa is controlled by BWSa, DPb is controlled by BWSb, DPc is
controlled by BWSc, and DPd is controlled by BWSd.DP a,b,c and d are 1 bit wide
ZZ
InputAsynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
MODE
Input Pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE will default HIGH, to an interleaved burst order.
VDD
Power Supply
Power supply inputs to the core of the device.
VDDQ
I/O Power Supply
Power supply for the I/O circuitry.
VSS
Ground
Ground for the device. Should be connected to ground of the system.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA Only).
Document #: 38-05252 Rev. **
Page 5 of 26
CY7C1372BV25
CY7C1370BV25
Pin Definitions
Pin Name
I/O Type
Pin Description
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK
(BGA only).
TCK
JTAG serial
clock
Serial clock to the JTAG circuit (BGA Only).
32M
64M
128M
–
No connects. Reserved for address expansion. Pins are not internally connected
NC
–
No connects. Pins are not internally connected.
DNU
–
Do not use pins.
Introduction
Functional Overview
The CY7C1370BV25 and CY7C1372BV25 are synchronouspipelined Burst NoBL SRAMs designed specifically to
eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 3.0 ns (200-MHz device).
Accesses can be initiated by asserting Chip Enable (CE1, CE2,
CE3 on the TQFP, CE1 on the BGA) active at the rising edge
of the clock. If Clock Enable (CEN) is active LOW and ADV/LD
is asserted LOW, the address presented to the device will be
latched. The access can either be a Read or Write operation,
depending on the status of the Write Enable (WE). BWS[d:a]
can be used to conduct byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed Write
circuitry.
Synchronous Chip Enable (CE1, CE2, CE3 on TQFP, CE1 on
BGA) and an asynchronous Output Enable (OE) simplify
depth expansion. All operations (Reads, Writes, and
Deselects) are pipelined. ADV/LD should be driven LOW once
the device has been deselected in order to load a new address
for the next operation.
Single Read Accesses
A Read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) chip
enable asserted active, (3) the Write Enable input signal WE
is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
Address Register and presented to the memory core and
control logic. The control logic determines that a Read access
is in progress and allows the requested data to propagate to
the input of the output register. At the rising edge of the next
clock the requested data is allowed to propagate through the
output register and onto the data bus within 3.0 ns (200-MHz
device) provided OE is active LOW. After the first clock of the
Read access the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. During the second
clock, a subsequent operation (Read/Write/Deselect) can be
Document #: 38-05252 Rev. **
initiated. Deselecting the device is also pipelined. Therefore,
when the SRAM is deselected at clock rise by one of the chip
enable signals, its output will three-state following the next
clock rise.
Burst Read Accesses
The CY7C1370BV25/72BV25 have an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to Ax is loaded into
the Address Register. The Write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DPa,b,c,d for CY7C1370BV25 and DQa,b/DPa,b for
CY7C1372BV25). In addition, the address for the subsequent
access (Read/Write/Deselect) is latched into the Address
Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DP
(DQa,b,c,d/DPa,b,c,d for CY7C1370BV25 and DQa,b/DPa,b for
CY7C1372BV25) (or a subset for byte Write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the Write is complete.
The data written during the Write operation is controlled by
BWS (BWSa,b,c,d for CY7C1370BV25 and BWSa,b for
CY7C1372BV25) signals. The CY7C1370BV25 and
CY7C1372BV25 provides byte Write capability that is
described in the Write Cycle Description table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
Page 6 of 26
CY7C1372BV25
CY7C1370BV25
(BWS) input will selectively write to only the desired bytes.
Bytes not selected during a byte Write operation will remain
unaltered. A Synchronous self-timed Write mechanism has
been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte Write operations.
Because the CY7C1370BV25/72BV25 is a common I/O
device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DP
(DQa,b,c,d/DPa,b,c,d for CY7C1370BV25 and DQa,b/DPa,b for
CY7C1372BV25) inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ and DP (DQa,b,c,d/DPa,b,c,d
for CY7C1370BV25 and DQa,b/DPa,b for CY7C1372BV25)
are automatically three-stated during the data portion of a
Write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1370BV25/72BV25 has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BWS (BWSa,b,c,d for CY7C1370BV25 and BWSa,b
for CY7C1372BV25) inputs must be driven in each cycle of the
burst Write in order to Write the correct bytes of data.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Address
Used
Operation
CE
CEN
ADV/L
D/
WE
BWSx
CLK
Comments
Deselected
External
1
0
L
X
X
L-H
I/Os three-state following next
recognized clock.
Suspend
–
X
1
X
X
X
L-H
Clock ignored, all operations
suspended.
Begin Read
External
0
0
0
1
X
L-H
Address latched.
Begin Write
External
0
0
0
0
Valid
L-H
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous
access was a Read operation.
Addresses incremented internally in
conjunction with the state of Mode.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous
access was a Write operation.
Addresses incremented internally in
conjunction with the state of MODE.
Bytes written are determined by
BWS[d:a].
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Linear Burst Sequence
Fourth
Address
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
00
01
10
11
01
00
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
Notes:
1. X = ”Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx= Valid
signifies that the desired Byte Write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWSx. See Write Cycle Description table for details.
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN = 1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
Document #: 38-05252 Rev. **
Page 7 of 26
CY7C1372BV25
CY7C1370BV25
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Notes:
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode
standby current
ZZ > VDD – 0.2V
20
mA
tZZS
Device operation to
ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Write Cycle Descriptions[8, 8, 9]
Function (CY7C1370BV25)
WE
BWSd
BWSc
BWSb
BWSa
Read
1
X
X
X
X
Write – No bytes written
0
1
1
1
1
Write Byte 0 – (DQa and DPa)
0
1
1
1
0
Write Byte 1 – (DQb and DPb)
0
1
1
0
1
Write Bytes 1, 0
0
1
1
0
0
Write Byte 2 – (DQc and DPc)
0
1
0
1
1
Write Bytes 2, 0
0
1
0
1
0
Write Bytes 2, 1
0
1
0
0
1
Write Bytes 2, 1, 0
0
1
0
0
0
Write Byte 3 – (DQd and DPd)
0
0
1
1
1
Write Bytes 3, 0
0
0
1
1
0
Write Bytes 3, 1
0
0
1
0
1
Write Bytes 3, 1, 0
0
0
1
0
0
Write Bytes 3, 2
0
0
0
1
1
Write Bytes 3, 2, 0
0
0
0
1
0
Write Bytes 3, 2, 1
0
0
0
0
1
Write All Bytes
0
0
0
0
0
Function (CY7C1372BV25)
WE
BWSb
BWSa
Read
1
x
x
Write - No Bytes Written
0
1
1
Write Byte 0 - (DQa and DPa)
0
1
0
Write Byte 1 - (DQb and DPb)
0
0
1
Write Both Bytes
0
0
0
Notes:
7. All Voltage referenced to Ground.
8. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
9. tCS and tCH refer to the set-up and hold time requirements of latching data
from the boundary scan register.
Document #: 38-05252 Rev. **
Page 8 of 26
CY7C1372BV25
CY7C1370BV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1370BV25/CY7C1372BV25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1-(fully)compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state that will not interfere with the operation of the
device.
Test Access Port (TAP)–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a 69-bit-long
register, and the x18 configuration has a 69-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data, or control signals into
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
Document #: 38-05252 Rev. **
Page 9 of 26
CY7C1372BV25
CY7C1370BV25
the SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE/PRELOAD
Reserved
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05252 Rev. **
Bypass
Page 10 of 26
CY7C1372BV25
CY7C1370BV25
TAP Controller State Diagram
1[10]
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Note:
10. The “0” or “1” next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05252 Rev. **
Page 11 of 26
CY7C1372BV25
CY7C1370BV25
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
.
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[8, 9]
Parameter
Description
Test Conditions
Min.
VOH1
Output HIGH Voltage
IOH = −4.0 mA
2.0
VOH2
Output HIGH Voltage
IOH = −100 µA
VDD− 0.2
VOL1
Output LOW Voltage
IOL = 8.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
GND ≤ VI ≤ VDDQ
Max.
Unit
V
V
0.4
V
0.2
V
1.7
VDD+0.3
V
−0.3
0.7
V
−5
5
µA
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Description
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
tTL
TCK Clock LOW
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
tTDIS
TDI Set-up to TCK Clock Rise
tCS
Capture Set-up to TCK Rise
Min.
100
Max.
40
40
Unit
ns
MHz
ns
ns
10
10
10
ns
ns
ns
10
Note:
11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05252 Rev. **
Page 12 of 26
CY7C1372BV25
CY7C1370BV25
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Description
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
tTDIH
TDI Hold after Clock Rise
tCH
Capture Hold after clock rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock HIGH to TDO Invalid
Min.
Max.
Unit
10
10
10
ns
ns
ns
20
ns
ns
0
TAP Timing and Test Conditions
ALL INPUT PULSES
1.25V
2.5V
1.25V
50Ω
0V
TDO
Z0 = 50Ω
CL = 20 pF
tTL
tTH
GND
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Instruction Field
512K x 36
1M x 18
xxxx
xxxx
Device Depth (27:23)
00111
01000
Defines depth of SRAM. 512K or 1M
Device Width (22:18)
00100
00011
Defines with of the SRAM. x36 or x18
Reserved for future use.
Revision Number (31:28)
Cypress Device ID (17:12)
xxxxx
xxxxx
Cypress JEDEC ID (11:1)
00011100100
00011100100
ID Register Presence (0)
1
1
Document #: 38-05252 Rev. **
Description
Reserved for version number.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Page 13 of 26
CY7C1372BV25
CY7C1370BV25
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size (x36)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan
51
70
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output Ring Contents. Places the boundary scan
register between the TDI and TDO. Forces all SRAM outputs to High-Z state.
This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register
between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output Contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use. This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output Ring Contents. Places the boundary scan
register between TDI and TDO. Does not affect the SRAM operation. This
instruction does not implement 1149.1 preload function and is therefore not
1149.1-compliant.
RESERVED
101
Do Not Use. This instruction is reserved for future use.
RESERVED
110
Do Not Use. This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Document #: 38-05252 Rev. **
Page 14 of 26
CY7C1372BV25
CY7C1370BV25
Boundary Scan Order (512K × 36)
Bit #
Signal
Name
Bump
ID
Signal
Name
Bit #
Boundary Scan Order (1M × 18)
Bump
ID
Bit #
Signal
Name
Bump
ID
Signal
Name
Bit #
Bump
ID
1
A
2R
36
CE3
6B
1
A
2R
36
DQb
2E
2
A
3T
37
BWSa
5L
2
A
2T
37
DQb
2G
3
A
4T
38
BWSb
5G
3
A
3T
38
DQb
1H
4
A
5T
39
BWSc
3G
4
A
5T
39
SN
5R
5
A
6R
40
BWSd
3L
5
A
6R
40
DQb
2K
6
A
3B
41
CE2
2B
6
A
3B
41
DQb
1L
7
A
5B
42
CE1
4E
7
A
5B
42
DQb
2M
8
DPa
6P
43
A
3A
8
DQa
7P
43
DQb
1N
9
DQa
7N
44
A
2A
9
DQa
6N
44
DPb
2P
10
DQa
6M
45
DPc
2D
10
DQa
6L
45
MODE
3R
11
DQa
7L
46
DQc
1E
11
DQa
7K
46
A
2C
12
DQa
6K
47
DQc
2F
12
NC
7T
47
A
3C
13
DQa
7P
48
DQc
1G
13
DQa
6H
48
A
5C
14
DQa
6N
49
DQc
1D
14
DQa
7G
49
A
6C
15
DQa
6L
50
DQc
1D
15
DQa
6F
50
A1
4N
16
DQa
7K
51
DQc
2E
16
DQa
7E
51
A0
4P
17
NC
7T
52
DQc
2G
17
DPa
6D
18
DQb
6H
53
DQc
1H
18
A
6T
19
DQb
7G
54
SN
5R
19
A
6A
20
DQb
6F
55
DQd
2K
20
A
5A
21
DQb
7E
56
DQd
1L
21
A
4G
22
DQb
6D
57
DQd
2M
22
A
4A
23
DQb
7H
58
DQd
1N
23
ADV/LD 4B
24
DQb
6G
59
DQd
2P
24
OE
4F
25
DQb
6E
60
DQd
1K
25
CEN
4M
26
DPb
7D
61
DQd
2L
26
WE
4H
27
A
6A
62
DQd
2N
27
CLK
4K
28
A
5A
63
DPd
1P
28
CE3
6B
29
A
4G
64
MODE
3R
29
BWSa
5L
30
A
4A
65
A
2C
30
BWSb
3G
31
ADV/LD 4B
66
A
3C
31
CE2
2B
32
OE#
4F
67
A
5C
32
CE1
4E
33
CEN#
4M
68
A
6C
33
A
3A
34
WE#
4H
69
A1
4N
34
A
2A
35
CLK
4K
70
A0
4P
35
DQb
1D
Document #: 38-05252 Rev. **
Page 15 of 26
CY7C1372BV25
CY7C1370BV25
DC Input Voltage ..................................... −0.5V to VDDQ + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +3.6V
DC Voltage Applied to Outputs
in High-Z State.........................................−0.5V to VDDQ + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >1500V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Ambient Temperature[12]
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
VDD/VDDQ
2.5 + 5%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
VDD / VDDQ Power Supply Voltage
Min.
Max.
Uni
t
2.375
2.625
V
VOH
Output HIGH Voltage
VDD = Min., IOH = –1.0 mA
VOL
Output LOW Voltage
VDD = Min., IOL = 1.0 mA
VIH
Input HIGH Voltage
1.7
VIL
Input LOW Voltage
−0.3
0.7
V
5
µA
-30
30
µA
-30
30
µA
5
µA
5.0-ns cycle, 200 MHz
280
mA
6.0-ns cycle, 167 MHz
230
mA
IX
Input Load Current
2.0
GND < VI < VDDQ
Input Current of MODE
Input Current of ZZ
Input = VSS
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device
Deselected, VIN > VIH or VIN
< VIL
f = fMAX = 1/tCYC
V
0.4
V
V
6.7-ns cycle, 150 MHz
190
mA
7.5-ns cycle, 133 MHz
160
mA
5.0-ns cycle, 200 MHz
100
mA
6.0-ns cycle, 167 MHz
80
mA
6.7-ns cycle, 150 MHz
65
mA
7.5-ns cycle, 133 MHz
60
mA
ISB2
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device
Deselected, VIN ≤ 0.3V or VIN
> VDDQ − 0.3V, f= 0
All speed grades
30
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs
Max. VDD, Device
Deselected, or VIN ≤ 0.3V or
VIN > VDDQ - 0.3V f = fMAX =
1/tCYC
5.0-ns cycle, 200 MHz
90
mA
6.0-ns cycle, 167 MHz
70
mA
6.7-ns cycle, 150 MHz
60
mA
7.5-ns cycle, 133 MHz
55
mA
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device
Deselected, VIN ≥ VIH or VIN
≤ VIL, f = 0
All speed grades
50
mA
ISB4
Notes:
12. TA is the case temperature.
13. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
14. The load used for VOH and VOL testing is shown in figure (b) of the A/C test conditions.
Document #: 38-05252 Rev. **
Page 16 of 26
CY7C1372BV25
CY7C1370BV25
Capacitance[16]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Max.
Unit
3
pF
3
pF
3
pF
TA = 25°C, f = 1 MHz,
VDD = VDDQ = 2.5V
AC Test Loads and Waveforms
R = 1667Ω
VDDQ
OUTPUT
ALL INPUT PULSES
OUTPUT
Z0 = 50Ω
RL = 50Ω
VL = 1.25V
2.5V
GND
R = 1538Ω
Rise Time:
1V/ns
INCLUDING
JIG AND
SCOPE
(a)
90%
10%
90%
10%
5 pF
[15]
Fall Time:
1V/ns
(c)
(b)
Thermal Resistance[16]
Parameter
Description
QJA
Thermal Resistance
(Junction to Ambient)
QJC
Thermal Resistance
(Junction to Case)
Test Conditions
TQFP Typ.
Units
Still Air, soldered on a 4.25 × 1.125 inch, 4-layer
printed circuit board
25
°C/W
9
°C/W
Switching Characteristics Over the Operating Range[17]
-200
Parameter
Description
Min.
-167
Max.
Min.
-150
Max.
Min.
-133
Max.
Min.
Max.
Unit
Clock
tCYC
Clock Cycle Time
5.0
6.0
6.7
7.5
ns
tCH
Clock HIGH
1.8
2.1
2.3
2.5
ns
tCL
Clock LOW
1.8
2.1
2.3
2.5
ns
Output Times
tCO
Data Output Valid After CLK Rise
3.0
3.4
3.8
4.2
ns
tEOV
OE LOW to Output Valid[16, 18, 20]
3.0
3.4
3.8
4.2
ns
tDOH
Data Output Hold After CLK Rise
tCHZ
Clock to High-Z[16, 17, 18, 19, 20]
tCLZ
Clock to Low-Z
[16, 17, 18, 19, 20]
tEOHZ
OE HIGH to Output High-Z[17, 18, 20]
tEOLZ
OE LOW to Output Low-Z
[17, 18, 20]
1.3
1.3
3.0
1.3
1.3
3.0
1.3
4.0
1.3
3.0
1.3
4.0
ns
3.5
1.3
4.0
ns
ns
4.0
ns
0
0
0
0
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.4
1.5
1.5
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.4
1.5
1.5
1.5
ns
Notes:
15. Input waveform should have a slew rate of < 1V/ns.
16. Tested initially and after any design or process change that may affect these parameters.
17. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
18. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
19. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst-case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
Document #: 38-05252 Rev. **
Page 17 of 26
CY7C1372BV25
CY7C1370BV25
Switching Characteristics Over the Operating Range[17]
-200
Parameter
Description
Min.
Max.
-167
Min.
Max.
-150
Min.
Max.
-133
Min.
Max.
Unit
tCENS
CEN Set-up Before CLK Rise
1.4
1.5
1.5
1.5
ns
tWES
WE, BWSx Set-up Before CLK Rise
1.4
1.5
1.5
1.5
ns
tALS
ADV/LD Set-up Before CLK Rise
1.4
1.5
1.5
1.5
ns
tCES
Chip Select Set-up
1.4
1.5
1.5
1.5
ns
tAH
Address Hold After CLK Rise
0.4
0.5
0.5
0.5
ns
tDH
Data Input Hold After CLK Rise
0.4
0.5
0.5
0.5
ns
tCENH
CEN Hold After CLK Rise
0.4
0.5
0.5
0.5
ns
tWEH
WE, BWx Hold After CLK Rise
0.4
0.5
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.4
0.5
0.5
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.4
0.5
0.5
0.5
ns
Hold Times
Document #: 38-05252 Rev. **
Page 18 of 26
CY7C1372BV25
CY7C1370BV25
DESELECT
DESELECT
SUSPEND
READ
READ
READ
DESELECT
READ
READ
WRITE
Read/Write/Deselect Sequence
WRITE
Switching Waveforms
CLK
tCH tCL
tCENS
tCYC
tCENH
CEN
tAS tAH
ADDRESS
WE and
BWSx
CEN HIGH blocks
all synchronous inputs
WA2
RA1
RA3
RA4
WA5
RA6
RA7
tWS tWH
tCES
tCEH
CE
tCLZ
Data
In/Out
tDOH
Q1
Out
tDS
tDH
tCHZ
tCHZ
tDOH
D2
In
Q3
Out
Q4
Out
D5
In
Q6
Out
Q7
Out
Device
tCO
originally
deselected
The combination of WE and BWSx (x = a, b, c, d for CY7C1370BV25 and x = a, b for CY7C1372B25) define a Write cyc
(see Write Cycle Description table) CE is the combination of CE1, CE2, and CE3. All chip enables need to be active
in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
OE held LOW.
= UNDEFINED
= DON’T CARE
Document #: 38-05252 Rev. **
Page 19 of 26
CY7C1372BV25
CY7C1370BV25
Burst Read
Burst Read
Begin Read
Burst Write
Burst Write
Burst Write
Begin Write
Burst Read
Burst Read
Burst Read
Burst Sequences
Begin Read
Switching Waveforms (continued)
CLK
tALH
tALS
tCH tCL
tCYC
ADV/LD
tAS tAH
ADDRESS
RA1
WA2
RA3
WE
tWS tWH
tWS tWH
BWSx
tCES tCEH
CE
tCLZ
Data
In/Out
tCHZ
tDOH
Q1
Out
Device
originally
deselected
tCO
Q1+1
Out
Q1+2
Out
tCO
tCLZ
tDH
Q1+3
Out
D2
In
D2+1
In
D2+2
In
Q3
Out
D2+3
In
tDS
The combination of WE and BWSx(x = a, b c, d) define a Write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= DON’T CARE
Document #: 38-05252 Rev. **
= UNDEFINED
Page 20 of 26
CY7C1372BV25
CY7C1370BV25
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-state
I/Os
tEOLZ
ZZ Mode Timing [21, 22]
CLK
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
Note:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
22. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05252 Rev. **
Page 21 of 26
CY7C1372BV25
CY7C1370BV25
Ordering Information
Speed
(MHz)
200
167
150
133
167
150
133
Ordering Code
CY7C1370BV25-200AC
CY7C1372BV25-200AC
Package
Name
A101
CY7C1370BV25-200BGC
CY7C1372BV25-200BGC
BG119
CY7C1370BV25-200BZC
CY7C1372BV25-200BZC
BA165A
CY7C1370BV25-167AC
CY7C1372BV25-167AC
A101
CY7C1370BV25-167BGC
CY7C1372BV25-167BGC
BG119
CY7C1370BV25-167BZC
CY7C1372BV25-167BZC
BA165A
CY7C1370BV25-150AC
CY7C1372BV25-150AC
A101
CY7C1370BV25-150BGC
CY7C1372BV25-150BGC
BG119
CY7C1370BV25-150BZC
CY7C1372BV25-150BZC
BA165A
CY7C1370BV25-133AC
CY7C1372BV25-133AC
A101
CY7C1370BV25-133BGC
CY7C1372BV25-133BGC
BG119
CY7C1370BV25-133BZC
CY7C1372BV25-133BZC
BA165A
CY7C1370BV25-167AI
CY7C1372BV25-167AI
A101
CY7C1370BV25-167BGI
CY7C1372BV25-167BGI
BG119
CY7C1370BV25-167BZI
CY7C1372BV25-167BZI
BA165A
CY7C1370BV25-150AI
CY7C1372BV25-150AI
A101
CY7C1370BV25-150BGI
CY7C1372BV25-150BGI
BG119
CY7C1370BV25-150BZI
CY7C1372BV25-150BZI
BA165A
CY7C1370BV25-133AI
CY7C1372BV25-133AI
A101
CY7C1370BV25-133BGI
CY7C1372BV25-133BGI
BG119
CY7C1370BV25-133BZI
CY7C1372BV25-133BZI
BA165A
Package Type
100-Lead Thin Quad Flat Pack
Operating
Range
Commercial
119 BGA
165 FBGA
100-Lead Thin Quad Flat Pack
119 BGA
165 FBGA
100-Lead Thin Quad Flat Pack
119 BGA
165 FBGA
100-Lead Thin Quad Flat Pack
119 BGA
165 FBGA
100-Lead Thin Quad Flat Pack
Industrial
119 BGA
165 FBGA
100-Lead Thin Quad Flat Pack
119 BGA
165 FBGA
100-Lead Thin Quad Flat Pack
119 BGA
165 FBGA
Shaded areas contain advance information.
Document #: 38-05252 Rev. **
Page 22 of 26
CY7C1372BV25
CY7C1370BV25
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101
51-85050-A
Document #: 38-05252 Rev. **
Page 23 of 26
CY7C1372BV25
CY7C1370BV25
Package Diagrams (continued)
119-lead PBGA (14 × 22 × 2.4 mm) BG119
51-85115-*A
Document #: 38-05252 Rev. **
Page 24 of 26
CY7C1372BV25
CY7C1370BV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*B
NoBL is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks
of their respective holders.
Document #: 38-05252 Rev. **
Page 25 of 26
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1372BV25
CY7C1370BV25
Document Title: CY7C1370BV25/CY7C1372BV25 512K x 36/1M x 18 Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05252
REV.
ECN No.
Issue Date
Orig. of
Change
**
113654
05/08/02
CJM
Document #: 38-05252 Rev. **
Description of Change
Changed from 38-01072 to 38-05252
Added ZZ pin functionality
Changed Voh and Vol values to reflect new char. values
Modified ESD voltage to 1500V
Changed tDOH to 1.3ns for 200 MHz and 167 MHz.
Changed VDD range to +10% / –5%
Changed IDD and ISB values to reflect new char values
Added 165 fBGA packaging
Added I-temp
Removed 180 MHz speed bin
Changed tEOHZ from 3.0 to 4.0 ns
Changed setup time from 1.5 ns to 1.4 ns for 200 MHz
Changes hold time from 0.5 to 0.4 ns from 200 MHz
Added swtiching waveforms for ZZ mode
Page 26 of 26
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