Integrated Automotive TFT-LCD Power Supply Regulator ISL78419 Features The ISL78419 is an integrated power management IC (PMIC) for TFT-LCDs used in central display, rear seat entertainment and virtual dashboards. The device integrates a boost converter for generating AVDD, an LDO regulator for VLOGIC. VON and VOFF are generated by a charge pump driven by the switch node of the boost converter. The ISL78419 also includes a VON slice circuit, reset function, and a high performance VCOM amplifier with a Digitally Controlled Potentiometer (DCP) that is used as a VCOM calibrator. • 2.5V to 5.5V input • 1.5A, 0.18Ω integrated boost FET • VON/VOFF supplies generated by charge pumps driven by the boost switch node • LDO for VLOGIC channel • 600kHz/1200kHz selectable switching frequency • Integrated gate pulse modulator The AVDD boost converter features a 1.5A/0.18Ω boost FET with 600kHz/1200kHz switching frequency. • Reset signal generated by supply monitor The integrated logic LDO includes a 350mA FET for driving the low voltage needed by external digital circuitry. • DCP - I2C serial interface, address: 0101000, MSB left - Wiper position stored in 8-bit nonvolatile memory and recalled on power-up - Endurance, 1,000 data changes per bit • Integrated VCOM amplifier The gate pulse modulator can control the gate voltage up to 30V, and both the rate and slew delay times are selectable. The supply monitor generates a reset signal when the system is powered down based on a user selected threshold level (programming resistor). • UVLO, UVP, OVP, OCP, and OTP protection • Pb-free (RoHS compliant) The ISL78419 provides a digitally controlled VCOM output using I2C interface. One VCOM amplifier is also integrated in the chip to provide a fast slewing 150mA drive (sourcing or sinking). The output of the VCOM is powered up with the voltage stored at the last programmed 8-bit (internal) EEPROM setting. • 28 Ld 4x5 QFN • AEC Q100 qualified Applications • Automotive TFT displays - Central displays, rear seat entertainment and dashboards The ISL78419 is rated to operate over the temperature range of (-40°C to +105°C) and is qualified according to AEC Q100. Pin Configuration EN LX VIN FREQ COMP SS ISL78419 (28 LD 4x5 QFN) TOP VIEW 28 27 26 25 24 23 FB 1 22 L_IN PGND 2 21 CD2 CE 3 20 L_OUT RE 4 19 RESET VGH 5 18 ADJ VGHM 6 17 VDIV VFLK 7 16 NEG VDPM 8 15 VOUT January 24, 2014 FN8292.2 1 10 11 12 13 14 SCL SDA POS RSET GPM_LO 9 AVDD GND THERMAL PAD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL78419 Application Diagram VIN AVDD L1 10µH C1, 2 20µF D1 SW LX C32 0.1µF AVDD BOOST CONTROLLER EN SS FREQ C7 AVDD 0.1µF R1 73.2kΩ VIN VIN C4, 5, 6 30µF SEQUENCER PGND R2 8.06kΩ FB COMP R12 5.5kΩ C20 15nF D4 C25 1µF VLOGIC VLOGIC C24 2.2µF R18 3.92kΩ C11 0.1µF L_OUT R6 1kΩ VOFF Z1 C16 1µF SW C8 47nF R17 8.25kΩ C10 47nF VON SCL SDA RSET POS D2 VFLK ADJ 133kΩ R8 C15 1µF AVDD LDO R9 10kΩ C9 1µF D3 VCOM GPM DCP C17 1nF CE C14 100pF C28 0.1µF RE VGHM AVDD OUT NEG C12 1µF VGH VDPM VGH GPM R5 100kΩ R22 22kΩ GPM_LO R7 83kΩ AVDD C19 0.47µF Q1 L_IN LDO VIN VDIV VCOM OP VOLTAGE DETECTOR CD2 RESET THERMAL PAD C18 0.47µF R14 85kΩ R26 100kΩ AVDD VGH V IN OPEN R15 115kΩ C26 1nF RESET R16 10kΩ VLOGIC Pin Descriptions PIN# SYMBOL DESCRIPTION 1 FB 2 PGND 3 CE Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the delay time. 4 RE Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling slew rate. 5 VGH 6 VGHM Gate Pulse Modulator Output for gate driver IC 7 VFLK Gate Pulse Modulator Control input from TCON 8 VDPM Gate Pulse Modulator Enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is enabled. A current source charges the capacitor on VDPM. 9 GPM_LO 10 AVDD 11 SCL AVDD boost converter feedback. Connect to the center of a voltage divider between AVDD and GND to set the AVDD voltage. Power ground Gate Pulse Modulator High Voltage Input. Place a 0.1µF decoupling capacitor close to the VGH pin. Gate Pulse Modulator Low Voltage Input; place a 0.47µF decoupling capacitor close to the GPM_LO pin. DCP and VCOM amplifier high voltage analog supply; place a 0.47µF decoupling capacitor close to the AVDD pin. I2C compatible clock input 2 FN8292.2 January 24, 2014 ISL78419 Pin Descriptions PIN# (Continued) SYMBOL DESCRIPTION 12 SDA I2C compatible serial bidirectional data line 13 POS VCOM Amplifier Non-inverting input 14 RSET DCP sink current adjustment pin; connect a resistor between this pin and GND to set the resolution of the DCP output voltage. 15 VOUT VCOM Amplifier output 16 NEG VCOM Amplifier inverting input 17 VDIV Voltage detector threshold. Connect to the center of a resistive divider between VIN and GND. 18 ADJ VLOGIC LDO feedback. Connect to the center of a resistive divider between L_OUT and GND to set VLogic voltage for TCON. 19 RESET Voltage detector reset output 20 L_OUT LDO output. Connect at least one 1µF capacitor to GND for stable operation. 21 CD2 Voltage detector rising edge delay. Connect a capacitor between this pin and GND to set the rising edge delay. 22 L_IN LDO input. Connect a 1µF decoupling capacitor close to this pin. 23 SS 24 COMP Boost converter compensation pin. Connect a series resistor and capacitor between this pin and GND to optimize transient response and stability. 25 FREQ Boost Converter frequency select; pull it to logic high to operate boost at 1.2MHz. Connect this pin to GND to operate boost at 600kHz. 26 VIN IC input supply. Connect a 0.1µF decoupling capacitor close to this pin. 27 LX AVDD boost converter switching node 28 EN AVDD enable pin Boost Converter Soft-Start. Connect a capacitor between this pin and GND to set the soft-start time. Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL78419ARZ 78419 ARZ VIN RANGE (V) TEMP RANGE (°C) 2.5 to 5.5 -40 to +105 PACKAGE (Pb-free) 28 Ld 4x5 QFN PKG. DWG. # L28.4x5A NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78419 For more information on MSL please see techbrief TB363. 3 FN8292.2 January 24, 2014 ISL78419 Table of Contents Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Enable Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Frequency Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Rectifier Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Linear Regulator (LDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Supply Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Gate Pulse Modulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 VCOM Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 DCP Memory Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 I2C Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Data Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Communication with ISL78419 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Register Description: Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Register Description: IVR and WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Initial VCOM Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 FN8292.2 January 24, 2014 ISL78419 Absolute Maximum Ratings Thermal Information RE, VGHM, GPM_LO and VGH to GND . . . . . . . . . . . . . . . . . . . . -0.3 to +36V LX, AVDD, POS, NEG, VOUT to GND . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V Voltage Between GND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5V All Other Pins to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0V ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 1kV Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 28 Ld 4x5 QFN Package (Notes 4, 5). . . . . 38 4.5 Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Functional Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature During Soldering . . . . . . . . . . . . . . . . . . . . . . . . +260°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VLDO = 2.5V, VON = 24V, VOFF = - 6V. Boldface limits apply over the operating temperature range, -40°C to +105°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 7) MAX (Note 6) UNITS GENERAL VIN 3.3 5.5 V VIN Supply Currents when Disabled VIN < UVLO 390 500 µA IS VIN Supply Currents ENABLE = 3.3V, overdrive AVDD and VGH 0.7 1.0 mA IENABLE ENABLE Pin Current ENABLE = 0V IS_DIS VIN Supply Voltage Range 2.5 0 µA LOGIC INPUT CHARACTERISTICS - ENABLE, FLK, SCL, SDA, FREQ VIL Low Voltage Threshold VIH High Voltage Threshold RIL Pull-Down Resistor 0.65 1.75 Enable, FLK, FREQ 0.85 V V 1.25 1.65 MΩ INTERNAL OSCILLATOR FOSC Switching Frequencies FREQ = low, TA = +25°C 550 600 650 kHz FREQ = high, TA = +25°C 1100 1200 1300 kHz AVDD BOOST REGULATOR DAVDD/ DIOUT AVDD Load Regulation 50mA < ILOAD < 250mA 0.2 % DAVDD/ DVIN AVDD Line Regulation ILOAD = 150mA, 2.5V < VIN < 5.5V 0.15 % VFB Feedback Voltage (VFB) ILOAD = 100mA, TA = +25°C IFB FB Input Bias Current rDS(ON) Switch ON-resistance ILIM Switch Current Limit DMAX Max Duty Cycle Freq = 1.2MHz, IAVDD = 100mA 5 0.808 V 100 nA 180 260 mΩ 1.125 1.5 1.875 80 90 % 91 % TA = +25°C Freq = 1.2MHz EFF 0.792 0.8 A FN8292.2 January 24, 2014 ISL78419 Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VLDO = 2.5V, VON = 24V, VOFF = - 6V. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 7) MAX (Note 6) UNITS LDO REGULATOR DVLDO/ DVIN Line Regulation ILDO = 1mA, 3.0V < VIN1 < 5.5V DVLDO/ DIOUT Load Regulation 1mA < ILDO < 350mA VDO Dropout Voltage Output drops by 2%, ILDO = 350mA ILIML Current Limit Output drops by 5% VADJ ADJ Reference Voltage ILOAD = 50mA, TA = +25°C IADJ ADJ Input Bias Current 1 mV/V 0.2 % 225 330 425 0.792 0.8 300 mV mA 0.808 V 0.1 µA 33 V 1.30 V GATE PULSE MODULATOR VGH VIH_VDPM VGH Voltage 7 VDPM Enable Threshold 1.13 IVGH VGH Input Current VFLK = 0 VGPM_LO GPM_LO Voltage 2 IGPM_LO VGPM_LO Input Current -2 VCEth1 VCEth2 1.215 125 µA 27.5 RE = 100kΩ, VFLK = VIN µA VGH-2 V 0.1 2 µA CE Threshold Voltage 1 0.6xVIN 0.8xVIN V CE Threshold Voltage 2 1.215 V CE Current 100 µA RVGHM_PD VGHM Pull-down Resistance 1.1 kΩ RONVGH VGH to VGHM On-resistance 23 Ω VDPM Charge Current 10 µA ICE IDPM SUPPLY MONITOR VIH_VDIV VDIV High Threshold VDIV rising 1.265 1.280 1.295 V VIL_VDIV VDIV Low Threshold VDIV falling 1.21 1.222 1.234 V VthCD2 CD2 Threshold voltage 1.200 1.217 1.234 ICD2 RIL_RESET tDELAY_RESET CD2 Charge Current RESET Pull-down Resistance RESET Delay on the Rising Edge V 10 µA 650 Ω 121.7k* CD s VCOM AMPLIFIER RLOAD = 10kΩ, CLOAD = 10pF, unless otherwise stated IS_com VOS IB VCOM Amplifier Supply Current 0.7 1.08 mA Offset Voltage 2.5 15 mV Non-inverting Input Bias Current 0 nA CMIR Common Mode Input Voltage Range 0 CMRR Common-Mode Rejection Ratio 60 75 dB PSRR Power Supply Rejection Ratio 70 85 dB IOUT(source) = 0.1mA AVDD - 1.39 mV IOUT(source) = 75mA AVDD - 1.27 V IOUT(sink) = 0.1mA 1.2 mV IOUT(sink) = 75mA 1 V VOH VOL Output Voltage Swing High Output Voltage Swing Low 6 AVDD V FN8292.2 January 24, 2014 ISL78419 Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VLDO = 2.5V, VON = 24V, VOFF = - 6V. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) SYMBOL MIN (Note 6) TYP (Note 7) Pull-up 150 225 mA Pull-down 150 200 mA PARAMETER ISC Output Short Circuit Current SR Slew Rate BW Gain Bandwidth TEST CONDITIONS -3dB gain point MAX (Note 6) UNITS 25 V/µs 20 MHz 8 Bits DIGITAL CONTROLLED POTENTIOMETER SETVR (Note 12) SET Voltage Resolution SETDNL SET Differential Nonlinearity (Notes 8, 9, 14) TA = +25°C ±1 LSB SETZSE SET Zero-Scale Error (Notes 10, 14) TA = +25°C ±2 LSB SETFSE SET Full-Scale Error (Notes 11, 14) TA = +25°C ±8 LSB 100 µA IRSET RSET Current AVDD to SET AVDD to SET Voltage Attenuation 1:20 V/V FAULT DETECTION THRESHOLD VUVLO Undervoltage Lock out Threshold OVPAVDD (Note 13) Boost Overvoltage Protection Off Threshold to Shutdown IC TOFF Thermal Shut-Down all Channels PVIN rising 2.25 2.33 2.41 V PVIN falling 2.125 2.20 2.27 V 15.0 15.5 16.0 V Temperature rising 153 °C POWER SEQUENCE TIMING tssVLOGIC VLOGIC Soft-start Time Iss Boost Soft-start Current Serial Interface Specifications SYMBOL PARAMETER 0.45 3 5.5 ms 8 µA For SCL and SDA Unless Otherwise Noted. TEST CONDITIONS MIN (Note 14) TYP (Note 7) MAX (Note 14) UNITS 400 kHz fSCL (Note 6) SCL Frequency tiN (Note 6) Pulse Width Suppression Time at SDA and SCL Inputs Any pulse narrower than the maximum specification is suppressed 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VIN, until SDA exits the 30% to 70% of VIN window 480 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VIN during the following START condition 480 ns tLOW Clock LOW Time Measured at the 30% of VIN crossing 480 ns tHIGH Clock HIGH Time Measured at the 70% of VIN crossing 400 ns tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge; both crossing 70% of VIN 480 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VIN to SCL falling edge crossing 70% of VIN 400 ns 7 FN8292.2 January 24, 2014 ISL78419 Serial Interface Specifications SYMBOL For SCL and SDA Unless Otherwise Noted. (Continued) PARAMETER TEST CONDITIONS MIN (Note 14) TYP (Note 7) MAX (Note 14) UNITS tSU:DAT Input Data Set-up Time From SDA exiting the 30% to 70% of VIN window, to SCL rising edge crossing 30% of VIN 40 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VIN to SDA entering the 30% to 70% of VIN window 0 ns tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VIN, to SDA rising edge crossing 30% of VIN 400 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge; both crossing 70% of VIN 400 ns CSCL Capacitive on SCL 5 pF CSDA Capacitive on SDA 5 pF Non-Volatile Write Cycle Time 25 ms tWp EEPROM Endurance TA = +25°C 1 kCyc EEPROM Retention TA = +25°C 88 kHrs NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Typical values are for TA = +25°C and VIN = 3.3V. 8. LSB = I V255 - V1I/254. V255 and V1 are the measured voltages for the DCP register set to FF hex and 01 hex respectively. 9. DNL = I Vi+1 - Vi I/LSB-1, i ∈ [ 1, 255 ] 10. ZS error = (V1 -VMIN)/LSB. VMIN = (VAVDD*R2) * [1-254*R1/(255*20*RSET)]/ (R1+R2). 11. FS error = (V255 - VMAX)/LSB. VMAX = (VAVDD*R2) * [1-0*R1/(255*20*RSET)]/ (R1+R2). 12. Established by design. Not a parametric spec. 13. Boost will stop switching as soon as boost output reaches OVP threshold. 14. Compliance to limits is assured by characterization and design. 8 FN8292.2 January 24, 2014 ISL78419 Typical Performance Curves 92 0.00 fOSC = 600kHz EFFICIENCY (%) 88 fOSC = 600kHz 86 LOAD REGULATION (%) 90 fOSC = 1.2MHz 84 82 80 78 76 -0.01 -0.02 fOSC = 1.2MHz -0.03 VIN = 3.3V, VOUT = 8.06V 0.0 50 100 150 200 250 300 VIN = 3.3V, VOUT = 8.06V 350 -0.04 50 100 IAVDD (mA) 150 200 250 IAVDD (mA) FIGURE 1. AVDD EFFICIENCY vs IAVDD FIGURE 2. AVDD LOAD REGULATION vs IAVDD L = 10µH, COUT = 40µF, CCOMP = 15nF, RCOMP = 5.5kΩ 0.14 LINE REGULATION (%) 0.12 0.10 0.08 0.06 IAVDD = 150mA 0.04 0.02 0.00 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 FIGURE 3. AVDD LINE REGULATION vs VIN CE = 1pF, RE = 100kΩ VGHM FIGURE 5. GPM CIRCUIT WAVEFORM 9 5.5 FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE VGHM CE = 100pF, RE = 100kΩ FIGURE 6. GPM CIRCUIT WAVEFORM FN8292.2 January 24, 2014 ISL78419 Typical Performance Curves (Continued) CE = 10pF, RE = 50kΩ CE = 10pF, RE = 150kΩ VGHM VGHM FIGURE 7. GPM CIRCUIT WAVEFORM FIGURE 8. GPM CIRCUIT WAVEFORM VGHM FIGURE 9. VGHM FOLLOWS VGH WHEN THE SYSTEM POWERS OFF FIGURE 10. VCOM RISING SLEW RATE 2.4854 0.000 LOAD REGULATION (%) 2.4852 2.4850 VLDO (V) 2.4848 2.4846 2.4844 ILDO = 1mA 2.4842 2.4840 2.4838 2.4836 3.0 -0.005 -0.010 -0.015 VLDO = 2.5V -0.020 -0.025 -0.030 3.5 4.0 4.5 VLDO_IN (V) FIGURE 11. LDO LINE REGULATION vs VIN 10 5.0 5.5 0 50 100 150 200 250 300 350 ILDO (mA) FIGURE 12. LDO LOAD REGULATION vs ILDO FN8292.2 January 24, 2014 ISL78419 Applications Information This restricts the maximum output current (average) based on Equation 3: Enable Control ΔI L V IN I OMAX = ⎛ I LMT – --------⎞ × --------⎝ 2 ⎠ VO With VIN > UVLO, only the Logic output channel is activated. All other functions in ISL78419 are shut down when the enable pin is pulled down. When the voltage at the enable pin reaches high threshold, the whole chip turns on. Frequency Selection The ISL78419 switching frequency can be user selected to operate at either constant 600kHz or 1.2MHz. Lower switching frequency can save power dissipation at very light load conditions. Also, low switching frequency more easily leads to discontinuous conduction mode, while higher switching frequency allows for smaller external components, such as inductor and output capacitors, etc. Higher switching frequency will get higher efficiency within some loading ranges depending on VIN, VOUT, and external components, as shown in Figure 1. Connecting the FREQ pin to GND sets the PWM switching frequency to 600kHz, or connecting FREQ pin to VIN for 1.2MHz. Soft-Start The soft-start is provided by an internal current source to charge the external soft-start capacitor. The ISL78419 ramps up the current limit from 0A up to the full value, as the voltage at the SS pin ramps from 0V to 0.8V. Hence, the soft-start time is 3.2ms when the soft-start capacitor is 22nF, 6.8ms for 47nF and 14.5ms for 100nF. Operation The boost converter is a current mode PWM converter operating at either 600kHz or 1.2MHz. It can operate in both discontinuous conduction mode (DCM) at light load and continuous conduction mode (CCM). In continuous conduction mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by Equation 1: V Boost 1 ------------------- = ------------V IN 1–D (EQ. 1) (EQ. 3) Where ΔIL is the peak-to-peak inductor ripple current, and is set by Equation 4: V IN D ΔI L = --------- × ---L fs (EQ. 4) Where fS is the switching frequency (600kHz or 1.2MHz). Capacitor An input capacitor is used to suppress the voltage ripple injected into the boost converter. The ceramic capacitor with a capacitance larger than 10µF is recommended. The voltage rating of the input capacitor should be larger than the maximum input voltage. Some input capacitors are recommended in Table 1. TABLE 1. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION CAPACITOR SIZE MFG PART NUMBER 10µF/6.3V 0603 TDK C1608X5R0J106M 10µF/16V 1206 TDK C3216X7R1C106M 10µF/10V 0805 Murata GRM21BR61A106K 22µF/10V 1210 Murata GRB32ER61A226K Inductor The boost inductor is a critical part that influences the output voltage ripple, transient response, and efficiency. Values of 3.3µH to 10µH are used to match the internal slope compensation. The inductor must be able to handle the following average and peak currents shown in Equation 5: IO I LAVG = ------------1–D (EQ. 5) ΔI L I LPK = I LAVG + -------2 Some inductors are recommended in Table 2 for different design considerations. Where D is the duty cycle of the switching MOSFET. Rectifier Diode The boost regulator uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle-by-cycle and terminates the PWM cycle if the current limit is reached. A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output voltage. The rectifier diode must meet the output current and peak inductor current requirements. Table 3 shows some recommendations for boost converter diode. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60kΩ is recommended. The boost converter output voltage is determined by Equation 2: R1 + R2 V Boost = --------------------- × V FB R2 (EQ. 2) The current through the MOSFET is limited to 1.5APEAK. 11 TABLE 2. BOOST CONVERTER INDUCTOR RECOMMENDATION INDUCTOR 10µH/ 4Apeak DIMENSIONS (mm) MFG PART NUMBER 8.3x8.3x4.5 Sumida CDR8D43-100NC 6.8µH/ 1.8Apeak 5.0x5.0x2.0 10µH/ 2.2Apeak 6.6x7.3x1.2 TDK NOTE Efficiency optimization PLF5020T-6R8M1R8 Cyntec PCME061B-100MS PCB space/profile optimization FN8292.2 January 24, 2014 ISL78419 TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION DIODE VR/IAVG RATING PACKAGE MFG PMEG2010ER 20V/1A SOD123W NXP MSS1P2U 20V/1A MicroSMP VISHAY Ceramic capacitors are recommended for the LDO input and output capacitors. Intersil recommends an output capacitor within the 1µF to 4.7µF range and a maximum feedback resistor impedance of 20kΩ. Larger capacitors help to reduce noise and deviation during transient load change. Some capacitors are recommended in Table 5. Output Capacitor TABLE 5. LDO OUTPUT CAPACITOR RECOMMENDATION The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: 1. The voltage drop due to the inductor ripple current flowing through the ESR of the output capacitor. 2. Charging and discharging of the output capacitor. IO V O – V IN 1 V RIPPLE = I LPK × ESR + ------------------------ × ---------------- × ---f V C O OUT s Note: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in Equation 6 assumes the effective value of the capacitor at a particular voltage and not the manufacturer’s stated value, measured at 0V. Table 4 shows some selections of output capacitors. MFG 10µF/25V 1210 TDK C3225X7R1E106M 10µF/25V 1210 Murata GRM32DR61E106K MFG PART NUMBER 1µF/10V 0603 TDK C1608X7R1A105K 1µF/6.3V 0603 MURATA GRM188R70J105K 2.2µF/6.3V 0603 TDK C1608X7R0J225K The Supply Monitor circuit monitors the voltage on VDIV, and sets open-drain output RESET low when VDIV is below 1.28V (rising) or 1.22V (falling). There is a delay on the rising edge, controlled by a capacitor on CD2. When VDIV exceeds 1.28V (rising), CD2 is charged up from 0V to 1.217V by a 10µA current source. Once CD2 exceeds 1.217V, RESET will go tri-state. When VDIV falls below 1.22V, RESET will become low with a 650Ω pull-down resistance. The delay time is controlled by Equation 8: (EQ. 8) t delay = 121.7k × CD2 For example, the delay time is 12.17ms if the CD2 = 100nF. TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION SIZE SIZE Supply Monitor Circuit (EQ. 6) For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. CAPACITOR CAPACITOR Figure 13 shows the Supply Monitor Circuit timing diagram. PART NUMBER 1.28V VDIV Compensation 1.22V The boost converter of ISL78419 can be compensated by an RC network connected from the COMP pin to ground. A 15nF and 5.5kΩ RC network is used in the evaluation. The larger value resistor and lower value capacitor can lower the transient overshoot, however, at the expense of the stability of the loop. Linear Regulator (LDO) 1.217V CD2 RESET The ISL78419 includes an LDO with adjustable output. It can supply current up to 350mA. The output voltage is adjusted by connection of the ADJ pin. RESET DELAY TIME IS CONTROLLED BY CD2 CAPACITOR FIGURE 13. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM The efficiency of the LDO depends on the difference between input voltage and output voltage (Equation 7) by assuming LDO quiescent current is much lower than LDO output current: ⎛ V LDO_IN ⎞ η ( % ) = ⎜ ------------------------------⎟ × 100% ⎝ V LDO_OUT⎠ (EQ. 7) The less difference between input and output voltage, the higher efficiency it is. 12 FN8292.2 January 24, 2014 ISL78419 VIN UVLO THRESHOLD 0 VGH RESET VDPM 1.215V VFLK VGH VGHM VGHM IS FORCED TO VGH WHEN VIN FALLS TO UVLO AND VGH > 3V GPM_LO Slope is IS controlled SLOPE CONTROLLED BY RE by RE Power on delay time TIME Delay time is controlled DELAY TIME IS POWER-ON DELAY is controlled by BY C by CE CONTROLLED BY CE CONTROLLED DPM CDPM FIGURE 14. GATE PULSE MODULATOR TIMING DIAGRAM Gate Pulse Modulator Circuit The gate pulse modulator circuit functions as a three way multiplexer, switching VGHM between ground, GPM_LO and VGH. Voltage selection is provided by digital inputs VDPM (enable) and VFLK (control). High to low delay and slew control is provided by external components on pins CE and RE, respectively. When VDPM is LOW, the block is disabled and VGHM is grounded. When the input voltage exceeds UVLO threshold, VDPM starts to drive an external capacitor. Once VDPM exceeds 1.215V, the GPM circuit is enabled, and the output VGHM is determined by VFLK, RESET signal and VGH voltage. If the RESET signal is high and VFLK is high, VGHM is pulled to VGH. When VFLK goes low, there is a delay controlled by capacitor CE, following which, VGHM is driven to GPM_LO, with a slew rate controlled by resistor RE. Note that GPM_LO is used only as a reference voltage for an amplifier, and thus does not have to source or sink a significant DC current. Low to high transition is determined primarily by the switch resistance and the external capacitive load. High to low transition is more complex. Take the case where the block is already enabled (VDPM is high). When VFLK is high, if CE is not externally pulled above threshold voltage 1, pin CE is pulled low. On the falling edge of VFLK, a current is passed into pin CE to charge the external capacitor up to threshold voltage 2, providing a delay which is adjustable by varying the capacitor on CE. Once this threshold is reached, the output starts to be pulled down from VGH to GPM_LO. The maximum slew current is equal to 500/(RE + 40k), and the dv/dt slew rate is Isl/CLOAD, where CLOAD is the load capacitance applied to VGHM. The slew rate reduces as VGHM approaches GPM_LO. If CE is always pulled up to a voltage above threshold 1, zero delay mode is selected; thus there will be no delay from FLK falling to the point where VGHM starts to fall. Slew down currents will be identical to the previous case. 13 At power-down, when VIN falls to UVLO, VGHM will be tied to VGH until the VGH voltage falls to 3V. Once the VGH voltage falls below 3V, VGHM will not be actively driven until VIN is driven. Figure 14 shows the VGHM voltage based on VIN, VGH and RESET. VCOM Amplifier The VCOM amplifier is designed to control the voltage on the back plane of an LCD display. This plane is capacitively coupled to the pixel drive voltage, which alternately cycles positive and negative at the line rate for the display. Thus, the amplifier must be capable of sourcing and sinking pulses of current, which can occasionally be quite large (in the range of 100mA for typical applications). The ISL78419 VCOM amplifier's output current is limited to 225mA typical. This limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. It does not necessarily prevent a large temperature rise if the current is maintained. (In this case, the whole chip may be shut down by the thermal trip to protect functionality.) If the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. This will happen in the µs time scale in practical systems and for pulses 2 or 3 times the current limit; the VCOM voltage will have settled again before the next line is processed. DCP Memory Description The ISL78419 contains 1 non-volatile byte known as the Initial Value Register (IVR). It is accessed by the I2C interface operations with Address 00h. The IVR contains the value that is loaded into the Volatile Wiper Register (WR) at power-up. The volatile WR, and the non-volatile IVR of a DCP are accessed with the same address. FN8292.2 January 24, 2014 ISL78419 The Access Control Register (ACR) determines which word at address 00h is accessed (IVR or WR). The volatile ACR must be set as follows: • When the ACR is all zeroes, which is the default at power-up: - A read operation to address 0 outputs the value of the non-volatile IVR - A write operation to address 0 writes the identical values to the WR and IVR of the DCP • When the ACR is 80h: - A read operation to address 0 outputs the value of the volatile WR - A write operation to address 0 only writes to the volatile WR It is not possible to write to an IVR without writing the same value to its WR. 00h and 80h are the only values that should be written to address 2. All other values are reserved and must not be written to address 2. TABLE 6. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 2 - ACR 1 Reserved 0 IVR WR WR: Wiper Register, IVR: Initial value Register. I2C Serial Interface The ISL78419 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data on to the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the DCP of the ISL78419 operates as a slave device in all applications. The fall and rise time of SDA and SCL signal should be in the range listed in Table 8. Capacitive load on I2C bus is also specified in Table 8. Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 15). On power-up of the ISL78419, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The DCP continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 15). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is high (see Figure 15). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile write byte, initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 16). The ISL78419 DCP responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL78419 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101000 as the seven MSBs. The LSB is in the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (see Table 7). TABLE 7. IDENTIFICATION BYTE FORMAT 0 All communication over the I2C interface is conducted by sending 1 0 1 0 (MSB) 0 0 R/W (LSB) the MSB of each byte of data first. SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS 14 FN8292.2 January 24, 2014 ISL78419 SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER SIGNALS FROM THE MASTER SIGNAL AT SDA S T A R T WRITE IDENTIFICATION BYTE 0 1 0 1 0 0 0 ADDRESS BYTE 0 0 0 0 0 0 X 0 0 SIGNALS FROM THE ISL78419 S T O P DATA BYTE A C K A C K A C K FIGURE 17. BYTE WRITE SEQUENCE SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA IDENTIFICATION BYTE WITH R/W = 0 0 1 0 1 0 0 0 0 A C K SIGNALS FROM THE SLAVE ADDRESS BYTE S T A IDENTIFICATION R BYTE WITH T R/W = 1 0 0 0 0 0 0 X 0 0 1 0 1 0 0 0 A C K S T O P A C K 1 A C K A C K FIRST READ DATA BYTE LAST READ DATA BYTE FIGURE 18. READ SEQUENCE Write Operation Data Protection A write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition (see Figure 17). After each of the three bytes, the ISL78419 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL78419 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins and the SDA output is at high impedance state. When the internal non-volatile write cycle is completed, the ISL78419 enters its standby state. The byte at address 02h determines if the Data Byte is to be written to volatile and/or non-volatile memory. A STOP condition also acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is received. If the Address Byte is 0 or 2, the Data Byte is transferred to the Wiper Register (WR) or to the Access Control Register respectively, at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If the Address Byte is 0, and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory. TABLE 8. I2C INTERFACE SPECIFICATION PARAMETER 15 MAX UNITS SDA and SCL Rise Time MIN TYP 1000 ns SDA and SCL Fall Time 300 ns I2C Bus Capacitive Load 400 pF FN8292.2 January 24, 2014 ISL78419 Read Operation should be zero (0). The ACR controls which word is accessed at register 00h as follows: A read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 18). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL78419 responds with an ACK; then the ISL78419 transmits the Data Byte. The master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte (see Figure 16). • 00h = Nonvolatile IVR • 80h = Volatile WR All other bits of the ACR should be written 0 or 1. Power-up default for this address is 00h. Register Description: IVR and WR The output of the DCP is controlled directly by the WR. Writes and reads can be made directly to this register to control and monitor without any non-volatile memory changes. This is done by setting address 02h to data 80h, then writing the data. The byte at address 02h determines if the Data Bytes being read are from volatile or non-volatile memory. Communication with ISL78419 The non-volatile IVR stores the power-up value of the DCP output. On power -up, the contents of the IVR are transferred to the WR. There are 3 register addresses in the ISL78419, of which two can be used. Address 00h and address 02h are used to control the device. Address 01h is reserved and should not be used. Address 00h contains the non-volatile Initial Value Register (IVR), and the volatile Wiper Register (WR). Address 02h contains only a volatile word and is used as a pointer to either the IVR or WR. To write to the IVR, first address 02h is set to data 00h, then the data is written. Writing a new value to the IVR register will set a new power-up position for the wiper. Also, writing to this register will load the same value into the WR as the IVR. Therefore, if a new value is loaded into the IVR, not only will the non-volatile IVR change, but the WR will also contain the same value after the write, and the wiper position will change. Reading from the IVR will not change the WR, if its contents are different. Register Description: Access Control The Access Control Register (ACR) is volatile and is at address 02h. It is 8 bits, and only the MSB is significant; all other bits Writing a new value to the IVR Write to ACR first 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 0 A 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A D0 D7 D6 D5 D4 D3 D2 D1 A Then, write to IVR 0 1 Note that the WR will also reflect this new value since both registers get writen at the same time D0:LSB, D7:MSB Writing a new value to WR only Write to ACR first 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 1 0 0 0 0 0 0 0 A 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A D0 D7 D6 D5 D4 D3 D2 D1 A 0 0 0 0 0 0 0 0 A 1 0 0 0 0 0 0 0 A Then, write to WR 0 1 Note that the IVR value will NOT change D0:LSB, D7:MSB Reading from IVR Write to the ACR first 0 1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A 0 1 0 0 0 1 A D0 D7 D6 D5 D4 D3 D2 D1 0 1 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0 1 0 0 0 0 A 0 0 0 0 0 0 0 0 A 0 1 0 0 0 1 A D0 D7 D6 D5 D4 D3 D2 D1 Then set the IVR address 0 1 Read from the IVR 0 1 Example 2 Reading from the WR Write to the ACR first 0 1 Then set the WR address 0 1 Read from the WR 0 1 FIGURE 19. 16 FN8292.2 January 24, 2014 ISL78419 Initial VCOM Setting Layout Recommendation A 256-step resolution is provided under digital control, which adjusts the sink current of the output. The output is connected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current. The equations that control the output are given in the following. The initial setting value is at 128. The WR value is set back to 128 if any error occurs during I2C read or write communication. When writing to the EEPROM, VGH needs to be higher than 12V when AVDD is 8V. Outside these conditions, writing operations may be not successful. The maximum resistor value of RSET is determined by Equations 9 and 10: The device's performance, including efficiency, output noise, transient response and control loop stability, is affected by the PCB layout. PCB layout is critical, especially at high switching frequency. RSET > V_AVDD ⁄ ( 20x100μA ) V AVDD 255 – Setting IOUT = ------------------------------------- ⋅ ----------------------------20 ( RSET ) 255 (EQ. 9) (EQ. 10) Where RL, RU and RSET in Equation 11 correspond to R7, R8 and R9 in the Application Diagram on page 2. R L ⋅ V AVDD RU 255 – Setting VOUT = -------------------------------- ⋅ ⎛ 1 – ------------------------------------- × -----------------------------⎞ ( RU + RL ) ⎝ 20 ( RSET )⎠ 255 (EQ. 11) Start-up Sequence When VIN rising exceeds UVLO, it takes 120µs to read the settings stored in the chip in order to activate the chip correctly. After all the settings are written in the registers, VLOGIC starts up with a 0.5ms soft-start time. When both VLOGIC is in regulation and EN is high, the boost converter starts up. The Gate Pulse modulator output VGHM is held low until VDPM is charged to 1.215V. The detailed power-on sequence is shown in Figure 20. Following are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VDC and VREF bypass capacitors close to the pins. 3. Loops with large AC amplitudes and fast slew rate should be made as small as possible. 4. The feedback network should sense the output voltage directly from the point of load, and be as far away from the LX node as possible. 5. The power ground (PGND) should be connected at the ISL78419 exposed die plate area. 6. The exposed die plate, on the underside of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB, as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. Minimize feedback input track lengths to avoid switching noise pick-up. 17 FN8292.2 January 24, 2014 ISL78419 EN UVLO UVLO VIN tSS_VLOGIC PANEL NORMAL OPERATION VLOGIC AVDD tSS_AVDD CONTROLLED BY VSS VOFF VON VCOM 1.280V 1.222V 1.217V VDIV CD2 1.215V RESET VDPM GPM ENABLED WHEN BOTH 1) EN = HIGH AND 2) VDPM > 1.215V VGHM VGHM OUTPUT TIED TO VGH WHEN VIN FALLS TO UVLO FIGURE 20. ISL78419 POWER ON/OFF SEQUENCE 18 FN8292.2 January 24, 2014 ISL78419 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE January 24, 2014 FN8292.2 Page 19 - 2nd line of the disclaimer changed from: "Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted" to: "Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted" - Updated "About Intersil" verbiage December 3, 2012 FN8292.1 Initial Release. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/en/support/qualandreliability.html#reliability For additional products, see www.intersil.com/en/products.html Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN8292.2 January 24, 2014 ISL78419 Package Outline Drawing L28.4x5A 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 06/08 2.50 4.00 B 22 5.00 PIN #1 INDEX AREA 28 23 6 PIN 1 INDEX AREA (4X) 6 24X 0.50 A 1 3.50 Exp. DAP 3.50 0.10 M C A B 4 28X 0.25 0.15 8 15 9 14 SIDE VIEW TOP VIEW 2.50 Exp. DAP 28X 0.400 BOTTOM VIEW SEE DETAIL "X" ( 3.80 ) 0.10 C Max 0.90 ( 2.50) C SEATING PLANE 0.08 C SIDE VIEW ( 4.80 ) ( 24X 0.50) ( 3.50 ) C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. (28X .250) DETAIL "X" ( 28 X 0.60) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. 20 The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN8292.2 January 24, 2014