APW7061 Synchronous Buck PWM Controller Features General Description • The APW7061 is a voltage mode, synchronous PWM Fast Transient Response cont roller which drives dual N-c hannel MOSFETs . It - 0~85% Duty Ratio • • • integrates t he c ont rols, monitoring and protec tion Excellent Output Voltage Regulation funct ions into a single package, which provides one - 0.8V Internal Reference c ontrolled power output s wit h under-voltage and - ±1% Over Line Voltage and Temperature over-current protections. Internal Soft-Start APW7061 provides excellent regulation for output load - Typical 2mS variation. An internal 0.8V temperature-compensated Over Current Protection reference voltage is designed to meet the various low output voltage applications. - Sense Low-side MOSFET’s RDS(ON) • • A power-on-reset (POR) circuit limits the VCC minimum Under Voltage Lockout opearting s upply voltage to ass ure the c ontroller Small Converter Size working well. Over current protec tion is achieved by monit oring t he volt age drop ac ros s the low s ide MOSFET, eliminating the need for a current sensing resistor and short circuit condition is detected through - 250kHz Free-running Oscillator • • 8-lead SOIC Package Lead Free Available (RoHS Compliant) the FB pin. The over-current protection triggers the soft -start function until the fault events be removed, Applications • Graphic Cards • Memory Power Supplies • DSL or Cable MODEMs • Set Top Boxes • Low-Voltage Distributed Power Supplies but Under-voltage protection will shutdown IC directly. Pull the COMP pin below 0.4V will shutdown t he controller, and both gate drive signals will be low. Pinouts VCC 1 8 LGATE FB 2 7 BOOT COMP 3 6 UGATE GND 4 5 PHASE ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 1 www.anpec.com.tw APW7061 Ordering and Marking Information APW7061 Lead Free Code Handling Code Temp. Range Package Code APW7061 K : Package Code K : SOP-8 Operating Junction Temp. Range C : 0 to 70 ° C Handling Code TU : Tube TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device APW7061 XXXXX XXXXX - Date Code No te : ANPEC lea d-fre e p ro ducts co ntain mo ld ing comp oun ds /di e attach m ate ri als and 100 % matte ti n p la te te rmin atio n fi nish ; wh ich are full y compl iant with Ro HS and compa tibl e wi th both SnPb an d le ad-free sold ieri ng op era tio ns. AN PEC le ad-free produ cts me et or exceed th e l ead -free req uireme nts of IPC /JEDEC J STD -02 0C fo r MSL classi ficati on at lea d-fre e p eak re flo w temp era ture. Block Diagram VCC GND Power-On Reset BOOT Gate Control Soft Start UGATE V CC IOCSET 250uA U.V.P Comparator 50%VR E F O.C.P Comparator :2 PWM Comparator PHASE VCC LGATE Error Amp V REF Triangle Wave FB COMP C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 2 www.anpec.com.tw APW7061 Application Circuit 12V L1 1uH R1 2R2 + C1 470uF 16V 25mR /SHDN C5 1uF 1 2 3 4 VCC FB COMP GND LGATE BOOT UGATE PHASE 8 7 6 5 R3 + C4 470uF 16V 25mR 1 2 3 C7 R4 620R Q1 APM4220 4 0R R2 20K C6 56pF + C3 470uF 16V 25mR 8 7 6 5 D1 1N4148 U1 APW7061 C2 4.7uF 0.1uF 2.5V L2 C8 0.01uF 8 7 6 5 R6 R5 100R Q2 APM4220 4 0R 2.2uH 1 2 3 D2 SR24 2A/40V R7 2.32KF 1% + C9 1000uF 6.3V 30mR + C10 1000uF 6.3V 30mR C11 4.7uF C12 0.1uF R8 1.07KF 1% Absolute Maximum Ratings Symbol Parameter Rating Unit 30 V VBOOT, UGATE BOOT to GND, UGATE to GND 30 V PHASE to GND 30 VCC, LGATE VCC to GND, LGATE to GND Operating Junction Temperature T STG Storage Temperature V 0~150 o C -65 ~ 150 o C o C TSDR Soldering Temperature (10 Seconds) 300 VESD Minimum ESD Rating ±2 KV Recommended Operating Conditions Symbol VCC VBOOT Parameter Supply Voltage Min. Nom. Max. Unit 7 12 19 V 26 V Boot Voltage Thermal Characteristics Symbol θJA Parameter Value Junction to Ambient Resistance in free air (SOP-8) C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 3 160 Unit o C/W www.anpec.com.tw APW7061 Electrical Characteristics Unless otherswise specified, these specifications apply over VCC= 12V, VBOOT = 12V and TA = 0 ~ 70oC. Typlcal values are at TA = 25oC. Symbol Parameter Test Conditions APW7061 Min Typ Max Unit SUPPLY CURRENT ICC IBOOT VCC Nominal Supply UGATE and LGATE Open 2 mA BOOT Nominal Supply UGATE Open 2 mA POWER-ON-RESET Rising VCC Threshold 7.0 7.2 7.4 V Falling VCC Threshold 6.6 6.8 7.0 V 220 250 280 kHz OSCILLATOR FOSC ∆VOSC Free Running Frequency VCC=12V Ramp Upper Threshold 3.0 V Ramp Lower Threshold 1.3 V Ramp Amplitude 1.7 VP-P 0.80 V REFERENCE VREF Reference Voltage Reference Voltage Tolerance -1 +1 % ERROR AMPLIFIER DC Gain 75 UGATE Duty Range 0 FB Input Current dB 85 % 0.1 uA GATE DRIVERS IUGATE Upper Gate Source VBOOT=12V, V UGATE=6V R UGATE Upper Gate Sink IUGATE=0.3A ILGATE Lower Gate Source VCC=12V, V LGATE =6V RLGATE Lower Gate Sink ILGATE =0.3A TD Dead Time 650 800 4 550 mA 8 700 4 Ω mA 8 Ω 30 nS 50 % 250 uA 2 mS 0.4 V 50 mV PROTECTION FB Under Voltage Level FB Falling OCSET source current SOFT START and SHUTDOWN TSS Internal Soft-Start Interval Shutdown Threshold COMP Falling Shutdown Hysteresis C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 4 www.anpec.com.tw APW7061 Functional Pin Description VCC (Pin 1) COMP (Pin 3) This pin provides a supply voltage to the device, When This pin is the output of the error amplifier. Add an VCC is rising above the threshold 4.2V, the device is ex ternal resist or and capacitor net work to provide turned on, and convers ely, when V CC drops below the loop c ompensation for the P WM c onverter (s ee the falling threshold, the device is turned off. A 1uF Applicat ion Informat ion). decoupling capacitor to GND is recommended. Pull this pin below 0.4V will shutdown t he controller, FB (Pin 2) forcing the UGATE and LGATE signals to be 0V. A soft st art c ycle will be init iated upon the release of FB pin is the inverting input of the error amplifier, and this pin. it receives the feedback voltage from an external resistive divider across the output (V OUT). The output PHASE (Pin 5) voltage is determined by: A resistor (ROCSET) is connected between this pin and VOUT R = 0.8V × 1 + OUT R GND the drain of the low-side MOSFET will determine the over current limit. A n int ernally generated 250uA where ROUT is the resistor connected from VOUT to FB, current source will flow through this resistor, creating and RGND is the resistor connected from FB to GND. a voltage drop. This voltage will be compared with the voltage across the low-side MOSFET. The threshold When the FB voltage is under 50% VREF, it will cause of the over current limit is therefore given by : the under voltage protection, and shutdown the device. Remove t he condit ion and restart the VCC voltage, ILIMIT = will enable again the device. 250 µ A × R OCSET R DS(ON) GND (Pin 4) An over current condit ion will cy cle the soft s tart Signal ground for the IC. funct ion unt il the over current condition is removed. Because of the comparator delay time, so the on time UGATE (Pin 6) of the low-side MOSFET must be longer than 800ns This pin provides gate drive for the high-side MOSFET. to have the over current protection work. BOOT (Pin 7) This pin provides the supply voltage to the high side MOS FE T driver. For driving logic level N-channel MOSEFT, a boots trap circuit can be use to create a suitable driver’s supply. LGATE (Pin 8) This pin provides the gate drive signal for the low side MOSFET. C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 5 www.anpec.com.tw APW7061 Typical Characteristics Power Up Power Down VCC(5V/div) VCC(5V/div) VOUT(1V/div) VOUT(1V/div) Time (5ms/div) Time (2ms/div) Enable (COMP is left open) Shutdown(COMP is pulled to GND) COMP(1V/div) COMP(1V/div) VOUT(1V/div) VOUT(1V/div) Time (2ms/div) C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 Time (5ms/div) 6 www.anpec.com.tw APW7061 Typical Characteristics (Cont.) UGATE Falling UGATE Rising VCC=12V, VI N=12V VCC=12V, VIN=12V LGATE(10V/div) LGATE(10V/div) PHASE(10V/div) PHASE(10V/div) UGATE(10V/div) UGATE(10V/div) Time (50ns/div) Time (50ns/div) Over Current Protection VCC=12V,VIN=12V, VOUT =2.5V, ROCSET=1kW RDS(ON)=16mW, L=2.2mH, IOUT =15A Under Voltage Protection IL(10A/div) VCC=12,VIN=12V VOUT=2.5V, L=2.2mH IL(10A/div) UGATE (20V/div) UGATE (20V/div) VOUT (1V/div) VOUT (1V/div) Time (10us/div) C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 Time (2us/div) 7 www.anpec.com.tw APW7061 Typical Characteristics (Cont.) Supply Current vs. Supply Voltage PWM Load Transient 4 VCC=12V VIN=12V VOUT =3.3V C OUT=470mFx2 ESR=22.5mW L=1.5mH f=400kHz Supply Current (mA) 3.5 ICC 3 2.5 2 ICC(SHDN) 1.5 VOUT(100mV/div) 1 0.5 IOUT1(5A/div) 0 0 2 4 6 8 10 12 Supply Voltage (V) Time (20us/div) UGATE Source Current vs. UGATE Voltage UGATE Sink Current vs. UGATE Voltage 1.2 VBOOT=12V 1.2 VBOOT=12V UGATE Sink Current (A) UGATE Source Current (A) 1.4 1 0.8 0.6 0.4 0.2 0 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 0 4 6 8 10 12 UGATE Voltage (V) UGATE Voltage (V) C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 2 8 www.anpec.com.tw APW7061 Typical Characteristics (Cont.) LGATE Source Current vs. LGATE Voltage LGATE Sink Current vs. LGATE Voltage 1.4 1.2 1 LGATE Sink Current (A) LGATE Source Current (A) VCC=12V VCC=12V 1.2 1 0.8 0.6 0.4 0.2 0.8 0.6 0.4 0.2 0 0 0 2 4 6 8 10 0 12 2 4 6 8 12 LGATE Voltage (V) LGATE Voltage (V) Source Current vs. Comp Voltage Sink Current vs. Comp Voltage 150 150 VCC=12V VCC=12V 125 Source Current (µA) 125 Sink Current (µA) 10 100 75 50 100 75 50 25 25 0 0 0 0.5 1 1.5 2 2.5 3 3.5 1 4 2 2.5 3 3.5 4 Comp Voltage (V) Comp Voltage (V) C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 1.5 9 www.anpec.com.tw APW7061 Typical Characteristics (Cont.) Reference Voltage vs. Junction Temperature Reference Voltage (V) 0.8 0.798 0.796 0.794 0.792 0.79 -40 -20 0 20 40 60 80 100 120 Junction Temperature (°C) Application Information least 1.3 times higher than the maximum input voltage. Component Selection Guidelines The maximum RMS c urrent rating requirement is Output Capacitor Selection approximately IOUT/2 , where IOUT is the load current. The s election of COU T is determined by the required During power up, the input capacitors have to handle effective series resist ance (ESR) and voltage rat ing large amount of surge current. If tantalum capacitors rat her t han t he ac tual c apacit anc e requirement . are us ed, make s ure they are surge t est ed by t he Therefore select high performance low ESR capacitors manufact ures . If in doubt, c onsult t he c apac it ors that are intended for switching regulator applications. manufac turer. In some applications, multiple capacitors have to be For high frequency decoupling, a ceramic capacitor paralled to achieve the desired ESR value. If tantalum between 0.1uF to 1uF can be connected between VCC capacitors are used, make sure they are surge tested and ground pin. by the manufactures. If in doubt, consult the capacitors manufac turer. Input Capacitor Selection Inductor Selection The input capacitor is chos en based on the volt age The inductanc e of the inductor is determined by the rat ing and the RMS c urrent rat ing. For reliable output voltage requirement. The larger the inductance, operation, select the capacitor voltage rating to be at the lower the inductor’s current ripple. This will translate C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 10 www.anpec.com.tw APW7061 Application Information (Cont.) Inductor Selection (Cont.) The poles and zero of this transfer function are: into lower output ripple voltage. The ripple current and FLC ripple voltage can be approximated by: VIN - VOUT IRIPPLE = Fs x L x = 1 2 × π × L × COUT VOUT VIN FESR = ∆VOUT = IRIPPLE x ESR 1 2 × π × ESR × COUT The FLC is the double poles of the LC filter, and FESR is where Fs is the switching frequency of the regulator. the zero introduced by the ESR of the output capacitor. There is a tradeoff exists between the inductor’s ripple current and the regulator load transient response time L PHASE Output A smaller inductor will give the regulator a faster load COUT trans ient res ponse at the expens e of higher ripple current and vice versa. The maximum ripple current ESR occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 30% of the maximum output current. Figure 1. The Output LC Filter Once the induct ance value has been chosen, s elect an inductor that is capable of carrying the required F LC -40dB/dec peak current without going into s aturation. In s ome ty pe of induc tors, es pec ially core that is make of ferrite, the ripple current will increase abruptly when it FESR saturates. This will result in a larger output ripple Gain voltage. -20dB/dec Compensation The output LC filter introduces a double pole, which contributes wit h – 40dB/decade gain slope and 180 Frequency degrees phase shift in the control loop. A compensation network between COMP pin and ground should be Figure 2. The Output LC Filter Gain & Frequency added. The simplest loop compensation network is shown in Figure. 4. The PWM modulator is shown in Figure. 3. The input The out put LC filter consist s of the output induc tor is the output of the error amplifier and the output is the and output capacitors. The transfer function of the LC P HA SE node. The trans fer func tion of t he PW M filter is given by: modulator is given by: GAINLC = 1 + s × ESR × COUT GAINPWM = s × L × COUT + s × ESR + 1 2 C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 11 VIN ∆V OSC www.anpec.com.tw APW7061 Application Information (Cont.) Compensation (Cont.) The c losed loop gain of the converter c an be written V IN as: GAINLC x GAINPWM x Driver PWM Comparator R2 x GAINAMP R1+ R2 Figure 5 s hows t he converter gain and the following guidelines will help t o des ign the c ompens at ion V OSC network. Output of Error Amplifier PHASE 1.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) x FS >FO>FZ Use the following equation to calculate R3: Driver R3 = Figure 3. The PWM Modulator VIN F ESR R1 + R2 FO × × 2 R2 gm FLC × Where: The compens ation circuit is s hown in Figure 4. R3 gm = 900uA/V and C1 introduce a zero and C2 introduces a pole to reduce the switc hing noise. The transfer function of 2.Place the zero FZ before the LC filter double poles error amplifier is given by: FLC: 1 1 // GAINAMP = gm× Zo = gm × R3 + sC1 sC2 1 s + R3 × C1 = gm × C1 + C2 s× s + × C2 R3 × C1 × C2 FZ = 0.75 x FLC Calculate the C1 by the equation: C1 = 1 2 × π × R1× 0.75 × FLC 3. Set the pole at the half the switching frequency: FP = 0.5 x FS Calculate the C2 by the equation: C1 C2 = π × R3 × C1 × F S − 1 The poles and zero of the compensation network are: 1 FP = C1× C2 2 × π × R3× C1+ C2 FZ ∆ VOSC 1 = 2 × π × R3 × C1 FZ=0.75FLC V OUT 20⋅log(gm⋅R3) Error Amplifier R1 FP=0.5FS Compensation Gain Gain FB R2 + V REF COMP FLC 20 ⋅ log R3 FO VIN ? VOSC FESR C2 PWM & Filter Gain Converter Gain C1 Frequency Figure 5. Converter Gain & Frequency Figure 4. Compensation Network C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 12 www.anpec.com.tw APW7061 Application Information (Cont.) • Keep t he switching nodes (UGATE, LGATE and MOSFET Selection The s election of the N-c hannel power MOSFETs are PHA SE) away from s ensit ive small signal nodes determined by the RDS(ON), reverse transfer capacitance since these nodes are fast moving signals. Therefore (C RSS) and max imum out put c urrent requirement . keep traces to these nodes as short as possible. The los ses in t he MOSFE Ts have two components: • The ground return of CIN must return to the combine conduc tion loss and transition loss. For the upper and COUT (-) terminal. lower MOSFE T, the losses are approximately given • Capacitor CBOOT should be connected as close to by the following : the BOOT and PHASE pins as possible. PUPPER = Iout (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS 2 PLOWER = Iout (1+ TC)(RDS(ON))(1-D) VDS 2 Voltage across drain and source of MOSFET where IOUT is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tsw is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the upper MOSFET include an additional transition loss. The switching internal, tsw, is a function of the reverse transfer capac it anc e CRSS. Figure 6 illustrat es t he t sw switching waveform internal of the MOSFET. The (1+TC) term is to factor in the temperature dependency Time Figure 6. Switching waveform across MOSFET of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET. VIN Layout Considerations In high power switching regulator, a correct layout is C IN APW7061 important to ensure proper operation of the regulator. PGND In general, int erconnec ting impedanc es should be minimized by using short, wide printed circuit traces. 11 + LGATE 12 Signal and power grounds are to be kept separate and finally combined using ground plane cons truction or U 9 1 UGATE single point grounding. Figure 8 illustrates the layout, PHASE 8 wit h bold lines indic at ing high c urrent pat hs . C OUT Q1 Q2 + L1 L O A D VO U T Component s along the bold lines should be placed close together. Below is a checklist for your layout: C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 Figure 7. Recommended Layout Diagram 13 www.anpec.com.tw APW7061 Package Information E e1 0.015X45 SOP-8 pin ( Reference JEDEC Registration MS-012) H e2 D A1 A 1 L 0.004max. Dim Millimeters Inches Min. Max. Min. Max. A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 e1 e2 0.33 0.51 0.013 0.020 φ1 C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 1.27BSC 0.50BSC 8° 8° 14 www.anpec.com.tw APW7061 Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 ° t 25 C to Peak Time Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate 3°C/second max. 3° C/second max. (TL to T P) Preheat 100°C 150° C - Temperature Min (Tsmin) °C 150 200° C - Temperature Max (Tsmax) 60-120 seconds 60-180 seconds - Time (min to max) (ts) Time maintained above: 183°C 217° C - Temperature (TL) 60-150 seconds 60-150 seconds - Time (t L) Peak/Classificatioon Temperature (Tp) See table 1 See table 2 Time within 5° C of actual 10-30 seconds 20-40 seconds Peak Temperature (tp) Ramp-down Rate 6°C/second max. 6° C/second max. 6 minutes max. 8 minutes max. Time 25° C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 15 www.anpec.com.tw APW7061 Classification Reflow Profiles(Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures Package Thickness Volume mm3 <350 <2.5 mm 240 +0/-5° C ≥2.5 mm 225 +0/-5° C Volume mm3 ≥350 225 +0/-5° C 225 +0/-5° C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm ° ° 260 +0 C* 260 +0 C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0 °C* 245 +0°C* ≥2.5 mm ° ° 250 +0 C* 245 +0 C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0° C. For example 260 °C+0° C) at the rated MSL level. Reliability Test Program Test item Method SOLDERABILITY HOLT PCT TST Description MIL-STD-883D-2003 MIL-STD 883D-1005.7 JESD-22-B, A102 MIL-STD 883D-1011.9 245°C,5 SEC 1000 Hrs Bias @ 125°C 168 Hrs, 100% RH, 121°C -65°C ~ 150°C, 200 Cycles Carrier Tape & Reel Dimensions t E P Po D P1 Bo F W Ao C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 D1 16 Ko www.anpec.com.tw APW7061 Reel Dimensions Application A 330 ± 1 SOP- 8 F 5.5 ± 1 B C 62 +1.5 12.75+ 0.15 D D1 J T1 T2 W P E 2 ± 0.5 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75± 0.1 Po P1 Ao Bo Ko t 2.0 ± 0.1 6.4 ± 0.1 5.2 ± 0. 1 1.55 +0.1 1.55+ 0.25 4.0 ± 0.1 2.1 ± 0.1 0.3± 0.013 Cover Tape Dimensions Application SOP- 8 Carrier Width 12 Cover Tape Width 9.3 Devices Per Reel 2500 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 C opyright ANPEC Electronics C orp. Rev. A.7 - Nov., 2005 17 www.anpec.com.tw