AD AD9269-40EBZ 16-bit, 20/40/65/80 msps, 1.8 v dual analog-to-digital converter Datasheet

16-Bit, 20/40/65/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9269
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Integrated quadrature error correction (QEC)
SNR
77.6 dBFS at 9.7 MHz input
71 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
44 mW per channel at 20 MSPS
100 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.1 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer (DCS)
Integer 1-to-6 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
AVDD
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
SDIO SCLK CSB
GND
SPI
ADC
VREF
VCM
REF
SELECT
RBIAS
VIN–B
ADC
VIN+B
DIVIDE
1 TO 6
CLK+ CLK–
SYNC
D15A
D0A
DCOA
DRVDD
CMOS
OUTPUT BUFFER
QUADRATURE
ERROR
CORRECTION
SENSE
MUX OPTION
VIN–A
ORA
DUTY CYCLE
STABILIZER
MODE
CONTROLS
DCS
PDWN DFS OEB
ORB
D15B
D0B
DCOB
08538-001
PROGRAMMING DATA
VIN+A
CMOS
OUTPUT BUFFER
AD9269
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
The AD9269 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
An optional SPI selectable dc correction and quadrature
error correction (QEC) feature corrects for dc offset, gain,
and phase mismatches between the two channels.
A standard serial port interface (SPI) supports various
product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing
and offset adjustments, and voltage reference modes.
The AD9269 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9268 16-bit
ADC, the AD9258 14-bit ADC, the AD9251 14-bit ADC
the AD9231 12-bit ADC, the AD6659 12-bit baseband
diversity receiver, and the AD9204 10-bit ADC, enabling a
simple migration path between 10-bit and 16-bit converters
sampling from 20 MSPS to 125 MSPS.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
AD9269
TABLE OF CONTENTS
Features .............................................................................................. 1
Clock Input Considerations ...................................................... 22
Applications ....................................................................................... 1
Power Dissipation and Standby Mode .................................... 24
Functional Block Diagram .............................................................. 1
Digital Outputs ........................................................................... 25
Product Highlights ........................................................................... 1
Timing ......................................................................................... 25
Revision History ............................................................................... 2
Built-In Self-Test (BIST) and Output Test .................................. 26
General Description ......................................................................... 3
Built-In Self-Test (BIST) ............................................................ 26
Specifications..................................................................................... 4
Output Test Modes ..................................................................... 26
DC Specifications ......................................................................... 4
Channel/Chip Synchronization .................................................... 27
AC Specifications.......................................................................... 6
DC and Quadrature Error Correction (QEC) ............................ 28
Digital Specifications ................................................................... 7
Serial Port Interface (SPI) .............................................................. 29
Switching Specifications .............................................................. 8
Configuration Using the SPI ..................................................... 29
Timing Specifications .................................................................. 9
Hardware Interface..................................................................... 29
Absolute Maximum Ratings.......................................................... 10
Configuration Without the SPI ................................................ 30
Thermal Characteristics ............................................................ 10
SPI Accessible Features .............................................................. 30
ESD Caution ................................................................................ 10
Memory Map .................................................................................. 31
Pin Configuration and Function Descriptions ........................... 11
Reading the Memory Map Register Table............................... 31
Typical Performance Characteristics ........................................... 13
Open Locations .......................................................................... 31
AD9269-80 .................................................................................. 13
Default Values ............................................................................. 31
AD9269-65 .................................................................................. 15
Memory Map Register Table ..................................................... 32
AD9269-40 .................................................................................. 16
Memory Map Register Descriptions ........................................ 34
AD9269-20 .................................................................................. 17
Applications Information .............................................................. 36
Equivalent Circuits ......................................................................... 18
Design Guidelines ...................................................................... 36
Theory of Operation ...................................................................... 19
Outline Dimensions ....................................................................... 37
ADC Architecture ...................................................................... 19
Ordering Guide .......................................................................... 37
Analog Input Considerations.................................................... 19
Voltage Reference ....................................................................... 21
REVISION HISTORY
1/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9269
GENERAL DESCRIPTION
The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit,
20/40/65/80 MSPS analog-to-digital converter (ADC). It features
a high performance sample-and-hold circuit and on-chip voltage
reference.
The product uses multistage differential pipeline architecture with
output error correction logic to provide 16-bit accuracy at 80 MSPS
data rates and to guarantee no missing codes over the full operating
temperature range.
The AD9269 incorporates an optional integrated dc correction and
quadrature error correction block (QEC) that corrects for dc
offset, gain, and phase mismatch between the two channels.
This functional block can be very beneficial to complex signal
processing applications such as direct conversion receivers.
The ADC also contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, gray code,
or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with
receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported,
and output data can be multiplexed onto a single output bus.
The AD9269 is available in a 64-lead RoHS-compliant LFCSP
and is specified over the industrial temperature range (−40°C to
+85°C).
Rev. 0 | Page 3 of 40
AD9269
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error 1
Differential
Nonlinearity
(DNL) 2
Integral Nonlinearity
(INL)2
MATCHING
CHARACTERISTICS
Offset Error
Gain Error1
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE
REFERENCE
Output Voltage
(1 V Mode)
Load Regulation
Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span,
VREF = 1.0 V
Input Capacitance 3
Input CommonMode Voltage
Input CommonMode Range
REFERENCE INPUT
RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
Temp
Full
Min
16
AD9269-20/AD9269-40
Typ
Max
Min
16
AD9269-65
Typ
Max
Min
16
AD9269-80
Typ
Max
Full
Full
Full
Full
Guaranteed
±0.05
±0.40
−2.0
−0.9/+1.2
Guaranteed
±0.05
±0.50
−2.0
−0.9/+1.4
Guaranteed
±0.05
±0.50
−2.0
−0.9/+1.65
25°C
Full
−0.5/+0.6
−0.5/+1.1
−0.5/+1.1
25°C
±2.0
25°C
25°C
±0.0
±0.2
Full
±2
Full
±5.50
0.981
0.993
±6.50
±6.50
±2.2
±0.50
±0.0
±0.2
±3.3
±0.55
±0.0
±0.2
±2
1.005
0.981
0.993
0.981
0.993
% FSR
% FSR
LSB
LSB
LSB
LSB
±0.65
±2
1.005
Unit
Bits
% FSR
% FSR
ppm/°C
1.005
V
Full
2
2
2
mV
25°C
2.8
2.8
2.8
LSB
rms
Full
2
2
2
V p-p
Full
Full
6.5
0.9
6.5
0.9
6.5
0.9
pF
V
Full
0.5
Full
Full
Full
Full
Full
Full
1.3
0.5
7.5
1.7
1.7
1.3
0.5
7.5
1.8
1.9
3.6
1.7
1.7
50.0/69.3
3.9/6.4
7.4/12.4
52.5/72.6
7.5
1.8
1.9
3.6
96.6
9.6
18.7
101.2
Rev. 0 | Page 4 of 40
1.3
1.7
1.7
V
kΩ
1.8
1.9
3.6
V
V
113
11.8
23
119
mA
mA
mA
AD9269
Parameter
POWER
CONSUMPTION
DC Input
Sine Wave Input2
(DRVDD = 1.8 V)
Sine Wave Input2
(DRVDD = 3.3 V)
Standby Power 4
Power-Down Power
Temp
Min
AD9269-20/AD9269-40
Typ
Max
Min
AD9269-65
Typ
Max
AD9269-80
Typ
Max
Unit
200
224.6
mW
mW
Full
Full
87.7/121.7
96.9/136.3
Full
114.4/165.7
235.6
279
mW
Full
Full
37/37
1.0
37
1.0
37
1.0
mW
mW
102.0/142.3
170.7
191.2
Min
1
199.8
Measured with a 1.0 V external reference.
Measured with a 10 MHz input frequency at a rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input and the CLK+, CLK− active.
2
Rev. 0 | Page 5 of 40
240
AD9269
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
TWO-TONE SFDR
fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
CROSSTALK 2
ANALOG INPUT BANDWIDTH
1
2
Temp
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
AD9269-20/AD9269-40
Min
Typ
Max
Min
78.0
77.5
AD9269-65
Typ
Max
Min
77.5
77.5
76.5
AD9269-80
Typ
Max
77.6
77.2
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
76.5
76.5
76.5
76.3
75.5
71.0
77.9
77.2
77.4
77.2
76.0
77.4
76.9
69.4
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
76.0
76.4
76.4
Unit
76.1
75.0
25°C
25°C
25°C
25°C
12.6
12.5
12.4
12.6
12.5
12.4
12.6
12.5
12.3
11.2
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
Full
25°C
−95
−90
−97
−93
−93
−92
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
Full
25°C
95
90
−80
−80
−89
−97
−90
−80
−80
95
91
80
93
92
dBc
dBc
dBc
dBc
dBc
dBc
80
89
95
90
80
80
25°C
25°C
Full
25°C
Full
25°C
−99
−100
25°C
Full
25°C
90
−110
700
−89
−100
−90
−99
−99
−99
−86
dBc
dBc
dBc
dBc
dBc
dBc
90
−110
700
dBc
dBc
MHz
−91
−100
−97
−89
90
−110
700
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 6 of 40
AD9269
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, SYNC, PDWN) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DCS)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, IOH = 50 μA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 μA
DRVDD = 1.8 V
High Level Output Voltage, IOH = 50 μA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 μA
1
2
Temp
Full
Full
Full
Full
Full
Full
Full
Min
AD9269-20/AD9269-40/AD9269-65/AD9269-80
Typ
Max
CMOS/LVDS/LVPECL
0.9
0.2
GND − 0.3
−10
−10
8
Full
Full
Full
Full
Full
Full
1.2
0
−50
−10
Full
Full
Full
Full
Full
Full
1.2
0
−10
40
Full
Full
Full
Full
Full
Full
1.2
0
−10
40
Full
Full
Full
Full
3.29
3.25
Full
Full
Full
Full
1.79
1.75
10
4
3.6
AVDD + 0.2
+10
+10
12
V
V
μA
μA
kΩ
pF
DRVDD + 0.3
0.8
+10
135
V
V
μA
μA
kΩ
pF
DRVDD + 0.3
0.8
+10
130
V
V
μA
μA
kΩ
pF
26
2
26
5
Rev. 0 | Page 7 of 40
V
V p-p
V
μA
μA
kΩ
pF
DRVDD + 0.3
0.8
−75
+10
30
2
Internal 30 kΩ pull-down.
Internal 30 kΩ pull-up.
Unit
0.2
0.05
V
V
V
V
0.2
0.05
V
V
V
V
AD9269
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate 1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
With QEC Active
Wake-Up Time 2
Standby
OUT-OF-RANGE RECOVERY TIME
480
20/40
Min
AD9269-65
Typ
Max
AD9269-80
Typ
Max
Full
Full
25.0/12.5
1.0
0.1
7.69
1.0
0.1
6.25
1.0
0.1
Full
Full
Full
Full
Full
Full
Full
Full
3
3
0.1
9
11
350
600/400
2
3
3
0.1
9
11
350
300
2
3
3
0.1
9
11
350
260
2
ns
ns
ns
Cycles
Cycles
μs
ns
Cycles
50/25
3
15.38
480
80
Unit
MHz
MSPS
ns
ns
ns
ps rms
3
480
65
Min
3
12.5
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
tSKEW
CH A/CH B DATA
N–9
N–8
N–7
N–6
N–5
tPD
08538-002
2
Full
Full
Full
AD9269-20/AD9269-40
Min
Typ
Max
Figure 2. CMOS Output Data Timing
N–1
N+4
tA
N+5
N
N+3
VIN
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
tSKEW
CH A
N–9
CH A/CH B DATA
CH B
N–9
CH A
N–8
CH B
N–8
CH A
N–7
tPD
Figure 3. CMOS Interleaved Output Timing
Rev. 0 | Page 8 of 40
CH B
N–7
CH A
N–6
CH B
N–6
CH A
N–5
08538-003
1
Temp
AD9269
TIMING SPECIFICATIONS
Table 5.
tDIS_SDIO
Conditions
Min
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
Figure 4. SYNC Input Timing Requirements
Rev. 0 | Page 9 of 40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
tHSYNC
SYNC
Max
2
2
40
2
2
10
10
10
CLK+
tSSYNC
Typ
0.24
0.40
08538-004
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
AD9269
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
AVDD to AGND
DRVDD to AGND
VIN+A, VIN+B, VIN−A, VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB to AGND
PDWN to AGND
D0x through D15x to AGND
DCOx to AGND
Operating Temperature Range (Ambient)
Maximum Junction Temperature Under Bias
Storage Temperature Range (Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The exposed paddle is the only ground connection for the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s PCB. Soldering the exposed paddle to the user’s board
also increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2
23
20
18
θJC1, 3
2.0
θJB1, 4
12
Unit
°C/W
°C/W
°C/W
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
3
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
ESD CAUTION
Rev. 0 | Page 10 of 40
AD9269
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
RBIAS
VCM
SENSE
VREF
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9269
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D15A (MSB)
D14A
D13A
D12A
D11A
DRVDD
D10A
D9A
D8A
D7A
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND
TO ENSURE PROPER HEAT DISSIPATION, NOISE, AND MECHANICAL
STRENGTH BENEFITS.
08538-005
D12B
D13B
DRVDD
D14B
D15B (MSB)
ORB
DCOB
DCOA
D0A (LSB)
D1A
D2A
DRVDD
D3A
D4A
D5A
D6A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK+
CLK–
SYNC
D0B (LSB)
D1B
D2B
D3B
D4B
D5B
DRVDD
D6B
D7B
D8B
D9B
D10B
D11B
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
0, EP
Mnemonic
AGND
1, 2
3
4 to 9, 11 to
18, 20, 21
10, 19, 28, 37
22
23
24
25 to 27, 29 to
36, 38 to 42
43
44
CLK+, CLK−
SYNC
D0B (LSB) to
D15B (MSB)
DRVDD
ORB
DCOB
DCOA
D0A (LSB) to
D15A (MSB)
ORA
SDIO/DCS
45
SCLK/DFS
46
47
CSB
OEB
48
PDWN
Description
The exposed paddle is the only ground connection. It must be soldered to the PCB analog ground to
ensure proper functionality and heat dissipation, noise, and mechanical strength benefits.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.
Channel B Digital Outputs. D0B is the LSB; D15B is the MSB.
Digital Output Driver Supply (1.8 V to 3.3 V).
Channel B Out-of-Range Digital Output.
Channel B Data Clock Digital Output.
Channel A Data Clock Digital Output.
Channel A Digital Outputs. D0A is the LSB; D15A is the MSB.
Channel A Out-of-Range Digital Output.
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O in SPI mode. 30 kΩ internal pull-down in SPI mode.
Duty Cycle Stabilizer (DCS). Static enable input for duty cycle stabilizer in non-SPI mode. 30 kΩ internal
pull-up in non-SPI (DCS) mode.
SPI Clock (SCLK). Input in SPI mode. 30 kΩ internal pull-down.
Data Format Select (DFS). Static control of data output format in non-SPI mode. 30 kΩ internal pull-down.
DFS high: twos complement output.
DFS low: offset binary output.
SPI Chip Select. Active low enable; 30 kΩ internal pull-up.
Digital Input. 30 kΩ internal pull-down.
Low: enable Channel A and Channel B digital outputs.
High: three-state outputs.
Digital Input. 30 kΩ internal pull-down.
High: power down device.
Low: run device, normal operation.
Rev. 0 | Page 11 of 40
AD9269
Pin No.
49, 50, 53, 54,
59, 60, 63, 64
51, 52
55
56
57
58
61, 62
Mnemonic
AVDD
Description
1.8 V Analog Supply Pins.
VIN+A, VIN−A
VREF
SENSE
VCM
RBIAS
VIN−B, VIN+B
Channel A Analog Inputs.
Voltage Reference Input/Output.
Reference Mode Selection.
Analog Output Voltage at Midsupply. Sets the common mode of the analog inputs.
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
Channel B Analog Inputs.
Rev. 0 | Page 12 of 40
AD9269
TYPICAL PERFORMANCE CHARACTERISTICS
AD9269-80
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
0
0
80MSPS
9.7MHz @ –1dBFS
SNR = 76.8dB (77.8dBFS)
SFDR = 94.3dBc
–20
–40
–40
AMPLITUDE (dBFS)
–60
–80
–100
–120
–60
–80
–100
–140
0
5
10
15
20
25
30
35
40
–140
0
5
10
15
FREQUENCY (MHz)
25
30
35
40
Figure 9. AD9269-80 Single-Tone FFT with fIN = 30.6 MHz
0
0
80MSPS
69MHz @ –1dBFS
SNR = 75.1dB (76.1dBFS)
SFDR = 89.5dBc
–20
80MSPS
210MHz @ –1dBFS
SNR = 70dB (71dBFS)
SFDR = 79.7dBc
–20
–40
–40
AMPLITUDE (dBFS)
–60
–80
–100
–120
–60
–80
–100
08538-035
–120
–140
0
5
10
15
20
25
30
35
40
–140
0
5
10
15
FREQUENCY (MHz)
25
30
35
40
Figure 10. AD9269-80 Single-Tone FFT with fIN = 210 MHz
0
10
80MSPS
28.3MHz @ –7dBFS
30.6MHz @ –7dBFS
SFDR = 89.5dBc (96.5dBFS)
–10
SFDR (dBc)
SFDR/IMD3 (dBc/dBFS)
–30
20
FREQUENCY (MHz)
Figure 7. AD9269-80 Single-Tone FFT with fIN = 69 MHz
–15
08538-036
AMPLITUDE (dBFS)
20
FREQUENCY (MHz)
Figure 6. AD9269-80 Single-Tone FFT with fIN = 9.7 MHz
AMPLITUDE (dBFS)
08538-034
08538-033
–120
–45
–60
–75
2F1 + F2
2F2 + F1
–90
F2 – F1
–105
F1 + F2
2F2 – F1
2F1 – F2
–30
IMD3 (dBc)
–50
–70
SFDR (dBFS)
–90
–110
–120
IMD3 (dBFS)
4
8
12
16
20
24
28
FREQUENCY (MHz)
32
36
–130
–95
08538-053
–135
Figure 8. AD9269-80 Two-Tone FFT with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz
Rev. 0 | Page 13 of 40
–85
–75
–65
–55
–45
–35
INPUT AMPLITUDE (dBFS)
–25
–15
Figure 11. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz
08538-054
AMPLITUDE (dBFS)
80MSPS
30.6MHz @ –1dBFS
SNR = 76.5dB (77.5dBFS)
SFDR = 85.7dBc
–20
AD9269
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
120
100
SFDRFS
SFDR (dBc)
90
100
70
SNR/SFDR (dBc/dBFS)
SNR/SFDR (dBFS/dBc)
80
SNR (dBFS)
60
50
40
30
20
80
SNRFS
SFDR
60
SNR
40
20
0
50
100
150
INPUT FREQUENCY (MHz)
200
0
–65 –60
08538-057
0
Figure 12. AD9269-80 SNR/SFDR vs. Input Frequency (AIN)
with 2 V p-p Full Scale
–50
–40
–30
–20
INPUT AMPLITUDE (dBFS)
–10
0
08538-061
10
Figure 15. AD9269-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
100
4.0M
90
2.8 LSB RMS
3.5M
SFDR (dBc)
80
SNR (dBFS)
NUMBER OF HITS
SNR/SFDR (dBFS/dBc)
3.0M
70
60
50
40
2.5M
2.0M
1.5M
30
1.0M
20
500k
10
40
50
60
SAMPLE RATE (MSPS)
70
80
0
OUTPUT CODE
Figure 16. Grounded Input Histogram
6
1.0
4
0.5
2
INL ERROR (LSB)
1.5
–0.5
0
–2
–1.5
0
16,384
32,768
OUTPUT CODE
49,152
65,536
–6
0
16,384
32,768
OUTPUT CODE
49,152
Figure 17. INL with fIN = 9.7 MHz
Figure 14. DNL Error with fIN = 9.7 MHz
Rev. 0 | Page 14 of 40
65,536
08538-037
–4
–1.0
08538-038
DNL ERROR (LSB)
Figure 13. AD9269-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz
0
08538-048
30
N – 12
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
20
08538-055
0
10
AD9269
AD9269-65
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
120
0
65MSPS
9.7MHz @ –1dBFS
SNR = 76.9dB (77.9dBFS)
SFDR = 95.9dBc
SFDRFS
100
–40
SNR/SFDR (dBc/dBFS)
–60
–80
–100
80
SNRFS
SFDR
60
SNR
40
20
–140
0
5
10
15
20
25
30
08538-030
–120
0
–65 –60
–50
FREQUENCY (MHz)
–10
0
Figure 21. AD9269-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Figure 18. AD9269-65 Single-Tone FFT with fIN = 9.7 MHz
100
0
65MSPS
69MHz @ –1dBFS
SNR = 75.5dB (76.5dBFS)
SFDR = 87.4dBc
–20
SFDR (dBc)
90
80
SNR/SFDR (dBFS/dBc)
–40
AMPLITUDE (dBFS)
–40
–30
–20
INPUT AMPLITUDE (dBFS)
08538-060
AMPLITUDE (dBFS)
–20
–60
–80
–100
70
SNR (dBFS)
60
50
40
30
20
–120
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 19. AD9269-65 Single-Tone FFT with fIN = 69 MHz
65MSPS
30.6MHz @ –1dBFS
SNR = 76.6dB (77.6dBFS)
SFDR = 89.9dBc
–60
–80
–100
–120
0
5
10
15
20
25
30
08538-031
AMPLITUDE (dBFS)
–40
–140
0
50
100
150
INPUT FREQUENCY (MHz)
200
Figure 22. AD9269-65 SNR/SFDR vs. Input Frequency (AIN) with
2 V p-p Full Scale
0
–20
0
FREQUENCY (MHz)
Figure 20. AD9269-65 Single-Tone FFT with fIN = 30.6 MHz
Rev. 0 | Page 15 of 40
08539-056
–140
08538-032
10
AD9269
AD9269-40
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
120
0
40MSPS
9.7MHz @ –1dBFS
SNR = 76.9dB (77.9dBFS)
SFDR = 95.1dBc
SFDRFS
100
SNR/SFDR (dBFS/dBFS)
–40
–60
–80
–100
SNRFS
SFDR
60
SNR
40
20
–140
0
2
4
6
8
10
12
14
16
18
20
08538-028
–120
0
–65 –60
FREQUENCY (MHz)
0
40MSPS
30.6MHz @ –1dBFS
SNR = 76.6dB (77.6dBFS)
SFDR = 88.8dBc
–20
–40
–60
–80
–100
–140
2
4
6
8
10
12
14
16
18
20
08538-029
–120
0
–50
–40
–30
–20
INPUT AMPLITUDE (dBFS)
–10
0
Figure 25. AD9269-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Figure 23. AD9269-40 Single-Tone FFT with fIN = 9.7 MHz
AMPLITUDE (dBFS)
80
08538-059
AMPLITUDE (dBFS)
–20
FREQUENCY (MHz)
Figure 24. AD9269-40 Single-Tone FFT with fIN = 30.6 MHz
Rev. 0 | Page 16 of 40
AD9269
AD9269-20
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, DCS disabled,
unless otherwise noted.
0
120
20MSPS
9.7MHz @ –1dBFS
SNR = 76.9dB (77.9dBFS)
SFDR = 95.6dBc
SFDRFS
100
–40
SNR/SFDR (dBc/dBFS)
–60
–80
–100
60
SFDR (dBc)
40
SNR (dBc)
20
–140
0
1
2
3
4
5
6
7
8
9
10
08538-024
–120
0
–90
FREQUENCY (MHz)
0
20MSPS
30.6MHz @ –1dBFS
SNR = 76.7dB (77.7dBFS)
SFDR = 90.7dBc
–20
–40
–60
–80
–100
–140
1
2
3
4
5
6
7
8
9
10
08538-026
–120
0
–80
–70
–60
–50
–40
–30
–20
INPUT AMPLITUDE (dBFS)
–10
0
Figure 28. AD9269-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Figure 26. AD9269-20 Single-Tone FFT with fIN = 9.7 MHz
AMPLITUDE (dBFS)
SNRFS
80
08538-058
AMPLITUDE (dBFS)
–20
FREQUENCY (MHz)
Figure 27. AD9269-20 Single-Tone FFT with fIN = 30.6 MHz
Rev. 0 | Page 17 of 40
AD9269
EQUIVALENT CIRCUITS
DRVDD
AVDD
08538-039
08538-042
VIN±x
Figure 34. Equivalent Digital Output Circuit
Figure 29. Equivalent Analog Input Circuit
AVDD
AVDD
DRVDD
30kΩ
350Ω
SDIO/DCS
375Ω
RBIAS
AND VCM
08538-041
08538-044
30kΩ
Figure 35. Equivalent RBIAS, VCM Circuit
Figure 30. Equivalent SDIO/DCS Input Circuit
DRVDD
DRVDD
AVDD
SCLK/DFS, SYNC,
OEB, AND PDWN
350Ω
350Ω
30kΩ
CSB
08538-043
08538-045
30kΩ
Figure 31. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit
Figure 36. Equivalent CSB Input Circuit
AVDD
AVDD
375Ω
SENSE
375Ω
08538-047
7.5kΩ
08538-046
VREF
Figure 37. Equivalent SENSE Circuit
Figure 32. Equivalent VREF Circuit
AVDD
5Ω
CLK+
15kΩ
0.9V
AVDD
15kΩ
5Ω
08538-040
CLK–
Figure 33. Equivalent Clock Input Circuit
Rev. 0 | Page 18 of 40
AD9269
THEORY OF OPERATION
In nondiversity applications, the AD9269 can be used as a baseband or direct downconversion receiver, in which one ADC is
used for I input data and the other is used for Q input data.
The AD9269 incorporates an optional, integrated dc correction
and quadrature error correction block (QEC) that can correct
for dc offset, gain, and phase mismatch between the two channels.
This functional block can be very beneficial to complex signal
processing applications such as direct conversion receivers.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD9269 are accomplished
using a 3-wire SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9269 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in
the preceding stage. The quantized outputs from each stage are
combined into a final 16-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with a
new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9269 is a differential switchedcapacitor circuit designed for processing differential input signals.
This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode
voltage of midsupply, users can minimize signal-dependent errors
and achieve optimum performance.
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 38). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current injected from the output stage of the
driving source. In addition, low Q inductors or ferrite beads can
be placed on each leg of the input to reduce high differential
capacitance at the analog inputs and, therefore, achieve the
maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end
at high IF frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. Refer to the AN-742
Application Note, Frequency Domain Response of SwitchedCapacitor ADCs; the AN-827 Application Note, A Resonant
Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs (see www.analog.com); and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters”
(Volume 39, April 2005) for more information. In general, the
precise values depend on the application.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the CMOS output buffers. The output buffers
are powered from a separate (DRVDD) supply, allowing adjustment of the output voltage swing. During power-down, the output
buffers go into a high impedance state.
Rev. 0 | Page 19 of 40
H
CPAR
H
VIN+x
CSAMPLE
S
S
S
S
CSAMPLE
VIN–x
H
CPAR
H
Figure 38. Switched-Capacitor Input Circuit
08538-006
The AD9269 dual-channel ADC design can be used for diversity
reception of signals, where the ADCs are operating identically on
the same carrier but from two separate antennae. The ADCs can
also be operated with independent analog inputs. The user can
sample any fS/2 frequency segment from dc to 200 MHz, using
appropriate low-pass or band-pass filtering at the ADC inputs
with little loss in ADC performance. Operation to 300 MHz
analog input is permitted, but it occurs at the expense of
increased ADC noise and distortion.
AD9269
Input Common Mode
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
The analog inputs of the AD9269 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide a dc
bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 39.
200Ω
33Ω
VIN
AVDD
90Ω
33Ω
VIN+x
VCM
08538-007
120Ω
ADC
10pF
ADA4938-2
0.1µF
100
200Ω
Figure 40. Differential Input Configuration Using the ADA4938-2
95
For baseband applications below ~10 MHz where SNR is a key
parameter, differential transformer-coupling is the recommended
input configuration (see Figure 41). To bias the analog input, the
VCM voltage can be connected to the center tap of the secondary
winding of the transformer.
SFDR (dBc)
90
85
80
SNR (dBFS)
75
VIN+x
R
70
2V p-p
49.9Ω
ADC
C
65
R
0.8
0.9
1.0
1.1
1.2
1.3
0.1µF
Figure 41. Differential Transformer-Coupled Configuration
Figure 39. SNR/SFDR vs. Input Common-Mode Voltage,
fIN = 32.5 MHz, fS = 80 MSPS
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies below
a few megahertz (MHz). Excessive signal power can also cause
core saturation, which leads to distortion.
An on-board, common-mode voltage reference is included in the
design and is available from the VCM pin. The VCM pin must
be decoupled to ground by a 0.1 μF capacitor, as described in
the Applications Information section.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9269. For applications above
~10 MHz where SNR is a key parameter, differential double balun
coupling is the recommended input configuration (see Figure 42).
Differential Input Configurations
Optimum performance is achieved while driving the AD9269 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and ADA4938-2 differential drivers provide
excellent performance and a flexible interface to the ADC.
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential driver
(see Figure 43). Refer to the AD8352 data sheet for more
information.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9269 (see Figure 40), and the
0.1µF
0.1µF
R
VIN+x
2V p-p
25Ω
PA
S
S
P
ADC
C
0.1µF
25Ω
0.1µF
R
VIN–x
VCM
Figure 42. Differential Double Balun Input Configuration
VCC
0.1µF
0Ω
ANALOG INPUT
16
1
8, 13
11
RD
RG
3
5
0.1µF 0Ω
R
VIN+x
200Ω
10
ADC
C
AD8352
4
ANALOG INPUT
0.1µF
0.1µF
2
CD
VCM
08538-008
0.7
INPUT COMMON-MODE VOLTAGE (V)
0.1µF
200Ω
R
VIN–x
14
0.1µF
0.1µF
Figure 43. Differential Input Configuration Using the AD8352
Rev. 0 | Page 20 of 40
VCM
08538-011
0.6
VIN–x
08538-049
60
0.5
08538-010
SNR/SFDR (dBFS/dBc)
VIN–x
76.8Ω
AD9269
In any configuration, the value of Shunt Capacitor C is dependent
on the input frequency and source impedance and may need to
be reduced or removed. Table 9 displays the suggested values to set
the RC network. However, these values are dependent on the
input signal and should be used only as a starting guide.
Table 9. Example RC Network
R Series
(Ω Each)
33
125
Frequency Range (MHz)
0 to 70
70 to 200
Internal Reference Connection
A comparator within the AD9269 detects the potential at the
SENSE pin and configures the reference into two possible modes,
which are summarized in Table 10. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 45), setting VREF to 1.0 V.
VIN+A/VIN+B
C Differential (pF)
22
Open
VIN–A/VIN–B
ADC
CORE
Single-Ended Input Configuration
VREF
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 44
shows a typical single-ended input configuration.
R
1kΩ
ADC
C
R
VIN–x
0.1µF
Figure 45. Internal Reference Configuration
VIN+x
1kΩ
AVDD
10µF
0.5V
1kΩ
If the internal reference of the AD9269 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 46 shows
how the internal reference voltage is affected by loading.
0
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9269. VREF can be configured using either the internal 1.0 V
reference or an externally applied 1.0 V reference voltage. The
various reference modes are summarized in the sections that
follow. The Reference Decoupling section describes the bestpractices PCB layout of the reference.
REFERENCE VOLTAGE ERROR (%)
Figure 44. Single-Ended Input Configuration
–0.5
–1.0
INTERNAL VREF = 0.993V
–1.5
–2.0
–2.5
–3.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
LOAD CURRENT (mA)
Figure 46. VREF Accuracy vs. Load Current
Table 10. Reference Configuration Summary
Selected Mode
Fixed Internal Reference
Fixed External Reference
SENSE Voltage (V)
AGND to 0.2
AVDD
Resulting VREF (V)
1.0 internal
1.0 applied to external VREF pin
Rev. 0 | Page 21 of 40
Resulting Differential Span (V p-p)
2.0
2.0
08538-014
0.1µF
SENSE
ADC
08538-009
49.9Ω
SELECT
LOGIC
AVDD
1kΩ
1V p-p
0.1µF
08538-012
10µF
1.0µF
AD9269
External Reference Operation
Clock Input Options
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. Figure 47 shows the typical drift characteristics
of the internal reference in 1.0 V mode.
The AD9269 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
4
Figure 49 and Figure 50 show two preferred methods for clocking the AD9269 (at rates up to 6× the specified sample rate when
using the internal clock divider function). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer.
3
2
VREF ERROR (mV)
0
–1
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 480 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9269 to approximately 0.8 V p-p differential.
–3
–4
–6
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
08538-052
–5
Figure 47. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 32). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9269 while preserving the fast rise and fall times of the signal that are critical to
a low jitter performance.
1nF
CLOCK
INPUT
0.1µF
CLK+
50Ω
CLK–
SCHOTTKY
DIODES:
HSMS2822
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9269 sample clock
inputs, CLK+ and CLK−, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased internally
(see Figure 48) and require no external bias.
Figure 49. Balun-Coupled Differential Clock (Up to 480 MHz)
Mini-Circuits®
ADT1-1WT, 1:1 Z
0.1µF
AVDD
CLOCK
INPUT
50Ω
XFMR
0.1µF
CLK+
100Ω
ADC
0.1µF
0.9V
CLK–
CLK+
CLK–
0.1µF
2pF
SCHOTTKY
DIODES:
HSMS2822
Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)
08538-016
2pF
ADC
0.1µF
1nF
08538-018
–2
Figure 48. Equivalent Clock Input Circuit
Rev. 0 | Page 22 of 40
08538-017
VREF ERROR (mV)
1
AD9269
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 51. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer
excellent jitter performance.
0.1µF
0.1µF
CLOCK
INPUT
Clock Duty Cycle
CLK+
0.1µF
AD951x
PECL DRIVER
CLOCK
INPUT
100Ω
ADC
0.1µF
240Ω
50kΩ
08538-019
CLK–
50kΩ
240Ω
Figure 51. Differential PECL Sample Clock (Up to 480 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 52. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517
clock drivers offer excellent jitter performance.
0.1µF
0.1µF
CLOCK
INPUT
CLK+
0.1µF
The AD9269 clock divider can be synchronized using the external
SYNC input. Bits[2:1] in Register 0x100 allow the clock divider
to be resynchronized on every SYNC signal or only on the first
SYNC signal after the register is written. A valid SYNC causes
the clock divider to reset to its initial state. This synchronization
feature allows multiple parts to have their clock dividers aligned
to guarantee simultaneous input sampling.
AD951x
LVDS DRIVER
CLOCK
INPUT
100Ω
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9269 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9269. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 54.
80
ADC
0.1µF
DCS OFF
DCS ON
79
50kΩ
08538-020
CLK–
50kΩ
77
SNR (dBFS)
Figure 52. Differential LVDS Sample Clock (Up to 480 MHz)
78
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 53).
76
75
74
73
72
0.1µF
CLOCK
INPUT
50Ω 1
1kΩ
AD951x
CMOS DRIVER
OPTIONAL
0.1µF
100Ω
1kΩ
70
30
CLK+
40
45
50
55
60
65
70
POSITIVE DUTY CYCLE (%)
Figure 54. SNR vs. Duty Cycle Stabilizer On/Off
ADC
CLK–
08538-021
0.1µF
150Ω
35
08538-064
71
VCC
RESISTOR IS OPTIONAL.
Figure 53. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9269 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 6.
Optimum performance is obtained by enabling the internal
duty cycle stabilizer (DCS) when using divide ratios other than
1, 2, or 4.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates of less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after the dynamic clock frequency increases or decreases
before the DCS loop is relocked to the input signal.
Rev. 0 | Page 23 of 40
AD9269
Jitter Considerations
POWER DISSIPATION AND STANDBY MODE
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
As shown in Figure 56, the analog core power dissipated by the
AD9269 is proportional to its sample rate. The digital power dissipation of the CMOS outputs is determined primarily by the
strength of the digital drivers and the load on each output bit.
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ]
The maximum DRVDD current (IDRVDD) can be calculated as
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 55.
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (34, in the case of the
AD9269).
80
210
0.05ps
ANALOG CORE POWER (mW)
190
70
65
0.5ps
60
55
1.0ps
1.5ps
50
3.0ps
45
1
10
100
FREQUENCY (MHz)
170
150
AD9269-65
130
110
AD9269-40
90
2.0ps
2.5ps
AD9269-20
1k
70
10
07938-022
SNR (dBFS)
0.2ps
AD9269-80
20
30
40
50
60
70
80
08538-051
75
CLOCK RATE (MSPS)
Figure 55. SNR vs. Input Frequency and Jitter
Figure 56. Analog Core Power vs. Clock Rate
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9269.
To avoid modulating the clock signal with digital noise, keep power
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
For more information, see the AN-501 Application Note and the
AN-756 Application Note, available on www.analog.com.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 56 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
Rev. 0 | Page 24 of 40
AD9269
The AD9269 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 1 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the PDWN
pin low returns the AD9269 to its normal operating mode. Note
that PDWN is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
DIGITAL OUTPUTS
The AD9269 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be multiplexed onto a single output bus to reduce the total number of
traces required.
The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies and
may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 11).
Table 11. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND
DRVDD
SCLK/DFS
Offset binary (default)
Twos complement
SDIO/DCS
DCS disabled
DCS enabled (default)
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Digital Output Enable Function (OEB)
The AD9269 provides a flexible three-state ability for the digital
output pins. The three-state mode is enabled by the OEB pin or
through the SPI interface. If the OEB pin is low, the output data
drivers and DCOs are enabled. If the OEB pin is high, the output
data drivers and DCOs are placed in a high impedance state.
This OEB function is not intended for rapid access to the data
bus. Note that OEB is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data outputs and DCO of
each channel can be independently three-stated by using the
output disable (OEB) bit, Bit 4 in Register 0x14.
TIMING
The AD9269 provides latched data with a pipeline delay of nine
clock cycles. Data outputs are available one propagation delay (tPD)
after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9269. These transients
may degrade converter dynamic performance.
The lowest typical conversion rate of the AD9269 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD9269 provides two data clock output (DCO) signals that
are designed to capture the data in an external register. The CMOS
data outputs are valid on the rising edge of DCO unless the DCO
clock polarity has been changed via the SPI. See Figure 2 and
Figure 3 for a graphical timing description.
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
Rev. 0 | Page 25 of 40
Twos Complement Mode
1000 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1111
OR
1
0
0
0
1
AD9269
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9269 includes a built-in test feature that is designed to
enable verification of the integrity of each channel as well as to
facilitate board-level debugging. A built-in self-test (BIST) feature
that verifies the integrity of the digital datapath of the AD9269
is included. Various output test options are also provided to place
predictable values on the outputs of the AD9269.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9269 signal path. Perform the BIST test after a reset to ensure
that the part is in a known state. During BIST, data from an internal
pseudorandom noise (PN) source is driven through the digital
datapath of both channels, starting at the ADC block output.
At the datapath output, CRC logic calculates a signature from
the data. The BIST sequence runs for 512 cycles and then stops.
When the sequence is complete, the BIST compares the signature
results with a predetermined value. If the signatures match, the
BIST sets Bit 0 in Register 0x24, signifying that the test passed.
If the BIST test failed, Bit 0 in Register 0x24 is cleared. The outputs
are connected during this test, so the PN sequence can be observed
as it runs. Writing the value 0x05 to Register 0x0E runs the BIST.
This enables Bit 0 (BIST enable) in Register 0x0E and resets the PN
sequence generator, Bit 2 (BIST init) in Register 0x0E. At the
completion of the BIST, Bit 0 in Register 0x24 is automatically
cleared. The PN sequence can be continued from its last value
by writing a 0 in Bit 2 in Register 0x0E. However, if the PN
sequence is not reset, the signature calculation does not equal the
predetermined value at the end of the test. At that point, the user
must rely on verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 17 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back end blocks, and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 in Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog
signal is ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI.
Rev. 0 | Page 26 of 40
AD9269
CHANNEL/CHIP SYNCHRONIZATION
The AD9269 has a SYNC input that offers the user flexible
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized to
the sample clock; however, to ensure that there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times that are shown in Table 5. Drive the SYNC
input using a single-ended CMOS-type signal.
Rev. 0 | Page 27 of 40
AD9269
DC AND QUADRATURE ERROR CORRECTION (QEC)
Table 13 gives the minimum and maximum correction ranges
of the algorithms. If the mismatches are greater than these ranges,
an imperfect correction results.
Table 13. QEC and DC Correction Range
Parameter
Gain
Phase
DC
Minimum
−1.1 dB
−1.79 degrees
−6 %
Maximum
+1.0 dB
+1.79 degrees
+6%
0
–15
–30
IMAGE
DC OFFSET
–45
–60
–75
2
–90
5
6
–105
4
3
–120
FREQUENCY (MHz)
08538-065
37.5M
30M
22.5M
15M
7.5M
0M
–7.5M
The convergence time of the QEC algorithm is dependent on
the statistics of the input signal. For large signals and large
imbalance errors, this convergence time is typically less than
2 million samples of the AD9269 data rate.
–15.0M
–135
–22.5M
The quadrature errors are corrected in a frequency independent
manner on the AD9269; therefore, systems with significant
mismatch in the baseband I and Q signal chains may have
reduced image suppression. The AD9269 QEC still corrects the
systematic imbalances.
QEC and DC Correction Range
–30.0M
The integrated quadrature error correction (QEC) algorithm of
the AD9269 attempts to measure and correct the amplitude and
phase imbalances of the I and Q signal paths to achieve higher
levels of image suppression than is achievable by analog means
alone. These errors can be corrected in an adapted manner, in
which the I and Q gain and quadrature phase mismatches are
constantly estimated and corrected, allowing for constant
tracking of slow changes in mismatches that are due to supply
and temperature.
When the QEC is enabled and a correction value has been
calculated, the value remains active as long as any of the QEC
functions (DC, gain, or phase correction) are being used.
–37.5M
In a multicarrier communication system, this can be even more
problematic because carriers of widely different power levels
can interfere with one another. For example, a large carrier
centered at +f1 can have an image appear at −f1 that may be
much larger than the desired carrier at −f1.
The default configuration on the AD9269 has the QEC and dc
correction blocks disabled, and Bits[2:0] in Register 0x110 must
be pulled high to enable the correction blocks. The quadrature
gain, quadrature phase, and dc correction algorithms can also
be disabled independently for system debugging or to save
power by pulling Bits[2:0] low in Register 0x110.
AMPLITUDE (dBFS)
In direct conversion or other quadrature systems, mismatches
between the real (I) and imaginary (Q) signal paths cause frequencies in the positive spectrum to image into the negative
spectrum, and vice versa. From an RF point of view, this is
equivalent to information above the local oscillator (LO)
frequency interfering with information below the LO frequency,
and vice versa. These mismatches may occur from gain and/or
phase mismatches in the analog quadrature demodulator or in
any other mismatches between the I and Q signal chains. In a
single-carrier zero-IF system where the carrier has been placed
symmetrically around dc, this causes self-distortion of the carrier
as the two sidebands fold onto one another and degrade the
error vector magnitude (EVM) of the signal.
Figure 57. QEC Mode Off
0
LO Leakage (DC) Correction
–15
–30
Rev. 0 | Page 28 of 40
–60
–75
–90
DC OFFSET
2
IMAGE
5
6
–105
4
3
–120
37.5M
30M
22.5M
08538-066
FREQUENCY (MHz)
Figure 58. QEC Mode On
15M
7.5M
0M
–7.5M
–15.0M
–22.5M
–135
–30.0M
In applications where constant tracking of the dc offsets and
quadrature errors are not needed, the algorithms can be
independently frozen to save power. When frozen, the image
and LO leakage (dc) correction are still performed, but changes
are no longer tracked. Bits[5:3] in Register 0x110 disable the
respective correction when frozen.
–45
–37.5M
AMPLITUDE (dBFS)
In a direct conversion receiver subsystem, LO to RF leakage of
the quadrature modulator shows up as dc offsets at baseband.
These offsets are added to dc offsets in the baseband signal
paths, and both contribute to a carrier at dc. In a zero-IF receiver,
this dc energy can cause problems because it appears in band of
a desired channel. As part of the QEC function, the dc offset is
suppressed by applying a low frequency notch filter to form
a null around dc.
AD9269
SERIAL PORT INTERFACE (SPI)
SPI functions are placed in high impedance mode. This mode
turns on any secondary functions of the SPI function pins.
The AD9269 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI provides
added flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields, which are documented in the
Memory Map section. For detailed operational information, see
the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and the length of the data
stream is determined by the W1 and W0 bits, as shown in
Figure 59.
CONFIGURATION USING THE SPI
All data is composed of 8-bit words. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read command or a write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Three pins define the SPI of this ADC: the SCLK, the SDIO, and
the CSB (see Table 14). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC.
The SDIO (serial data input/output) is a dual-purpose pin that
allows data to be sent to and read from the internal ADC
memory map registers. The CSB (chip select bar) is an activelow control that enables or disables the read and write cycles.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Table 14. Serial Port Interface Pins
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
Pin
SCLK
SDIO
CSB
Function
Serial clock. A serial shift clock input that is used to
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active-low control that gates the read
and write cycles.
HARDWARE INTERFACE
The pins described in Table 14 constitute the physical interface
between the programming device of the user and the serial port
of the AD9269. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The falling edge of the CSB, in conjunction with the rising edge
of SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 59 and
Table 5.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, permanently enabling the device; this is
called streaming. The CSB can stall high between bytes to allow
for additional external timing. When the CSB is tied high, the
tHIGH
tDS
tS
tDH
tCLK
tH
tLOW
CSB
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 59. Serial Port Interface Timing Diagram
Rev. 0 | Page 29 of 40
D4
D3
D2
D1
D0
DON’T CARE
08538-023
SCLK DON’T CARE
AD9269
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between this
bus and the AD9269 to prevent these signals from transitioning
at the converter inputs during critical sampling periods.
SPI ACCESSIBLE FEATURES
SDIO/DCS and SCLK/DFS serve a dual function when the
SPI interface is not being used. When the pins are strapped to
DRVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9269.
Feature
Mode
CONFIGURATION WITHOUT THE SPI
Test I/O
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the
PDWN pin serve as standalone CMOS-compatible control pins.
When the device is powered up, it is assumed that the user intends
to use the pins as static control lines for the duty cycle stabilizer,
output data format, output enable, and power-down feature control. In this mode, connect the CSB chip select to DRVDD,
which disables the serial port interface.
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9269 part-specific features are described in
detail in Table 17.
Table 16. Features Accessible Using the SPI
Clock
Offset
Output Mode
Output Phase
Output Delay
VREF
Table 15. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
OEB
PDWN
External
Voltage
DRVDD (default)
AGND
DRVDD
AGND (default)
DRVDD
AGND (default)
DRVDD
AGND (default)
Configuration
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Chip in power-down or standby
Normal operation
Rev. 0 | Page 30 of 40
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have known
data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage
AD9269
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
DEFAULT VALUES
Each row in the memory map register table (see Table 17) contains
eight bit locations. The memory map is divided into four sections:
the chip configuration registers (Address 0x00 to Address 0x02);
the device index and transfer registers (Address 0x05 and
Address 0xFF); the program registers, including setup, control,
and test (Address 0x08 to Address 0x2E); and the digital feature
control registers (Address 0x100 to Address 0x11D).
After the AD9269 is reset, critical registers are loaded with default
values. The default values for the registers are given in the memory
map register table (see Table 17).
Table 17 documents the default hexadecimal value for each
hexadecimal address shown. The column with the heading Bit 7
(MSB) is the start of the default hexadecimal value given. For
example, Address 0x05, the channel index register, has a hexadecimal default value of 0x03. This means that in Address 0x05,
Bits[7:2] = 0, and the remaining Bits[1:0] = 1. This setting is
the default channel index setting. The default value results in
both ADC channels receiving the next write command. For
more information on this function and others, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI. This
document details the functions controlled by Register 0x00 to
Register 0xFF. The remaining registers, Register 0x100 to
Register 0x11D, are documented in the Memory Map Register
Descriptions section following Table 17.
OPEN LOCATIONS
All address and bit locations that are not included in the SPI
map are not currently supported for this device. Unused bits of
a valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open, it is omitted from the SPI map (for example, Address 0x13)
and should not be written.
Logic Levels
An explanation of logic level terminology follows:
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and then the bit autoclears.
Channel-Specific Registers
Some channel setup functions can be programmed differently
for each channel. In these cases, channel address locations are
internally duplicated for each channel. These registers and bits
are designated in the memory map register table as local. These
local registers and bits can be accessed by setting the appropriate
Channel A (Bit 0) or Channel B (Bit 1) bits in Register 0x05.
If both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, set only Channel A or Channel B
to read one of the two registers. If both bits are set during an
SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in the memory map
register table affect the entire part or the channel features for
which independent settings are not allowed between channels.
The settings in Register 0x05 do not affect the global registers
and bits.
Rev. 0 | Page 31 of 40
AD9269
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17.
Addr.
Register
(Hex)
Name
Chip configuration registers
0x00
SPI port
configuration
(global)
0x01
Chip ID (global)
0x02
Chip grade (global)
(MSB)
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
LSB
first
Soft reset
1
1
Soft
reset
LSB first
0
8-bit chip ID, Bits[7:0]
AD9269 = 0x75
Open
Default
Value
(Hex)
0x18
0x75
Open
Speed grade ID, Bits[6:4]
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
N/A
Device index and transfer registers
0x05
Channel index
Open
Open
Open
Open
Open
Open
ADC B
default
ADC A
default
0x03
0xFF
Open
Open
Open
Open
Open
Open
Transfer
0x00
00 = chip run
01 = full powerdown
10 = standby
11 = chip-wide
digital reset
(local)
Open
Duty
cycle
stabilize
Clock divider, Bits[2:0]
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
0x80
Transfer
Open
Program registers (may or may not be indexed by device index)
External pin function
0x08
Modes
External
0x00 =
powerfull power-down
down
0x01 = standby
enable
(local)
(local)
0x09
Clock (global)
0x0B
Clock divider
(global)
Open
Open
Open
Open
Open
Open
Open
Rev. 0 | Page 32 of 40
Comments
The nibbles are
mirrored so that
LSB- or MSB-first
mode registers
correctly, regardless of shift mode
Unique chip ID
used to differentiate devices;
read only
Unique speed
grade ID used to
differentiate
devices; read
only
Bits are set to
determine which
device on chip
receives the next
write command;
the default is all
devices on chip
Synchronously
transfers data
from the master
shift register to
the slave
Determines
various generic
modes of chip
operation
0x00
0x00
The divide ratio is
the value plus 1
AD9269
Register
Name
Test mode (local)
(MSB)
Bit 7
Bit 6
User test mode
(local)
00 = single
01 = alternate
10 = single once
11 = alternate
once
0x0E
BIST enable
Open
0x10
8-bit device offset adjustment [7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
Output
Open
Output
00 = 3.3 V CMOS
Output mux
disable
invert
10 = 1.8 V CMOS
enable
(local)
(interleaved)
(OEB)
(local)
0x00
0x14
Offset adjust
(local)
Output mode
0x00
Configures the
outputs and the
format of the data
0x15
OUTPUT_ADJUST
1.8 V DCO drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
0x22
Determines
CMOS output
drive strength
properties
0x16
OUTPUT_PHASE
3.3 V DCO
drive strength
00 = 1 stripe
(default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
Open
DCO
output
polarity
0=
normal
1=
inverted
(local)
0x00
On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock;
internal latching
is unaffected
0x17
OUTPUT_DELAY
Enable
DCO
delay
0x00
This sets the fine
output delay of
the output clock
but does not
change internal
timing
0x19
USER_PATT1_LSB
0x00
0x1A
User-Defined
Pattern 1, LSB
User-defined
Pattern 1, MSB
User-Defined
Pattern 2, LSB
User-Defined
Pattern 2, MSB
Least significant
byte of MISR;
read only
Open
Bit 5
Reset PN
long gen
Bit 4
Reset PN
short
gen
Open
Open
(LSB)
Bit 3
Bit 2
Bit 1
Bit 0
Output test mode [3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = one/zero word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
Open
BIST init
Open
BIST
enable
Default
Value
(Hex)
0x00
Addr.
(Hex)
0x0D
0x00
Open
Open
Open
Enable
data
delay
Open
B7
B6
B5
B4
00 = offset binary
01 = twos
complement
10 = gray code
11 = offset binary
(local)
1.8 V data
3.3 V data
drive strength
drive strength
00 = 1 stripe
00 = 1 stripe
01 = 2 stripes
(default)
10 = 3 stripes
01 = 2 stripes
(default)
10 = 3 stripes
11 = 4 stripes
11 = 4 stripes
Open
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Open
DCO/data delay, Bits[2:0]
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
B3
B2
B1
B0
USER_PATT1_MSB
B15
B14
B13
B12
B11
B10
B9
B8
0x00
0x1B
USER_PATT2_LSB
B7
B6
B5
B4
B3
B2
B1
B0
0x00
0x1C
USER_PATT2_MSB
B15
B14
B13
B12
B11
B10
B9
B8
0x00
0x24
MISR_LSB
Open
Open
Open
Open
Open
Open
Open
B0
0x00
Rev. 0 | Page 33 of 40
Comments
When set, the test
data is placed on
the output pins
in place of
normal data
When Bit 0 is set,
the BIST function
is initiated
Device offset trim
AD9269
Register
Name
Features
(MSB)
Bit 7
Open
Bit 6
Open
Bit 5
Open
Bit 4
Open
Bit 3
Open
Bit 2
Open
Bit 1
Open
0x2E
Output assign
Open
Open
Open
Open
Open
Open
Open
0=
ADC A
1=
ADC B
(local)
Ch A =
0x00
Ch B =
0x01
Open
Open
Open
Open
Open
Clock
divider
next
sync
only
Run
GCLK
Clock
divider
sync
enable
Master
sync
enable
0x01
Open
Disable
SDIO
pulldown
Gain
enable
Force
gain
0x88
Digital feature control
0x100
Sync control
(global)
Open
Enable
GCLK
detect
0x101
USR2
0x110
QEC Control 0
0x111
QEC Control 1
Open
0x112
QEC gain
bandwidth control
QEC phase
bandwidth control
QEC DC
bandwidth control
QEC Initial Gain 0
QEC Initial Gain 1
QEC Initial Phase 0
QEC Initial Phase 1
QEC Initial DC I 0
QEC Initial DC I 1
QEC Initial DC Q 0
QEC Initial DC Q 1
Open
DC
enable
Force
DC
KEXP_GAIN
Open
KEXP_PHASE
0x02
Open
KEXP_DC
0x02
0x113
0x114
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11C
0x11D
Enable
OEB
(Pin 47)
(local)
Open
(LSB)
Bit 0
OR OE
(local)
Default
Value
(Hex)
0x01
Addr.
(Hex)
0x2A
Open
Freeze DC
Open
Open
Open
Open
Freeze
phase
Open
Freeze
gain
Open
Phase
enable
Force
phase
Initial gain, Bits[7:0]
Initial gain, Bits[14:8]
Initial phase, Bits[7:0]
Initial phase, Bits[12:8]
Initial DC I, Bits[7:0]
Initial DC I, Bits[13:8]
Initial DC Q, Bits[7:0]
Initial DC Q, Bits[13:8]
Comments
Disable the OR pin
for the indexed
channel
Assign an ADC
to an output
channel
Enables internal
oscillator for
clock rates of
<5 MHz
0x00
0x00
0x02
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
MEMORY MAP REGISTER DESCRIPTIONS
Bit 0—Master Sync Enable
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Bit 0 must be high to enable any of the sync functions.
USR2 (Register 0x101)
Bit 7—Enable OEB (Pin 47)
Sync Control (Register 0x100)
Bits[7:3]—Open
Normally set high, this bit allows Pin 47 to function as the output
enable. If this bit is set low, it disables Pin 47.
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable bit
(Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 and Bit 0 are high, and the device is operating
in continuous sync mode as long as Bit 2 of the sync control is low.
Bits [6:4]—Open
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below ~5 MSPS. When a low encode rate is detected, an
internal oscillator, GCLK, is enabled to ensure the proper operation
of several circuits. If this bit is set low, the detector is disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
Rev. 0 | Page 34 of 40
AD9269
QEC Phase Bandwidth Control (Register 0x113)
Bits[7:5]—Open
Bit 1—Open
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
Bits[4:0]—KEXP_PHASE
QEC Control 0 (Register 0x110)
Bits[7:6]—Open
QEC DC Bandwidth Control (Register 0x114)
Bits[7:5]—Open
Bits[5:3]—Freeze DC/Freeze Phase/Freeze Gain
Bits[4:0]—KEXP_DC
These bits can be used to freeze the corresponding dc, phase,
and gain offset corrections of the quadrature error correction
(QEC) independently. When asserted high, QEC is applied
using frozen values, and the estimation of the quadrature errors
is halted.
These bits adjust the time constants of the dc control feedback
loop for quadrature error correction.
Bits[2:0]—DC Enable/Phase Enable/Gain Enable
These bits allow the corresponding dc, phase, and gain offset
corrections to be enabled independently.
QEC Control 1 (Register 0x111)
Bits[7:3]—Open
Bit 2—Force DC
When set high, this bit forces the initial static correction values
from Register 0x11A and Register 0x11B for the I data and
Register 0x11C and Register 0x11D for the Q data.
These bits adjust the time constants of the phase control
feedback loop for quadrature error correction.
QEC Initial Gain 0, QEC Initial Gain 1 (Register 0x116 and
Register 0x117)
Bits[14:0]—Initial Gain
When the force gain bit (Register 0x111, Bit 0) is set high, these
values are used for gain error correction.
QEC Initial Phase 0, QEC Initial Phase 1 (Register 0x118 and
Register 0x119)
Bits[12:0]—Initial Phase
When the force phase bit (Register 0x111, Bit 1) is set high,
these values are used for phase error correction.
Bit 1—Force Phase
QEC Initial DC I 0, QEC Initial DC I 1 (Register 0x11A and
Register 0x11B)
Bits[13:0]—Initial DC I
When set high, this bit forces the initial static correction values
from Register 0x118 and Register 0x119.
When the force dc bit (Register 0x111, Bit 2) is set high, these
values are used for dc error correction.
Bit 0—Force Gain
When set high, this bit forces the initial static correction values
from Register 0x116 and Register 0x117.
QEC Initial DC Q 0, QEC Initial DC Q 1 (Register 0x11C and
Register 0x11D)
Bits[13:0]—Initial DC Q
QEC Gain Bandwidth Control (Register 0x112)
Bits[7:5]—Open
When the force dc bit (Register 0x111, Bit 2) is set high, these
values are used for dc error correction.
Bits[4:0]—KEXP_GAIN
These bits adjust the time constants of the gain control feedback
loop for quadrature error correction.
Rev. 0 | Page 35 of 40
AD9269
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design and layout of the AD9269 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements required for certain pins.
Power and Ground Recommendations
When connecting power to the AD9269, it is strongly recommended that two separate supplies be used. Use one 1.8 V supply
for analog (AVDD), and use a separate 1.8 V to 3.3 V supply for the
digital output supply (DRVDD). If a common 1.8 V AVDD and
DRVDD supply must be used, the AVDD and DRVDD domains
must be isolated with a ferrite bead or filter choke and separate
decoupling capacitors. Several different decoupling capacitors
can be used to cover both high and low frequencies. Locate these
capacitors close to the point of entry at the PCB level and close
to the pins of the part, with minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9269. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
Exposed Paddle Thermal Heat Sink Recommendations
The exposed paddle (Pin 0) is the only ground connection for
the AD9269; therefore, it must be connected to analog ground
(AGND) on the customer’s PCB. To achieve the best electrical
and thermal performance, mate an exposed (no solder mask)
continuous copper plane on the PCB to the AD9269 exposed
paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. Fill or plug these vias with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), at www.analog.com.
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 41.
RBIAS
The AD9269 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
Externally decouple the VREF pin to ground with a low ESR,
1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic
capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it
may be necessary to provide buffers between this bus and the
AD9269 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
Rev. 0 | Page 36 of 40
AD9269
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
64
49
48
PIN 1
INDICATOR
1
PIN 1
INDICATOR
8.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
SEATING
PLANE
33
32
16
17
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
0.30
0.23
0.18
6.35
6.20 SQ
6.05
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
091707-C
TOP VIEW
Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad (CP-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9269BCPZ-80 2
AD9269BCPZRL7-802
AD9269BCPZ-652
AD9269BCPZRL7-652
AD9269BCPZ-402
AD9269BCPZRL7-402
AD9269BCPZ-202
AD9269BCPZRL7-202
AD9269-80EBZ
AD9269-65EBZ
AD9269-40EBZ
AD9269-20EBZ
1
2
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND.
Rev. 0 | Page 37 of 40
Package Option
CP-64-4
CP-64-4
CP-64-4
CP-64-4
CP-64-4
CP-64-4
CP-64-4
CP-64-4
AD9269
NOTES
Rev. 0 | Page 38 of 40
AD9269
NOTES
Rev. 0 | Page 39 of 40
AD9269
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08538-0-1/10(0)
Rev. 0 | Page 40 of 40
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