Gennum GS1501 Hdtv serial digital formatter with anc fifo Datasheet

+'/,1;™ GS1501
HDTV Serial Digital Formatter
with ANC FIFOs
DATA SHEET
DESCRIPTION
• SMPTE 292M compliant
The GS1501 HDTV Serial Digital Formatter formats the
HDTV Luma and Chroma data according to SMPTE 292M
prior to serialization by the GS1522 HDTV Serializer. The
GS1501 optionally inserts TRS and line number signals
based on externally supplied H, V and F signals. The
device also allows the insertion of CRCs based on TRS
signals embedded in the input data streams, should the
user choose not to supply external HVF signals.
• NRZ(I) encoding
• SMPTE 292M scrambler with BYPASS option
• internal FIFOs for ANC data insertion
(1024 Bytes on Y and C channels)
• selectable TRS insertion
• selectable line number insertion
• selectable line based CRC insertion
Following the insertion of TRS, Line Number, and CRC,
protected words of 000-003 and 3FC to 3FF occurring
during the active video period are optionally re-mapped to
004 and 3FB respectively. In addition, ANC data may be
inserted into the video stream through an internal FIFO
interface. Prior to exiting the device SMPTE 292M compliant
NRZ(I) encoding and scrambling may be performed on the
data stream.
• selectable active picture illegal code re-mapping
• 20 bit 3.3V CMOS compatible input data bus
• optimized output interface to GS1522
• single +3.3V power supply
• 5V tolerant I/O
APPLICATIONS
• SMPTE 292M Serial Digital Interfaces
TRS_Y/C
DET_TRS
2
FOEN
FM_I/E
ANC_Y/C
CODE
PROTECT
FFRST
TRS_INS
LN_INS
CRC_INS
2
DATA_IN
[19:10]
(LUMA)
DATA_IN
[9:0]
INPUT
BUFFER
and
BLANKER
TRS
INSERTION
ANC DATA
TRS
and
LINE NUMBER
DETECTION
BP_SC
3
ILLEGAL CODE
REMAPPING
INSERTION
LINE NUMBER
INSERTION
FIFOS
DATA_OUT
NRZI
ENCODER
[19:0]
SMPTE
SCAMBLER
CRC INSERTION
(CHROMA)
PCLK_IN
2
10
3
BLANK
[H:V:F]
RSTLN
ANC_IN[9:0]
2
REN
WEN
W_CLK
FM_I/E
3
SRST
OEN
FF_STA
[2:0]
GS1501 FUNCTIONAL BLOCK DIAGRAM
Revision Date: July 2002
Document No. 52234 - 4
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
GS1501
KEY FEATURES
TABLE OF CONTENTS
1. PIN OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
2. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. DETAILED DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14
4. REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. PACKAGE & ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2
GENNUM CORPORATION
52234 - 4
GS1501
2.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
GENNUM CORPORATION
VDD
GND
VDD
GND
DATA_IN[9]
DATA_IN[8]
DATA_IN[7]
DATA_IN[6]
DATA_IN[5]
DATA_IN[4]
DATA_IN[3]
DATA_IN[2]
DATA_IN[1]
DATA_IN[0]
VDD
GND
DATA_IN[13]
DATA_IN[12]
DATA_IN[11]
DATA_IN[10]
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
65
38
VDD
NC
66
37
GND
NC
67
36
OEN
VDD
68
35
TN
GND
69
34
NC
TEST
70
33
NC
NC
71
32
NC
NC
72
31
NC
FF_STA[0]
73
30
NC
FF_STA[1]
74
29
NC
FF_STA[2]
75
28
NC
ANC_IN[9]
76
27
NC
ANC_IN[8]
77
26
NC
VDD
78
25
VDD
GND
79
24
GND
ANC_IN[7]
80
23
F
VDD
81
22
V
GND
82
21
H
ANC_IN[6]
83
20
VDD
ANC_IN[5]
84
19
GND
ANC_IN[4]
85
18
VDD
ANC_IN[3]
86
17
GND
ANC_IN[2]
87
16
CRC_INS
ANC_IN[1]
88
15
LN_INS
ANC_IN[0]
89
14
GND
VDD
90
13
TRS_INS
GND
91
12
TRS Y/C
W_CLK
92
11
SRST
VDD
93
10
BP_SC
GND
94
9
RSTLN
FOEN
95
8
CODE_PROTECT
FFRST
96
7
GND
WEN
97
6
BLANK
REN
98
5
DET_TRS
VDD
99
4
GND
FM_I/E
100
3
VDD
ANC_Y/C
101
2
GND
VDD
102
1
PCLK_IN
GS1501
TOP
VIEW
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
VDD
GND
DATA_OUT[6]
DATA_OUT[5]
DATA_OUT[4]
DATA_OUT[3]
DATA_OUT[2]
DATA_OUT[1]
DATA_OUT[0]
VDD
GND
DATA_OUT[8]
DATA_OUT[7]
VDD
GND
DATA_OUT[14]
DATA_OUT[13]
DATA_OUT[12]
DATA_OUT[11]
DATA_OUT[10]
DATA_OUT[9]
DATA_OUT[19]
DATA_OUT[18]
DATA_OUT[17]
DATA_OUT[16]
DATA_OUT[15]
GS1501
DATA_IN[19]
DATA_IN[18]
DATA_IN[17]
DATA_IN[16]
DATA_IN[15]
DATA_IN[14]
1. PIN OUT
1.1 PIN ASSIGNMENT
3
52234 - 4
1.2 PIN DESCRIPTIONS
PIN NUMBER
NAME
TIMING
TYPE
DESCRIPTION
1
PCLK_IN
Synchronous
Input
2, 4, 14, 19, 24,
37, 46, 50, 58,
69, 79, 82, 91,
94, 110, 116,
128
GND
N/A
Ground
Ground. Ground power supply connections.
3, 18, 20, 25, 38,
47, 51, 59, 68,
78, 81, 90, 93,
99, 109, 115,
127
VDD
N/A
Power
Power. Positive power supply connections.
5
DET_TRS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable the detection of
the TRS signals embedded in the video stream. When DET
_TRS is high, the device detects the TRS signals embedded in
the input video stream and uses the detected HVF signals
instead of the external HVF signals. When DET _TRS is low,
TRS detection is disabled. The device uses the external
supplied HVF signals.
6
BLANK
Synchronous
wrt PCLK_IN
Input
Control Signal Input. When BLANK is low, the device sets the
accompanying LUMA and CHROMA data to their appropriate
blanking levels. When BLANK is high, the LUMA and CHROMA
data streams pass through this stage of the device unaltered.
See Figure 3.
7, 17
GND
N/A
8
CODE_PROTECT
Nonsynchronous
Input
Control Signal Input. Used to enable or disable re-mapping of
out-of-range words contained in the active portion of the video
signal. When this signal is high, the device re-maps out-ofrange words contained within the active portion of the video
signal into CCIR-601 compliant words. Values between 000-003
are re-mapped to 004. Values between 3FC and 3FF are remapped to 3FB. When this signal is low, out-of-range words in
the active video region pass through the device unaltered.
9
RSTLN
Synchronous
wrt PCLK_IN
Input
Control Signal Input. Line number reset signal which must be
asserted once per frame at the beginning of the frame (for
example, on the falling edge of the F signal). A high to low
transition will reset the line number counter of the device to one
(1). See Figure 2 for timing.
10
BP_SC
Nonsynchronous
Input
Control Signal Input. Used to enable or bypass the SMPTE292M
scrambler and NRZ(I) encoder. When BP_SC is low, the video
stream is scrambled according to SMPTE 292M and NRZ(I)
encoded. When BP_SC is high, the scrambler and NRZ(I)
encoder are by-passed.
11
SRST
Nonsynchronous
Input
Control Signal Input. Used to reset the SMPTE292M scrambler
and NRZI encoder. When SRST is low, the scrambler and
encoder operate normally. A low to high transition on SRST
causes the scrambler and encoder to reset.
12
TRS_Y/C
Nonsynchronous
Input
Control Signal Input. Only used when DET_TRS is high. When
TRS_Y/C is high, the device detects and uses TRS signals
embedded in the LUMA (DATA_IN[19:10]) channel. When
TRS_Y/C is low, the device detects and uses TRS signals
embedded in the CHROMA (DATA_IN[9:0]) channel.
Parallel data clock input. 74.25MHz or 74.25/1.001MHz.
GS1501
This pin must be connected to GND for normal operation
4
GENNUM CORPORATION
52234 - 4
1.2 PIN DESCRIPTIONS (Continued)
NAME
TIMING
TYPE
DESCRIPTION
13
TRS_INS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable insertion of TRS
into the video streams. When TRS_INS is high, the device
inserts SMPTE 292M compliant TRS signals into the input LUMA
and CHROMA data streams based on the supplied HVF
signals. When TRS_INS is low, the device does not insert TRS
signals.
15
LN_INS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable insertion of line
numbers into the video stream. When LN_INS is high, the
device inserts SMPTE 292M compliant line number information
into the LUMA and CHROMA channels. When LN_INS is low,
the device does not insert the line number information into the
LUMA and CHROMA channels. Line number insertion is only
available when user supplied external FVH data is used
(DET_TRS set LOW).
16
CRC_INS
Nonsynchronous
Input
Control Signal Input. Used to enable or disable insertion of
CRC's into the video stream. When CRC_INS is high, the device
calculates and inserts line based CRCs. When CRC_INS is low,
this feature is disabled.
21
H
Synchronous
wrt PCLK_IN
Input
Control Signal Input. This signal indicates the Horizontal
blanking period of the input video data stream. The device
inserts HDTV TRS based on the supplied HVF signals. Refer to
Figure 4 for required timing of H relative to LUMA
(DATA_IN[19:10]) and CHROMA (DATA_IN[9:0]).
22
V
Synchronous
wrt PCLK_IN
Input
Control Signal Input. This signal indicates the vertical blanking
period of the input video data streams. Refer to Figure 4 for
required timing of V relative to LUMA (DATA_IN[19:10]) and
CHROMA (DATA_IN[9:0]).
23
F
Synchronous
wrt PCLK_IN
Input
Control Signal Input. This signal indicates the ODD/EVEN field
of the input video data streams. Refer to Figure 4 for required
timing of F relative to LUMA (DATA_IN[19:10]) and CHROMA
(DATA_IN[9:0]). When the input video format is progressive
scan, F should remain low at all times.
26, 27, 28, 29,
30, 31, 32, 33,
34, 65, 66, 67,
71, 72,
NC
N/A
35
TN
N/A
TEST
Test Pin. Used for test purposes only. This pin must be
connected to VDD for normal operation
36
OEN
See A/C
Electrical
Characteristic
s section
Input
Control Signal Input. Used to enable DATA_OUT[19:0] output
bus or set it to a high Z state. When OEN is low, the
DATA_OUT[19:0] bus is enabled. When OEN is high, the
DATA_OUT[19:0] bus is disabled and in a high Z state.
64, 63, 62, 61,
60, 57, 56, 55,
54, 53, 52, 49,
48, 45, 44, 43,
42, 41, 40, 39
DATA_OUT[19:0]
Synchronous
wrt PCLK_IN
Outputs
Output Data Bus. The device generates a 20 bit wide data
stream running at 74.25 (or 74.25/1.001) MHz. DATA_OUT[19]
is the MSB and DATA_OUT[0] is the LSB.
70
TEST
N/A
TEST
No Connect. Do not connect these pins
Test Pin. Used for test purposes only. This pin must be
connected to GND for normal operation.
5
GENNUM CORPORATION
52234 - 4
GS1501
PIN NUMBER
1.2 PIN DESCRIPTIONS (Continued)
NAME
75, 74, 73
FF_STA[2:0]
76, 77, 80, 83,
84, 85, 86, 87,
88, 89
ANC_IN[9:0]
92
W_CLK
TIMING
TYPE
DESCRIPTION
Output
Control Signal Output. FF_STA[2:0] is the FIFO status output to
indicate the content level of the internal FIFO.
FF_STA[2:0]=000: Error flag, FIFO is under run.
FF_STA[2:0]=001: FIFO is empty.
FF_STA[2:0]=010: FIFO is almost empty (32 bytes filled).
FF_STA[2:0]=011: FIFO is ready.
FF_STA[2:0]=100: FIFO is half full.
FF_STA[2:0]=101: FIFO is almost full (992 bytes filled).
FF_STA[2:0]=110: FIFO is full.
FF_STA[2:0]=111: Error flag, FIFO is over run.
When ANC_Y/C is high, FF_STA indicates the status of the
LUMA ANC data buffer. When ANC_Y/C is low, it indicates the
status of the CHROMA ANC data buffer. See timing diagrams
Figures 5 to 14 and Table 1.
Synchronous
wrt W_CLK
Input
ANC Data Input Bus. ANC data to be inserted into the video
stream is supplied via the ANC_IN[9:0] input data port.
ANC_IN[9] is the MSB (pin 76) and ANC_IN[0] is the LSB (pin
89). When FM_I/E=1, ANC data intended to be placed into the
current HANC region is written into the internal FIFO during the
time that the preceding active video region is passing through
the device. The device begins inserting ANC data stored in the
FIFO immediately after the line based CRC words regardless of
any other ANC data that may be present in the stream (i.e. the
device will over-write existing ANC data in the data stream).
N/A
Input
Input Clock. Used to write information to the internal FIFO. On
the rising edge of W_CLK, externally supplied ANC data may
be written into the internal LUMA or CHROMA FIFO as
determined by ANC_Y/C.
6
GENNUM CORPORATION
52234 - 4
GS1501
PIN NUMBER
1.2 PIN DESCRIPTIONS (Continued)
NAME
TIMING
TYPE
DESCRIPTION
95
FOEN
Nonsynchronous
Input
Control Signal Input. Used to enable or disable the FIFO status
flags. When FOEN is low, the FIFO status flags are enabled.
When FOEN is high, the FIFO status flags are disabled.
96
FFRST
Synchronous
wrt PCLK_IN
Input
Control Signal Input. FFRST is used to supply synchronous
reset signals to the FIFO. When FFRST is low, the FIFO is reset
and all internal read and write address pointers are set to their
starting locations.
97
WEN
Synchronous
wrt W_CLK
Input
Control Signal Input. Used to enable or disable writing to the
internal FIFO. When WEN is high, writing to the internal FIFO is
not allowed. Internal write address pointers are stopped at their
current position. WEN is sampled on the rising edge of W_CLK.
When WEN is low, writing to the FIFO is enabled.
98
REN
Synchronous
wrt PCLK_IN
Input
Control Signal Input. Used to enable or disable incrementation
of the internal read address pointers. When REN is low, the
internal read address pointers are incremented with each clock
pulse. When REN is high, the internal read address pointers are
stopped at their current position.
100
FM_I/E
Nonsynchronous
Input
Control Signal Input. When FM_I/E is high, the device operates
in a mode where the FIFO reset and read enable signals are
generated internally. In this mode, the device limits the data
insertion to the HANC region of the video stream. The ANC data
to be inserted into the current HANC region are externally
supplied via the FIFO interface during the active video period of
the previous line using the WEN signal. When FM_I/E is low, the
device operates in another mode where the FIFO reset and
read enable signals are generated externally by the user and
supplied to the device via the FFRST and REN control signal
inputs.
101
ANC_Y/C
Synchronous
wrt W_CLK
Input
Control Signal Input. Used to control insertion of ANC data into
the LUMA or CHROMA FIFO. When ANC_Y/C is high, data
written to the device is placed into the internal LUMA FIFO, or
read into the Luma data stream. When ANC_Y/C is low, data
written to the device is placed into the internal CHROMA FIFO,
or read into the Chroma data stream.
103,104,105,
106, 107, 108,
111, 112, 113,
114
DATA_IN [19:10]
(LUMA channel)
Synchronous
wrt PCLK_IN
Input
Input Data Bus. LUMA CHANNEL. DATA_IN [19] is the MSB of
the LUMA input signal (pin 103). DATA_IN [10] is the LSB of the
LUMA input signal (pin 114).
117, 118, 119,
120, 121, 122,
123, 124, 125,
126
DATA_IN [9:0]
(CHROMA channel)
Synchronous
wrt PCLK_IN
Input
CHROMA Input Data Bus. CHROMA CHANNEL DATA_IN [9] is
the MSB of the CHROMA signal (pin 117). DATA_IN [0] is the
LSB of the CHROMA signal (pin 126).
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GENNUM CORPORATION
52234 - 4
GS1501
PIN NUMBER
2. ELECTRICAL CHARACTERISTICS
2.1 ABSOLUTE MAXIUMUM RATINGS
PARAMETER
VALUE
Supply Voltage
-0.5V to +4.6V
Input Voltage Range (any input)
-0.5V < VIN < 5.5V
GS1501
0°C ≤ TA ≤ 70°C
Operating Temperature Range
-40°C ≤ TS ≤ 125°C
Storage Temperature Range
260°C
Lead Temperature (soldering 10
seconds)
2.2 DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0°C to 70°C, unless otherwise shown
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3.0
3.3
3.6
V
Positive Supply Voltage
VDD
Supply Current
ΙDD
ƒ = 74.25MHz, TA = 25°C
-
413
480
mA
Input Logic LOW Voltage
VIL
ILEAKAGE < 10µA
-
-
0.8
V
Input Logic HIGH Voltage
VIH
ILEAKAGE < 10µA
2.1
3.3
5.0
V
Output Logic LOW Voltage
VOL
VDD = 3.0 to 3.6V, IOL = 4mA
-
0.3
0.4
V
Output Logic HIGH Voltage
VOH
VDD = 3.0 to 3.6V, IOH = -4mA
2.6
-
-
V
NOTES
2.3 AC ELECTRICAL CHARACTERISTICS
VDD = 3.0 to 3.6V, TA = 0°C to 70°C, unless otherwise shown
MIN
TYP
MAX
UNITS
Clock Input Frequency
PARAMETER
SYMBOL
FHSCI
CONDITIONS
-
74.25
80
MHz
Input Data Setup Time
tSU
2.5
-
-
ns
50% levels
Input Data Hold Time
tIH
1.5
-
-
ns
50% levels
40
-
60
%
Input Clock Duty Cycle
Output Data Hold Time
tOH
With 15pF load
2.0
-
-
ns
Output Enable Time
toen
With 15pF load
-
-
8
ns
Output Disable Time
todis
With 15pF load
-
-
10
ns
Output Data Delay Time
tOD
Output Data Rise/Fall Time
NOTES
Also supports 74.25/
1.001MHz
With 15pF load
-
-
10
ns
Note 2
With 15pF load
-
-
2.75
ns
20% to 80% levels
FIFO Input Data Setup Time
tFSU
8.0
-
-
ns
Note 1
FIFO Input Data Hold Time
tFIH
4.0
-
-
ns
Note 1
NOTES:
1. The following signals need to adhere to this timing: ANC_Y/C, REN, WEN, ANC_IN[9:0], FFRST.
2. Timing of the FF_STA[2:0] outputs may be greater than specified.
8
GENNUM CORPORATION
52234 - 4
3. DETAILED DESCRIPTION
3.3.2 FIFO Write Control
Data enters and exits the device synchronous to the rising
edge of PCLK_IN as shown in Figure 1.
The FIFO control signal WEN is the write enable signal used
to enable the loading of ANC data into the internal FIFO by
the user through the FIFO interface. Note that the device
only allows loading to one of the two internal FIFO buffers
through the FIFO interface at a time. When ANC_Y/C is
high, the LUMA FIFO may be loaded. When ANC_Y/C is
low, the CHROMA FIFO may be loaded.
3.2 INPUT BLANKER
Data words entering the GS1501 can be dynamically set to
Luma and Chroma blanking levels if desired as shown in
Figure 3. Blanking is applied to both the LUMA and
CHROMA channels simultaneously.
When the internal FIFO is not in the full or overrun states, it
is ready to accept ANC data. This should prompt the user
to supply up to 1024 data words to the FIFO by writing them
through the FIFO interface. Upon seeing a rising edge on
W_CLK, the device will accept the word being presented on
ANC_IN[9:0] into the selected FIFO. Each time W_CLK is
toggled, the internal write address pointer (LUMA or
CHROMA) is incremented while WEN is low. If WEN is high,
the write address pointer is not incremented and writing to
the FIFO is disabled.
3.3 FIFO
The device does not flag transmission errors which might
exist in the ANC data packages. The internal FIFO is 1024
words deep for each of LUMA and CHROMA channels. For
those formats where the HANC region is greater than 1024
words, the user must take steps to ensure the FIFO does
not overflow, otherwise data may be lost. The GS1501
provides status signals to indicate the current content level
of the internal FIFO buffers, as described in section 3.1.
3.3.4 FIFO Read Control
3.3.1 FIFO Status Bits
The FIFO control signal REN is the read enable signal used
to enable ANC data insertion from the internal LUMA or
CHROMA FIFO buffer into its corresponding video stream,
depending on the value of ANC_Y/C. The read address
pointer increments with the internal clock at the video data
rate while REN is low. If REN is high, the read address
pointer will not increment. Both address pointers for read
and write can be reset to their starting positions by toggling
the FIFO reset signal FFRST from high to low.
The device provides a status output signal FF_STA[2:0] that
indicates the state of the current content level of the internal
FIFOs. FF_STA[2:0] outputs 110, should the user supplied
ANC data have completely filled the internal FIFO buffer. It
is noted that once the internal FIFO is full, any attempt to
write data into the FIFO will cause the FIFO to overrun. The
device flags this overrun state by setting FF_STA[2:0]=111.
FF_STA[2:0] outputs 001, should all ANC data in the FIFO
be extracted and inserted into the video stream and the
internal FIFO becomes empty. It is noted that once the
internal FIFO is empty, any attempt to read data from the
FIFO will cause the FIFO to underrun. The device flags this
underrun state by setting FF_STA[2:0]=000 and no data is
inserted into the video stream. When ANC_Y/C is high,
FF_STA indicates the status of the LUMA FIFO buffer and
when ANC_Y/C is low, FF_STA indicates the status of the
CHROMA FIFO buffer.
The device will insert the ANC data into the video streams
whenever data is present in the respective FIFO buffer and
the control signal REN is low. ANC data will be extracted
from the internal FIFO buffer and inserted into the video
stream until it is completely empty. When all words have
been read from the FIFO, the FF_STA[2:0] signal will be set
to 001.
3.3.4 ANC/Data Insertion
It is important that the FIFO status flags are as up-to-date
as possible. Therefore, certain FIFO status flags are
synchronized with respect to W_CLK, and others are
synchronized with respect to PCLK_IN. During a write
cycle, status flags controlled by W_CLK experience a threecycle latency with respect to W_CLK. During a read cycle,
status flags controlled by PCLK_IN experience a threecycle latency with respect to PCLK_IN. This information is
summarized in Table 1, and illustrated in Figures 5 to 14.
In many cases, the user only wants to insert ANC data into
the HANC region. In order to make this frequently used
mode easy, the device provides an automated insertion
mode. When the control signal FM_I/E is high, the FIFO
control signals FFRST and REN cannot be used for the
purpose described above. In this mode of operation, the
device generates these reset and enable signals internally,
which allows an automated insertion of ANC data into the
HANC region of the incoming LUMA or CHROMA data
streams. The user still needs to supply a proper WEN signal
to enable the loading of ANC data into the FIFO. Up to 1024
ANC data words of each of the LUMA or CHROMA FIFO(s)
NOTE: If a simultaneous FIFO read and write operation is to
be performed, the FF_STA[2:0] outputs should not be used
as they may indicate incorrect FIFO status.
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GS1501
3.1 DATA INPUT AND OUTPUTS
may be inserted during the HANC period. These data
should be supplied into the FIFO during the active video
period. Once all words have been read from the FIFO, the
FF_STA signal will be set to 001.
3.3.5 FIFO External Reset
In external FIFO control mode, the internal FIFO address
pointers are reset to zero (0) using FFRST. A recommended
external reset process is shown in Figure 15.
TABLE 1: FIFO Status Indicator
DESCRIPTION
GS1501
FF_STA[2:0]
SYNCHRONIZED TO
000
ERROR flag; FIFO is under run
PCLK_IN
001
FIFO is empty
PCLK_IN
010
FIFO is almost empty; ≤ 32 bytes filled
PCLK_IN
011
FIFO is ready
100
FIFO is half full
W_CLK
101
FIFO is almost full; ≥ 992 bytes filled
W_CLK
110
FIFO is full
W_CLK
111
ERROR flag; FIFO is over run
W_CLK
-
PCLK_IN
DATA_IN
DATA
DATA
DATA
DATA_OUT
tSU
DATA
DATA
DATA
DATA
tIH
tOH
tOD
Fig. 1 Synchronous I/O Time
PCLK_IN
DATA_IN[19:0]
3FF
n Frames
000
000
EAV For Line#1
XYZ
(EAV ID)
LN0
LN1
Line#1 Inserted
Here
RSTLN
Transistion From Low To High Can Happen at Any Point
Fig. 2 RSTLN Timing
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GENNUM CORPORATION
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PCLK_IN
DATA_IN[19:0]
WORD
X
WORD
X+1
WORD
X+2
WORD
X+3
WORD
X+4
WORD
X+6
WORD
X+7
WORD
X+8
Data To Be Blanked
GS1501
BLANK
Fig. 3 Timing of Dynamic Data Blanking
PCLK_IN
DATA_IN[19:10]
(LUMA)
3FF
000
000
XYZ
(EAV ID)
YLN 0
3FF
000
000
XYZ
(SAV ID)
DATA_IN[9:0]
(CHROMA)
3FF
000
000
XYZ
(EAV ID)
CLN 0
3FF
000
000
XYZ
(SAV ID)
WORD11
WORD12
H
V
F
Fig. 4 HVF Input Timing
PCLK_IN
DATA_IN[19:10]
(LUMA)
WORD1
WORD2
WORD3
WORD4
WORD5
WORD6
WORD7
WORD8
WORD9
WORD10
WORD13
9 Cycles
(Will begin reading ANC data out of the FIFO and writing it into the LUMA stream at Word1)
REN
W_CLK
110
(Full)
FF_STA[2:0]
101
(Almost Full)
Note that reference is made to the input data stream since the output is scrambled
Fig. 5 FIFO Full to Almost Full Read Timing
PCLK_IN
DATA_IN[19:10]
(LUMA)
WORD41
WORD42
WORD43
REN
WORD44
WORD45
WORD46
(Low)
W_CLK
FF_STA[2:0]
101
(Almost Full)
100
(Half Full)
Fig. 6 FIFO Almost Full to Half Full Read Timing
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PCLK_IN
WORD521
WORD522
WORD523
REN
WORD524
WORD525
GS1501
DATA_IN[19:10]
(LUMA)
WORD526
(Low)
W_CLK
100
(Half Full)
FF_STA[2:0]
011
(Ready)
Fig. 7 FIFO Half Full to Ready Read Timing
PCLK_IN
DATA_IN[19:10]
(LUMA)
WORD998
WORD
1000
WORD999
REN
WORD
1001
WORD
1002
WORD
1003
(Low)
W_CLK
011
(Ready)
FF_STA[2:0]
010
(Almost Empty)
Fig. 8 FIFO Ready to Almost Empty Read Timing
PCLK_IN
DATA_IN[19:10]
(LUMA)
REN
WORD
1028
WORD
1029
WORD
1030
WORD
1031
WORD
1032
WORD
1033
WORD
1034
WORD
1035
WORD
1036
WORD
1037
WORD
1038
WORD
1039
Set High 9 Cycles Before Point Where Reading
Data From FIFO And Writing It Into The Luma
Stream Is To Stop
W_CLK
FF_STA[2:0]
010
(Almost Empty)
001
(Empty)
000
(Read Error)
001
(Empty)
Fig. 9 FIFO Almost Empty to Empty to Read Error Timing
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PCLK_IN
GS1501
WEN
W_CLK
ANC_IN[9:0]
WORD1
WORD2
WORD3
WORD4
001
(Empty)
FF_STA[2:0]
WORD5
WORD6
010
(Almost Empty)
Fig. 10 FIFO Empty to Almost Empty Write Timing
PCLK_IN
WEN
(Low)
W_CLK
ANC_IN[9:0]
WORD33
WORD34
WORD35
WORD36
100
(Half Full)
011
(Ready)
FF_STA[2:0]
WORD37
Fig. 11 FIFO Ready to Half Full Write Timing
PCLK_IN
WEN
(Low)
W_CLK
ANC_IN[9:0]
FF_STA[2:0]
WORD509
WORD510
WORD511
WORD512
011
(Ready)
WORD513
100
(Half Full)
Fig. 12 FIFO Ready to Half Full Write Timing
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PCLK_IN
WEN
(Low)
GS1501
W_CLK
ANC_IN[9:0]
WORD989
WORD990
WORD991
WORD992
101
(Almost Full)
100
(Half Full)
FF_STA[2:0]
WORD993
Fig. 13 FIFO Half Full to Almost Full Write Timing
PCLK_IN
WEN
W_CLK
ANC_IN9:0]
FF_STA[2:0]
WORD
1022
WORD
1023
WORD
1024
101
(Almost Full)
WORD
1025
110
(Full)
WORD
1026
WORD
1027
WORD
1028
111
(Write Error)
WORD
1029
110
(Full)
Fig. 14 FIFO Almost Full to Full to Write Error Timing
PCLK_IN
W_CLK
FFRST
At least 5 cycles of slowest clock
High for at least 1 cycle
after FFRST toggles
REN/WEN
Fig. 15 Recommended External FIFO Reset Process
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4. REFERENCES
Compliant with SMPTE 292M.
5. PACKAGE & ORDERING INFORMATION
5.1 PACKAGE DIMENSIONS
GS1501
23.20 ±0.25
20.0 ±0.10
18.50 REF
12 TYP
0.75 MIN
0 -7
0.30 MAX RADIUS
17.20 ±0.25
12.50 REF
0-7
14.0 ±0.10
0.13 MIN.
RADIUS
0.88
±0.15
1.6
REF
3.00 MAX
0.50 BSC
0.27 ±0.08
128 pin MQFP
2.80 ±0.25
5.2 ORDERING INFORMATION
PART NUMBER
PACKAGE
TEMPERATURE RANGE
GS1501-CQR
128 pin MQFP
0°C to 70°C
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
REVISION NOTES:
Upgrade document to Data Sheet and reformat.
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
For latest product information, visit www.gennum.com
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX
Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
© Copyright May 2002 Gennum Corporation. All rights reserved. Printed in Canada.
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