ON NCP1573D Low voltage synchronous buck controller Datasheet

NCP1573
Low Voltage Synchronous
Buck Controller
The NCP1573 is a low voltage buck controller. It provides the
control for a DC−DC power solution producing an output voltage as
low as 0.980 V over a wide current range. The NCP1573−based
solution is powered from 12 V with the output derived from a 2−7 V
supply. It contains all required circuitry for a synchronous NFET buck
regulator using the V2™ control method to achieve the fastest possible
transient response and best overall regulation. NCP1573 operates at a
fixed internal 200 kHz frequency and is packaged in an SO−8.
This device provides Power Good with delay and built−in adaptive
non−overlap.
Features
0.980 V ± 1.0% Reference Voltage
V2 Control Topology
200 ns Transient Response
Power Good
Programmable Power Good Delay
40 ns Gate Rise and Fall Times (3.3 nF Load)
Adaptive FET Non−Overlap Time
Fixed 200 kHz Oscillator Frequency
On/Off Control Through Use of the COMP Pin
Overvoltage Protection through Synchronous MOSFETs
Synchronous N−Channel Buck Design
Dual Supply, 12 V Control, 2−7 V Power Source
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1
SO−8
D SUFFIX
CASE 751
PIN CONNECTIONS AND
MARKING DIAGRAM
VCC
PWRGD
PGDELAY
COMP
A
L
Y
W
July, 2006 − Rev. 4
8
GND
VFB
GATE(L)
GATE(H)
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
© Semiconductor Components Industries, LLC, 2006
1
1573
ALYW
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1
Package
Shipping
NCP1573D
SO−8
98 Units/Rail
NCP1573DR2
SO−8
2500 Tape & Reel
Publication Order Number
NCP1573/D
NCP1573
12 V PWRGD VLOGIC
GND
5.0 V
33 μF/8.0 V/1.6 Arms
R1
50 k
C1
C4
VCC
10
C3
GATE(L)
COMP
GATE(H)
L1
100 pF
C6
VFB
PGDELAY
2.5 V/10 A
2.7 μH
GND
PWRGD
NCP1573
C12
0.01 μF
+
C2
NTD4302
Q1
0.47 μF
R4
+
+
+
5.1 k
R3
NTD4302
Q2
+
C8
+
C9
+
C10
C11
GND
56 μF/4.0 V/1.6 Arms
SP−CAP 40 mΩ
R5
3.3 k
C13
0.1 μF
Figure 1. Applications Circuit
MAXIMUM RATINGS*
Rating
Value
Unit
150
°C
−65 to 150
°C
2.0
kV
230 peak
°C
2
−
48
165
°C/W
°C/W
Operating Junction Temperature
Storage Temperature Range
ESD Susceptibility (Human Body Model)
Lead Temperature Soldering:
Reflow: (Note 1)
Moisture Sensitivity Level
Package Thermal Resistance, SO−8
Junction−to−Case, RθJC
Junction−to−Ambient, RθJA
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
IC Power Input
VCC
15 V
−0.5 V
N/A
1.5 A Peak
450 mA DC
Compensation Capacitor
COMP
6.0 V
−0.5 V
10 mA
10 mA
Voltage Feedback Input
VFB
6.0 V
−0.5 V
1.0 mA
1.0 mA
Power Good Output
PWRGD
15 V
−0.5 V
1.0 mA
20 mA
Power Good Delay
PGDELAY
6.0 V
−0.5 V
1.0 mA
10 mA
High−Side FET Driver
GATE(H)
15 V
−0.5 V
−2.0 V for 50 ns
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
Low−Side FET Driver
GATE(L)
15 V
−0.5 V
−2.0 V for 50 ns
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
Ground
GND
0.5 V
−0.5 V
1.5 A Peak
450 mA DC
N/A
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NCP1573
ELECTRICAL CHARACTERISTICS (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF,
CPGDELAY = 0.01 μF, CCOMP = 0.1 μF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
VFB Bias Current
VFB = 0 V
−
0.2
2.0
μA
COMP Source Current
COMP = 1.5 V, VFB = 0.8 V
15
30
60
μA
COMP Sink Current
COMP = 1.5 V, VFB = 1.2 V
15
30
60
μA
Reference Voltage
COMP = VFB
TJ < 25°C
0.970
0.965
0.980
0.980
0.990
0.995
V
V
COMP Max Voltage
VFB = 0.8 V
2.4
2.7
−
V
COMP Min Voltage
VFB = 1.2 V
−
0.1
0.2
V
Open Loop Gain
−
−
98
−
dB
Unity Gain Bandwidth
−
−
20
−
kHz
PSRR @ 1.0 kHz
−
−
70
−
dB
Output Transconductance
−
−
32
−
mmho
Output Impedance
−
−
2.5
−
MΩ
GATE(H) and GATE(L)
Rise Time
1.0 V < GATE(L), GATE(H) < VCC − 2.0 V
−
40
80
ns
Fall Time
VCC − 2.0 V < GATE(L), GATE(H) < 1.0 V
−
40
80
ns
GATE(H) to GATE(L) Delay
GATE(H) < 2.0 V, GATE(L) > 2.0 V
40
60
100
ns
GATE(L) to GATE(H) Delay
GATE(L) < 2.0 V, GATE(H) > 2.0 V
40
60
100
ns
Minimum Pulse Width
GATE(X) = 4.0 V
−
250
−
ns
High Voltage (AC)
Measure GATE(L) or GATE(H)
0.5 nF < CGATE(H) = CGATE(L) < 10 nF
Note 2.
VCC − 0.5
VCC
−
V
Low Voltage (AC)
Measure GATE(L) or GATE(H)
0.5 nF < CGATE(H) = CGATE(L) < 10 nF
Note 2.
−
0
0.5
V
GATE(H)/(L) Pull−Down
Resistance to GND. Note 2.
20
50
115
kΩ
TJ < 25°C
0.852
0.847
0.882
0.882
0.912
0.917
V
V
TJ < 25°C
0.663
0.658
0.685
0.685
0.709
0.714
V
V
−
0.15
0.4
V
7.0
12
18
μA
3.45
4.0
4.3
V
Power Good
Lower Threshold, VO Rising
Lower Threshold, VO Falling
PWRGD Low Voltage
ISINK = 1.0 mA, VFB = 0 V
Delay Charge Current
PGDELAY = 2.0 V
Delay Clamp Voltage
−
Delay Charge Threshold
Ramp PGDELAY, Monitor PWRGD
3.1
3.3
3.5
V
“Good” Signal Delay
With 0.01 μF. Note 2.
1.0
3.0
5.0
ms
2. Guaranteed by design. Not tested in production.
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NCP1573
ELECTRICAL CHARACTERISTICS (continued) (0°C < TJ < 125°C, 11.4 V < VCC < 12.6 V, CGATE(H) = CGATE(L) = 3.3 nF,
CPGDELAY = 0.01 μF, CCOMP = 0.1 μF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
0.475
0.525
0.575
V
−
80
−
%
PWM Comparator
PWM Comparator Offset
VFB = 0 V, Increase COMP Until GATE(H)
Starts Switching
Ramp Max Duty Cycle
−
Artificial Ramp
Duty Cycle = 50%
15
25
35
mV
Transient Response
COMP = 1.5 V, VFB 20 mV Overdrive.
Note 3
−
200
300
ns
VFB Input Range
Note 3
0
−
1.4
V
150
200
250
kHz
−
10
15
mA
Oscillator
Switching Frequency
−
General Electrical Specifications
VCC Supply Current
COMP = 0 V (No Switching)
3. Guaranteed by design. Not tested in production.
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL
FUNCTION
1
VCC
2
PWRGD
3
PGDELAY
4
COMP
5
GATE(H)
High−side switch FET driver pin. Capable of delivering peak currents of 1.5 A.
6
GATE(L)
Low−side synchronous FET driver pin. Capable of delivering peak currents of 1.5 A.
7
VFB
Error amplifier and PWM comparator input.
8
GND
Power supply return.
Power supply input.
Open collector output goes low when VFB is out of regulation. User must externally limit
current into this pin to less than 20 mA.
External capacitor programs PWRGD low−to−high transition delay.
Error amp output. PWM comparator reference input. A capacitor to LGND provides error amp
compensation. Pulling pin < 0.475 V locks gate outputs to a zero percent duty cycle state.
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NCP1573
GND
VCC
−
VFB
Error Amp
+
+
−
PWM Latch
PWM COMP
−
VCC
R
+
Q
GATE(H)
0.980 V
Non
Overlap
S
Reset Dominant
GATE(L)
COMP
0.525 V
− +
Σ
OSC
Art Ramp
80%, 200 kHz
+
0.25 V
−
+
−
12 μA
PGDELAY
−
+
+
−
0.88 V/0.69 V
PGDELAY Latch
S
−
Q
+
+
−
R
Set Dominant
Figure 2. Block Diagram
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3.3 V
PWRGD
NCP1573
TYPICAL PERFORMANCE CHARACTERISTICS
10
216
Oscillator Frequency (kHz)
ICC (mA)
9
8
7
6
5
0
20
40
60
80
Temperature (°C)
100
214
212
210
208
206
204
202
120
0.984
27
0.983
26
0.982
0.981
0.980
0.979
0.978
0
20
40
60
80
Temperature (°C)
100
120
24
23
22
0
20
40
60
80
Temperature (°C)
100
120
Figure 6. Artificial Ramp Amplitude vs. Temperature
(50% Duty Cycle)
540
0.60
535
0.55
Bias Current (μA)
PWM Offset Voltage (mV)
100
25
20
120
Figure 5. Reference Voltage vs. Temperature
530
525
520
40
60
80
Temperature (°C)
21
0.977
0.976
20
Figure 4. Oscillator Frequency vs. Temperature
Ramp Amplitude (mV)
Reference Voltage (V)
Figure 3. Supply Current vs. Temperature
0
0.50
0.45
0
20
40
60
80
Temperature (°C)
100
0.40
120
Figure 7. PWM Offset Voltage vs. Temperature
0
20
40
60
80
Temperature (°C)
100
Figure 8. VFB Bias Current vs. Temperature
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NCP1573
TYPICAL PERFORMANCE CHARACTERISTICS
3.5
30
3.0
Output Current (μA)
29
COMP Voltages (V)
31
Sink Current
28
27
Source Current
26
2.5
2.0
1.0
0
20
40
60
80
Temperature (°C)
100
0
120
Figure 9. Error Amp Output Currents vs. Temperature
COMP Fault
Threshold Voltage
0
20
40
60
80
Temperature (°C)
100
120
Figure 10. COMP Voltages vs. Temperature
38
55
34
GATEH Rise Time
Gate Non−Overlap Time (ns)
GATEH Fall Time
36
GATE Rise/Fall Times (ns)
COMP Minimum
Voltage
1.5
0.5
25
24
COMP Maximum
Voltage
32
30
28
GATEL Rise Time
26
GATEL Fall Time
24
50
GATEH to GATEL
Delay Time
45
GATEL to GATEH
Delay Time
40
35
22
20
0
20
40
60
80
Temperature (°C)
100
30
120
Figure 11. GATE Output Rise and Fall Times vs.
Temperature
40
60
80
Temperature (°C)
100
120
70
Turn−On Threshold,
VFB Rising
900
PWRGD Low Voltage (mV)
PWRGD Threshold Voltages (mV)
20
Figure 12. GATE Non−Overlap Times vs. Temperature
1000
800
700
Turn−Off Threshold,
VFB Falling
600
0
0
20
40
60
80
Temperature (°C)
100
120
Figure 13. PWRGD Thresholds vs. Temperature
65
60
55
50
45
40
0
20
40
60
80
Temperature (°C)
100
Figure 14. PWRGD Output Low Voltage vs.
Temperature
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NCP1573
TYPICAL PERFORMANCE CHARACTERISTICS
1.45
PGDELAY Discharge Current (mA)
PGDELAY Charge Current (μA)
13.4
13.1
12.8
12.5
12.2
11.9
11.6
0
20
40
60
80
Temperature (°C)
100
1.40
1.35
1.30
1.25
1.20
1.15
120
Figure 15. PGDELAY Charge Current vs. Temperature
20
100
120
4.00
PGDELAY Voltages (V)
3.90
257
255
253
PGDELAY
Max Voltage
3.80
3.70
3.60
3.50
3.40
PGDELAY Upper
Threshold Voltage
3.30
251
40
60
80
Temperature (°C)
Figure 16. PGDELAY Discharge Current vs.
Temperature
259
Discharge Threshold Voltage (mV)
0
0
20
40
60
80
Temperature (°C)
100
120
Figure 17. PGDELAY Discharge Threshold Voltage vs.
Temperature
3.20
0
20
40
60
80
Temperature (°C)
100
Figure 18. PGDELAY Voltages vs. Temperature
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NCP1573
APPLICATION INFORMATION
THEORY OF OPERATION
VIN
The NCP1573 is a simple, synchronous, fixed−frequency,
low−voltage buck controller using the V2 control method. It
provides a programmable−delay Power Good function to
indicate when the output voltage is out of regulation.
VCOMP
0.5 V
VFB
V2 Control Method
The V2 control method uses a ramp signal generated by
the ESR of the output capacitors. This ramp is proportional
to the AC current through the main inductor and is offset by
the DC output voltage. This control scheme inherently
compensates for variation in either line or load conditions,
since the ramp signal is generated from the output voltage
itself. The V2 method differs from traditional techniques
such as voltage mode control, which generates an artificial
ramp, and current mode control, which generates a ramp
using the inductor current.
−
GATE(H)
+
GATE(L)
PWM
RAMP
Slope
Compensation
COMP
GATE(H)
STARTUP
Figure 20. Idealized Waveforms
VFB
−
Error
Signal
+
NORMAL OPERATION
A variation in line voltage changes the current ramp in the
inductor, which causes the V2 control scheme to compensate
the duty cycle. Since any variation in inductor current
modifies the ramp signal, as in current mode control, the V2
control scheme offers the same advantages in line transient
response.
A variation in load current will affect the output voltage,
modifying the ramp signal. A load step immediately changes
the state of the comparator output, which controls the main
switch. The comparator response time and the transition
speed of the main switch determine the load transient
response. Unlike traditional control methods, the reaction
time to the output load step is not related to the crossover
frequency of the error signal loop.
The error signal loop can have a low crossover frequency,
since the transient response is handled by the ramp signal
loop. The main purpose of this ‘slow’ feedback loop is to
provide DC accuracy. Noise immunity is significantly
improved, since the error amplifier bandwidth can be rolled
off at a low frequency. Enhanced noise immunity improves
remote sensing of the output voltage, since the noise
associated with long feedback traces can be effectively
filtered.
Line and load regulation are drastically improved because
there are two independent control loops. A voltage mode
controller relies on the change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation. A
current mode controller maintains a fixed error signal during
line transients, since the slope of the ramp signal changes in
this case. However, regulation of load transients still requires
a change in the error signal. The V2 method of control
maintains a fixed error signal for both line and load variation,
since the ramp signal is affected by both line and load.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope in the output ripple can
lead to pulse width jitter and variation caused by both random
and synchronous noise. A ramp waveform generated in the
oscillator is added to the ramp signal from the output voltage
Output
Voltage
Error
Amplifier
tS
Reference
Voltage
Figure 19. V2 Control with Slope Compensation
The V2 control method is illustrated in Figure 19. The
output voltage generates both the error signal and the ramp
signal. Since the ramp signal is simply the output voltage, it
is affected by any change in the output, regardless of the
origin of that change. The ramp signal also contains the DC
portion of the output voltage, allowing the control circuit to
drive the main switch from 0% to 100% duty cycle as
required.
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NCP1573
to provide the proper voltage ramp at the beginning of each
switching cycle. This slope compensation increases the noise
immunity, particularly at duty cycles above 50%.
PWRGD
High
Start Up
The NCP1573 features a programmable Soft Start
function, which is implemented through the error amplifier
and the external compensation capacitor. This feature
prevents stress to the power components and limits output
voltage overshoot during start−up. As power is applied to the
regulator, the compensation capacitor connected to the
COMP pin is charged by a 30 μA current source. When the
capacitor voltage exceeds the 0.525 V offset of the PWM
comparator, the PWM control loop will allow switching to
occur. The upper gate driver GATE(H) is activated, turning
on the upper MOSFET. The current ramps up through the
main inductor and linearly powers the output capacitors and
load. When the regulator output voltage exceeds the COMP
pin voltage minus the 0.525 V PWM comparator offset
threshold and the artificial ramp, the PWM comparator
terminates the initial pulse.
Low
VOUT
70%
90%
Percent of
Designed VOUT
Figure 21. PWRGD Assertion
Overvoltage Protection
Overvoltage protection is provided as a result of the
normal operation of the V2 control method and requires no
additional external components. The control loop responds
to an overvoltage condition within 200 ns, turning off the
upper MOSFET and disconnecting the regulator from its
input voltage. This results in a crowbar action to clamp the
output voltage, preventing damage to the load. The regulator
remains in this state until the overvoltage condition ceases.
Normal Operation
During normal operation, the duty cycle of the gate drivers
remains approximately constant as the V2 control loop
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load conditions
will result in changes in duty cycle to maintain regulation.
Power Good
The PWRGD pin is asserted when the output voltage is
within regulation limits. Sensing for the PWRGD pin is
achieved through the VFB pin. When the output voltage is
rising, PWRGD goes high at 90% of the designed output
voltage. When the output voltage is falling, PWRGD goes
low at 70% of the designed output voltage. PWRGD is an
open−collector output and should be externally pulled to
logic high through a resistor to limit current to no more than
20 mA. Figure 21 shows the hysteretic nature of the
PWRGD pin’s operation.
Input Supplies
The NCP1573 can be used in applications where a 12 V
supply is available along with a lower voltage supply. Often
the lower voltage supply is 5 V, but it can be any voltage less
than the 12 V supply minus the required gate drive voltage
of the top MOSFET. The greater the difference between the
two voltages, the better the efficiency due to increasing VGS
available to turn on the upper MOSFET. In order to maintain
power supply stability, the lower supply voltage should be
at least 1.5 times the desired voltage.
A lower supply voltage between 2−7 V is recommended.
CONVERTER DESIGN
Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
Gate Charge Effect on Switching Times
When using the onboard gate drivers, the gate charge has
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading.
Transient Response
The 200 ns reaction time of the control loop provides fast
transient response to any variations in input voltage and
output current. Pulse−by−pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
DVOUT + DIOUT
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t
ǒESL
) ESR ) TR Ǔ
Dt
COUT
NCP1573
bypass capacitor bank, which has to initially support the
sudden load change.
The minimum inductance value for the input inductor is
therefore:
where:
ΔIOUT / Δt = load current slew rate;
ΔIOUT = load transient;
Δt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors
and circuit traces;
tTR = output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula:
LIN +
where:
LIN = input inductor value;
ΔV = voltage seen by the input inductor during a full load
swing;
(dI/dt)MAX = maximum allowable input current slew rate.
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double−pole network
with a slope of −2.0, a roll−off rate of −40 dB/dec, and a
corner frequency:
fC +
DVESR
ESRMAX +
DIOUT
There are many factors to consider when choosing the
output inductor. Maximum load current, core and winding
losses, ripple current, short circuit current, saturation
characteristics, component height and cost are all variables
that the designer should consider. However, the most
important consideration may be the effect inductor value has
on transient response.
The amount of overshoot or undershoot exhibited during
a current transient is defined as the product of the current
step and the output filter capacitor ESR. Choosing the
inductor value appropriately can minimize the amount of
energy that must be transferred from the inductor to the
capacitor or vice−versa. In the subsequent paragraphs, we
will determine the minimum value of inductance required
for our system and consider the trade−off of ripple current
vs. transient response.
In order to choose the minimum value of inductance, input
voltage, output voltage and output current must be known.
Most computer applications use reasonably well regulated
bulk power supplies so that, while the equations below
specify VIN(MAX) or VIN(MIN), it is possible to use the
nominal value of VIN in these calculations with little error.
Current in the inductor while operating in the continuous
current mode is defined as the load current plus ripple current.
ESRCAP
ESRMAX
ESRMAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
ESLMAX +
DVESL
DI
ǸLC
Selection of the Output Inductor
where:
ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheet).
ESRMAX = maximum allowable ESR.
The actual output voltage deviation due to ESR can then be
verified and compared to the value assigned by the designer:
DVESR + DIOUT
1
2p
where:
L = input inductor;
C = input capacitor(s).
where:
ΔVESR = change in output voltage due to ESR (assigned
by the designer)
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula:
Number of capacitors +
DV
(dIńdt)MAX
Dt
Selection of the Input Inductor
A common requirement is that the buck controller must
not disturb the input voltage. One method of achieving this
is by using an input inductor and a bypass capacitor. The
input inductor isolates the supply from the noise generated
in the switching portion of the buck regulator and also limits
the inrush current into the input capacitors upon power up.
The inductor’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the load changes from no load to full load
(load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
IL + ILOAD ) IRIPPLE
The ripple current waveform is triangular, and the current
is a function of voltage across the inductor, switch FET
on−time and the inductor value. FET on−time can be defined
as the product of duty cycle and switch frequency, and duty
cycle can be defined as a ratio of VOUT to VIN. Thus,
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NCP1573
IRIPPLE +
Ra for an inductor designed to conduct 20 A to 30 A is
approximately 45°C/W. The inductor temperature is given as:
(VIN * VOUT)VOUT
(fOSC)(L)(VIN)
T(inductor) + DT(inductor) ) Tambient
Peak inductor current is defined as the load current plus
half of the peak current. Peak current must be less than the
maximum rated FET switch current, and must also be less
than the inductor saturation current. Thus, the maximum
output current can be defined as:
IOUT(MAX) + ISWITCH(MAX) *
VCC Bypass Filtering
A small RC filter should be added between module VCC
and the VCC input to the IC. A 10 Ω resistor and a 0.47 μF
capacitor should be sufficient to ensure the controller IC does
not operate erratically due to injected noise, and will also
supply reserve charge for the onboard gate drivers.
ǒVIN(MAX) * VOUTǓVOUT
ǒ2ǓǒfOSCǓǒLǓǒVIN(MAX)Ǔ
Since the maximum output current must be less than the
maximum switch current, the minimum inductance required
can be determined.
L(MIN) +
Input Filter Capacitors
The input filter capacitors provide a charge reservoir that
minimizes supply voltage variations due to changes in current
flowing through the switch FETs. These capacitors must be
chosen primarily for ripple current rating.
(VIN(MIN) * VOUT)VOUT
(fOSC)(ISWITCH(MAX))(VIN(MIN))
This equation identifies the value of inductor that will
provide the full rated switch current as inductor ripple current,
and will usually result in inefficient system operation. The
system will sink current away from the load during some
portion of the duty cycle unless load current is greater than
half of the rated switch current. Some value larger than the
minimum inductance must be used to ensure the converter
does not sink current. Choosing larger values of inductor will
reduce the ripple current, and inductor value can be designed
to accommodate a particular value of ripple current by
replacing ISWITCH(MAX) with a desired value of IRIPPLE:
VIN
VOUT
COUT
CONTROL
INPUT
Figure 22.
Consider the schematic shown in Figure 22. The average
current flowing in the input inductor LIN for any given
output current is:
IIN(AVE) + IOUT
VOUT
VIN
Input capacitor current is positive into the capacitor when
the switch FETs are off, and negative out of the capacitor
when the switch FETs are on. When the switches are off,
IIN(AVE) flows into the capacitor. When the switches are on,
capacitor current is equal to the per−phase output current
minus IIN(AVE). If we ignore the small current variation due
to the output ripple current, we can approximate the input
capacitor current waveform as a square wave. We can then
calculate the RMS input capacitor ripple current:
(L)(DIOUT)
(VIN * VOUT)
(L)(DIOUT)
(VOUT)
Inductor value selection also depends on how much output
ripple voltage the system can tolerate. Output ripple voltage
is defined as the product of the output ripple current and the
output filter capacitor ESR.
Thus, output ripple voltage can be calculated as:
VRIPPLE + ǒESRCǓǒIRIPPLEǓ +
CIN
IRMS(CIN)
However, reducing the ripple current will cause transient
response times to increase. The response times for both
increasing and decreasing current steps are shown below.
TRESPONSE(DECREASING) +
LOUT
IIN(AVE)
(VIN(MIN) * VOUT)VOUT
L(RIPPLE) +
(fOSC)(IRIPPLE)(VIN(MIN))
TRESPONSE(INCREASING) +
LIN
Ǹ
IRMS(CIN) +
ǒESRCǓǒVIN * VOUTǓVOUT
ǒfOSCǓǒLǓǒVINǓ
V
I 2IN(AVE) ) OUT
VIN
ǒIOUT per phase * IIN(AVE)Ǔ2 * I 2
IN(AVE)
ƪ
ƫ
The input capacitance must be designed to conduct the
worst case input ripple current. This will require several
capacitors in parallel. In addition to the worst case current,
attention must be paid to the capacitor manufacturer’s
derating for operation over temperature.
As an example, let us define the input capacitance for a
5 V to 3.3 V conversion at 10 A at an ambient temperature
of 60°C. Efficiency of 80% is assumed. Average input
current in the input filter inductor is:
Finally, we should consider power dissipation in the
output inductors. Power dissipation is proportional to the
square of inductor current:
PD + (I 2L)(ESRL)
The temperature rise of the inductor relative to the air
surrounding it is defined as the product of power dissipation
and thermal resistance to ambient:
DT(inductor) + (Ra)(PD)
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NCP1573
IIN(AVE) + (10 A)(3.3 Vń5 V) + 6.6 A
PON(BOTTOM) +
Input capacitor RMS ripple current is then
Ǹ
IIN(RMS) +
ǒnumber of bottom−side FETsǓ
where:
n = number of phases.
Note that RDS(ON) increases with temperature. It is good
practice to use the value of RDS(ON) at the FET’s maximum
junction temperature in the calculations shown above.
6.62 ) 3.3 V
5V
[(10 A * 6.6 A)2 * 6.6 A2]
+ 4.74 A
If we consider a Rubycon MBZ series capacitor, the ripple
current rating for a 6.3 V, 1800 nF capacitor is 2000 mA at
100 kHz and 105°C. We determine the number of input
capacitors by dividing the ripple current by the
per−capacitor current rating:
IRMS(TOP) +
ǸI
2
PK
* (IPK)(IRIPPLE) ) D I 2RIPPLE
3
IRMS(BOTTOM) + I 2PK * (IPKIRIPPLE) )
Number of capacitors + 4.74 Ań2.0 A + 2.3
A total of at least 3 capacitors in parallel must be used to
meet the input capacitor ripple current requirements.
Output Switch FETs
Output switch FETs must be chosen carefully, since their
properties vary widely from manufacturer to manufacturer.
The NCP1573 system is designed assuming that n−channel
FETs will be used. The FET characteristics of most concern
are the gate charge/gate−source threshold voltage, gate
capacitance, on−resistance, current rating and the thermal
capability of the package.
The onboard FET driver has a limited drive capability. If
the switch FET has a high gate charge, the amount of time
the FET stays in its ohmic region during the turn−on and
turn−off transitions is larger than that of a low gate charge
FET, with the result that the high gate charge FET will
consume more power. Similarly, a low on−resistance FET
will dissipate less power than will a higher on−resistance
FET at a given current. Thus, low gate charge and low
RDS(ON) will result in higher efficiency and will reduce
generated heat.
It can be advantageous to use multiple switch FETs to
reduce power consumption. By placing a number of FETs in
parallel, the effective RDS(ON) is reduced, thus reducing the
ohmic power loss. However, placing FETs in parallel
increases the gate capacitance so that switching losses
increase. As long as adding another parallel FET reduces the
ohmic power loss more than the switching losses increase,
there is some advantage to doing so. However, at some point
the law of diminishing returns will take hold, and a marginal
increase in efficiency may not be worth the board area
required to add the extra FET. Additionally, as more FETs
are used, the limited drive capability of the FET driver will
have to charge a larger gate capacitance, resulting in
increased gate voltage rise and fall times. This will affect the
amount of time the FET operates in its ohmic region and will
increase power dissipation.
The following equations can be used to calculate power
dissipation in the switch FETs.
For ohmic power losses due to RDS(ON):
PON(TOP) +
ǒRDS(ON)(BOTTOM)ǓǒIRMS(BOTTOM)Ǔ2
(RDS(ON)(TOP))(IRMS(TOP))2
(number of topside FETs)
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(1 * D) 2
I RIPPLE
3
NCP1573
IRIPPLE +
external p−channel FET gates the 12 V supply to the IC. The
signal also controls an alternate supply that drives a linear
regulator. The linear regulator provides back−up power for
the load during low−power operation.
In this case, the 12 V supply turn−on and turn−off is so fast
that the controller does not charge or discharge the output
capacitance significantly during the transition intervals.
This minimizes glitching during the transitions. Also, note
that a resistor divider and a diode connect the logic signal to
the COMP pin of the NCP1573. The divider and diode
network serve to hold the COMP voltage up when the IC is
powered down. When the power management state changes
and the IC powers back up, having the COMP voltage at its
correct level further reduces glitching. The correct COMP
level is determined to be the IC reference voltage (0.98 V)
plus the channel start−up offset of the controller (0.525 V),
plus about 10 mV to account for artificial ramp amplitude
(total of 1.615 V). The divider voltage must be about 100 mV
higher to allow for the diode forward voltage. Note that very
little current is assumed to flow through the diode since only
capacitor leakage current should be present.
There will always be some small voltage adjustment
during transitions due to manufacturing tolerances. Having
the COMP voltage slightly low will result in a temporary sag
in the output voltage as the linear regulator turns off and the
switching supply turns on. Similarly, a positive change in
VOUT will occur if the COMP voltage is slightly too high.
(VIN * VOUT)(VOUT)
(fOSC)(L)(VIN)
I
I
I
IPEAK + ILOAD ) RIPPLE + OUT ) RIPPLE
2
3
2
where:
D = Duty cycle.
For switching power losses:
PD + nCV2(fOSC)
where:
n = number of switch FETs (either top or bottom),
C = FET gate capacitance,
V = maximum gate drive voltage (usually VCC),
fOSC = switching frequency.
System Considerations for the NCP1573
The NCP1573 controller is optimized for converter
designs where the power supply for the controller IC has
very short turn−on and turn−off times. Such systems can be
found providing power to graphics cards or memory where
standby power is also provided. The key features of the
NCP1573 are that undervoltage lockout and soft start
resetting are not included. These features must be absent to
allow the NCP1573 to interface in a glitch−free manner with
back−up power supplies.
A schematic showing a possible system implementation
using the NCP1573 is included in Figure 23. Note that an
PWRGD
12 V
GND
3
R11
10 k
2
Q3
NTMS10P02R2
R3
10
Rubycon MBZ
R1
47 k
Q5
MGSF1N02ELT1
4
VCC
GND
PWRGD
VFB
PGDELAY GATEL
COMP
C2 +
1800 μF
R10
10 k
GATEH
NCP1573
8
7
6
SWN
C6
100 pF
5
VFB
C13
0.1 μF
LDO_ON_3.3
R5
16.9 k
D1
1N5817
R7
16.2 k
Figure 23.
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U2
CS5201
VIN
VOUT ADJUST
R8
1.25 k
R9
1.25 k
Q4
NTMS10P02R2
Q1
MTB1306
U1
1
3
C12
0.01 μF
C1 +
1800 μF
C4
0.1 μF
2
5V
5V
L1 2.7 μH
R4
Q2
5.1 k
MTB1306
R6
3.3 k
2.5 V
+
C8
+
1800 μF
C9
1800 μF
Rubycon MBZ
Q6
MGSF1N02ELT1
1
NCP1573
Providing fast turn−on and turn−off edges to the IC power
is very important in minimizing glitching because there is no
undervoltage lockout circuitry. For example, if the switcher
were powered up and regulating, and the supply began to
decrease slowly, the GATE outputs of the IC would continue
to switch until the driver circuitry ran out of headroom
(when VCC reaches approximately 5 V). When the drivers
collapse, an on−chip resistor from the GATE pins to ground
will bottom the external n−channel FETs and the switch
node becomes disconnected from the DC−DC converter.
Until this happens, it is entirely possible that the bottom FET
may have a large duty cycle and be trying to discharge the
VOUT capacitance. Additionally, as the bias circuitry in the
IC collapses, the reference voltage to the error amplifier may
change and result in false regulation. The circuit in Figure 23
will operate properly with turn−on and turn−off times on the
order of 500 μs or faster.
12 V VCC
12 V VCC
VOUT
COMP
VOUT
COMP
Figure 24. Output Transient with COMP Voltage
Positioned 100 mV Too High
Figure 25. Output Transient with COMP Voltage
Positioned 100 mV Too Low
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NCP1573
Layout Considerations
4. The IC should not be placed in the path of
switching currents. If a ground plane is used, care
should be taken by the designer to ensure that the
IC is not located over a ground or other current
return path.
1. The fast response time of V2 technology increases
the IC’s sensitivity to noise on the VFB line.
Fortunately, a simple RC filter, formed by the
feedback network and a small capacitor (100 pF
works well, shown below as C6) placed between
VFB and GND, filters out most noise and provides a
system practically immune to jitter. This capacitor
should be located as close as possible to the IC.
2. The COMP capacitor (shown below as C13)
should be connected via its own path to the IC
ground. The COMP capacitor is sensitive to the
intermittent ground drops caused by switching
currents. A separate ground path will reduce the
potential for jitter.
3. The VCC bypass capacitor (0.1 μF or greater,
shown below as C4) should be located as close as
possible to the IC. This capacitor’s connection to
GND must be as short as possible. The 10 Ω
resistor (shown below as R3) should be placed
close to the VCC pin.
R4
C6
VOUT
R6
C4
C12
R3
U1
C13
R1
5V
GND
12 V PWRGD
Figure 26.
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NCP1573
PACKAGE DIMENSIONS
−X−
SO−8
D SUFFIX
CASE 751−07
ISSUE W
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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NCP1573/D