AD ADP1055DC1-EVALZ Digital controller for power supply applications with pmbus interface Datasheet

Digital Controller for Power Supply
Applications with PMBus Interface
ADP1055
Data Sheet
FEATURES
Extended black box data recorder for fault recording
User trimming on input and output voltages and currents
Digital current sharing
−40°C to +125°C operation
PMBus Revision 1.2 compliant with PEC and extended
manufacturer specific commands
32-bit password protection with command masking
64 address selections (16 base addresses, expandable to 64)
6 PWM control signals, 625 ps resolution
Frequency from 48 kHz to 1 MHz
Duty cycle double update rate
Digital control loop (PID + additional pole or zero
configurability)
Programmable loop filters (CCM, DCM, low/normal
temperature)
Fast line voltage feedforward
Adaptive dead time compensation for improved efficiency
Remote voltage sense
Redundant programmable OVP
Current sense
Primary side cycle-by-cycle fast protection
Secondary side cycle-by-cycle fast overcurrent protection
Secondary side averaged reverse current protection using
diode emulation mode with fixed debounce
Synchronous rectifier control for improved efficiency
in light load mode
Nonlinear gain for faster transient response from DCM to CCM
Frequency synchronization
Soft start and soft stop functionality
Average and peak constant current mode
External PN junction temperature sensing
4 GPIOs (2 GPIOs configurable as active clamp snubber PWMs)
APPLICATIONS
Isolated dc-to-dc power supplies and modules
Redundant power supply systems
GENERAL DESCRIPTION
The ADP1055 is a flexible, feature-rich digital secondary side
controller that targets ac-to-dc and isolated dc-to-dc secondary
side applications. The ADP1055 is optimized for minimal
component count, maximum flexibility, and minimum design
time. Features include differential remote voltage sense, primary
and secondary side current sense, pulse-width modulation (PWM)
generation, frequency synchronization, redundant OVP, and
current sharing. The control loop digital filter and compensation
terms are integrated and can be programmed over the PMBus™
interface. Programmable protection features include
overcurrent (OCP), overvoltage (OVP) limiting, undervoltage
lockout (UVLO), and external overtemperature (OTP).
The built-in EEPROM provides extensive programming of the
integrated loop filter, PWM signal timing, inrush current, and
soft start timing and sequencing. Reliability is improved through
a built-in checksum and programmable protection circuits.
A comprehensive GUI is provided for easy design of loop filter
characteristics and programming of the safety features. The
industry-standard PMBus provides access to the many monitoring
and system test functions. The ADP1055 is available in a 32-lead
LFCSP and operates from a single 3.3 V supply.
TYPICAL APPLICATION DIAGRAM
VOUT
DC
INPUT
LOAD
DRIVER
CS1
DRIVER
iCoupler ®
SR1 SR2
VFF
CS2– CS2+
OVP
VS+ VS–
ISHARE
OUTA
OUTB
OUTC
OUTD
SYNC
ADP1055
RES ADD JTD JRTN GPIO1 TO GPIO4
NC
CTRL SMBALRT
SDA SCL
VCORE
VDD AGND DGND
PMBus
12004-001
VDD
Figure 1.
Rev. A
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ADP1055
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Matched Cycle-by-Cycle Current Limit (OCP Equalization) ... 25
Applications ....................................................................................... 1
Low Temperature Filter ............................................................. 25
General Description ......................................................................... 1
Voltage Loop Autocorrection ................................................... 25
Typical Application Diagram .......................................................... 1
Nonlinear Gain/Response ......................................................... 26
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Integrator Windup and Output Voltage Regulation Loss
(Overshoot Protection) ............................................................. 26
Specifications..................................................................................... 5
Accurate Secondary Overcurrent Protection ......................... 26
Absolute Maximum Ratings.......................................................... 10
Secondary Fast Overcurrent Protection .................................. 27
Thermal Resistance .................................................................... 10
Secondary Fast Reverse Current Protection............................... 27
Soldering ...................................................................................... 10
Feedforward and Input Voltage Sense ..................................... 27
ESD Caution ................................................................................ 10
Accurate Overvoltage and Undervoltage Protection............. 28
Pin Configuration and Function Descriptions ........................... 11
Fast Overvoltage Protection...................................................... 28
Typical Performance Characteristics ........................................... 13
External Frequency Synchronization ...................................... 28
Controller Architecture ................................................................. 16
Temperature Sensing ................................................................. 29
Start-Up and Power-Down Sequencing ...................................... 17
GPIO and PGOOD Signals ....................................................... 29
VDD and VCORE Pins.............................................................. 17
GPIO3 and GPIO4 as Snubber PWM Outputs ...................... 31
Power-Up and Power-Down Commands ............................... 17
Average Constant Current Mode ............................................. 32
Power Sequencing ...................................................................... 17
32-Bit Key Code ......................................................................... 32
Power-Up and Soft Start Routine ............................................. 17
SR Phase-In, SR Transition, and SR Fast Phase-In ................ 33
Soft Stop Routine ........................................................................ 17
Output Voltage Slew Rate .......................................................... 33
VDD/VCORE OVLO ................................................................ 18
Adaptive Dead Time Compensation ....................................... 33
Control Loop and PWM Operation............................................. 19
SR Delay ....................................................................................... 34
Voltage Sense, Feedback, and Control Loop............................. 19
Current Sharing (ISHARE Pin) ................................................ 34
Output Voltage Sense ................................................................. 19
Droop Sharing ............................................................................ 36
Digital Filter ................................................................................ 19
Light Load Mode and Deep Light Load Mode ....................... 37
Digital Filter Programming Registers ...................................... 20
Pulse Skipping............................................................................. 37
Digital Compensation Filters During Soft Start..................... 20
Soft Stop ....................................................................................... 37
Filter Transition .......................................................................... 20
Duty Cycle Double Update Rate .............................................. 37
PWM and Synchronous Rectifier Outputs (OUTA, OUTB,
OUTC, OUTD, SR1, SR2) ......................................................... 21
Duty Balance, Volt-Second Balance, and Flux Balancing ..... 38
Fault Responses and State Machine Mechanics ......................... 39
Synchronous Rectification ........................................................ 21
Priority of Faults ......................................................................... 39
Modulation Limit ....................................................................... 22
Flags ............................................................................................. 39
Switching Frequency Programming ........................................ 22
First Fault ID (FFID) ................................................................. 39
ADCs and Telemetry ...................................................................... 23
Fault Condition During Soft Start and Soft Stop ................... 40
ADCs for Current Sensing ........................................................ 23
Watchdog Timer ......................................................................... 40
ADCs for Voltage Sensing ......................................................... 24
Standard PMBus Flags ............................................................... 42
ADCs for Temperature Sensing ................................................ 24
Black Box Feature ........................................................................... 43
Theory of Operation ...................................................................... 25
Black Box Operation .................................................................. 43
Accurate Primary Overcurrent Protection ............................... 25
Black Box Contents .................................................................... 43
Primary Fast Overcurrent Protection ...................................... 25
Black Box Timing ....................................................................... 44
Rev. A | Page 2 of 140
Data Sheet
ADP1055
Black Box Readback ....................................................................45
VDD Pin ....................................................................................... 53
Black Box Power Sequencing.....................................................45
SDA and SCL Pins ...................................................................... 53
Power Supply Calibration and Trim .............................................46
CS1 Pin ......................................................................................... 53
Voltage Calibration and Trim ....................................................46
Exposed Pad................................................................................. 53
CS1 Trim ......................................................................................46
VCORE Pin .................................................................................. 53
VFF Calibration and Trim .........................................................46
RES Pin ......................................................................................... 53
PMBus Digital Communication....................................................47
JTD and JRTN Pins..................................................................... 53
Features .........................................................................................47
OVP Pin ....................................................................................... 53
Overview ......................................................................................47
SYNC Pin ..................................................................................... 53
Transfer Protocol .........................................................................47
AGND and DGND ..................................................................... 53
Data Transfer Commands ..........................................................48
EEPROM .......................................................................................... 54
Group Command Protocol ........................................................49
Overview ...................................................................................... 54
Clock Generation and Stretching..............................................49
Page Erase Operation ................................................................. 54
Start and Stop Conditions ..........................................................49
Read Operation (Byte Read and Block Read) ......................... 54
Repeated Start Condition ...........................................................49
Write Operation (Byte Write and Block Write) ...................... 55
General Call Support ..................................................................49
EEPROM Password .................................................................... 55
Alert Response Address (ARA).................................................49
Downloading EEPROM Settings to Internal Registers ......... 56
PMBus Address Selection ..........................................................50
Saving Register Settings to the EEPROM ................................ 56
Fast Mode .....................................................................................50
EEPROM CRC Checksum......................................................... 56
10-Bit Addressing ........................................................................50
Software GUI ................................................................................... 57
Packet Error Checking................................................................50
Standard PMBus Commands Supported by the ADP1055 ....... 58
Electrical Specifications..............................................................50
Manufacturer Specific Commands ............................................... 60
Fault Conditions ..........................................................................50
Standard PMBus Command Descriptions .................................. 62
Timeout Conditions ...................................................................51
Standard PMBus Commands .................................................... 62
Data Transmission Faults ...........................................................51
Manufacturer Specific PMBus Command Descriptions ........... 86
Data Content Faults ....................................................................52
Supported Switching Frequencies ...............................................126
Layout Guidelines............................................................................53
Outline Dimensions ......................................................................140
CS2+ and CS2− Pins ...................................................................53
Ordering Guide .........................................................................140
VS+ and VS− Pins .......................................................................53
REVISION HISTORY
3/15—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 7
Changes to Snubber Configuration Section ................................31
Change to Debounce Bit, Table 159 ..............................................93
Changes to Supported Switching Frequencies Section ............126
3/14—Revision 0: Initial Version
Rev. A | Page 3 of 140
ADP1055
Data Sheet
ADP1055
VDD
OVP
VS–
VS+
VFF
CS2+
CS1
CS2–
FUNCTIONAL BLOCK DIAGRAM
+ –
DAC
UVLO
ADC
ADC
ADC
VFF
CS2
ADC
LDO
CS1
VCORE
OCP1
VFB
OVP
ISHARE
PWM
ENGINE
DIGITAL
COMPENSATOR
DIGITAL CORE
8kB
EEPROM
SR1
STATE
MACHINE
GPIO1
TO
GPIO4
I2C
INTERFACE
SR2
SYNC
DGND
SDA
SCL SMBALRT
ADC
ADC
ADD
JTD JRTN
REF
AGND
CTRL
Figure 2. Functional Block Diagram (Simplified Internal Structure)
Rev. A | Page 4 of 140
RES
12004-002
OUTB
OUTD
IREV
METERING
OUTA
OUTC
OCP2
Data Sheet
ADP1055
SPECIFICATIONS
VDD = 3.0 V to 3.6 V, TA = −40°C to +125°C, unless otherwise noted. FSR = full-scale range.
Table 1.
Parameter
SUPPLY
Supply Voltage
Supply Current
POWER-ON RESET
Power-On Reset
Undervoltage Lockout
Overvoltage Lockout
OVLO Debounce
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
VDD
IDD
4.7 μF capacitor connected to AGND
Normal operation (CTRL pin is high)
Normal operation (CTRL pin is low)
During EEPROM programming (40 ms)
During black box write
Current with VDD < VCORE POR
3.0
3.3
63
55
IDD + 8
IDD + 8
100
3.6
V
mA
mA
mA
mA
μA
POR
UVLO
OVLO
VDD rising
VDD falling
2.75
3.8
2.85
4.0
2.0
500
3.0
2.97
4.1
V
V
V
μs
μs
Set to 2 μs (Register 0xFE4D[5] = 0)
Set to 500 μs (Register 0xFE4D[5] = 1)
0.33 μF capacitor connected to DGND
VDD falling
TA = 25°C
No black box recording
(Register 0xFE48[1:0] = 00)
With black box recording
(Register 0xFE48[1:0] = 01, 10, or 11)
VCORE PIN
Power-On Reset (POR)
Output Voltage
Maximum Time from POR to
Outputs Switching
OSCILLATOR AND PLL
PLL Frequency
OUTA, OUTB, OUTC, OUTD, SR1,
SR2 PINS
Output Low Voltage
Output High Voltage
Rise Time
Fall Time
VOLTAGE FEEDFORWARD (VFF PIN)
ADC Clock Frequency
Feedforward (Slow) Input
Voltage Range
ADC Usable Input Voltage Range
Measurement Accuracy (Slow
and Fast Feedforward)
RES = 10 kΩ (±0.1%)
VOL
VOH
VFF
Sink current = 10 mA
Source current = 10 mA
CLOAD = 50 pF
CLOAD = 50 pF
For reporting; equivalent resolution
of 12 bits
V
V
ms
45
ms
200
210
MHz
0.8
V
V
ns
ns
VDD − 0.8
3.5
1.5
1.6
MHz
V
0
1.57
V
−2.5
−2.0
−1.5
+2.5
+2.0
+1.5
1.0
% FSR
% FSR
% FSR
μA
1.6
V
0
1.56
1
Factory trimmed at 1.0 V
0% to 100% of usable input voltage range
10% to 90% of usable input voltage range
900 mV to 1.1 V
Leakage Current
FEEDFORWARD FUNCTION
(VFF PIN)
Feedforward (Fast) Input
Voltage Range
Sampling Period for
Feedforward (Fast) ADC
VS LOW SPEED ADC
Input Voltage Range
Usable Input Voltage Range
ADC Clock Frequency
190
2.1
2.6
10
0.6
Equivalent resolution of 12 bits
Differential voltage from VS+ to VS−
1
1
0
0
1
1.56
Rev. A | Page 5 of 140
μs
1.6
1.55
V
V
MHz
ADP1055
Parameter
ADC Update Rate
Data Sheet
Symbol
Measurement Accuracy
Temperature Coefficient
Leakage Current
Common-Mode Voltage Offset
Error
VS OVP DIGITAL COMPARATOR
VS OVP Accuracy
VS OVP Comparator Speed
Current Sense Measurement
CS1 Fast OCP Threshold
CS1 Fast OCP Speed
CS1 Accurate OCP Speed
Leakage Current
CURRENT SENSE 2 (CS2+, CS2−
PINS)
Current Sense Measurement
Resolution
ADC Clock Frequency
30 mV Range1
Usable Input Range
60 mV Range1
Usable Input Range
480 mV Range1
Usable Input Range
Maximum voltage differential from VS−
to AGND of ±200 mV
−0.25
Typ
10.5
Max
Unit
ms
+2.75
+2.0
+1.75
110
1.0
+0.25
% FSR
% FSR
% FSR
ppm/°C
μA
% FSR
+2.0
% FSR
μs
+2.0
80
% FSR
μs
10
6
±50
MHz
Bits
mV
−2.75
−2.0
−1.75
−2.0
82
−2.0
Does not include debounce time
(Register 0xFE30[13:11] = 00)
VS HIGH SPEED ADC
Sampling Frequency
Equivalent Resolution
Dynamic Range
FAST OVP COMPARATOR (OVP PIN)
Threshold Accuracy
Current Sense Measurement
Accuracy
Min
Register 0xFE4D[3:2] = 00, equivalent
resolution of 7 bits
VS UVP DIGITAL COMPARATOR
VS UVP Accuracy
Propagation Delay
Propagation Delay (Latency)
CURRENT SENSE 1 (CS1 PIN)
Input Voltage Range
Usable Input Voltage Range
ADC Clock Frequency
Update Rate
Test Conditions/Comments
Registers are updated at this rate,
equivalent resolution of 12 bits
Factory trimmed at 1.0 V
0% to 100% of usable input voltage range
10% to 90% of usable input voltage range
900 mV to 1.1 V
VDD = 3.3 V, VS± = 1.0 V
Factory trimmed at 1.206 V
Other thresholds (0.8 V to 1.6 V)
Register 0xFE2F[1:0] = 00
VIN
−1.2
−2.0
0
40
0
0
1
+1.5
+2.0
80
%
%
ns
1.6
1.56
V
V
MHz
ms
+1.5
+2.0
+2.5
% FSR
% FSR
% FSR
Bits
V
mV
ns
ms
μA
1.56
10.5
Registers are updated at this rate,
equivalent resolution of 12 bits
Factory trimmed at 1.0 V; tested under dc
input conditions
10% to 60% of usable input voltage range
10% to 90% of usable input voltage range
0% to 100% of usable input voltage range
−1.5
−2.0
−2.5
Register 0xFE2C[2] = 0
Register 0xFE2C[2] = 1
1.17
242
12
1.2
250
40
10.5
1.23
258
80
1.5
12
For updating registers (constant current
mode enabled or disabled)
Bits
1.56
Register 0xFE4F[1:0] = 00
Register 0xFE4F[1:0] = 01
Register 0xFE4F[1] = 10
Rev. A | Page 6 of 140
0
0
0
0
0
0
30
21
60
45
480
414
MHz
mV
mV
mV
mV
mV
mV
Data Sheet
Parameter
Temperature Coefficient
30 mV Range
60 mV Range
480 mV Range
CURRENT SENSE MEASUREMENT
ACCURACY (CS2+, CS2− PINS)
30 mV Setting
60 mV Setting
480 mV Setting
Internal Level Shifting Current
CS2 Accurate OCP Speed
COMMON-MODE VOLTAGE OFFSET
ERROR (CS2+, CS2− PINS)
30 mV Range
60 mV Range
480 mV Range
CS2 OCP FAST COMPARATORS
(CS2+, CS2− PINS)
CS2 Forward Comparator
Accuracy
Range of 0 mV to 60 mV
Range of 0 mV to 600 mV
Reverse Comparator Accuracy
Range of 0 mV to 30 mV
Range of −30 mV to 0 mV
Propagation Delay
JTD TEMPERATURE SENSE
ADC Clock Frequency
Update Rate
Reverse Sensing Enabled
Reverse Sensing Disabled
ADP1055
Symbol
Test Conditions/Comments
VDD = 3.3 V
0 mV to 19 mV
0 mV to 21 mV
0 mV to 41 mV
0 mV to 45 mV
0 mV to 374 mV
0 mV to 414 mV
Min
0 mV to 19 mV
0 mV to 21 mV
0 mV to 41 mV
0 mV to 45 mV
0 mV to 374 mV
0 mV to 414 mV
All ranges
−2.9
−3.1
−1.9
−2.1
−1.5
−1.7
Typ
Max
Unit
326
354
172
194
83
84
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
+2.9
+3.1
+1.9
+2.1
+1.5
+1.7
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
μA
ms
+1.0
+0.5
+0.25
% FSR
% FSR
% FSR
25
2.6
Maximum voltage differential from CS2−
to AGND of ±50 mV
−1.0
−0.5
−0.25
For CS2 fast OCP and peak constant
current mode
Threshold set at 0 mV
Threshold set at 15.24 mV
Threshold set at 30.48 mV
Threshold set at 45.71 mV
Threshold set at 60 mV
Threshold set at 0 mV
Threshold set at 152.4 mV
Threshold set at 304.8 mV
Threshold set at 457.1 mV
Threshold set at 600 mV
Threshold set at 0 mV
Threshold set at 7.62 mV
Threshold set at 15.24 mV
Threshold set at 22.86 mV
Threshold set at 30 mV
Threshold set at 0 mV
Threshold set at −7.62 mV
Threshold set at −15.24 mV
Threshold set at −22.86 mV
Threshold set at −30 mV
Register 0xFE2D[1:0] = 00 (diode
emulation mode)
−10.3
−10.1
−23.8
+16.7
−10.2
−10.2
−0.8
0.1
−7.1
+7.6
0.9
1.3
−11.8
−11.8
−13.8
+16.9
12.7
12.5
17.1
16.9
−9.5
+23.2
17.6
17.4
40
80
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
ns
1.56
MHz
200
130
ms
ms
For updating registers (14-bit resolution)
Rev. A | Page 7 of 140
ADP1055
Parameter
Measurement Accuracy for
External Temperature Sensor
Forward Temperature Sensor
Reverse Temperature Sensor
CTRL, SMBALRT, SYNC, GPIO1 TO
GPIO4, ISHARE PINS
Input Low Voltage
Input High Voltage
Propagation Delay
GPIOx Rise Time
GPIOx Fall Time
Leakage Current
SYNC PIN
Minimum On Pulse
Synchronization Range2
Leakage Current
BLACK BOX PROGRAMMING TIME
SDA/SCL PINS
Input Low Voltage
Input High Voltage
Output Low Voltage
Leakage Current
SERIAL BUS TIMING
Clock Operating Frequency
Bus Free Time
Start Hold Time
Start Setup Time
Stop Setup Time
SDA Setup Time
SDA Hold Time
SCL Low Timeout
SCL Low Period
SCL High Period
Clock Low Extend Time
SCL, SDA Fall Time
SCL, SDA Rise Time
EEPROM RELIABILITY
Endurance3
Data Retention4
Data Sheet
Symbol
Test Conditions/Comments
With BC847A transistor (nf = 1.00);
Register 0xFE5A[2:0] = 0x04
Error from −40°C to +25°C
Error from 25°C to 125°C
Error from 25°C to 125°C
Digital inputs/outputs
VIL
VIH
Min
Typ
−11.7
−8.9
−9.7
Max
Unit
+13.4
+14.7
+14.4
°C
°C
°C
0.8
V
V
ns
ns
ns
μA
VDD − 0.8
GPIOx configured as an output
GPIOx configured as an output
SMBALRT, SYNC, GPIO1 TO GPIO4, and
ISHARE pins
CTRL pin
Synchronization to external frequency
40
3.5
1.5
1.0
10.0
1000
50
40
−10.0
+10.0
1.0
36 × 1.2
1.2
VIL
VIH
VOL
0.8
2.1
0.4
1.0
μA
kHz
ns
% fSW
μA
ms
V
V
V
μA
See Figure 3
tBUF
tHD;STA
tSU;STA
tSU;STO
tSU;DAT
tHD;DAT
tTIMEOUT
tLOW
tHIGH
tLO;SEXT
tF
tR
Between stop and start conditions
Hold time after (repeated) start condition;
after this period, the first clock is generated
Repeated start condition setup time
For write and for readback
10
1.3
0.6
0.6
0.6
100
300
25
1.3
0.6
20
20
TJ = 85°C
TJ = 125°C
TJ = 85°C
TJ = 125°C
10,000
1000
20
15
1
100
400
35
25
300
300
kHz
μs
μs
μs
μs
ns
ns
ms
μs
μs
ms
ns
ns
Cycles
Cycles
Years
Years
Differential voltage from CS2+ to CS2−.
fSW is the switching frequency set in Register 0x33.
Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C.
4
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.
2
3
Rev. A | Page 8 of 140
Data Sheet
ADP1055
tR
tF
tHD;STA
tLOW
SCL
SDA
tHD;DAT
tHIGH
tSU;STA
tSU;DAT
tSU;STO
tBUF
P
S
S
Figure 3. Serial Bus Timing Diagram
Rev. A | Page 9 of 140
P
12004-003
tHD;STA
ADP1055
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Supply Voltage (Continuous), VDD
Digital Pins: OUTA, OUTB, OUTC,
OUTD, SR1, SR2, GPIO1, GPIO2,
GPIO3, GPIO4, SMBALRT, SYNC
VS−, AGND, DGND
VS+
JTD, JRTN, ADD
CS1, CS2+, CS2−
SDA, SCL
ISHARE
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Peak Solder Reflow Temperature
SnPb Assemblies
(10 sec to 30 sec)
RoHS-Compliant Assemblies
(20 sec to 40 sec)
ESD
Charged Device Model
Human Body Model
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Rating
4.2 V
−0.3 V to VDD + 0.3 V
Table 3. Thermal Resistance
Package Type
32-Lead LFCSP
−0.3 V to +0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
θJA
44.4
θJC
6.4
Unit
°C/W
SOLDERING
It is important to follow the correct guidelines when laying out
the PCB footprint for the ADP1055 and when soldering the
device onto the PCB. For detailed information about these
guidelines, see the AN-772 Application Note.
ESD CAUTION
240°C
260°C
500 V
2.5 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 10 of 140
Data Sheet
ADP1055
32
31
30
29
28
27
26
25
JTD
ADD
RES
JRTN
AGND
DGND
VDD
VCORE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADP1055
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
ISHARE
SMBALRT
SDA
SCL
CTRL
GPIO1
GPIO2
GPIO3
NOTES
1. NC = NO CONNECT. LEAVE THIS PIN UNCONNECTED.
2. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT
THE EXPOSED PAD ON THE UNDERSIDE OF THE PACKAGE BE
SOLDERED TO THE PCB AGND PLANE.
12004-004
SR1
SR2
OUTA
OUTB
OUTC
OUTD
SYNC
GPIO4
9
10
11
12
13
14
15
16
OVP
VS+
VS–
CS2+
CS2–
NC
VFF
CS1
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
OVP
2
VS+
3
VS−
4
CS2+
5
CS2−
6
7
NC
VFF
8
CS1
9
SR1
10
SR2
11
12
13
14
15
OUTA
OUTB
OUTC
OUTD
SYNC
16
GPIO4
17
GPIO3
Description
Overvoltage Protection. This signal is referenced to AGND and is used for redundant OVP protection. The nominal
voltage at this pin should be 1 V. If this pin is not used, connect it to AGND.
Noninverting Voltage Sense Input. This signal is referenced to VS−. The nominal input voltage at this pin is 1 V. The
resistor divider on this input must have a tolerance specification of 0.5% or better to allow for trimming. This pin is
the input to the high frequency flash ADC.
Inverting Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider on this input
must have a tolerance specification of 0.5% or better to allow for trimming. To reduce common-mode noise, connect
a 0.1 μF capacitor from VS− to AGND.
Noninverting Differential Current Sense Input. This signal is referenced to CS2−. If this pin is not used, connect it to
AGND.
Inverting Differential Current Sense Input. If this pin is not used, connect it to AGND. This pin must have a low
ohmic connection to AGND thought the sense resistor.
No Connect. Leave this pin unconnected.
Voltage Feedforward. Two optional functions can be implemented using this pin: feedforward and input voltage
loss detection. This pin is typically connected upstream of the output inductor through a resistor divider network
in an isolated converter. The nominal voltage at this pin should be 1 V. This signal is referenced to AGND. If this pin
is not used, connect it to AGND.
Primary Side Current Sense Input. This pin is connected to the primary side current sensing ADC and to the fast
OCP comparator. This signal is referenced to PGND. The resistors on this input must have a tolerance specification
of 0.5% or better to allow for trimming. If this pin is not used, connect it to AGND.
Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled
when not in use. This signal is referenced to AGND.
Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled
when not in use. This signal is referenced to AGND.
PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.
PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.
PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.
PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referenced to AGND.
Synchronization Input Signal. This pin is used as a reference for the internal PWM frequency. This signal is
referenced to AGND and must have a nominal duty cycle of 50%. If this pin is not used, connect it to AGND and
program Register 0xFE55[6] = 1.
Programmable General-Purpose Input/Output. If this pin is not used, connect it to AGND. This pin can also be
configured as an active snubber PWM output.
Programmable General-Purpose Input/Output. If this pin is not used, connect it to AGND. This pin can also be
configured as an active snubber PWM output.
Rev. A | Page 11 of 140
ADP1055
Pin No.
18
19
20
Mnemonic
GPIO2
GPIO1
CTRL
21
22
23
SCL
SDA
SMBALRT
24
25
ISHARE
VCORE
26
VDD
27
28
29
30
DGND
AGND
JRTN
RES
31
32
ADD
JTD
EP
Data Sheet
Description
Programmable General-Purpose Input/Output. If this pin is not used, connect it to AGND.
Programmable General-Purpose Input/Output. If this pin is not used, connect it to AGND.
Power Supply On Input. This signal is referenced to AGND. This pin is the hardware PSON control signal. It is
recommended that a 1 nF capacitor be connected from the CTRL pin to AGND for decoupling. If this pin is not
used, connect it to AGND.
I2C/PMBus Serial Clock Input and Output (Open Drain). This signal is referenced to AGND.
I2C/PMBus Serial Data Input and Output (Open Drain). This signal is referenced to AGND.
Power-Good Output (Open Drain). This signal is referenced to AGND. This pin is also used as the PMBus ALERT
signal.
Digital Current Sharing Input and Output (Open Drain). This signal is referenced to AGND.
VDD for the Digital Core. Connect a decoupling capacitor of at least 330 nF (1 μF maximum) from this pin to DGND
as close to the IC as possible to minimize the PCB trace length. Do not use the VCORE pin as a reference or load it
in any way.
Positive Supply Input. This signal is referenced to AGND. Connect a 4.7 μF decoupling capacitor from this pin to
AGND as close to the IC as possible to minimize the PCB trace length.
Digital Ground. This pin is the ground reference for the digital circuitry. Star connect to AGND.
IC Analog Ground.
Temperature Sensor Return. If this pin is not used, connect it to AGND.
Resistor Input. This pin sets the internal reference for the internal PLL frequency. Connect a 10 kΩ resistor (±0.1%)
from RES to AGND. Do not load this pin with any capacitance. This signal is referenced to AGND.
I2C/PMBus Address Select Input. Connect a resistor from ADD to AGND. This signal is referenced to AGND.
Thermal Sensor Input. A PN junction sensor is connected from this pin to the JRTN pin. If this pin is not used,
connect it to JRTN.
Exposed Pad. For increased reliability of the solder joints and maximum thermal capability, it is recommended
that the exposed pad on the underside of the package be soldered to the PCB AGND plane.
Rev. A | Page 12 of 140
Data Sheet
ADP1055
TYPICAL PERFORMANCE CHARACTERISTICS
4
1.5
1.0
MAX
0.5
MEAN
0
MIN
–0.5
–1.0
–1.5
MIN SPEC
–2.0
0
50
100
150
TEMPERATURE (°C)
MAX SPEC
3
2
MAX
1
MEAN
0
–1
MIN
–2
–3
MIN SPEC
–4
–50
MAX SPEC
CS2 60mV ADC ACCURACY (%FSR)
2.0
1.5
1.0
MAX
0.5
MEAN
0
MIN
–0.5
–1.0
–1.5
MIN SPEC
0
1.5
1.0
MAX
0.5
MEAN
0
–0.5
MIN
–1.0
–1.5
–2.0
50
100
150
TEMPERATURE (°C)
–2.5
–50
MIN SPEC
0
2.5
2.0
CS2 480mV ADC ACCURACY (%FSR)
1.0
MAX
0.5
MEAN
0
MIN
–0.5
–1.0
–1.5
0
50
TEMPERATURE (°C)
100
150
12004-104
MIN SPEC
–2.0
150
MAX SPEC
MAX SPEC
1.5
100
Figure 9. CS2 60 mV ADC Accuracy vs. Temperature
(from 10% to 90% of FSR)
Figure 6. CS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
2.0
50
TEMPERATURE (°C)
12004-103
–2.0
12004-101
CS1 ADC ACCURACY (%FSR)
150
2.5
MAX SPEC
2.0
VFF ADC ACCURACY (%FSR)
100
Figure 8. CS2 30 mV ADC Accuracy vs. Temperature
(from 10% to 90% of FSR)
2.5
–2.5
–50
50
TEMPERATURE (°C)
Figure 5. VS ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
–2.5
–50
0
Figure 7. VFF ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
Rev. A | Page 13 of 140
1.5
1.0
MAX
0.5
MEAN
0
MIN
–0.5
–1.0
–1.5
–2.0
–50
MIN SPEC
0
50
100
TEMPERATURE (°C)
Figure 10. CS2 480 mV ADC Accuracy vs. Temperature
(from 10% to 90% of FSR)
150
12004-105
–2.5
–50
12004-100
VS ADC ACCURACY (%FSR)
2.0
CS2 30mV ADC ACCURACY (%FSR)
MAX SPEC
12004-102
2.5
ADP1055
Data Sheet
70
60
1.225
MAX SPEC
50
ACTUAL THRESHOLD (mV)
1.220
1.215
MAX
1.210
MEAN
1.205
MIN
1.200
1.195
40
30
20
0
–10
MIN SPEC
1.190
0
50
100
150
TEMPERATURE (°C)
–30
Figure 11. OVP Fast Comparator at 1.206 V vs. Temperature
0
ACTUAL THRESHOLD (mV)
1.22
1.21
MAX
1.20
MEAN
MIN
1.19
1.18
500
400
300
100
0
50
100
150
–100
0
100
200
300
400
500
600
PROGRAMMED THRESHOLD (mV)
12004-110
0
MAX SPEC
MEAN
MIN SPEC
200
MIN SPEC
1.17
12004-107
CS1 OCP FAST COMPARATOR AT 1.2V (V)
60
600
TEMPERATURE (°C)
Figure 15. CS2 Forward Comparator Accuracy, 0 mV to 600 mV Range
Figure 12. CS1 OCP Fast Comparator at 1.2 V vs. Temperature
15
260
MAX SPEC
258
10
MAX SPEC
MEAN
MIN SPEC
5
ACTUAL THRESHOLD (mV)
256
254
252
MAX
250
MEAN
248
MIN
246
0
–5
–10
–15
–20
–25
244
MIN SPEC
242
0
–30
50
100
150
TEMPERATURE (°C)
12004-108
CS1 OCP FAST COMPARATOR AT 250mV (mV)
50
700
MAX SPEC
1.23
240
–50
20
30
40
PROGRAMMED THRESHOLD (mV)
Figure 14. CS2 Forward Comparator Accuracy, 0 mV to 60 mV Range
1.24
1.16
–50
10
12004-109
–20
Figure 13. CS1 OCP Fast Comparator at 250 mV vs. Temperature
–35
0
–5
–10
–15
–20
–25
–30
PROGRAMMED THRESHOLD (mV)
Figure 16. CS2 Reverse Comparator, 0 mV to −30 mV Range
Rev. A | Page 14 of 140
12004-111
1.185
–50
MAX SPEC
MEAN
MIN SPEC
10
12004-106
OVP FAST COMPARATOR AT 1.206V (V)
1.230
Data Sheet
ADP1055
ACTUAL THRESHOLD (mV)
30
25
MAX SPEC
MEAN
MIN SPEC
20
15
10
5
0
–10
0
5
10
15
20
25
30
PROGRAMMED THRESHOLD (mV)
12004-112
–5
20
MAX SPEC
15
10
MAX
5
MEAN
0
MIN
–5
–10
MIN SPEC
–15
–50
0
50
100
150
TEMPERATURE (°C)
MAX SPEC
15
MAX
10
5
MEAN
0
–5
MIN
MIN SPEC
–10
–15
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 19. Reverse Temperature Sensor Error vs. Temperature
12004-113
FORWARD TEMPERATURE SENSOR ERROR (°C)
Figure 17. CS2 Reverse Comparator, 0 mV to 30 mV Range
20
Figure 18. Forward Temperature Sensor Error vs. Temperature
Rev. A | Page 15 of 140
12004-114
REVERSE TEMPERATURE SENSOR ERROR (°C)
35
ADP1055
Data Sheet
CONTROLLER ARCHITECTURE
The ADP1055 is an application specific digital controller based
on finite state machine (FSM) architecture. The ADP1055 supports
a subset of the PMBus Revision 1.2 standard and also has extended
manufacturer specific commands to provide a feature rich digital
power product.
Dedicated ADCs and comparators constitute the analog front
end of the controller, feeding information to the digital core. The
information is processed and used to generate the programmable
PWM signals and to take action for various features such as light
load or overvoltage/overcurrent protection.
The ADP1055 has six PWM outputs: OUTA to OUTD for the
primary side switches and SR1 and SR2 for the secondary side
synchronous rectifiers. The ADP1055 allows individual
programming of the PWM outputs to form the timing of the
power switches for any power topology, such as full bridge, full
bridge phase shifted, current doubler, or active clamp.
Primary side information (current or voltage) is sensed and
processed via the CS1 and VFF pins, whereas secondary side
information is obtained via the CS2±, ISHARE, VS±, and OVP
pins. A dedicated temperature sensor uses the JTD and JRTN
pins. The input voltage is measured using the VFF pin and is
used for line voltage feedforward. Extensive fault protection
schemes are provided, and the controller also has a black box to
record the state of the device (all sensor information including
voltages, currents, temperatures, and flags) upon shutdown.
I2C/PMBus communication is facilitated by the SDA, SCL, and
SMBALRT pins. Four GPIO pins can be used as flag output
signals or as an interrupt service routine (ISR) to trigger a
PMBus fault action. The CTRL pin is used as described in the
PMBus specification.
Detailed descriptions of all ADP1055 features are provided in
the Theory of Operation section.
Rev. A | Page 16 of 140
Data Sheet
ADP1055
START-UP AND POWER-DOWN SEQUENCING
VDD AND VCORE PINS
The proper amount of decoupling capacitance must be placed
between the VDD and AGND pins, as close as possible to the
device to minimize the trace length. It is recommended that the
VCORE pin not be loaded in any way.
POWER-UP AND POWER-DOWN COMMANDS
The outputs start switching, depending on the configuration of
the OPERATION command (Register 0x01) and the ON_OFF_
CONFIG command (Register 0x02).
If the ADP1055 is programmed to be always on (Register
0x02[4] = 0), the device begins the soft start ramp. Figure 21
shows the entire soft start process.
12004-015
12004-016
The PMBus commands OPERATION (Register 0x01) and
ON_OFF_CONFIG (Register 0x02) control the power-up and
power-down behavior of the ADP1055.
Figure 21. Example of Soft Start and Soft Stop Settings in the GUI
Figure 20. OPERATION (Register 0x01) and ON_OFF_CONFIG
(Register 0x02)
The soft start proceeds as follows.
POWER SEQUENCING
1.
Power sequencing is controlled using Register 0x60 through
Register 0x66. The delays for the turn-on command (Register
0x60, TON_DELAY) and the turn-off command (Register 0x64,
TOFF_DELAY) can each be programmed from 0 ms to 1024 ms
in steps of 1 ms.
2.
The soft start ramp-up time (Register 0x61, TON_RISE) and
the ramp-down time (Register 0x65, TOFF_FALL) can be
programmed from 0 ms to 100 ms in steps of 1 ms.
All values are rounded to the nearest available value. If a value is
programmed outside the allowed range, it is forced to the nearest
legal value.
Upon power-up, the ADP1055 waits for the programmed
TON_DELAY (Register 0x60) and ramps to the regulation
voltage according to the time programmed in TON_RISE
(Register 0x61).
The soft start begins to ramp up the internal digital
reference. The total duration of the soft start ramp is
programmable using the TON_RISE command. The
TON_MAX command specifies the maximum on time
before which the output voltage must exceed the
VOUT_UV_FAULT_LIMIT (Register 0x44). If the
VOUT_UV_FAULT_LIMIT is set to 0, the TON_MAX
value is ignored.
When VDD is applied to the device, a certain time elapses
before the ADP1055 can regulate the power supply.
If the soft start from precharge function is enabled
(Register 0xFE51[0] = 1), the soft start ramp starts from the
current value of the output voltage sensed on VS± and,
therefore, the soft start ramp time is reduced proportionally.
1.
SOFT STOP ROUTINE
POWER-UP AND SOFT START ROUTINE
2.
3.
4.
When VDD is above UVLO and VCORE reaches above
VCORE POR through an internal regulator, the ADP1055
downloads the user settings from Page 1 of the EEPROM
into the internal registers.
After the EEPROM download, the ADP1055 determines its
address, programmed by the ADD pin and the I2C slave
base address (Register 0xD0, SLV_ADDR_SELECT).
The ADP1055 waits for an idle time, after which the device
is ready for normal operation. If the black box must erase a
page to precondition the EEPROM for storing, the idle
time is extended by ~35 ms (see the Black Box Timing
section).
If the ADP1055 is programmed to power up at this time
(OPERATION is enabled), the soft start ramp begins.
Otherwise, the ADP1055 waits for the OPERATION
command.
The soft stop process occurs in a manner similar to the soft start
process, using the TOFF_DELAY, TOFF_MAX, and TOFF_FALL
commands. These commands are the counterparts of the
TON_DELAY, TON_MAX, and TON_RISE commands used
for soft start. For more information about soft stop, see the Soft
Stop section.
Rev. A | Page 17 of 140
ADP1055
Data Sheet
VDD/VCORE OVLO
The ADP1055 has built-in overvoltage protection (OVP) on its
supply rails. When the VDD or VCORE voltage rises above the
OVLO threshold, the response can be programmed using
Register 0xFE4D. It is recommended that when a VDD/VCORE
OVP fault occurs, the response be set to download the EEPROM
before restarting the ADP1055. All features related to the OVLO
function—such as debounce, fault ignore, and download EEPROM
upon receiving a fault condition—are programmable using
Register 0xFE4D[7:4].
VDD overvoltage is ignored when the device is downloading
information from the EEPROM, even if the overvoltage occurs
during the initial power-up or due to the setting of Register
0xFE4D[6]. VDD overvoltage is recognized as a fault only after
the EEPROM download is complete. The ADP1055 has a 4 ms
idle time after an EEPROM download.
If the VDD overvoltage occurs during the ramp-up of VDD and
the ADP1055 has not initiated the EEPROM download, the
device responds according to the default setting of Bit 7 in
Register 0xFE4D, which is to ignore VDD OV.
Rev. A | Page 18 of 140
Data Sheet
ADP1055
CONTROL LOOP AND PWM OPERATION
VOLTAGE SENSE, FEEDBACK, AND CONTROL LOOP
The VS± pins are used for the monitoring and protection of the
remote load voltage. The differential VS± input pins are the main
feedback sense point for the power supply control loop. The VS±
sense point on the power rail requires an external resistor divider
to bring the nominal common-mode signal to 1 V at the VS± pins.
This resistor divider is programmed into VOUT_SCALE_LOOP
and VOUT_SCALE_MONITOR accordingly. The resistor divider
is necessary because the input range is 0 V to 1.6 V. The
divided-down signal is internally fed into a high frequency (HF)
ADC. The HF ADC is also the high frequency feedback loop for
the power supply.
OUTPUT VOLTAGE SENSE
The output voltage is fed back to the VS± pins, where it is compared with a reference set by a 12-bit DAC (see Figure 22). The
difference is then fed into the flash ADC; in this configuration,
the flash ADC does not see the fraction of the output voltage set
by the resistor divider, but instead sees only the error voltage. The
error voltage is then fed into the digital filter, which decides the
duty cycle command for the next switching period. The number
of samples taken by the flash ADC can be configured in Register
0xFE67[7:4] (see Table 215). The recommended configuration
of this register is automatically configured using the GUI.
VOUT
format and can be used to calculate all stability criteria for the
power supply.
From the sensed voltage to the duty cycle, the transfer function
of the filter in z-domain is as follows:


1  B z 1 




D
C
1
256



H(z)  
ADD_PZ



A 1 
 LFG (1 z 1) HFG 

z
1





256




where:
A = filter pole register value (in decimal).
B = filter zero register value (in decimal).
C = high frequency gain register value (in decimal).
D = low frequency gain register value (in decimal).
LFG = 5.968 × m × 106/fSW.
HFG = 3.73× m × 105/fSW.
m = 1 when 48.8 kHz ≤ fSW < 97.7 kHz.
m = 2 when 97.7 kHz ≤ fSW < 195.3 kHz.
m = 4 when 195.3 kHz ≤ fSW < 390.6 kHz.
m = 8 when 390.6 kHz ≤ fSW.
ADD_PZ is an additional pole or additional zero that can be
added to the compensator.
The additional zero takes this form:
ADP1055
1
VS+
REF
DAC
+
50mV HF
ADC
–
DPWM
The additional pole takes this form:
1
E
1 
 z 1 

256


TRIM
DAC
where E is the value (in decimal) of the additional pole zero
frequency gain register (Register 0xFE60 and Register 0xFE61).
LF
ADC
VS ADC (12 BITS)
VOUT_OV_LIMIT
VOUT_UV_LIMIT
12004-017
LPF
VS–
E
 z 1
256
To transfer the z-domain value to the s-domain, plug the following bilinear transformation equation into the H(z) equation:
z(s) 
Figure 22. Output Voltage Sense and Feedback
The output voltage is also sampled using a low frequency ADC.
The output voltage is fed to a low-pass filter that is used to set the
output of a trim DAC; the trim DAC finely adjusts the output
voltage as part of the autocorrection loop (see the Voltage Loop
Autocorrection section).
DIGITAL FILTER
The loop response of the power supply can be changed using the
internal programmable digital filter. A Type 3 filter architecture
has been implemented. To tailor the loop response to the specific
application, the low frequency gain, zero location, pole location,
and high frequency gain can all be set individually (see the Digital
Filter Programming Registers section). It is recommended that
the Analog Devices, Inc., software GUI be used to program the
filter. The software GUI displays the filter response in Bode plot
2 f SW  s
2 f SW  s
where fSW is the switching frequency.
The digital filter introduces an extra phase delay element into
the control loop. The digital filter circuit sends the duty cycle
information to the PWM circuit at the beginning of each switching cycle (unlike an analog controller, which makes decisions on
the duty cycle information continuously). Therefore, the extra
phase delay for phase margin, Φ, introduced by the filter block is
Φ = 360 × (fC/fSW)
where:
fC is the crossover frequency.
fSW is the switching frequency.
At one-tenth the switching frequency, the phase delay is 36°. For
double update rate, the phase delay is reduced to 18°. The GUI
Rev. A | Page 19 of 140
ADP1055
Data Sheet
incorporates this phase delay into its calculations. Note that the
GUI does not account for other delays such as gate driver and
propagation delays.
RAMP TIME
0x5F
PS ON
DIGITAL FILTER PROGRAMMING REGISTERS
Three sets of registers allow three different filters to be
programmed.


Normal mode filter (used for CCM or heavy load and
configured in Register 0xFE01 to Register 0xFE04)
Light load mode filter (configured in Register 0xFE05 to
Register 0xFE08)
Soft start filter (configured in Register 0xFE09 to
Register 0xFE0C)
The software GUI allows the user to program the light load
mode filter in the same manner as the normal mode filter. It is
recommended that the GUI be used for this purpose.
DIGITAL COMPENSATION FILTERS DURING SOFT
START
The ADP1055 has a dedicated soft start filter (SSF) that can be
used to fine-tune and optimize the dynamic response during
the output voltage ramp-up.
During soft start, the ADP1055 determines the load condition
and after the voltage reaches 12.5% of the nominal output
voltage value, it determines the current load condition and
switches filters accordingly to the light load mode threshold
(Register 0xFE5F[3:1]). If the load current is below the light
load mode threshold, the ADP1055 switches to the light load
mode filter (LLF). If the load current is above the light load
mode threshold, the normal mode filter is used until the end of
the soft start ramp, even if the device subsequently enters light
load mode based on a change to the load current.
Other configurations can be programmed to use different filters
during soft start, as follows:


Force soft start filter (Register 0xFE51[2]). This option forces
the ADP1055 to use the soft start filter. In some cases, this
option allows better fine-tuning of the ramp-up voltage.
Disable light load mode during soft start (Register 0xFE51[1]).
This option prevents the use of the light load mode filter
during soft start, even if the light load condition is met.
The light load mode filter is available for use after the end
of the soft start ramp.
Figure 23 shows the use of filters during soft start.
LLF
NMF/SSF
NMF/SSF
NMF/SSF
ZONE 1
ZONE 2
LLM/NMF
BASED ON
LOAD
LLM/NMF
BASED ON
LOAD
ZONE 3
12004-018

12.5% REF
VOUT
Figure 23. Digital Filters During Soft Start (Low Temperature Filter Not Shown)
As shown in Figure 23, in Zone 1, the ADP1055 starts with the
normal mode filter or the soft start filter. Zone 2 begins when the
voltage reaches 12.5% of the nominal output voltage value. At this
point, the ADP1055 checks whether the system is in light load
mode, and the choice of filter is based on the following criteria:


If the system is in light load mode, the ADP1055 switches
to the light load mode filter (unless the option to disable
the LLM filter was previously selected).
If the system is not in light load mode, the ADP1055
continues to use the filter used in Zone 1: the normal mode
filter or the soft start filter.
The ADP1055 changes to the LLM filter if the load changes
during Zone 2 (voltage rises from 12.5% to 100% of the soft
start ramp. The filter does not revert to LLM if the load drops
until after the end of soft start.
In Zone 3 the filter changes to the NMF or LLM filter, depending
on the load.
FILTER TRANSITION
To avoid output voltage glitches and to provide a seamless
transition from one filter to another, the ADP1055 supports
programmable filter transitions. This feature allows a gradual
transition from one filter to another. Filter transitions are
programmed using Register 0xFE4A[2:0]. When the ADP1055
switches filters, the switching action is changed in 32 steps. The
step size can be programmed over several cycles (1tSW to 32tSW)
to avoid glitches in the output. The filter used depends on the
state of the synchronous rectifiers and whether the system is in
continuous conduction mode (CCM) or discontinuous conduction
mode (DCM) (see Table 5).
Table 5. State of Synchronous Rectifiers and Filter Used
Load
Medium to heavy load
Below LLM threshold
State of SRx Outputs
Regular Mode
Diode Emulation Mode
SRs in CCM
SRs in CCM
SRs in LLM
Diode emulation SRs
Deep LLM
SRs are off
SRs are off
Filter Used
Normal mode filter (Register 0xFE01 to Register 0xFE04).
LLM filter (Register 0xFE05 to Register 0xFE08.) When diode
emulation mode is in use, the LLM filter is activated after the LLM
threshold is crossed.
LLM filter (Register 0xFE05 to Register 0xFE08).
Rev. A | Page 20 of 140
Data Sheet
ADP1055
Go and Auto Go Command
PWM AND SYNCHRONOUS RECTIFIER OUTPUTS
(OUTA, OUTB, OUTC, OUTD, SR1, SR2)
The PWM outputs (OUTA to OUTD) and the SR outputs (SR1
and SR2) are all synchronized with each other. Therefore, when
reprogramming more than one of these outputs, it is important
to first update all the registers and then latch the information
into the ADP1055 at the same time. This simultaneous updating
of the PWM outputs is facilitated by the GO command
(Register 0xFE00). The GO command acts as a gate to apply all
functions related to the commands at the same time.
The PWM and SR outputs are used for control of the primary
side drivers and the synchronous rectifier drivers. These outputs
can be used for several control topologies, such as full-bridge,
phase-shifted ZVS configurations and interleaved, two switch
forward converter configurations. Delays between the rising and
falling edges can be individually programmed (see Figure 24).
t2
The GO command gates the following functions:
PWM1 (OUTA)
t1






t4
PWM2 (OUTB)
t3
t5
PWM3 (OUTC)
t6
t8
PWM4 (OUTD)
t7
SYNC RECT 1 (SR1)
t10
During reprogramming, the outputs are temporarily disabled.
It is recommended that the PWM outputs be disabled when
not in use.
The PMBus allows the user to change the voltage setting and
the switching frequency on-the-fly. The auto go command
(Register 0xFE5B) is an added level of protection that restricts the
user from making a change to certain commands (see Table 203).
t9
t12
SYNC RECT 2 (SR2)
tPERIOD
For more information about the various programmable
switching frequencies and PWM timings, see the Switching
Frequency Programming section.
12004-020
t11
tPERIOD
Figure 24. PWM Timing Diagram
SYNCHRONOUS RECTIFICATION
Take special care to avoid shoot-through and cross-conduction.
It is recommended that the software GUI be used to program
these outputs. Figure 25 shows an example configuration to
drive a full-bridge topology with synchronous rectification.
SR1 and SR2 are recommended for use as the PWM control
signals when using synchronous rectification. These PWM
signals can be configured much like the other PWM outputs.
VIN
OUTA
OUTC
OUTB
OUTD
SR1
SR2
DRIVER
SR1
ISOLATOR
SR2
OUTA
OUTB
OUTC
OUTD
12004-019
DRIVER
Frequency synchronization
Line voltage feedforward
Double update rate, volt-second balance
Digital filter settings
Frequency and PWM settings
Voltage reference change
Figure 25. PWM Pin Assignment for Full-Bridge, Phase-Shifted Topology
with Synchronous Rectification
Rev. A | Page 21 of 140
ADP1055
Data Sheet
The GUI provided with the ADP1055 is recommended for
programming this feature (see Figure 27).
MODULATION LIMIT
12004-022
The modulation limit register (Register 0xFE53) can be
programmed to apply a maximum duty cycle modulation limit
to any PWM signal, thus acting as a clamp for the maximum
modulation range of any PWM output. When modulation is
enabled, the maximum modulation limit is applied to all PWM
outputs collectively. As shown in Figure 26, this limit is the
maximum time variation for the modulated edges from the
default timing, following the configured modulation direction.
Figure 27. Setting Modulation Limits (Modulation Range Shown by Arrows)
SWITCHING FREQUENCY PROGRAMMING
The FREQUENCY_SWITCH command (Register 0x33) sets
the switching frequency of the ADP1055 in kilohertz. This
command has two data bytes formatted in the linear data format;
the programmable frequency ranges from 48 kHz to 1000 kHz.
tMODULATION_LIMIT
OUTx
12004-021
tRX
tFX
Figure 26. Modulation Limit Settings
There is no minimum duty cycle limit setting. Therefore, the
user must set the rising edges and falling edges based on the
case with the least modulation to enter pulse skipping mode
under very light load conditions.
The ADP1055 does not support every possible frequency due to
the infinite combinations of exponent and mantissa values that
can be programmed. If a programmed frequency does not exactly
match a supported value, it is rounded up to the nearest available
frequency. It is recommended that the READ_FREQUENCY
command (Register 0x95) be used to determine the exact value
of the switching frequency. Table 244 lists the supported
frequencies.
Each LSB in Register 0xFE53[6:0] corresponds to a unit of a
base time step size. The base time step size (20 ns, 40 ns, 80 ns,
or 160 ns) depends on the switching frequency; therefore, the
modulation limit is based on the value in Register 0xFE53[6:0]
multiplied by the corresponding base time step size. The
modulated edges are prevented from extending beyond one
switching cycle, but the maximum duty cycle is 100% (the
minimum pulse width is 5 ns).
Rev. A | Page 22 of 140
Data Sheet
ADP1055
ADCs AND TELEMETRY
Two kinds of ADCs are used in the ADP1055:
CS1 ADC for Primary Side Current

The CS1 pin is typically used for the monitoring and protection
of the primary side current. The primary side current is sensed
using a current transformer (CT). The input signal at the CS1 pin
is fed into the CS1 ADC for current monitoring. Figure 29 shows
the typical configuration for the current sense. The READ_IIN
command reports the average input current; this reading is
updated every 10.5 ms.
Σ-Δ ADCs have a resolution of one bit and operate differently
from traditional flash ADCs. The equivalent resolution obtainable depends on how long the output bit stream of the Σ-Δ ADC
is sampled.
OUTA
OUTC
OUTB
OUTD
NYQUIST ADC
NOISE
1V
I = 10A
1kΩ
ADC
12 BITS
I = 100mA
VREF
Σ-∆ ADC
NOISE
FAST
OCP
1:100
12004-027
FREQUENCY
10Ω
CS1
12004-023
MAGNITUDE
Σ-Δ ADCs also differ from Nyquist rate ADCs in that the quantization noise is not uniform across the frequency spectrum. At
lower frequencies, the noise is lower, and at higher frequencies,
the noise is higher (see Figure 28).
VIN
Figure 29. Current Sense 1 (CS1) Operation
Figure 28. Noise Performance for Nyquist Rate and Σ-Δ ADCs
The low frequency ADC runs at approximately 1.56 MHz. For a
specified bandwidth, the equivalent resolution can be calculated
as follows:
ln(1.56 MHz/BW)/ln2 = N bits
For example, at a bandwidth of 95 Hz, the equivalent
resolution/noise is
ln(1.56 MHz/95)/ln2 = 14 bits
At a bandwidth of 1.5 kHz, the equivalent resolution/noise is
ln(1.56 MHz/1.5 kHz)/ln2 = 10 bits
The ADC output information is available in the value registers
(Register 0xFE96 to Register 0xFEA3) or through the PMBus
READ_x commands, where x = VOUT, IOUT, and so on.
CS2 ADC for Secondary Side Current
The CS2+ and CS2− pins are differential inputs used for the
monitoring and protection of the secondary side current. The
ADP1055 supports differential sensing using low-side current
sensing with two ranges for the ADC: 30 mV and 60 mV.
The low input range is used to operate in level shifting mode,
when the CS2 terminals are connected directly to the shunt
resistor (see Figure 30). In this mode, a pair of internal resistors
and current sources are used to perform the necessary level
shifting. In this mode, only low-side current sensing is possible,
and the ADC range is programmable to 30 mV or 60 mV.
ILOAD
AGND
CS2 RANGES
RANGE1 = 0mV TO 30mV
RANGE2 = 0mV TO 60mV
ADCs FOR CURRENT SENSING
The ADP1055 has two current sense inputs: CS1 and CS2±.
These inputs sense, protect, and control the primary input current
and the secondary output current information. The CS1 and
CS2± inputs can be calibrated to reduce errors due to external
components for accurate telemetry.
CS2–
CS2+
CS2 FAST OCP
0mV TO 60mV/6 BITS
(STEP SIZE 0.952mV)
CS2 ADC
IOUT_OC_LIMIT
IOUT_UC_LIMIT
CS2 IREV LIMIT
0mV TO –30mV
(STEP SIZE 0.4762mV)
ADP1055
Figure 30. Differential Low-Side Sensing
Rev. A | Page 23 of 140
12004-025

Low frequency (LF) Σ-Δ ADCs that runs at 1.56 MHz for
accurate measurement and telemetry
High frequency (HF) flash ADCs for the feedback and
control loop
ADP1055
Data Sheet
An additional range of 480 mV (single-ended input only) can
be used for high-side sensing or simply as an input with a
higher range (see Figure 31). The high input range is used for
operation in single-ended mode, where external circuitry must
be provided for level shifting of the current signal.
ILOAD
The input voltage signal can be sensed at the secondary winding
of the isolation transformer before the output inductor and must
be filtered by an RCD network to eliminate the voltage spike at
the switch node (see Figure 32).
CS2+ RANGE: 0mV TO 480mV
In nonisolated topologies, the VFF ADC is connected directly
to the primary voltage via a resistive divider with some filtering
to eliminate voltage spikes on the bulk capacitor when the power
switch is turned on or off. The READ_VIN command reports
the average input voltage; this reading is updated every 10.5 ms.
CS2+
VS ADC for Output Voltage
VOUT
RSNS
CS2–
AGND
The VS± pins of the ADP1055 are used for the monitoring,
control, and protection of the power supply output. Typically,
the output voltage is divided down using a resistive divider such
that at the rated output, there is 1.0 V on the VS± pins. The
READ_VOUT command reports the average output voltage;
this reading is updated every 10.5 ms.
CS2 FAST OCP
0mV TO 600mV/7 BITS
(STEP SIZE 9.52mV)
CS2 ADC
IOUT_OC_LIMIT
IOUT_UC_LIMIT
12004-024
CS2 IREV LIMIT
0mV TO –30mV
(STEP SIZE 0.4762mV)
ADP1055
ADCs FOR TEMPERATURE SENSING
For information about the temperature sensing ADCs, see the
Temperature Sensing section.
Figure 31. Single-Ended High-Side Sensing
The READ_IOUT command reports the average output current;
this reading is updated every 2.6 ms.
ADCs FOR VOLTAGE SENSING
VFF ADC for Input Voltage
The VFF pin is typically used for the monitoring and protection
of the primary side voltage. Figure 32 shows a typical configuration
for the feedforward circuit.
VFF
ADC
R
0V TO 1.6V
R1
Vx
R2
VFF
FEEDFORWARD
ADC
1/x
0.6V TO 1.6V
DIGITAL
FILTER
DPWM
ENGINE
12004-026
FROM
SECONDARY
WINDING
Figure 32. Feedforward Configuration
Rev. A | Page 24 of 140
Data Sheet
ADP1055
THEORY OF OPERATION
ACCURATE PRIMARY OVERCURRENT PROTECTION
The CS1 ADC is used to measure the average value of the
primary current. The 12 MSBs of the reading (CS1_VALUE,
Register 0xFE98[13:4]) are converted into PMBus format and
compared to the threshold set using the PMBus command
IIN_OC_FAULT_LIMIT (Register 0x5B) to make a fault
decision. The fault response is set by the IIN_OC_FAULT_
RESPONSE command (Register 0x5C).
PRIMARY FAST OVERCURRENT PROTECTION
The input signal on the CS1 pin is also fed into a comparator
for pulse-by-pulse OCP protection. The fast OCP comparator
is used to limit the peak primary current within each switching
cycle. Two thresholds—the 250 mV or 1.2 V threshold—are
programmable using Register 0xFE2C[2].
When the CS1 OCP threshold is crossed, the PWM outputs
(OUTA to OUTD) are immediately terminated for the remainder
of the switching cycle. For the full-bridge topology, where the
switching period is divided into two halves, a CS1 OCP event
during one half does not terminate the PWM outputs for the
second half.
The CS1 OCP comparator provides programmable blanking
and debounce to prevent false triggering; these features are
programmable using Register 0xFE4E and Register 0xFE2C.
The comparator also features a programmable timeout condition
(set in Register 0xFE4E[2:0]), which specifies that the CS1 fast
OCP condition must be present for a specified number of
consecutive switching cycles before the IIN_OC_FAST_FAULT
flag is set.
The CS1 fast OCP fault can also be set using the GPIO1
general-purpose input/output pin.
MATCHED CYCLE-BY-CYCLE CURRENT LIMIT (OCP
EQUALIZATION)
For a half-bridge converter, the cycle-by-cycle limit feature
cannot guarantee an equal duty cycle between the two half
cycles of the switching period. The imbalances of each half cycle
can cause the center point voltage of the capacitive divider to
drift from VIN/2 (half the input voltage) toward either ground or
the input voltage. This drift, in turn, can lead to output voltage
regulation failure, transformer saturation, and the doubling of
voltage stress on the synchronous rectifiers.
To avoid these problems, the ADP1055 implements a matched
cycle-by-cycle limit. This feature produces a PWM pulse width
in the second half cycle that is of equal duration as the preceding
pulse when a CS1 fast OCP event occurs (IIN_OC_FAST_
FAULT). In other words, when a cycle-by-cycle limit is triggered,
the ADP1055 forces the duty cycle in the subsequent half cycle
to be exactly the same as that of the previous half cycle.
However, if the CS1 cycle-by-cycle current limit always has the
highest priority to terminate the PWM outputs meaning that if
a cycle-by-cycle fault occurs during the period where the duty
cycle is being equalized, the cycle-by-cycle current fault takes
priority. The CS1 OCP duty cycle equalization feature (Register
0xFE57[6]) can be enabled for all topology configurations. The
edge selection is the same as for the volt-second balance feature.
LOW TEMPERATURE FILTER
During the soft start process, the soft start filter can be used in
combination with the normal mode filter and the light load mode
filter. The soft start filter can be configured as a low temperature
filter. Using Register 0xFE62[1:0], the low temperature filter is
activated on one of three selectable inputs: the external forward
temperature reading, the external reverse temperature reading,
or the rising edge of GPIO2.
The low temperature pole is activated at a temperature of 10°C;
subsequent thresholds are at 6°C, 2°C, and so on, down to −14°C
(Register 0xFE62[6:4]). The temperature hysteresis is programmed
in steps of 5°C in Register 0xFE62[3:2]. The change of filters
from one to another always takes place after a 2 sec time hysteresis
plus any other filter transition speed. It is recommended that
the ADP1055 GUI be used to program this feature. Table 6
summarizes the use of the filters for low and high temperatures.
Table 6. Filter Options for Low and High Temperatures
Load Condition
Light load
Heavy load with low
temperature, filter
disabled
Heavy load with low
temperature, filter
enabled
Low
Temperature
Light load filter
SSF/NMF with
ADD_PZ
High
Temperature
Light load filter
SSF/NMF with
ADD_PZ
SSF with
ADD_PZ
SSF/NMF with
ADD_PZ
VOLTAGE LOOP AUTOCORRECTION
Output voltage sampling is performed using the high speed
Nyquist ADC. The output voltage is sampled just before the end of
the switching period (tSW) or just before half the switching period
(tSW/2) if double update rate is enabled. The output voltage ripple
ramp changes as the input voltage changes, causing the sampling
voltage to also change. Assuming a steady state condition, any
dc offsets can be eliminated by sampling the output voltage
synchronously with the switching frequency.
Due to the relationship between the output voltage ripple ramp
and the input voltage, the average output voltage can drift to a
higher value when the input voltage is at its maximum value. To
correct for this drift, the ADP1055 uses a low frequency autocorrection loop based on the LF ADC on the VS± pins. Under
ideal conditions, the voltage on this input is 1.0 V.
Rev. A | Page 25 of 140
ADP1055
Data Sheet
4
The LF ADC is trimmed in production and has high accuracy
over supply, voltage, and temperature; therefore, the autocorrection
loop eliminates all errors due to offsets in the high frequency
ADC. The ADP1055 assumes that the voltage on the LF ADC is
accurate and precise and changes the setpoint (or reference)
accordingly so that the VS± pins measure 1.0 V. Any additional
offset in the output voltage is due to the tolerances of the external
resistor dividers alone.
3
BOOSTED GAIN
2
The speed of the autocorrection loop can be changed using
Register 0xFE4A[5:3]. This feature can also be disabled.
VIN_MIN
1
t
2 SW
tSW
2tSW
–1
0
1
2
3
4
12004-029
–2
Figure 34. Ideal Settings for Nonlinear Gain (Highest Gain Setting
for Highest Error)
INTEGRATOR WINDUP AND OUTPUT VOLTAGE
REGULATION LOSS (OVERSHOOT PROTECTION)
The ADP1055 limits the amount of integrator gain when the
output voltage is out of regulation for a long period of time due
to any of the following:



TIME
12004-028
SAMPLE
HERE
–3
ERROR VOLTAGE (%HF ADC FSR)
0V
SAMPLE
HERE
–1
–4
–4
TIME
VIN_MAX
0
–3
3tSW
0V
1
–2
The autocorrection loop stores the correction value until the
ADP1055 is power cycled. When the power is turned off and
then on again, the autocorrection loop is repeated to maintain
the most accurate output voltage.
VRIPPLE
0xFE29[0] = 0
0xFE29[0] = 1
SAMPLE
HERE
Figure 33. Output Voltage Sampling Point at Minimum
and Maximum Input Voltage
NONLINEAR GAIN/RESPONSE
To enhance the dynamic performance of the power supply
during a load transient, the nonlinear gain can be used. The
error voltage is the reference voltage minus the divided-down
output voltage by use of a resistive divider. During steady state,
this error voltage is 0 V. During a transient condition, the error
voltage is not zero and the digital compensator acts on the error
voltage and adjusts the control input to correct for the error.
This may take several switching cycles, especially during a
transition from DCM to CCM. In such cases, a boosted error
signal aids in reducing the settling time and can even avoid an
overshoot in some cases. The ADP1055 has a programmable
increase in error voltage depending on how far the absolute
error voltage is with respect to 0 V. There are four ranges: 1% to
2%, 2% to 3.5%, 3.5% to 4%, and >4%.
The nonlinear gain boost is programmable in Register 0xFE5E
and Register 0xFE29[0].
It is recommended that the loop gain of the power supply be
measured with the highest programmed gain setting. It is also
recommended that an additional gain margin of 4 dB be used
when this feature is used due to the nonlinear effect.
Large reduction in input voltage
Large and sudden change in output voltage setpoint
Excessive load
The ADP1055 limits the amount of integrator gain to prevent
overshoot caused by integrator windup. When duty cycle saturation
occurs due to any of these conditions, there is an inherent lag in
the system because the integrator is the slowest element of the
feedback control path. The ADP1055 inherently prevents the
integrator gain from increasing beyond a large value, but offers
an additional layer of protection. If the output voltage is out of
regulation for more than a certain number of switching cycles,
the reference/setpoint is set to the current output voltage, and a
soft start from precharge is initiated at a rate programmed by the
VOUT_TRANSITION_RATE command (Register 0x27). This
behavior eliminates any overshoot in the output voltage. This
setting and the number of switching cycles can be programmed
in Register 0xFE4A[7:6].
ACCURATE SECONDARY OVERCURRENT
PROTECTION
The CS2 ADC is used to measure the average value of the
secondary current via the CS2± pins. The 12 MSBs of the
reading (CS2_VALUE, Register 0xFE99[13:2]) are converted
into PMBus format and compared to the configured threshold
to make a fault decision. The LSB of the reading is equal to
CS2 range/2x
where:
CS2 range is the value set in Register 0xFE4F[1:0].
x is the number of bits in Register 0xFE4B[4:3].
Rev. A | Page 26 of 140
Data Sheet
ADP1055
SECONDARY FAST OVERCURRENT PROTECTION
The input signal on the CS2± pins is also fed into two comparators
for fast OCP protection. The fast OCP comparator is used to
limit the instantaneous secondary current in either the positive
or the negative direction. The CS2 OCP comparator also features a
programmable timeout condition (set in Register 0xFE4F[6:4]),
which specifies that the CS2 fast OCP condition must be present in
consecutive switching cycles before the IOUT_OC_FAST_FAULT
flag is set.
When the CS2 fast OCP comparator is used to sense the output
inductor current instead of the load current (see Figure 1), the
comparator can be used for cycle-by-cycle peak current limiting
of the inductor current. Cycle-by-cycle peak current limiting is
executed by the termination of the PWM outputs (OUTA to
OUTD) to disable power transfer to the secondary side. In an
isolated buck derived topology, the inductor current during the
on time of the primary switch is a fraction of the inductor current;
this feature can be used when the CS1 pin is not used. The CS2
fast OCP threshold can be set in steps of 9.52 mV for the 480 mV
CS2 ADC range and in steps of 0.952 mV for the 30 mV and
60 mV CS2 ADC ranges using Register 0xFE2D.
SECONDARY FAST REVERSE CURRENT PROTECTION
A programmable comparator is used to detect reverse current.
The comparator can also be used for diode emulation mode to
improve light load efficiency. The IOUT_UC_FAST fault is set
when the CS2 reverse comparator is asserted. After it is set, the
IOUT_UC_FAST fault is cleared between 328 μs and 656 μs
after the deassertion of the CS2 reverse comparator.
For all three CS2 ADC ranges (30 mV, 60 mV, and 480 mV), the
threshold is programmed in Register 0xFE2E[7:2], and the
debounce is programmed in Register 0xFE2E[1:0].
The operation of diode emulation mode depends on the accurate
sensing of the zero crossing of the inductor current, which in
turn is dependent on proper sensing of the inductor current
through the sense resistor. The accuracy of the fast reverse current
protection is heavily dependent on the sensing of the inductor
current; proper layout techniques (Kelvin sensing) must be
followed.
The fast reverse current comparator range is extended to a
positive range (0 mV to 30 mV) in addition to the negative
range (−30 mV to 0 mV). With this dual range, an accurate
sensing of the zero crossing can be tweaked and trimmed to
turn off the synchronous rectifiers at exactly the zero crossing
of the inductor current by compensating for the gate driver
delay and layout inadequacies and by ensuring that there is no
excessive voltage stress or voltage spike across the devices.
FEEDFORWARD AND INPUT VOLTAGE SENSE
The ADP1055 supports voltage line feedforward control to
improve line transient performance.
The feedforward scheme modifies the modulation value based
on the VFF voltage. When the VFF input is 1 V, the line feedforward has no effect. For example, if the digital filter output
remains unchanged and the VFF voltage changes to 50% of its
original value (but still higher than 0.5 V), the modulation of the
falling edges of OUTA to OUTD doubles (see Figure 35). The
voltage line feedforward function is optional and is programmable using Register 0xFE29 and Register 0xFECD[2:0]. It is
recommended that feedforward be enabled during soft start.
The VFF voltage must be set to 1 V when the nominal input
voltage is applied. The voltage at the VFF pin is sampled synchronously with the switching period and, therefore, the decision to
modify the PWM outputs based on input voltage is performed at
this rate. Typically, the feedforward block can detect and respond
to a 3% change in input voltage and make a change to the PWM
outputs approximately every 1 μs.
To prevent false triggering of the feedforward block due to
noise/voltage spikes on the VFF pin that are carried from the
switch node, a small filter capacitor may be needed. The filter
capacitor should not be too large, and the time constant should
typically be much less than 1 μs. An additional ADC connected
to the VFF pin is used to report the ADC value and therefore,
the input value, using the resistive dividers. The primary input
voltage can be calculated by multiplying Vx by the turns ratio
(N1/N2), as follows:
VPRIMARY = Vx × (R1 + R2)/R2 × (N1/N2)
For fault comparison, the input voltage is monitored using the
VFF ADC, and the 9 MSBs (VFF_VALUE, Register 0xFE96[13:2])
are converted into PMBus format and compared to the threshold
to make a fault decision. Fault limits and their responses can be
set using PMBus commands such as VIN_UV_FAULT_LIMIT
(Register 0x59), VIN_OV_FAULT_LIMIT (Register 0x55),
VIN_UV_FAULT_RESPONSE (Register 0x5A), and
VIN_OV_FAULT_RESPONSE (Register 0x56).
VFF
DIGITAL
FILTER
OUTPUT
tMODULATION
tMODULATION
OUTx
Rev. A | Page 27 of 140
tS
tS
Figure 35. Feedforward Control on Modulation
12004-031
Thresholds and limits can be set for CS2 using these PMBus
commands: IOUT_OC_FAULT_LIMIT (Register 0x46) and
IOUT_OC_WARN_LIMIT (Register 0x4A). The fault response
is programmable in Register 0x47.
ADP1055
Data Sheet
ACCURATE OVERVOLTAGE AND UNDERVOLTAGE
PROTECTION
Accurate overvoltage protection is provided by the PMBus
commands VOUT_OV_FAULT_LIMIT (Register 0x40),
VOUT_OV_FAULT_RESPONSE (Register 0x41), and
VOUT_OV_WARN_LIMIT (Register 0x42).
Similarly, accurate undervoltage protection is provided by the
PMBus commands VOUT_UV_WARN_LIMIT (Register 0x43),
VOUT_UV_FAULT_LIMIT (Register 0x44), and VOUT_UV_
FAULT_RESPONSE (Register 0x45).
All readings are obtained from the low frequency Σ-Δ ADC on
the VS+ and VS− pins.
The accurate OVP fault decision is taken after a sampling
interval of 82 μs (7-bit averaged value). For OVP, additional
sampling time up to a maximum of 320 μs can be programmed
in steps of 82 μs using Register 0xFE4D[3:2]. If additional
sampling time is enabled, the OV fault condition must be
present for the number of additional samples programmed
before the VOUT_OV flag is set.
The nominal output voltage at the VS± pins is 1 V, and the OVP
and UVP thresholds are set above and below this level. For UVP,
the output voltage is monitored using the low frequency Σ-Δ ADC;
the nine MSBs of the reading (VS_VALUE, Register 0xFE97[13:5])
are converted into PMBus format and compared with the output
undervoltage fault limit threshold. OVP functions similarly, but
uses the seven MSBs of the reading (Register 0xFE97[13:7]).
FAST OVERVOLTAGE PROTECTION
The ADP1055 has a dedicated OVP pin for redundant overvoltage
protection. This pin performs fast overvoltage protection, where
a comparator compares the fractional output voltage by means of
resistive dividers to the voltage set by a DAC (see Figure 36). The
nominal output voltage at the OVP pin is 1 V. The OVP threshold
is programmable using Register 0xFE2F[7:2]. A debounce time
(from 40 ns to 10 μs) can be added using Register 0xFE2F[1:0]
before the fault response is taken. The fault response is set using
the manufacturer specific command VOUT_OV_FAST_FAULT
(Register 0xFE34).
VOUT
ADP1055
OVP
FAST OVP
0.8V TO 1.6V
STEP SIZE = 12.5mV
DAC
EXTERNAL FREQUENCY SYNCHRONIZATION
The ADP1055 has a SYNC pin that is used for frequency
synchronization. The internal digital phase-locked loop (DPLL)
is capable of determining the master frequency on the SYNC pin
(fSYNC) and locking the internal switching frequency to the external
frequency. The lock or capture range is ±10% of the switching
frequency, which is programmed using the FREQUENCY_
SWITCH command (Register 0x33).
The PWM outputs are synchronized to the OUTA pin at the start
of the switching period. For example, consider a duty cycle on
OUTA where the rising (or falling) edge of OUTA is at a time of
x μs after the t = 0 of the switching period. After synchronization,
the time difference between the rising edge of the external master
synchronization frequency (fSYNC) and the rising (or falling) edge
of OUTA is x μs. The other PWM outputs are adjusted accordingly.
In short, frequency synchronization also locks on to the phase.
The DPLL can recognize the external master frequency within
one clock cycle and, after the DPLL has locked on to fSYNC, the
time required to achieve synchronization depends on how far
apart fSYNC and the internal switching frequency (fSW) are. A
typical synchronization time when fSYNC jumps from 90 kHz to
110 kHz with fSW = 100 kHz is approximately 200 μs. The
synchronization time depends on the bandwidth of the DPLL,
which is approximately fSW/25. Therefore, a higher fSW translates
to a higher bandwidth.
Using the INTERLEAVE command (Register 0x37), a phase
shift in steps of 22.5° can be added. Additional functions that
are part of the standard PMBus INTERLEAVE command
include the group ID number and the respective number in the
group, both programmable using Register 0x37.
The ADP1055 supports only a specific number of switching
frequencies. Due to the PWM programming resolution of 5 ns
for programming the minimum and maximum PWM modulation
limit, the switching frequency and the master clock frequency
may not be an exact multiple of each other.
Although the DPLL can detect fSYNC exactly, due to the quantization
of the internal frequency settings, there is a possibility that fSYNC
and fSW may not be the same and may differ by a small amount.
To prevent the frequency from jumping from one value of fSW to
another (which causes the switching period to change) due to
the quantization of fSW, fSW is set to the closest quantized value
to fSYNC rounded down. Due to this effect or due to a non-ideality
(jitter) of the master clock, a dither can be added to the clock
frequency (using Register 0xFE55[1]) of 5 ns or 10 ns. Using
this dither, fSW is equal to fSYNC on average.
For a full-bridge topology, it is recommended that Register
0xFE55[0] = 0 so that half the switching period is an exact
multiple of 5 ns.
6-BIT
THRESHOLD
12004-032
AGND
Figure 36. Fast Overvoltage Protection
Rev. A | Page 28 of 140
Data Sheet
ADP1055
After synchronization, if the master clock suddenly changes to
0 Hz, the ADP1055 continues to operate at the last known master
frequency. However, if the device is power cycled through a soft
start, the master frequency is not retained, and the ADP1055
defaults to the internal frequency set by FREQUENCY_SWITCH
(Register 0x33). If the device is off and the master frequency is
already present on the SYNC pin, the switching frequency is
already set to the master frequency when the ADP1055 turns on.
It is recommended that the synchronization function be
disabled when not in use (Register 0xFE55[6] = 1) because
switching noise may be coupled into the SYNC pin.
The switching frequency can be read back using the PMBus
command READ_FREQUENCY (Register 0x95).
MASTER CLOCK FREQUENCY (fSYNC )
INTERNAL SWITCHING FREQUENCY (fSW)
SYNCHRONIZATION TIME
DEPENDS ON DPLL BANDWIDTH
SYNCHRONIZATION
TIME DEPENDS ON
DPLL BANDWIDTH
NOMINAL fSW
UNIT
OFF
UNIT
ON
12004-033
90% fSW
UNIT
ON
TIME
Care must be taken to isolate the thermal sensor so that
switching noise is not coupled into the base by the parasitic
capacitances from base to ground and emitter to ground. It is
recommended that a low-pass filter be added by placing a large
capacitor of 220 pF to 470 pF across the base emitter junction to
remove any noise. Adding a reverse diode introduces an
additional error due to the reverse leakage current. The
reference current (IREF), used for the sensing algorithm to 10 μA,
can be programmed by setting Register 0xFE5A[2:0] = 0x04.
The update rate for each subsequent temperature reading
(external forward reading, followed by external reverse reading)
is approximately 200 ms if reverse sensing is enabled, and
approximately 130 ms if reverse sensing is disabled, with 14-bit
resolution (Register 0xFE5A[6:5] = 0x3).
FREQUENCY
110% fSW
placed in the position of forward diode. The nonideality factor
(nf) of the transistor in ΔVBE = nf × VT × ln(I/IS).
Figure 37. Tracking of SYNC Function
Overtemperature protection (OTP) can be set using
OT_FAULT_LIMIT (Register 0x4F), OT_FAULT_RESPONSE
(Register 0x50), and OT_WARN_LIMIT (Register 0x51). OTP
functions for the forward diode only. The hysteresis for OTP is
the difference between the OT_FAULT_LIMIT and OT_WARN_
LIMIT values. For example, if OT_FAULT_LIMIT is set to disable
all PWM outputs at 125°C and OT_WARN_LIMIT is set to 115°C,
the ADP1055 stops switching at 125°C and begins switching
again only when the temperature falls below 115°C.
TEMPERATURE SENSING
GPIO AND PGOOD SIGNALS
The ADP1055 has two external temperature sensors. For the
external temperature sensors, PN junction devices such as
transistors are connected back to back; these devices are called
forward diode and reverse diode (see Figure 38).
Four dedicated pins serve as general-purpose inputs/outputs
(GPIOs). Each pin can be configured as an input or output with
a programmable polarity (set in Register 0xFE40). Do not
change the configuration of the pin from input to output or
from output to input on the fly.
FORWARD
DIODE
REVERSE
DIODE
12004-034
JRTN
12004-035
JTD
Figure 39. GPIO1 Configured as an Output with Normal Polarity
Figure 38. Temperature Sensor, Forward and Reverse Sensing
The ADP1055 measures the temperature readings of the external
forward diode and the external reverse diode in that order. Using
proprietary zero offset circuitry (patent pending), the inputs to
the ADCs are zeroed out before each temperature measurement
to compensate for temperature dependent offset variation, which
affects the measurement result. This allows the forward and
reverse sensing PN diodes to be kept far away from each other
without affecting the reading significantly due to offset errors.
12004-036
The temperature can be read using the following standard PMBus
commands: READ_TEMPERATURE_2 (Register 0x8E) for the
external sensing forward diode, and READ_TEMPERATURE_3
(Register 0x8F) for the external sensing reverse diode.
Figure 40. GPIO1 Configured as an Input with Negated Polarity
When the pin is configured as an input, a programmable action
can be taken (similar to the PMBus voltage faults) using Register
0xFE39 to Register 0xFE3C (GPIOx_FAULT_RESPONSE).
When the GPIOx pin is configured as an output, internal signals
known as PGOOD1 and PGOOD2 can be logically combined
and output on the pin. The logic functions for the GPIO pins
are programmable in Register 0xFE41 and Register 0xFE42.
The ADP1055 is factory calibrated at ambient temperature for
minimum error using the BC847A transistor (with nf = 1.00)
Rev. A | Page 29 of 140
ADP1055
Data Sheet
12004-037
The POWER_GOOD_ON register (Register 0x5E) sets the voltage
that the output voltage must exceed before POWER_GOOD can
be set. Similarly, the output voltage must fall below the
POWER_GOOD_OFF threshold (set in Register 0x5F) for
POWER_GOOD to be reset.
VOUT NOMINAL
Figure 41. Logical Functions Available Using PGOOD1 (LOGIC) PGOOD2
In addition to triggering the GPIOs, the PGOOD1_FAULT
and PGOOD2_FAULT flags are set in Register 0xFE93[6]
(FAULT_UNKNOWN[6]) and Register 0xFE93[7] (FAULT_
UNKNOWN[7]) (where 0 means no fault). The same debounce
applies to the flags.
PSON
TIME
Figure 43. POWER_GOOD Flag Tripped by VOUT
Note that the PMBus signal POWER_GOOD cannot be brought
out to the GPIOx pins, but it can be brought out to the SMBALRT
pin. The PMBus signal POWER_GOOD is accessible through
STATUS_WORD (Register 0x79[11]). POWER_GOOD is
asserted (0 means power is good) only if all of the following
conditions are met:




VOUT has exceeded POWER_GOOD_ON.
VOUT has not fallen below POWER_GOOD_OFF.
PGOOD1_FAULT is not set.
PGOOD2_FAULT is not set.
UVP is not associated with this flag; however, the PGOOD1_
FAULT and PGOOD2_FAULT flags can be programmed to
select UVP (VOUT_UV_FAULT). There is no debounce for
POWER_GOOD.
VOUT
SET AND
RESET LOGIC
POWER_GOOD_ON
VOUT_UTHD
POWER_GOOD_OFF
VOUT_LTHD
RESET
SET
PGOOD1_FAULT
PGOOD2_FAULT
OFF
Figure 44. POWER_GOOD Signal Path
Rev. A | Page 30 of 140
POWER_GOOD
12004-040
12004-038
Figure 42. Signals Routed into PGOOD1 and PGOOD2
POWER_GOOD
12004-039
VOUT_UV
Various flags can be programmed into PGOOD1 and PGOOD2
using Register 0xFE44 and Register 0xFE45. When coupled
with the GPIOs, these flags can be used to trigger signals to
provide external logic functions by means of discrete circuits.
For example, in Figure 42, the overtemperature flag or the
VIN_UV flag can set PGOOD2. This feature is useful for
signaling the power chain downstream so that any appropriate
action can be taken. A delay (debounce) can be added to the
PGOODx signals using Register 0xFE43.
Data Sheet
ADP1055
GPIO3 AND GPIO4 AS SNUBBER PWM OUTPUTS
12004-043
The GPIO3 and GPIO4 pins of the ADP1055 can be configured
as two signals used for an active snubber. This circuitry can be
used to provide a drive signals for an active clamp.
Snubber Configuration
The on time of the snubber and the dead time of the snubber
signals can be programmed using Register 0xFE63 and
Register 0xFE64[5:0], respectively. The active clamp signals
turn on after a selectable dead time (0 ns to 315 ns in steps of
5 ns, programmable using Register 0xFE64[5:0]). Using
Register 0xFE65[7], the active clamp signals can be configured
on one of the following:
12004-044


Figure 47. Option 1: GPIO3 and GPIO4 Configured as Regular Signals
Falling edge of SR1 or SR2 signal
Falling edge of OUTC and OUTD
Figure 48. Option 2: GPIO3 Configured as an Active Snubber PWM Output;
GPIO4 Configured as a Regular Signal
12004-045
The snubber signal stays on for a fixed value regardless of the
duty cycle and load condition programmed in Register 0xFE63.
However, the snubber signal is toggled as soon as it encounters
the next SRx rising edge or the next OUTx falling edge, even if
the programmed on time is of a greater value.
12004-041
Figure 49. Option 3: GPIO3 Configured as a Regular Signal;
GPIO4 Configured as an Active Snubber PWM Output
12004-046
Figure 45. Active Clamp Snubber Configured on SRx Signals
12004-042
Figure 50. Option 4: GPIO3 and GPIO4 Configured
as Active Snubber PWM Outputs
Figure 46. Active Clamp Snubber Configured on OUTx Signals
Miscellaneous Snubber Configuration
Using Register 0xFE64[7:6]), the snubber configuration can be
set to one of these options:




Option 1: Both GPIO3 and GPIO4 are configured as regular
signals, as described in the GPIO and PGOOD Signals section
(see Figure 47).
Option 2: GPIO3 is configured as an active snubber
PWM output; GPIO4 is configured as a regular signal
(see Figure 48).
Option 3: GPIO3 is configured as a regular signal; GPIO4 is
configured as an active snubber PWM output (see Figure 49).
Option 4: Both GPIO3 and GPIO4 are configured as active
snubber PWM outputs (see Figure 50).
The GPIO polarity bit can be configured using the same bits
described in the GPIO and PGOOD Signals section. The
polarity bit allows true versatility with the use of either P channel
or N channel FETs, depending on the application. These PWM
signals can be blanked during soft start and soft stop using
Register 0xFE46[14] and Register 0xFE47[14]. The signals are
active as long as the system does not shut down in response to a
fault condition or a PSOFF command is issued.
Rev. A | Page 31 of 140
ADP1055
Data Sheet
The constant current control loop has relatively low bandwidth
because the current is averaged over a 328 μs period (9-bit
decimation of the CS2 bit stream). The output voltage changes
at a maximum rate of 1.18 V/sec at the VS± pins; therefore, the
instantaneous value of the current can exceed the constant
current limit for a very short period of time, depending on the
severity of the transient condition.
AVERAGE CONSTANT CURRENT MODE
The ADP1055 supports constant current (CC) mode. The
constant current mode threshold is set in one of two ways:

Using the PMBus definition of CC mode (Register
0xFE4F[2] = 0)
Using the manufacturer specific CC mode (Register
0xFE4F[2] = 1)
For a faster dynamic response of the constant current mode, the
turbo mode can be used. In turbo mode, the averaging time can
be decreased to a period of ~41 μs (6-bit decimation of the CS2
bit stream). In turbo mode, the slew rate of the output voltage
can be programmed using Register 0xFE5D[5:4].
In both modes, the constant current limit can be set as a
percentage of the IOUT_OC_FAULT_LIMIT—for example,
±3.125%, ±6.25%, ±12.5%, ±25%, ±50%, or ±100%—using
Register 0xFE5D[3:0].
In the PMBus definition of CC mode, the constant current
mode is activated on a IOUT_OC_FAULT fault, and the load
current is limited to the CC limit, as specified in Register
0xFE5D[3:0]. Only positive percentages are applicable when the
PMBus definition of CC mode is used. The fault responses to
IOUT_OC_FAULT in this case are defined as per the PMBus
format. The system enters CC mode on detection of the CS2
current (~2.6 ms, 12-bit averaging of CS2 ADC). Any further
changes in the current while the device is in CC mode take
place according to the averaging speed selectable in Register
0xFE4F[7]. For CC mode to work properly using the PMBus
faults, the IOUT_OC_FAULT debounce must be set to 0 ms.
In the manufacturer specific CC mode, the CC limit is exactly
the limit that is programmed, and there is no need to trip the
IOUT_OC_FAULT before entering CC mode. Fault responses
to IOUT_OC_FAULT in this case are to ignore the fault or to
shut down the device in response to the fault (Register 0x47[7:6] =
11). Other settings programmed in the response section (for
example, Register 0x47[7:6] = 00, 01, or 10) are ignored.
As the output voltage is reduced to maintain a constant load
current, xxx_FAULT_RESPONSE (for example, Register
0x47[7:6] = 01) can be used to program a fault response when
the output voltage falls below a specific threshold set by
IOUT_OC_LV_LIMIT (Register 0x48).
It is important to note that although constant current mode can
be applied to any current fault (input or output current) according
to the PMBus specification, the ADP1055 applies the constant
current mode only to maintain a constant output current. For
example, if the IOUT_UC_FAULT is programmed to enter
constant current mode, the ADP1055 does not boost the output
voltage to maintain the current level set by IOUT_UC_LIMIT.
Using the manufacturer specific fault response for constant
current mode, the system can be forced into constant current
mode at a specific threshold, and if this threshold persists for a
specified amount of time (based on the debounce time), the
IOUT_OC_FAULT is tripped (see Figure 52).
Below the IOUT_OC_FAULT_LIMIT threshold, the ADP1055
operates in constant voltage mode, using the output voltage as
the feedback signal for closed-loop operation.
DEPENDENT ON SLEW RATE
AND CC TURBO MODE
VOUT NOMINAL
IOUT_OC_FAST
HICCUP
CC LIMIT
When the ADP1055 crosses the constant current mode threshold,
the CS2 current reading is used to control the output voltage
regulation point. The output voltage is ramped down linearly as
the load increases to ensure that the load current remains
constant.
IOUT_OC_FAULT_LIMIT
IOUT NOMINAL
TIME
IOUT_OC_
DEBOUNCE
STARTS
CONVERTER
STARTS
AFTER RETRY
ATTEMPT
IOUT_OC_
IOUT_OC_
DEBOUNCE
DEBOUNCE
STARTS
STARTS
VOUT
IOUT_OC_DEBOUNCE
ENDS AND FAULT TRIPS
Figure 52. Constant Current with Hiccup
(0,0)
IOUT
IOUT_OC_FAULT_LIMIT
12004-047
32-BIT KEY CODE
The ADP1055 supports a 32-bit password (key code) in
addition to the EEPROM password set by Register 0xD5. This
32-bit key code enables another level of protection for the user
and the manufacturer to limit access to certain commands and
operations.
Figure 51. Typical Characteristics in Constant Current (CC) Mode
Rev. A | Page 32 of 140
12004-048

Data Sheet
ADP1055
Entering the Key Code
1.
The command mask feature allows any PMBus command or
manufacturer specific command to be masked in the ADP1055.
If the command is masked, a read or a write to that command
results in a no acknowledge (NACK). PMBus commands are
masked using Register 0xF4; manufacturer specific commands
are masked using Register 0xF5. Using command masking, the
user can block access to certain commands—such as commands
that configure the switching frequency, the digital compensator,
or the output voltage setpoint—while allowing access to the
readback commands (READ_x, where x = IOUT, IN, VOUT,
VIN, and so on). The SLV_ADDR_SELECT (Register 0xD0),
EEPROM_PASSWORD (Register 0xD5), KEY_CODE (Register
0xD7), EEPROM_INFO (Register 0xF1), CMD_MASK
(Register 0xF4), and EXTCMD_MASK (Register 0xF5)
commands are not maskable. It is recommended that the
ADP1055 GUI be used to configure the masking function (see
Figure 53).
3.
SR PHASE-IN, SR TRANSITION, AND SR FAST
PHASE-IN
The SR1 and SR2 outputs are recommended for use as the
PWM control signals when using synchronous rectification for
the output (or secondary) rectifiers. These PWM signals can be
configured similar to other PWM outputs.
12004-050
Command Mask
2.
Figure 54. Example of SR Outputs in Light Load Mode (LLM)
12004-051
The key code is a unique 32-bit pass code that is entered using
the KEY_CODE command (Register 0xD7). Because this command is a block read/block write command, the first data byte
of this command is the number of bytes (4). When entering the
key code, the data has this format: {0x04, KeyCode[7:0],
KeyCode[15:8], KeyCode[23:16], KeyCode[31:17]}. (Note the
low byte to high byte order of the 32-bit key code.) After the
correct key code is entered, the user has full write access to all
commands, including PMBus and manufacturer specific commands such as CMD_MASK (Register 0xF4) and EXTCMD_
MASK (Register 0xF5), which can be used to disable other
commands using the command masking feature. The key code
is also needed to change the EEPROM password (Register 0xD5).
After the EEPROM is unlocked, enter the 32-bit key code
(default key code is 0xFFFFFFFF) using the KEY_CODE
command (Register 0xD7).
Enter the new key code using the same command, for
example, 0x1FEEDBAC (a pneumonic for negative feedback
in twos complement format).
The key code is now changed to the new key code. Save the
new key code into the user settings page of the EEPROM
using the STORE_USER_ALL command (Register 0x15).
Figure 55. Example of SR Outputs in Heavy Load (CCM)
When the mode changes from LLM to CCM, an abrupt change in
the SR outputs may cause the output voltage to dip momentarily.
An optional SR transition process (during which the pulse
width of the SR PWM outputs is increased slowly) can be
applied to the SR1 and SR2 outputs. The SR transition can be
enabled by setting Register 0xFE50[5].
The speed at which the SR edges move from zero duty cycle
to maximum duty cycle (as determined by the control loop)
can be programmed from 5 ns per tSW to 5 ns per 1024 tSW
(tSW = switching cycle) using Register 0xFE5F[7:4].
OUTPUT VOLTAGE SLEW RATE
The output voltage slew rate (or transition rate) can be set using the
PMBus VOUT_TRANSITION_RATE command (Register 0x27).
The slew rate determines how quickly the output voltage is
adjusted in response to a change in the digital reference.
12004-049
The fastest slew rate supported by the ADP1055 is 1 kV/sec,
and the slowest rate is 14.3 V/sec. A PMBus command setting
of 0 sets the slew rate to the slowest setting. This slew rate is the
rate that the internal setpoint reference can change; the actual
change of the output voltage depends on the bandwidth of the
control loop and its ability to track the reference.
Figure 53. Snapshot of the GUI Showing Lock and Unlock of Commands
Changing the Key Code
To change the key code, first unlock the EEPROM as described
in the Unlock the EEPROM section.
The VOUT_TRANSITION_RATE command can be disabled
using Register 0xFE65[2].
ADAPTIVE DEAD TIME COMPENSATION
Register 0xFE1D to Register 0xFE24 are the adaptive dead time
(ADT) registers. These registers allow the dead time between
Rev. A | Page 33 of 140
ADP1055
Data Sheet
PWM edges to be adapted on the fly. The ADT feature is activated
when the primary or secondary current (CS1 or CS2) falls below
the threshold programmed in Register 0xFE1E. The software
GUI allows the user to easily program the dead time values, and
it is recommended that the GUI be used for this purpose.
resonant transition occurs when energy is dumped from the
inductor to the capacitor (capacitor being charged with opposite
polarity voltage). At one point, there is close to 0 V across the
MOSFET, and at this point the power switch is turned on.
If this energy is not sufficient, the MOSFET turns on without
ZVS. In this case, ADT can be used to wait until the resonant
transition reaches its peak value so that a near ZVS turn-on is
achieved.
12004-052
SR DELAY
Figure 56. Adaptive Dead Time Window in the GUI
The ADP1055 is well suited for dc-to-dc converters in isolated
topologies. Each time a PWM signal crosses the isolation barrier,
an additional propagation delay is added due to the isolating components. The ADP1055 allows programming of an adjustable
delay (0 ns to 315 ns in steps of 5 ns) using Register 0xFE52[5:0].
This delay moves both SR1 and SR2 later in time with respect to
OUTA to OUTD to compensate for the added delay due to the
isolating components. In this way, the edges of all PWM outputs
can be aligned, and the SR delay can be applied separately as a
constant dead time.
Before ADT is configured, the primary current threshold must
be programmed. Each individual PWM rising and falling edge
(t1 to t12) can then be programmed to have a specific dead time
offset at no load (zero current). This offset can be positive or
negative and is relative to the nominal edge position. When the
current is between zero and the threshold, the amount of dead time
is linearly adjusted in steps of 5 ns. The averaging period of the
CS1/CS2 current is selected using Register 0xFE1E[7], and the
speed of the dead time adjustment can also be programmed to
accommodate faster or slower adjustment in Register 0xFE1D[5:0].
CURRENT SHARING (ISHARE PIN)
For example, if the CS1 threshold is set to 2 A, t1 has a nominal
rising edge of 100 ns. If the ADT setting for t1 is 40 ns at no load,
t1 moves to 140 ns when the current is 0 A and to 120 ns when
the current is 1 A. Similarly, ADT can be applied in the negative
direction.
The current reading from CS1 or CS2 can be output to the ISHARE
pin in the form of a digital bit stream, which is the output of the
current sense ADC (see Figure 57). The bit stream is proportional
to the current delivered by this unit to the load. By filtering this
digital bit stream using an external RC filter, the current information is turned into an analog voltage that is proportional to
the current delivered by this unit to the load. This voltage can
be compared to the share bus voltage. If the unit is not supplying
enough current, an error signal can be applied to the VS± feedback point. This signal causes the unit to increase its output voltage
and, in turn, its current contribution to the load.
The ADT feature is useful in quasi resonant topologies where an
energy transfer occurs from the inductor (generally, from one or
more of the leakage inductance, magnetizing inductance, and
external inductance) to the capacitor (usually the drain-source
capacitance of the MOSFET power switch) for the purpose of
achieving zero voltage switching (ZVS).
The ADP1055 supports both analog current sharing and digital
current sharing. The ADP1055 can use either the CS1 current
information or the CS2 current information for current sharing.
Analog Current Sharing
Analog current sharing uses the internal current sensing
circuitry to provide a current reading to an external current
error amplifier. Therefore, an additional differential current
amplifier is not necessary.
Generally, the condition for ensuring ZVS is that the energy in
the inductor must exceed the energy in the capacitor. A
CURRENT
CURRENT
SENSE
ADC
CS2–
VOLTAGE
BIT STREAM
SHARE
BUS
ISHARE
BIT STREAM
LPF
Figure 57. Analog Current Share Configuration
Rev. A | Page 34 of 140
12004-054
CS2+
Data Sheet
ADP1055
Digital Share Bus
The digital share bus is based on a single-wire communication
bus principle; that is, the clock and data signals are contained
together.
The digital share bus scheme is similar in principle to the traditional analog share bus scheme. The difference is that instead of
using a voltage on the share bus to represent current, a digital
word is used.
When two or more ADP1055 devices are connected, they synchronize their share bus timing. This synchronization is performed
by the start bit at the beginning of a communications frame. If a
new ADP1055 is hot-swapped onto an existing digital share bus,
the device waits to begin sharing until the next frame. The new
ADP1055 monitors the share bus until it sees a stop bit, which
designates the end of a share frame. It then performs synchronization with the other ADP1055 devices during the next start bit.
The digital share bus frame is shown in Figure 60.
The ADP1055 outputs a digital word onto the share bus. The
digital word is a function of the current that the power supply is
providing (the higher the current, the larger the digital word).
The power supply with the highest current controls the bus
(master). A power supply that is putting out less current (slave)
sees that another supply is providing more power to the load
than it is.
Figure 59 shows the possible signals on the share bus.
During the next cycle, the slave increases its current output contribution by increasing its output voltage. This cycle continues
until the slave outputs the same current as the master, within a
programmable tolerance range. Figure 58 shows the configuration of the digital share bus.
LOGIC 1
LOGIC 0
VDD
PREVIOUS
BIT
DIGITAL
WORD
ISHARE
Figure 59. Share Bus High, Low, and Idle Bits
The length of a bit (tBIT) is fixed at 10 μs. A Logic 1 is defined as
a high-to-low transition at the start of the bit and a low-to-high
transition at 75% of tBIT. A Logic 0 is defined as a high-to-low
transition at the start of the bit and a low-to-high transition at
25% of tBIT.
POWER SUPPLY A
SHARE
BUS
The bus is idle when it is high during the whole period of tBIT.
All other activity on the bus is illegal. Glitches up to tGLITCH
(200 ns) are ignored.
ISHARE
DIGITAL
WORD
12004-053
CURRENT SENSE
INFO
POWER SUPPLY B
The digital word that represents the current information is eight
bits long. The ADP1055 takes the eight MSBs of the CS1 or CS2
reading (the current share signal specified in Register 0xFE2B[3])
and uses this reading as the digital word. When read, the share
bus value at any given time is equal to the CS1 or CS2 current
reading (see Figure 61).
Figure 58. Digital Current Share Configuration
2 STOP BITS
(IDLE)
PREVIOUS
FRAME
START BIT
0
NEXT
BIT
tBIT
8-BIT DATA
2 STOP BITS
(IDLE)
FRAME
Figure 60. Digital Current Share Frame Timing Diagram
Rev. A | Page 35 of 140
START BIT
0
NEXT FRAME
12004-055
CURRENT SENSE
INFO
t0
12004-056
t1
IDLE
ADP1055
Data Sheet
Digital Share Bus Scheme
Digital Share Bus Configuration
Each power supply compares the digital word that it is outputting
with the digital words of all the other supplies on the bus.
The digital share bus can be configured in various ways. The
bandwidth of the share bus loop is programmable in Register
0xFE2B[2:0]. The extent to which a slave tries to match the
current of the master is programmable in Register 0xFE2A[3:0].
The slave moves up 1 LSB for every share bus transaction (eight
data bits plus start and stop bits; see the description of Register
0xFE2B in Table 156). The master moves down x LSBs per share
bus transaction, where x is the share bus setting in Register
0xFE2A[7:4]. The maximum limit for the output voltage of the
slave is 400 mV at the VS± pins. The ISHARE_FAULT is set
when the current share loop reaches its maximum value, that is,
400 mV at the VS± pins. It is recommended that there be a load
line of 5 mΩ to 10 mΩ between the output terminals of the power
supply to the load.
Round 1
In Round 1, every supply first places its MSB on the bus. If a
supply senses that its MSB is the same as the value on the bus, it
continues to Round 2. If a supply senses that its MSB is less than
the value on the bus, it means that this supply must be a slave.
When a supply becomes a slave, it stops communicating on the
share bus because it knows that it is not the master. The supply then
increases its output voltage in an attempt to share more current.
If two units have the same MSB, they both continue to Round 2
because either of them may be the master.
Round 2
DROOP SHARING
In Round 2, all supplies that are still communicating on the bus
place their second MSB on the share bus. If a supply senses that
its MSB is less than the value on the bus, it means that this supply
must be a slave and it stops communicating on the share bus.
The droop sharing functionality is implemented using the
VOUT_DROOP command (Register 0x28). Using this command,
a fixed amount of load line in mV/A can be applied to the
output voltage. The output voltage is continuously sampled with
a selectable rate (set in Register 0xFE65[1:0]) before the droop
is applied. Under droop current sharing, the output voltage
changes at a rate determined by the VOUT_TRANSITION_ RATE
command. Setting 0xFE65[2] = 1 changes the internal voltage
reference to the fastest internal supported rate.
Round 3 to Round 8
The same algorithm is repeated for up to eight rounds to allow
supplies to compare their digital words and, in this way, to
determine whether each unit is the master or a slave.
PSU A
VDD
0x4A
MASTER
IOUT = 35A
1mΩ
CS2–
+
35mV
–
CURRENT
SENSE
ADC
12 BITS
1195 DEC
0x4AB
DIGITAL
FILTER
÷16
8 BITS
74 DEC
0x4A
ISHARE
DIGITAL
WORD
0x4A
8-BIT
WORD
SHARE
BUS
8-BIT
WORD
0xB5
1 LSB = 29.3µV
35mV/29.3µV = 1195
Figure 61. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus
Rev. A | Page 36 of 140
12004-057
CS2+
Data Sheet
ADP1055
LIGHT LOAD MODE AND DEEP LIGHT LOAD MODE
To facilitate a reduction of power loss at light loads, the ADP1055
supports light load mode and deep light load mode. The threshold,
speed, and hysteresis for deep light load mode are selectable in
Register 0xFE4B. In deep light load mode, a selectable set of
PWM outputs can be disabled using Register 0xFE4C. Typical
examples include shutting down the synchronous rectifiers or
shutting down certain PWM outputs in an interleaved topology
for phase shedding.
The ADP1055 enters pulse skipping mode when the required
duty cycle is less than the modulation value set in Register 0xFE53.
Register 0xFE50[0] = 0 sets all modulated edges to the start of
the switching period. In the case of negative edge modulation,
this setting can cause the PWM outputs to be inverted; therefore,
setting Register 0xFE50[0] = 1 programs the device to make the
PWM outputs = 0 V in pulse skipping. For topologies such as the
full-bridge phase shifted topology, where two PWM outputs are
on without modulation for half the switching period, the setting
in Register 0xFE50[4] allows the ADP1055 to disable such
PWM outputs whether modulation is enabled or not.
12004-058
SOFT STOP
Figure 62. Light Load Settings in the GUI
The threshold, speed, and hysteresis for light load mode are
programmed in Register 0xFE5F. In SR light load mode (SR
LLM), the synchronous rectifiers operate in the forward
conduction mode only; that is, they are turned off during the
freewheeling period of the switching period in a buck derived
isolated topology (either half wave or full wave rectifier on the
output). In this way, the loss associated with the diode drop of
the MOSFET is minimized by turning the channel of the
MOSFET on, as well as maintaining the output inductor in
discontinuous conduction mode (DCM). The rising and falling
edges of the synchronous rectifiers in SR LLM are programmed
in Register 0xFE19 to Register 0xFE1C.
When entering SR LLM from SR normal mode or deep LLM, or
when exiting SR LLM to SR normal mode based on the hysteresis
level, the SR edges move as programmed by the phase-in speed
in Register 0xFE5F[7:4].
The SR LLM settings (Register 0xFE19 to Register 0xFE1C)
determine the minimum and maximum rising and falling edges
of the SR PWM outputs in SR LLM mode. If the load demands
a duty cycle between the minimum and maximum settings, the
SR edges are adjusted according to the required duty cycle for
OUTA to OUTD.
12004-059
To enable the deep light load mode, the light load mode
threshold must be greater than zero.
Figure 63. Overlay of All SR Modes
PULSE SKIPPING
The ADP1055 supports a pulse skipping mode in which a PWM
pulse is not turned on for the entire switching period. Pulse
skipping can be activated by setting Register 0xFE50[1] = 1.
The ADP1055 supports soft stop functionality. Soft stop can be
enabled for normal shutdown of the power supply using the
OPERATION and ON_OFF_CONFIG commands, as described
in the Power-Up and Power-Down section. Soft stop can also be
enabled during a fault triggered condition using Register
0xFE51[7:6]. The soft stop time is programmed using the
TOFF_DELAY and TOFF_FALL commands (Register 0x64 and
Register 0x65). During soft stop, various faults such as OTP,
OVP, and GPIO faults can be masked using Register 0xFE47. To
maintain a zero output voltage, the SR1 and SR2 PWM outputs
can be programmed to stay on for an additional time (see the
description of Register 0xFE50[7:6] in Table 193).
DUTY CYCLE DOUBLE UPDATE RATE
The ADP1055 senses the output voltage just before the beginning
of the switching period and, depending on the error voltage, the
next duty cycle command is initiated. Because a transient
condition can occur at any time between switching periods, the
one-cycle update of the duty cycle causes a phase loss that is
equal to
Φ = 360 × (td × fC)
where:
td is the combined delay of the ADC sampling plus the loop
calculations for the compensator plus any additional propagation
delay.
fC is the crossover frequency.
The minimum delay for the system is D × tSW because it is only
after D × tSW that the effect of the duty cycle command takes
place. Due to this phase loss (which increases as the crossover
frequency approaches the switching frequency), the crossover
frequency of the system cannot be widened with satisfactory
phase margin. To reduce the phase loss, the ADP1055 uses a
double update rate for the duty cycle, whereby the output voltage
is sampled just before half the switching period and the new duty
cycle command is issued. In this way, the phase loss from two
subsequent duty cycle commands is halved to D × tSW/2.
Duty cycle double update rate is optional and is enabled by
setting Register 0xFE57[0] = 1. When using the duty cycle
double update rate, it is recommended that duty balance also be
enabled (Register 0xFE57[7] = 1).
Rev. A | Page 37 of 140
ADP1055
Data Sheet
for Register 0xFE56 causes the device to sample the peak
current at the end of the logical AND of OUTA and OUTD
(Peak 1) and the logical AND of OUTB and OUTC (Peak 2).
If Peak 1 > Peak 2, the result is positive and the duty cycle
of the selected edges is reduced. If Peak 2 > Peak 1, the result is
negative and the duty cycle of the selected edges is increased.
DUTY BALANCE, VOLT-SECOND BALANCE, AND
FLUX BALANCING
For power topologies that use the first and third quadrant of the
BH curve, it is recommended that duty balance be enabled
when using double update rate. Due to the nature of double
update rate, it is possible that the average magnetizing current
(and therefore the flux density of the transformer core) is not
zero, but is equal to some positive or negative dc level. To prevent
flux walking and an imbalance in the transformer, a combination
of the duty balance and volt-second balance features can be used.
In interleaved topologies, the volt-second balance feature can also
be used for current balancing to ensure that each interleaved
phase contributes equal power.
2.
3.
For example, if a full bridge topology requires the diagonal edges of
the H bridge to be equalized, the algorithm for duty balance
averages the duty cycle over several switching cycles. Duty balance
is a purely digital correction that is applied to the PWM edges
based on past duty cycles and does not take into account any
feedback from an ADC, as is the case for volt-second balance.
12004-060
Duty balance is enabled by setting Register 0xFE57[7] = 1; the
speed at which the duty cycle is balanced is controlled by setting
Register 0xFE57[5:4]. Additionally, the extent to which duty cycle
correction (maximum of ±160 ns for duty balance and volt-second
balance each) can take place is specified using Register 0xFE57[2:1].
Apply edge correction. Using the same example, negative edge
correction is applied to OUTA and OUTD, whereas positive
edge correction is applied to OUTB and OUTC. Appropriate
edge correction is applied to the SR outputs as well.
Enable volt-second balance by setting Register 0xFE25[6] = 1.
This setting is gated by a GO command (Register 0xFE00).
Volt-second balance is automatically disabled when the
voltage on the CS1 pin is below 25 mV.
Figure 64. Volt-Second Balance with Register 0xFE56 = 0x96
Volt-second balance uses a sample-and-hold circuit (patent
pending) that samples the peak current during both halves of
the switching period. This feature is configured using Register
0xFE56. The recommended settings for using the volt-second
balance feature are as follows.
12004-061
Use Register 0xFE56 to set the positive and negative edges.
Bits[7:4] set the positive period of integration, and Bits[3:0]
set the negative period of integration. The edges are
logically AND’ed together.
Typically, the diagonal edges of the H bridge are balanced.
For example, in a full bridge topology, a setting of 10010110
Figure 65. Volt-Second Balance with Register 0xFE56 = 0x69
VIN
OUTA
OUTC
VOUT
SR2
OUTB
OUTD
SR1
SAMPLE
AND HOLD
WITH RESET
CS1
INPUT
VS BALANCE
ALGORITHM
VS BALANCE
EDGE SELECT
REGISTERS
ADP1055
Figure 66. Simplified Internal Structure of the Volt-Second Balance Circuit
Rev. A | Page 38 of 140
PWM
12004-115
1.
Data Sheet
ADP1055
FAULT RESPONSES AND STATE MACHINE MECHANICS
When a potentially abnormal condition occurs in the power
supply that is regulated by the ADP1055, a flag is asserted and
the system waits for a programmed debounce time. If the flag is
continuously asserted until the end of the debounce time, it is
latched as a fault. The fault is then processed according to the
programmed fault response setting. The fault is cleared only when
the flag condition is removed. The debounce circuitry is reset when
the flag condition is removed; until then the fault remains set.
FLAGS
PRIORITY OF FAULTS
The ADP1055 also has a set of latched fault registers (Register
0xFE8C to Register 0xFE93). The latched fault registers have the
same flags as the PMBus STATUS_x commands (Register 0x7A
to Register 0x80), but the flags in the latched registers remain set
so that intermittent faults can be detected. The CLEAR_FAULTS
command (Register 0x03) clears the latched fault registers and
resets all the flags.
The response to each fault is configurable and is based on a priority
level (see Table 7). A higher number indicates a higher priority.
Table 7. Priority of Faults
Priority
12 (highest)
11
10
9
8
7
6
5
4
3
2
1 (lowest)
Fault and Configured Fault Response
Voltage fault: disable output
Voltage fault: shutdown with no retry
Current fault: shutdown with no retry
Voltage fault: shutdown with limited retry
Current fault: shutdown with limited retry
Voltage fault: shutdown with unlimited retry
Current fault: shutdown with unlimited retry
Voltage fault: wait delay and shutdown with
limited or unlimited retry
Current fault: constant current with wait delay
Current fault: constant current without tripping
VOUT_LV
Current fault: constant current mode
Voltage fault: ignore fault
The ADP1055 has an extensive set of flags that are set when
certain limits, conditions, and thresholds are exceeded. The
response to these flags is individually programmable. Flags can
be ignored or used to trigger actions such as turning off certain
PWM outputs or entering constant current mode. Flags can also
be used to turn off the power supply. The ADP1055 can be programmed to respond when these flags are reset.
FIRST FAULT ID (FFID)
The first fault ID (FFID) information is used to capture the first
fault that caused the system to shut down. Register 0xFE95 contains
the ID of the first fault that caused the system to shut down. Faults
captured in the first fault ID register have configured actions of
shutdown immediate, shutdown with retries, and disable PWM
outputs with watchdog timeout. The contents of Register 0xFE95
cannot be overwritten unless the information is first cleared.
The FFID can be cleared by the CLEAR_FAULTS command
(Register 0x03), by a power cycle of the device, or by a PSON
signal using Register 0x01, Register 0x02, or both. If the black
box feature is enabled, the FFID can also be cleared when the
information is saved into the black box.
Table 8. Example First Fault ID Scenarios
Test Setup
OCP has retry/delay of 100 ms
with Priority 10, debounce = 0.
OVP has retry/delay of 200 ms
with Priority 9, debounce = 0.
OCP has retry/delay of 100 ms
with Priority 10, debounce = 0.
OVP has retry/delay of 0 ms with
Priority 11, debounce = 0.
OCP has retry/delay of 100 ms
with Priority 8, debounce = 5 ms.
OVP has retry/delay of 200 ms
with Priority 9, debounce = 100 ms.
OCP has retry/delay of 100 ms
with Priority 8, debounce = 0.
OVP has retry/delay of 200 ms
with Priority 7, debounce = 0.
Condition
OCP occurs at t = 0.
OVP occurs at t = 10 ms.
Result
OCP fault is processed due to smaller debounce time (no retry time), as
well as higher priority.
OCP occurs at t = 0.
OVP occurs at t = 10 ms.
OCP fault is processed at t = 0; device waits 100 ms before action is taken.
OCP fault is replaced by OVP, and then OVP fault is processed at t = 10 ms
due to higher priority even though retry delay is larger.
OCP occurs at t = 50 ms.
OVP occurs at t = 0.
OVP is registered as a fault at t = 100 ms. OCP is registered as a fault at
t = 55 ms. However, at t = 100 ms, OCP loses priority and OVP is processed
due to higher priority. Exception: If delay of OCP was smaller (for example,
5 ms), then OCP action is processed.
OCP fault is processed due to higher priority.
OCP occurs at t = 0.
OVP occurs at t = 0.
Rev. A | Page 39 of 140
ADP1055
Data Sheet
Using the priority of faults (see the Priority of Faults section),
the fault that causes the ADP1055 to shut down is the one stored
in the FFID. For example, a configuration includes these faults:


OVP fault with a delay of 100 ms and five retry times
OCP fault with an action to shut down immediately with a
0 ms delay
If the OVP fault occurs and after the third retry attempt, the
OCP fault occurs, the OCP fault is stored in the FFID register.
On the other hand, if all five OVP retries occur before the OCP
fault occurs, the OVP fault is stored in the FFID. This statement
is true only if Register 0xFE_48[1:0] is set to 01. If it is set to 10,
the FFID is set to OVP on the first retry time.
Note that warning flags such as IOUT_OC_WARN and
VOUT_OV_WARN do not have debounce times.
The ADP1055 has a fault handler that can detect and track
faults and, in the case where a fault is programmed to shut
down and retry (restart) the system, the fault handler cycles the
ADP1055 through a shutdown and soft start procedure.
Throughout the soft start ramp, the fault handler continues to
monitor the device for any faults that can trigger a fault
response. Soft start blanking can be configured to ignore faults
during the soft start ramp.
If a fault condition triggers a shutdown-retry cycle, the fault
handler tracks the number of retry attempts of the programmed
fault response and permanently shuts down the device when the
configured number of retry times is reached. A shutdown-retry
cycle is considered successful if the triggering fault is cleared at
the end of the soft start ramp, at which point voltage regulation
is achieved. Following a successful retry attempt, the fault handler
removes the fault from its queue, clears all retry attempt counters,
and monitors the device for the next highest priority fault.
Debounce times can be added to a flag condition to effectively
delay the fault condition beyond the end of the soft start ramp.
Note that the fault handler considers this a successful retry
attempt (because no fault is seen when transitioning from soft
start to normal operation). The fault handler clears the fault and
resets the retry counters. For example, consider a TON_RISE
time of 10 ms, with a fault response set to shut down and retry
three times, and a flag condition that occurs during the soft
start ramp (t1 < 10 ms). If the debounce time (td) is small
enough such that t1 + td < TON_RISE, the fault condition is
latched before the end of the soft start ramp, and the ADP1055
shuts down and retries accordingly, while incrementing the
retry counter.
The delayed fault initiates another set of three shutdown-retry
cycles. This behavior effectively causes the system to retry
indefinitely, even though the fault response is programmed to
retry only three times.
A notable exception is TON_MAX_FAULT when overshoot
protection is enabled. If the ADP1055 detects an out-ofregulation condition for x consecutive switching cycles during
the soft start ramp (that is, the output voltage does not track the
desired ramp-up voltage), the ADP1055 tries to remedy the
situation by exiting soft start and retrying. As a result, the soft
start ramp ends prematurely, which has the effect of resetting
the retry counter.
Table 9 provides a summary of faults and respective debounce
times.
FAULT CONDITION DURING SOFT START AND
SOFT STOP
If a fault condition occurs during soft start, the controller responds
as programmed unless the flag is blanked. Flag blanking during
soft start and soft stop is programmed in Register 0xFE46 and
Register 0xF47, respectively.
If a fault (for example, TON_MAX or IIN_OC) occurs at any
time during the soft start process with an action set to a value
other than shutdown, the remainder of the soft start ramp
continues at the transition rate specified by the PMBus
command VOUT_TRANSITION_RATE (Register 0x27).
During soft start, the TON_MAX fault is valid; after output
regulation is reached, the UVP fault is valid. This means that
the system does not start monitoring for UVP fault until after
the soft-start ramp-up.
WATCHDOG TIMER
In the case where the voltage fault response is set to disable the
outputs and wait for the faults to clear (Bits[7:6] = 11), the
ADP1055 disables the PWM outputs but does not immediately
shut down and restart through a soft start cycle. The ADP1055
keeps the PWM outputs disabled until the fault is cleared, after
which the PWM outputs are reenabled.
If the fault is not cleared, the system can potentially remain in a
dormant condition for an infinitely long time. To prevent this
condition, a watchdog timer can be set to time out the fault
condition. The WDT_SETTING command (Register 0xFE3F)
is used to set a timeout of 0 sec, 1 sec, 5 sec, or 10 sec, after
which the system shuts down, captures the FFID, and requires a
power-up (CTRL pin or OPERATION command) to restart.
After three retries, the ADP1055 shuts down, requiring a
power-up to start again. However, if the debounce time (td) is
large enough such that t1 + td > TON_RISE, the fault condition
is latched after the ADP1055 transitions from soft start to
normal operation. In this scenario, the fault condition is cleared
and the retry counter is reset at the end of the soft start ramp.
Rev. A | Page 40 of 140
Data Sheet
ADP1055
Table 9. Summary of Faults with Debounce Times
Function/PMBus
Command
VOUT_OV_FAST
Pin
OVP
Comments
An analog comparator on this pin provides this protection.
Debounce
0xFE2F[1:0]
LSB
VOUT_OV
VS±
0xFE30[3:0]
1.6/27
VOUT_OV_WARN
VOUT_UV_WARN
VOUT_UV
VS±
VS±
VS±
N/A
N/A
0xFE30[10:8]
1.6/27
1.6/29
1.6/29
N/A
N/A
VOUT_UV_FAULT_R
ESPONSE
IOUT_OC
CS2±
The ADC on this pin is averaged every 82 μs with 7-bit
accuracy for this fault. This information is compared with
the VOUT_OV_FAULT_LIMIT to set the flag.
Same as VOUT_OV.
Same as VOUT_UV.
The ADC on this pin is averaged every 328 μs with 9-bit
accuracy for this fault. This information is compared with
the VOUT_UV_FAULT_LIMIT to set the flag.
The ADC on this pin is averaged every 2.6 ms with 12-bit
accuracy for this fault. This information is compared with
the IOUT_OC_FAULT_LIMIT to set the flag.
The ADC on this pin is averaged every 328 μs with 9-bit
accuracy for CC mode. This information is compared with
the IOUT_OC_FAULT_LIMIT ± the threshold set in Register
0xFE5D[2:0] to enter CC mode. For turbo mode, the
averaging is every 41 μs with an equivalent 6-bit
resolution.
The ADC on this pin is averaged every 10.5 ms with 12-bit
accuracy for this fault. This information is compared with
the IOUT_OC_LV_FAULT_LIMIT to set the flag.
An analog comparator on this pin provides this protection.
0xFE31[3:0]
IOUT_OC:
CS2_Range/212
IOUT_OC_
FAULT_RESPONSE
IOUT_OC_LV
CS2±
IOUT_OC_FAST
CS2±
IOUT_UC
CS2±
IOUT_UC_FAST
CS2±
IIN_OC
CS1
IIN_OC_FAST
The ADC on this pin is averaged every 10.5 ms with 12-bit
accuracy for this fault. This information is compared with
IOUT_UC_FAULT_LIMIT to set the flag.
The ADC on this pin is averaged every 328 μs with 9-bit
accuracy for constant current mode. This information is
compared with the IOUT_UC_FAULT_LIMIT ± the threshold
set in Register 0xFE5D[2:0] to enter CC mode. For turbo
mode, the averaging is every 41 μs with an equivalent 6-bit
resolution.
An analog comparator on this pin provides this protection.
CC mode:
CS2_Range/29
CC turbo mode:
CS2_Range/26
0xFE30[15:14]
CS2_Range/212
0xFE2D[1:0]
0xFE31[7:4]
IOUT_UC:
CS2_Range/212
IOUT_OC_FAST_
FAULT_RESPONSE
IOUT_UC_FAULT_
RESPONSE
CC mode:
CS2_Range/29
CC turbo mode:
CS2_Range/26
0xFE2E[0]
1.6/212
0xFE31[11:8]
CS1
The ADC on this pin is averaged every 10.5 ms with 12-bit
accuracy for this fault. This information is compared with
the IOUT_OC_FAULT_LIMIT to set the flag.
An analog comparator on this pin provides this protection.
ISHARE
CS2±
When maximum limit to change output voltage is reached.
0xFE31[15:12]
IOUT_OC_WARN
VIN_LOW
CS2±
VFF
N/A
CS2_Range/212
1.6/29
VIN_UV
VFF
0xFE30[13:11]
1.6/29
VIN_UV_WARN
VIN_OV
VFF
VFF
N/A
0xFE30[7:4]
1.6/29
VIN_OV_WARN
POUT_OP
VFF
N/A
Same as IOUT_OC.
The ADC on this pin is averaged every 328 μs with 9-bit
accuracy for this fault. This information is compared with
the VIN_LOW to set the flag.
The ADC on this pin is averaged every 328 μs with 9-bit
accuracy for this fault. This information is compared with
the VIN_UV_FAULT_LIMIT to set the flag.
Same as VIN_UV.
The ADC on this pin is averaged every 328 μs with 9-bit
accuracy for this fault. This information is compared with
the VIN_OV_FAULT_LIMIT to set the flag.
Same as VIN_OV.
The multiplication of VS and CS2 ADCs averaged every
2.6 ms with 11-bit accuracy for this fault. This information is
compared with the POUT_OP_FAULT_LIMIT to set the flag.
Rev. A | Page 41 of 140
Fault response
Command
VOUT_OV_FAST_
RESPONSE
VOUT_OV_FAULT_
RESPONSE
0xFE2C[1:0]
N/A
0xFE32[11:8]
IOUT_UC_FAST_
FAULT_RESPONSE
IIN_OC_FAULT_
RESPONSE
IIN_OC_FAST_
FAULT_RESPONSE
ISHARE_FAULT_
RESPONSE
VIN_UV_FAULT_
RESPONSE
N/A
VIN_OV_FAULT_
RESPONSE
POUT_OP_FAULT_
RESPONSE
ADP1055
Data Sheet
Function/PMBus
Command
OT
Pin
N/A
OT_WARN
GPIOx_FAULT
N/A
GPIOx
N/A
0xFE32[15:0]
TON_MAX
N/A
Immediate.
0xFE32[7:4]
1.6/29 for VS
TON_MAX_WARN
VDD/VCORE_OV
N/A
VDD
VCORE
VDD
N/A
0xFE4D[5]
1.6/29 for VS
Immediate.
Immediate.
0xFE4D[4]
VDD UV
Debounce
0xFE32[3:0]
Fault response
Command
OT_FAULT_
RESPONSE
Comments
The ADC on this pin is averaged every 200 ms with 14-bit
accuracy for this fault to provide two consecutive readings
(external forward and external reverse temperature
sensors). This information is compared with the
OT_FAULT_LIMIT to set the flag. If external reverse is
disabled, the averaging is performed every 130 ms.
Same as OT.
Immediate.
LSB
GPIOx_FAULT_
RESPONSE
TON_MAX_FAULT_
RESPONSE
0xFE4D[6]
Shutdown
STANDARD PMBUS FLAGS
Figure 67 shows the standard PMBus flags supported by the ADP1055.
STATUS_VOUT
STATUS_INPUT
7 VOUT_OV_FAULT
STATUS_WORD
(UPPER BYTE)
6 VOUT_OV_WARNING
5 VOUT_UV_WARNING
4 VOUT_UV_FAULT
3 VOUT_MAX WARNING
2 TON_MAX_FAULT
1 TOFF_MAX_WARNING
0 VOUT TRACKING ERROR
7 VIN_OV_FAULT
6 VIN_OV_WARNING
5 VIN_UV_WARNING
7 VOUT
6 IOUT/POUT
5 INPUT
4 VIN_UV_FAULT
3 UNIT OFF FOR LOW INPUT VOLTAGE
4 MFR_SPECIFIC
2 IIN_OC_FAULT
3 POWER_GOOD
2 FANS
0 PIN_OP_WARNING
1 IIN_OC_WARNING
1 OTHER
0 UNKNOWN
STATUS_IOUT
7 IOUT_OC_FAULT
6 IOUT_OC_LV_FAULT
5 IOUT_OC_WARNING
STATUS_MFR_SPECIFIC
STATUS_BYTE
ALSO IS THE LOWER BYTE OF
STATUS_WORD
7 GPIO4
6 GPIO3
5 GPIO2
4 IOUT_UC_FAULT
7 BUSY
4 GPIO1
3 CURRENT SHARE FAULT
6 OFF
3 IIN_OC_FAST_FAULT
2 IN POWER LIMITING MODE
5 VOUT_OV_FAULT
2 IOUT_UC_FAST_FAULT
1 POUT_OP_FAULT
4 IOUT_OC_FAULT
1 IOUT_OC_FAST_FAULT
0 POUT_OP_WARNING
3 VIN_UV_FAULT
0 VOUT_OV_FAST
2 TEMPERATURE
1 CML
0 NONE OF THE ABOVE
STATUS_MFR_UNKNOWN
7 OT_FAULT
15 EEPROM UNLOCKED
6 OT_WARNING
14 ADAPTIVE DEAD TIME
5 UT_WARNING
13 SOFT START FILTER
4 UT_FAULT
12 SOFT START RAMP
3 RESERVED
11 MODULATION LIMIT
2 RESERVED
10 VOLT-SEC BALANCE LIMIT
1 RESERVED
9
LIGHT_LOAD_MODE (LLM)
0 RESERVED
8
CONSTANT CURRENT
7
PGOOD2_FAULT
6
PGOOD1_FAULT
5
SYNC_UNLOCK
STATUS_CML
STATUS_OTHER
4
SR OFF
7 INVALID/UNSUPPORTED COMMAND
7 RESERVED
3
ADDRESS_WARNING
6 INVALID/UNSUPPORTED DATA
6 RESERVED
2
VCORE_OV
5 PACKET ERROR CHECK FAILED
5 INPUT A FUSE/BREAKER FAULT
1
VDD_OV
4 MEMORY FAULT DETECTED
4 INPUT B FUSE/BREAKER FAULT
0
VDD_UV
3 PROCESSOR FAULT DETECTED
3 INPUT A OR-ING DEVICE FAULT
2 RESERVED
2 INPUT B OR-ING DEVICE FAULT
1 OTHER COMMUNICATION FAULT
1 OUTPUT OR-ING DEVICE FAULT
0 OTHER MEMORY OR LOGIC FAULT
0 RESERVED
Figure 67. Standard PMBus Flags Supported by the ADP1055
Rev. A | Page 42 of 140
12004-062
STATUS_TEMPERATURE
Data Sheet
ADP1055
BLACK BOX FEATURE
BLACK BOX OPERATION
The ADP1055 supports a configurable black box feature. Using
this feature, the device records to the EEPROM vital data about
the faults that cause the system to shut down. Two dedicated
EEPROM pages are used for this purpose: Page 2 and Page 3.
When the ADP1055 encounters a fault with the action to shut
down the device, a snapshot of the current telemetry is taken, as
well as the first fault that caused the shutdown (see Figure 68).
If the black box feature is enabled, this information is saved to
the EEPROM before the device shuts down.
SHUTDOWN
DEBOUNCE
VOUT
FAULT
DETECTED
If a device experiences multiple concurrent faults, the ID of the
first fault that triggers the system to shut down is captured in
the FIRST_FAULT_ID register (Register 0xFE95). The FFID
and all flag status and telemetry data are captured in the black
box at every write to the black box (see the Black Box Contents
section for a list of the data saved). The last valid byte of each
record is a PEC byte, which is used to calculate the validity of
each record stored in the EEPROM.
Following each recording, the record number (Rec_No) is
incremented, and this number is compared to the maximum
allowed number of records. If Rec_No equals the maximum
record number (158,000 or 16,000), no additional black box
recording is allowed because the EEPROM has reached its
maximum allowed erase program cycles and any additional
recording is unreliable.
BLACK BOX CONTENTS
PWM
12004-063
WRITE
Figure 68. Black Box Write Operation
This black box feature is extremely helpful in troubleshooting a
failed system during testing and evaluation. If a system is recalled
for failure analysis, it is possible to read this information from
the EEPROM to help investigate the root cause of the failure.
Only a limited number of writes to the EEPROM are allowed.
Using Register 0xFE48[1:0], the user can set the level of information that is logged in the black box, as follows:




No recording.
Only record telemetry just before the final shutdown.
Record telemetry of final shutdown and all intermittent
retry attempts (if device is set to shut down and retry).
Record telemetry of final shutdown, all retry attempts, and
normal power-down operations using the CTRL pin or the
OPERATION command.
Using Register 0xFE48[2], the user can program the maximum
number of records to 158,000 (recommended when the ambient
temperature of the ADP1055 is less than 85°C) or to 16,000
(when the ambient temperature of the ADP1055 is less than
125°C). If the number of records exceeds the programmed
value, the recording of data to the EEPROM is halted and the
STATUS_CML bit (Register 0x7E[0]) is set and remains set.
Data accumulated after the limit is reached is not reliable and
should be ignored.
Page 2 and Page 3 of the EEPROM are reserved for black box
operation. The size of each EEPROM page is 512 bytes; each
page is composed of eight records with 64 bytes each. Page 2
and Page 3 combined give a total of 16 records, which function
as a circular buffer for recording black box information.
The EEPROM is a page erase memory, and an entire page must
be erased before the page can be written to. Due to the page erase
requirement of the EEPROM, after writing the eighth record of
any page, the next page is automatically erased to allow for
continuous black box recording.
Each time a record is written in the black box, the device
increments the record number. Each EEPROM write records
the registers listed in Table 10.
PEC Byte
The packet error checking (PEC) byte at the end of each black
box record is specific to each record and is calculated using a
CRC-8 polynomial: C(x) = x8 + x2 + x1 + 1. The PEC byte is
calculated on the first four bytes of each record (called the
header block), one byte at a time. In a write to EEPROM, the
PEC byte is appended to the data and is the last valid byte of
that record. In a read from EEPROM, the header block of each
record is used to calculate an expected PEC code, and this
internally calculated PEC code is compared to the received PEC
byte. If the comparison fails, the PEC_ERR bit (STATUS_
CML[5]) is set, and that record is discarded because the validity
of the data has been compromised.
Rev. A | Page 43 of 140
ADP1055
Data Sheet
Table 10. Contents of Black Box Records
BLACK BOX TIMING
Byte
Register Address
Header Block
1
Rec_No[7:0]
2
Rec_No[15:8]
3
Rec_No[23:16]
4
0xFE95
Data Block
5
0x78
Two EEPROM pages (Page 2 and Page 3) are used to store the
black box data; each page contains eight records. Due to the
page erase requirement of the EEPROM, when the black box
has completed writing the last record to either page (Rec_No =
8n − 1; n > 0, that is, 7, 15, 23, 31, and so on), a page erase
operation is automatically initiated on the other page. The erase
operation takes an additional 32 ms to complete.
6
0x79
7
0x7A
8
0x7B
9
0x7C
10
0x7D
11
0x7E
12
0x7F
13
0x80
14
0xFE94
15
0xFE94
16
0x88
17
0x88
18
0x89
19
0x89
20
0x8B
21
0x8B
22
0x8C
23
0x8C
24
0x8D
25
0x8D
26
0x8E
27
0x8E
28
0x8F
29
0x8F
30
0x94
31
0x94
32
0x95
33
0x95
34
0x96
35
0x96
PEC Block
36
PEC[7:0]
Undefined Block
37
…
64
Register Name
FIRST_FAULT_ID[7:0]
STATUS_WORD[7:0] (same as
STATUS_BYTE[7:0])
STATUS_WORD[15:8]
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
STATUS_TEMPERATURE
STATUS_CML
STATUS_OTHER
STATUS_MFR_SPECIFIC
STATUS_UNKNOWN[7:0]
STATUS_UNKNOWN[15:8]
READ_VIN[7:0]
READ_VIN[15:8]
READ_IIN[7:0]
READ_IIN[15:8]
READ_VOUT[7:0]
READ_VOUT[15:8]
READ_IOUT[7:0]
READ_IOUT[15:8]
Reserved[7:0]
Reserved[15:8]
READ_TEMPERATURE_2[7:0]
READ_TEMPERATURE_2[15:8]
READ_TEMPERATURE_3[7:0]
READ_TEMPERATURE_3[15:8]
READ_DUTY_CYCLE[7:0]
READ_DUTY_CYCLE[15:8]
READ_FREQUENCY[7:0]
READ_FREQUENCY[15:8]
READ_POUT[7:0]
READ_POUT[15:8]
During the erase operation, any PMBus transaction to the
device receives a no acknowledge (NACK), and the busy bit
(Bit 7) of STATUS_BYTE is set accordingly. At the end of the
erase operation, the device resumes normal operation. The
minimum time required to program a complete black box
record is calculated as follows:
TPROG_BBOX (MIN) = (num_of_bytes + 1) × TPROG
where:
TPROG = 30.72 μs.
num_of_bytes = 36 (36 bytes in each black box record).
If the erase operation is part of the sequence of saving data to the
black box, the additional erase time is added to TPROG_BBOX (MIN),
as follows:
TPROG_BBOX (MIN) = ~1.2 ms
TERASE = ~32 ms
TPROG_BBOX (MAX) = ~33.2 ms
When black box writing is enabled with the option to record
retry attempts (Register 0xFE48[1:0] = 10 or 11), data can be
saved between every unsuccessful attempt to restart the device.
It is recommended that the minimum retry time be set to a value
greater than 1.2 ms. If the retry time is insufficient for black box
recording, the device prolongs the retry time so that the recording
can finish before attempting to restart the power supply. This
delay may result in inconsistent retry times between successive
restart attempts. The retry time is programmed using the PMBus
commands xxx_FAULT_RESPONSE, where xxx refers to the
various configurable faults for that device.
At every eighth recording, the TERASE time is added to the
TPROG_BBOX (MIN) time, resulting in the TPROG_BBOX (MAX) time. If the
retry time is less than the maximum time, the device again delays
the restart attempt to wait for the completion of the black box
recording and the successive page erase.
Black box operation is a direct result of a fault condition that
triggers a power supply shutdown. To ensure that the black box
is written to in the event of a brownout condition, a holdup
capacitor on the VDD pin is recommended to ensure that all
the information is written to the black box before the ADP1055
reaches the UVLO threshold. (Instead of a holdup capacitor, an
equivalent capacitor from the rail where 3.3 V is derived can be
used to maintain the VDD voltage above UVLO.) The capacitor
must be large enough to maintain power to the system over a
time that exceeds TPROG_BBOX (MIN) which is approximately 10 μF
on a 10 V rail until VDD falls below UVLO.
Rev. A | Page 44 of 140
Data Sheet
ADP1055
BLACK BOX READBACK
BLACK BOX POWER SEQUENCING
Two dedicated commands can be used to read back the contents
of the black box data stored in the EEPROM. The READ_
BLACKBOX_CURR command (Register 0xF2) is a block read
command that returns the current record N (last record saved)
with all related data, as defined in the Black Box Contents section.
The READ_BLACKBOX_PREV command (Register 0xF3) is a
block read command that returns the data for the previous record
N − 1 (next-to-last record saved). Because these commands are
block read commands, the first byte received is called the
BYTE_COUNT and indicates to the PMBus master how many
more bytes to read. In the ADP1055, BYTE_COUNT = 36.
When the ADP1055 is powered up, the contents of the user
settings in the EEPROM are downloaded into the internal
registers. Immediately after this, the contents of the black box
data (that is, Page 2 and Page 3) are read from the EEPROM by
the device to determine the last valid Rec_No saved and to
determine whether a page erase operation is required before
starting up the device in normal mode.
For information about how to read from the EEPROM directly
using these commands, see the Read Operation (Byte Read and
Block Read) section. It is recommended that the GUI be used to
read back the contents of the black box; the black box data is
readily available in the GUI, which displays the data in a graphical
format.
If the highest Rec_No is located on the last record of either page
(that is, the next record to store data is at the start of the other
page) and the other page has not been erased, the ADP1055
automatically initiates a page erase to the other page to prepare
it for further black box recording. The ADP1055 performs a
soft start sequence only after the page erase is completed.
Rev. A | Page 45 of 140
ADP1055
Data Sheet
POWER SUPPLY CALIBRATION AND TRIM
The ADP1055 allows the entire power supply to be calibrated
and trimmed digitally in the production environment. The device
can calibrate items including the output voltage, input voltage,
input current, and input power, and it can trim for tolerance
errors introduced by sense resistors, current transformers, and
resistor dividers, as well as for its own internal circuitry.
The ADP1055 is factory trimmed, but it can be retrimmed by
the user to compensate for the errors introduced by external
components. The ADP1055 GUI allows the user to revert the
trim settings to their factory default values using the RESTORE_
DEFAULT_ALL command (Register 0x12). To unlock the trim
registers for write access, perform consecutive writes to TRIM_
PASSWORD (Register 0xD6) using the correct password. This
password is the same one used to unlock the EEPROM using
EEPROM_PASSWORD (Register 0xD5). The factory default
password is 0xFF.
The ADP1055 allows the user enough trim capability to trim for
external components with a tolerance of 0.5% or better. If the
ADP1055 is not trimmed in the production environment, it is
recommended that components with a tolerance of 0.1% or
better be used for the inputs to CS1, VFF, and VS± to meet the
data sheet specifications.
VOLTAGE CALIBRATION AND TRIM
The voltage sense point can be calibrated digitally to minimize
errors due to external components using the VOUT_TRIM
command (Register 0x22). This calibration can be performed in
the production environment, and the settings can be stored in
the EEPROM of the ADP1055.
The voltage sense inputs are optimized for sensing signals at
1 V. In a 12 V system, a 12:1 resistor divider is required to reduce
the 12 V signal down to 1 V. It is recommended that the output
voltage of the power supply be reduced to 1 V at this pin for best
performance. The tolerance of the resistor divider introduces
errors that must be trimmed. The ADP1055 has enough trim
range to trim out errors introduced by resistors with a tolerance
of 0.5% or better.
CS1 TRIM
The current sense can be calibrated using a dc or ac signal to
minimize errors due to external components.
Using a DC Signal
A known voltage (Vx) is applied at the CS1 pin. The CS1 ADC
should output a digital code equal to Vx/1.6 × 4096. Adjust the
CS1 gain trim register (Register 0xFE82) until the CS1 ADC
value in Register 0xFE98 reads the correct digital code. For
example, Register 0xFE98[13:2] reads a value of 1010 0000 0000
when there is 1.0 V on the CS1 pin.
Using an AC Signal
A known current (Ix) is applied to the CS1 pin. This current
passes through a current transformer, a diode rectifier, and an
external resistor (RCS1) to convert the current information to a
voltage (Vx). This voltage is fed into the CS1 pin. The voltage
(Vx) is calculated as follows:
Vx = Ix × (N1/N2) × RCS1
where N1/N2 is the turns ratio of the current transformer.
The CS1 ADC outputs a digital code equal to Vx/1.6 × 4096.
Adjust the CS1 gain trim register (Register 0xFE82) until the
CS1 ADC value in Register 0xFE98 reads the correct digital code.
VFF CALIBRATION AND TRIM
The VFF feedforward ADC (see Figure 32) is used for voltage
line feedforward and is factory trimmed. This ADC cannot be
trimmed by the user.
The VFF slow ADC requires a gain trim.
1.
2.
VPRIMARY = Vx × (R1 + R2)/R2 × (N1/N2)
where:
Vx is the voltage at the VFF pin.
N1/N2 is the turns ratio. }
The VS ADC produces a digital code equal to VS±/1.6 × 4096.
The VS± inputs require a gain trim. The following steps should
be performed before any other trim routine.
1.
2.
3.
Set the output regulation point to 100% of the nominal
value.
Enable the power supply with no load current. The power
supply output voltage is divided down by the resistor divider
to give 1 V across the VS+ and VS− differential input pins.
Adjust the VS trim register (Register 0xFE80) until the VS±
voltage value in Register 0xFE97[13:2] reads 1010 0000 0000
when there is 1.0 V on the pins.
Enable the power supply with full load current at the nominal
input voltage. The secondary peak reverse voltage on the
output rectifiers is filtered by an external RCD circuit (see
Figure 32).
To trim the VFF ADC, reverse-calculate the primary
voltage as follows:
3.
Adjust the VFF gain trim register (Register 0xFE81) until
this calculated voltage is equal to the desired primary input
voltage. For example, Register 0xFE96[13:2] reads a value
of 1010 0000 0000 when there is 1.0 V on the VFF pin.
The resistors in Figure 32 are sized such that the first time
constant, RC, is long enough to prevent overcharging of the
capacitor (roughly 200 ns in a typical application), whereas the
second time constant, (R1 + R2) × C, is long enough to keep the
average voltage constant during the rectifier off time.
Rev. A | Page 46 of 140
Data Sheet
ADP1055
PMBUS DIGITAL COMMUNICATION
FEATURES
The function of the PMBus slave is to decode the command
sent from the master device and respond as requested.
Communication is established using an I2C-like 2-wire interface
with a clock line (SCL) and data line (SDA). The PMBus slave is
designed to externally move chunks of 8-bit data (bytes) while
maintaining compliance with the PMBus protocol. The PMBus
protocol is based on the SMBus Specification (Version 2.0,
August 2000). The SMBus specification is, in turn, based on the
Philips I2C Bus Specification (Version 2.1, January 2000). The
PMBus incorporates the following features:










Slave operation on multiple device systems
7-bit addressing
100 kbits/sec and 400 kbits/sec data rates
Packet error checking
Support for the Group Command Protocol
Support for the Alert Response Address Protocol with
arbitration
General call address support
Support for clock low extension (clock stretching)
Separate multiple byte receive and transmit FIFO
Extensive fault monitoring
OVERVIEW
The PMBus slave module is a 2-wire interface that can be used
to communicate with other PMBus compliant devices. Its transfer
protocol is based on the Philips I2C transfer mechanism. The
ADP1055 is always configured as a slave device in the overall
system. The ADP1055 communicates with the master device
using one data pin (SDA) and one clock pin (SCL). Because the
ADP1055 is a slave device, it cannot generate the clock signal.
However, it is capable of clock-stretching the SCL line to put the
master device in a wait state when it is not ready to respond to
the master’s request.
Communication is initiated when the master device sends a
command to the PMBus slave device. Commands can be read
or write commands, in which case data is transferred between
the devices in a byte wide format. Commands can also be send
commands, in which case the command is executed by the slave
device upon receiving the stop bit. The stop bit is the last bit in a
complete data transfer, as defined in the PMBus/SMBus/I2C
communication protocol. During communication, the master
and slave devices send acknowledge or no acknowledge bits as a
method of handshaking between devices.
In addition, the PMBus slave on the ADP1055 supports packet
error checking (PEC) to improve reliability and communication
robustness. The ADP1055 can communicate with master PMBus
devices that support PEC, as well as with master devices that do
not support PEC. See the SMBus specification for a more detailed
description of the communication protocol.
When communicating with the master device, it is possible for
illegal or corrupted data to be received by the PMBus slave device.
In this case, the PMBus slave device should respond to the
invalid command or data, as defined by the PMBus specification,
and indicate to the master device that an error or fault condition
has occurred. This method of handshaking can be used as a first
level of defense against inadvertent programming of the slave
device that can potentially damage the chip or system.
The PMBus specification defines a set of generic PMBus
commands that is recommended for a power management
system. However, each PMBus device manufacturer can choose
to implement and support certain commands as it deems fit for
its system. In addition, the PMBus device manufacturer can
choose to implement manufacturer-specific commands whose
functions are not included in the generic PMBus command set.
The list of standard PMBus and manufacturer-specific commands
can be found in the Standard PMBus Commands Supported by
the ADP1055 section and Manufacturer Specific Commands
section.
TRANSFER PROTOCOL
The PMBus slave follows the transfer protocol of the SMBus
Specification (Version 2.0), which is based on the fundamental
transfer protocol format of the Philips I2C Bus Specification
(Version 2.1). Data transfers are byte wide, lower byte first. Each
byte is transmitted serially, most significant bit (MSB) first.
Figure 69 shows a basic transfer.
S
7-BIT
ADDRESS
R/W
A
8-BIT DATA
A
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
...
P
12004-064
The PMBus slave with PEC allows a device to interface to a
PMBus compliant master device, as specified by the PMBus
Power System Management Protocol Specification (Revision 1.2,
September 6, 2010). The PMBus slave is a 2-wire interface that
can be used to communicate with other PMBus compliant
devices and is compatible in a multimaster, multislave bus
configuration. The PMBus slave can communicate with master
PMBus devices that support packet error checking (PEC), as
well as with master devices that do not support PEC.
Figure 69. Basic Data Transfer
For an in-depth discussion of the transfer protocols, see the
SMBus and I2C specifications.
Rev. A | Page 47 of 140
ADP1055
Data Sheet
DATA TRANSFER COMMANDS
S
Data transfer using the PMBus slave is established using PMBus
commands. The PMBus specification requires that all PMBus
commands start with a slave address with the R/W bit cleared
(set to 0), followed by the command code. (The only exception
is SMBALRT Alert Response Address Protocol.)
A
PEC
BYTE
A
A
P
7-BIT
SLAVE
ADDRESS
W
A
COMMAND
CODE
12004-069
DATA
BYTE
1
A
...
DATA
BYTE
W
A
PEC
BYTE
A
A
DATA
BYTE
LOW
A
COMMAND
CODE
BYTE
COUNT = M
A
DATA
BYTE
M
PEC
BYTE
A
A
A
P
COMMAND
CODE
DATA
BYTE 1
A
A
7-BIT
SLAVE
ADDRESS
Sr
DATA
BYTE N
...
A
R
A
PEC
BYTE
NA
P
= MASTER-TO-SLAVE
P
= SLAVE-TO-MASTER
Figure 76. Block Read Protocol with PEC
S
DATA
BYTE
HIGH
A
A
12004-066
A
Figure 71. Write Byte Protocol with PEC
A
7-BIT
SLAVE
ADDRESS
DATA
BYTE
1
W
A
A
...
COMMAND
CODE
DATA
BYTE
M
A
BYTE
COUNT = M
A
Sr
7-BIT
SLAVE
ADDRESS
A
R
A
P
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
A
DATA
BYTE 1
A
...
DATA
BYTE N
A
PEC
BYTE
NA
= MASTER-TO-SLAVE
Figure 72. Write Word Protocol with PEC
= SLAVE-TO-MASTER
P
12004-072
BYTE
COUNT = N
12004-067
A
A
BYTE
COUNT = N
= SLAVE-TO-MASTER
PEC
BYTE
W
7-BIT
SLAVE
ADDRESS
S
= MASTER-TO-SLAVE
S
7-BIT
SLAVE
ADDRESS
12004-070
S
Figure 75. Block Write Protocol with PEC
COMMAND
CODE
COMMAND
CODE
A
P
Figure 74. Read Word Protocol with PEC
Figure 70. Send Protocol with PEC
W
NA
= SLAVE-TO-MASTER
= SLAVE-TO-MASTER
7-BIT SLAVE
ADDRESS
PEC
BYTE
A
A
= MASTER-TO-SLAVE
= MASTER-TO-SLAVE
S
DATA
BYTE HIGH
A
R
12004-071
W
7-BIT
SLAVE
ADDRESS
Sr
A
= SLAVE-TO-MASTER
12004-065
7-BIT SLAVE
ADDRESS
COMMAND
CODE
A
= MASTER-TO-SLAVE
S = start condition
P = stop condition
Sr = repeated start condition
W = write bit (0)
R = read bit (1)
A = acknowledge bit (0)
NA = no acknowledge bit (1)
S
W
DATA
BYTE LOW
All PMBus commands supported by the ADP1055 device follow
one of the protocol types shown in Figure 70 to Figure 77. (For
PMBus master devices that do not support PEC, the PEC byte is
removed.) Figure 70 to Figure 77 use the following abbreviations:







7-BIT
SLAVE
ADDRESS
Figure 77. Block Write and Block Read Protocol with PEC
W
DATA
BYTE
COMMAND
CODE
A
A
PEC
BYTE
A
7-BIT
SLAVE
ADDRESS
Sr
A
R
The PMBus slave module of the ADP1055 also supports
manufacturer-specific extended commands. These commands
follow the same protocol as the standard PMBus commands.
However, the command code consists of two bytes:
A
P
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
Figure 73. Read Byte Protocol with PEC
12004-068
S
7-BIT
SLAVE
ADDRESS


Command code extension: 0xFE
Extended command code: 0x00 to 0xFF
Using the manufacturer-specific extended commands, the PMBus
device manufacturer can add an additional 256 manufacturerspecific commands to its PMBus command set.
Rev. A | Page 48 of 140
Data Sheet
ADP1055
GROUP COMMAND PROTOCOL
START AND STOP CONDITIONS
In addition to the communication protocols described in the
Data Transfer Commands section, the PMBus slave supports a
special group command in which commands are sent to multiple
slaves in a single serial transmission. The commands to each
slave can be different from one another, with each set of {slaveaddress, command} separated by a repeated start (Sr) bit (see
Figure 78). At the end of a transmission to all slaves, a single
stop (P) bit is sent to initiate concurrent execution of the
received commands by all slaves.
Start and stop conditions involve serial data transitions while
the serial clock is at a logic high level. The PMBus slave device
monitors the SDA and SCL lines to detect the start and stop
conditions and transition its internal state machine accordingly.
Figure 79 shows typical start and stop conditions.
Sr
SLAVE 2
ADDRESS
Sr
SLAVE M
ADDRESS
A
COMMAND
CODE
1
W
A
COMMAND
CODE
2
W
A
W
COMMAND
CODE
M
A
DATA
1...N
Figure 79. Start and Stop Transitions
A
PEC
1
A
A
DATA
1...N
A
PEC
2
A
A
DATA
1...N
A
PEC
M
A
REPEATED START CONDITION
In general, a repeated start (Sr) condition is the absence of a stop
condition between two transfers. The PMBus communication
protocol makes use of the repeated start condition only when
performing a read access (read byte, read word, and block read).
Other uses of the repeated start condition are not allowed.
P
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
Figure 78. Group Command Protocol with PEC
CLOCK GENERATION AND STRETCHING
The ADP1055 is always a PMBus slave device in the overall
system; therefore, the device never needs to generate the clock,
which is done by the master device in the system. However, the
PMBus slave device is capable of clock stretching to put the
master in a wait state. By stretching the SCL signal during the
low period, the slave device communicates to the master device
that it is not ready and that the master device must wait.
Conditions where the PMBus slave device stretches the SCL line
low include the following:



Master device is transmitting at a higher baud rate than the
slave device.
Receive FIFO buffer of the slave device is full and must be
read before continuing to prevent a data overflow
condition.
Slave device is not ready to send data that the master has
requested.
Note that the slave device can stretch the SCL line only during the
low period. Also, whereas the I2C specification allows indefinite
stretching of the SCL line, the PMBus specification limits the
maximum time that the SCL line can be stretched, or held low,
to 25 ms, after which the ADP1055 must release the communication lines and reset its state machine.
GENERAL CALL SUPPORT
The PMBus slave is capable of decoding and acknowledging a
general call address. The PMBus device responds to both its own
address and the general call address (0x00).
Note that all PMBus commands must start with the slave address
with the R/W bit cleared (set to 0), followed by the command code.
This is also true when using the general call address to communicate with the PMBus slave device. The only exception to this
rule is when the SMBALRT alert response address is used.
ALERT RESPONSE ADDRESS (ARA)
If a PMBus slave device supports the SMBALRT hardware pin
to interrupt the master on a fault condition, the SMBus Alert
Response Address Protocol must be supported to allow communication between the master and slave on the device that triggers
the fault.
When the SMBALRT pin on the slave is asserted, the master
queries the address of the slave device that triggered the fault by
sending the alert response address (0001 to 100x). In response
to this address, the slave with the asserted SMBALRT pin
acknowledges (ACKs) the address and responds with its own
slave address (7-bit address and plus 0). If multiple slave devices
have their SMBALRT pins asserted, the slave with the lowest
address wins the arbitration and subsequently deasserts its
SMBALRT pin.
S
7-BIT
ARA
x
A
SLAVE
ADDRESS
A
PEC
BYTE
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
Figure 80. ARA Protocol with PEC
Rev. A | Page 49 of 140
A
P
12004-075
SLAVE 1
ADDRESS
12004-073
S
12004-074
Note that the PEC byte transmitted to each slave is calculated
using only its slave address, command code, and data bytes.
ADP1055
Data Sheet
PMBUS ADDRESS SELECTION
10-BIT ADDRESSING
2
Control of the ADP1055 is implemented via the I C interface.
The ADP1055 device is connected to the I2C bus as a slave device
under the control of a master device. The PMBus address of the
ADP1055 is set by connecting an external resistor from the ADD
pin to AGND. Table 11 lists the recommended resistor values
and associated PMBus addresses.
Table 11. PMBus Address Settings
PMBus
Addr 1
0x40
PMBus
Addr 2
0x50
PMBus
Addr 3
0x60
PMBus
Addr 4
0x70
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
1% Resistor (Ω)
(E96 series)
210 (or connect
to AGND)
750
1330
2050
2670
3570
4420
5360
6340
7320
8450
9530
10,700
12,100
13,700
15,000 (or connect
to VDD)
Using a resistor enables the selection of 16 different base addresses
from 0x40 to 0x4F. Additional addresses can be selected using the
SLV_ADDR_SELECT command (Register 0xD0). For example,
a device can be programmed to have an address of 0x65 by
connecting a 3.57 kΩ resistor at the ADD pin and programming
Register 0xD0[5:4] to 10 and saving to the EEPROM. The next
time that the power is cycled to the ADP1055, the device responds
to an address of 0x65. Other addresses can be selected.
2
If an incorrect resistor value is used and the resulting I C
address is close to a threshold between two addresses, the
STATUS_UNKNOWN flag is set (Register 0xFE94[3]). It is
recommended that 1% tolerance resistors be used on the ADD
pin. However, 5% resistors can be selected, but the use of some
of the addresses will not be allowed due to the overlap of
address ranges.
In addition to its programmed address, the ADP1055 responds
to the standard PMBus broadcast address (general call) of 0x00.
FAST MODE
Fast mode (400 kHz) uses essentially the same mechanics as
the standard mode of operation; the electrical specifications
and timing are most affected. The PMBus slave is capable of
communicating with a master device operating in standard
mode (100 kHz) or fast mode.
The PMBus slave device does not support 10-bit addressing as
defined in the I2C specification.
PACKET ERROR CHECKING
The PMBus controller implements packet error checking (PEC)
to improve reliability and communication robustness. Packet
error checking is implemented by appending a PEC byte at the
end of the message transfer. The PEC byte is calculated using a
CRC-8 algorithm on all ADDR, CMD, and DATA bytes from
the start to stop bits (excluding the ACK, NACK, start, restart,
and stop bits). The PEC byte is appended to the end of the
message by the device that supplied the last data byte. The
receiver of the PEC byte is responsible for calculating its
internal PEC code and comparing it to the received PEC byte.
The ADP1055 can communicate with master PMBus devices that
support PEC, as well as with master devices that do not support
PEC. If a PEC byte is available, the PMBus device checks the
PEC byte and issues an acknowledge (ACK) if the PEC byte is
correct. If the PEC byte comparison fails, the PMBus device
issues a no acknowledge (NACK) in response to the PEC byte
and does not process the command sent from the master.
The PMBus device uses built-in hardware to calculate the PEC
code using the CRC-8 polynomial, C(x) = x8 + x2 + x1 + 1. The
PEC code is calculated one byte at a time, in the order that it is
received. In a read transaction, the PMBus device appends the
PEC byte following the last data byte. In a write transaction, the
PMBus device compares the received PEC byte to the internally
calculated PEC code.
ELECTRICAL SPECIFICATIONS
All logic complies with the Electrical Specification outlined in
the PMBus Power System Management Protocol Specification
Part 1, Revision 1.2, dated September 6, 2010.
FAULT CONDITIONS
The PMBus protocol provides a comprehensive set of fault
conditions that must be monitored and reported. These fault
conditions can be grouped into two major categories: communication faults and monitoring faults.
Communication faults are error conditions associated with the
data transfer mechanism of the PMBus protocol (see the following
sections for more information).
Monitoring faults are error conditions associated with the
operation of the PMBus device, such as output overvoltage
protection, and are specific to each PMBus device. For more
information about the monitoring fault conditions, see the Fault
Responses and State Machine Mechanics section.
Rev. A | Page 50 of 140
Data Sheet
ADP1055
TIMEOUT CONDITIONS
Reading Too Few Bits (Item 10.8.3)
The SMBus specification, Version 2.0, includes three clock
stretching specifications related to timeout conditions. The
timeout conditions are described in the following sections.
Transmission is interrupted by a start or stop condition before a
complete byte (eight bits) has been read. Not supported; any
received data is ignored.
TTIMEOUT
Hosts Sends or Reads Too Few Bytes (Item 10.8.4)
A timeout condition occurs if any single SCL clock pulse is held
low for longer than the TTIMEOUT MIN of 25 ms. Upon detecting the
timeout condition, the PMBus slave device has 10 ms to abort
the transfer, release the bus lines, and be ready to accept a new
start condition. The device initiating the timeout is required to
hold the SCL clock line low for at least TTIMEOUT MAX = 35 ms,
guaranteeing that the slave device is given enough time to reset
its communication protocol.
If a host ends a packet with a stop condition before the required
bytes are sent/received, it is assumed that the host intended to
stop the transfer. Therefore, the PMBus slave does not consider
this to be an error and takes no action, except to flush any
remaining bytes in the transmit FIFO.
TLOW:SEXT
The TLOW:SEXT = 25 ms specification is defined as the cumulative
time that the SCL line is held low by the slave device in any one
message from the start to the stop condition. The PMBus slave
device is guaranteed by design not to violate this specification. If
the slave device violates this specification, the master is allowed
to abort the transaction in progress and issue a stop condition at
the conclusion of the byte transfer in progress.
TLOW:MEXT
The TLOW:MEXT = 10 ms specification is defined as the cumulative
time that the SCL line is held low by the master device in any one
byte of a message between the start-to-acknowledge, acknowledgeto-acknowledge, or acknowledge-to-stop. If this specification is
violated, the PMBus device treats it as a timeout condition and
aborts the transfer. This check is not implemented in the ADP1055.
DATA TRANSMISSION FAULTS
Data transmission faults occur when two communicating devices
violate the PMBus communication protocol. The following
items are taken from the PMBus specification (Revision 1.2,
September 6, 2010). See the PMBus specification for more
information about each fault condition.
Corrupted Data, PEC (Item 10.8.1)
This item refers to parity error checking. The PMBus slave
device compares the received PEC byte with the calculated
expected PEC byte of each transmission, starting from the start
bit to the stop bit. If the comparison fails, it responds as follows:





Send a no acknowledge (NACK) for the PEC byte.
Flush and ignore the received command and data.
Set the CML bit (Bit 1) in the STATUS_BYTE register.
Set the PEC bit (Bit 5) in the STATUS_CML register.
Notify the host through SMBALRT, if enabled.
Host Sends Too Many Bytes (Item 10.8.5)
If a host sends more bytes than are expected for the corresponding
command, the PMBus slave considers this a data transmission
fault and responds as follows:





Send a no acknowledge (NACK) for all unexpected bytes as
they are received.
Flush and ignore the received command and data.
Sets the CML bit (Bit 1) in the STATUS_BYTE register.
Set the invalid/unsupported data bit (Bit 6) in the
STATUS_CML register.
Notify the host through SMBALRT, if enabled.
Host Reads Too Many Bytes (Item 10.8.6)
If a host reads more bytes than are expected for the corresponding
command, the PMBus slave considers this a data transmission
fault and responds as follows:




Send all 1s (0xFF) as long as the host continues to request
data.
Set the CML bit (Bit 1) in the STATUS_BYTE register.
Set the Other bit (Bit 1) in the STATUS_CML register.
Notify host through SMBALRT, if enabled.
Device Busy (Item 10.8.7)
PMBus slave device is too busy to respond to a request from the
master device. This error can occur if the slave device is busy
accessing the EEPROM (for example, erasing a page, downloading
from EEPROM, or uploading to EEPROM). The PMBus slave
considers this a data transmission fault and responds as follows:





Sending Too Few Bits (Item 10.8.2)
Transmission is interrupted by a start or stop condition before a
complete byte (eight bits) has been sent. Not supported; any
transmitted data is ignored.
Rev. A | Page 51 of 140
Send an acknowledge (ACK) for the address byte.
Send a no acknowledge (NACK) for the command and
data bytes.
Send all 1s (0xFF) as long as the host continues to request
data.
Set the busy bit (Bit 7) in the STATUS_BYTE register.
Notify the host through SMBALRT, if enabled.
ADP1055
Data Sheet
DATA CONTENT FAULTS
Data Out of Range Fault (Item 10.9.4)
Data content faults occur when data transmission is successful,
but the PMBus slave device cannot process the data that is
received from the master device.
Data sent to the PMBus slave that is out of range is treated as a
data content fault. See the Invalid or Unsupported Data (Item
10.9.3) section for the actions taken by the PMBus device.
Improperly Set Read Bit in the Address Byte (Item 10.9.1)
Reserved Bits (Item 10.9.5)
All PMBus commands start with a slave address with the R/W
bit cleared to 0, followed by the command code. The only
exception is the transmission of the SMBus alert response
address (0001 to 100x). If a host starts a PMBus transaction
with R/W set in the address phase (equivalent to an I2C read),
the PMBus slave considers this a data content fault and
responds as follows:
Accesses to reserved bits are not a fault. Writes to reserved bits
are ignored, and reads from reserved bits return 0s.






Send an acknowledge (ACK) for the address byte.
Send a no acknowledge (NACK) for the command and
data bytes.
Send all 1s (0xFF) as long as the host continues to request
data.
Set the CML bit (Bit 1) in the STATUS_BYTE register.
Set the Other bit (Bit 1) in the STATUS_CML register.
Notify the host through SMBALRT, if enabled.
Invalid or Unsupported Command Code (Item 10.9.2)
If an invalid or unsupported command code is sent to the
PMBus slave, the code is considered to be a data content fault,
and the PMBus slave responds as follows:





Send a no acknowledge (NACK) for the illegal/
unsupported command byte and data bytes.
Flush and ignore the received command and data.
Set the CML bit (Bit 1) in the STATUS_BYTE register.
Set the invalid/unsupported command bit (Bit 7) in the
STATUS_CML register.
Notify the host through SMBALRT, if enabled.
Write to Read-Only Commands
If a host performs a write to a read-only command, the PMBus
slave considers this a data content fault and responds as follows:





Note that this is the same error described in the Host Sends Too
Many Bytes (Item 10.8.5) section.
Read from Write-Only Commands
If a host performs a read from a write-only command, the PMBus
slave considers this a data content fault and responds as follows:



If invalid or unsupported data is sent to the PMBus slave (for
certain commands), the PMBus slave considers this to be a data
content fault and responds as follows:




Send all 1s (0xFF) as long as the host continues to request
data.
Set the CML bit (Bit 1) in the STATUS_BYTE register.
Set the Other bit (Bit 1) in the STATUS_CML register.
Note that this is the same error described in the Host Reads Too
Many Bytes (Item 10.8.6) section.
Invalid or Unsupported Data (Item 10.9.3)

Send a no acknowledge (NACK) for all unexpected data
bytes as they are received.
Flush and ignore the received command and data.
Set the CML bit (Bit 1) in the STATUS_BYTE register.
Set the invalid/unsupported data received bit (Bit 6) in the
STATUS_CML register.
Notify the host through SMBALRT, if enabled.
Send an acknowledge (ACK) for the unsupported data
bytes (cannot send a no acknowledge (NACK) for the data
because the decoding happens only after the data is
acknowledged and sent to the decoding unit).
Flush and ignore the received command and data.
Set the CML bit (Bit 1) in the STATUS_BYTE register.
Set the invalid/unsupported data received bit (Bit 6) in the
STATUS_CML register.
Notify the host through SMBALRT, if enabled.
Rev. A | Page 52 of 140
Data Sheet
ADP1055
LAYOUT GUIDELINES
This section describes best practices to ensure optimal performance
of the ADP1055. In general, place all components as close to the
ADP1055 as possible. All signals should be referenced to their
respective grounds.
CS1 PIN
CS2+ AND CS2− PINS
EXPOSED PAD
Route the traces from the sense resistor to the ADP1055 parallel
to each other. Keep the traces close together and as far from the
switch nodes as possible.
Solder the exposed thermal pad on the underside of the ADP1055
package to the PCB AGND plane.
VS+ AND VS− PINS
Route the traces from the remote voltage sense point to the
ADP1055 parallel to each other. Keep the traces close together
and as far from the switch nodes as possible. Place a 100 nF
capacitor from VS− to AGND to reduce common-mode noise.
VDD PIN
Place decoupling capacitors as close to the device as possible. A
4.7 μF capacitor from VDD to AGND is recommended.
SDA AND SCL PINS
Route the traces to the SDA and SCL pins parallel to each other.
Keep the traces close together and as far from the switch nodes
as possible. It may be advantageous to add a filtering circuit, as
shown in Figure 81.
+5V
1
R55
100Ω
C63
33pF
2
C61
33pF
2
2
D41
1N4148
1
2
D43
1N4148
AGND
2
Place a 330 nF decoupling capacitor from the VCORE pin to
DGND, as close to the device as possible.
RES PIN
Place a 10 kΩ, 0.1% resistor from the RES pin to AGND, as
close to the device as possible.
JTD AND JRTN PINS
Route a single trace to the ADP1055 from the junction diode
using a trace to JRTN. If single-ended sensing is preferred, tie
the return to AGND using a dedicated trace. Make sure to lay
out the temperature sensor by isolating it and keeping it away
from any direct switch nodes. It is recommended that a 220 nF
to 470 nF capacitor be placed between the base-emitter junctions
of the thermal sensor.
Route the OVP traces away from any switching nodes to avoid
spuriously tripping the comparator at that pin.
SYNC PIN
1
C62
33pF
VCORE PIN
OVP PIN
D50
1N4148
C60
33pF
R56
100Ω
SDA
1
Figure 81. I C Filtering Circuit
J26
HDR1X
1
2
3
4
12004-076
SCL
D48
1N4148
Route the traces from the current sense transformer to
the ADP1055 parallel to each other. Keep the traces close
together and as far from the switch nodes as possible.
It is important to route the trace to the SYNC pin to prevent any
noise from being coupled to the information in the signal. It is
recommended that this trace be kept away from switch nodes
and routed as an internal layer so that the AGND plane acts as a
shield to this trace.
AGND AND DGND
Create an AGND ground plane (preferably in the inner layer)
and make a single-point (star) connection to the power supply
system ground. Connect DGND to AGND with a very short
trace using a star connection. It may be advantageous to have an
entire VDD plane as an additional layer for noise immunity.
Rev. A | Page 53 of 140
ADP1055
Data Sheet
EEPROM
The ADP1055 has a built-in EEPROM controller that is used to
communicate with the embedded 8k × 8-byte EEPROM. The
EEPROM, also called Flash®/EE, is partitioned into two major
blocks: the INFO block and the main block. The INFO block
contains 128 8-bit bytes (for internal use only), and the main
block contains 8k 8-bit bytes. The main block is further partitioned
into 16 pages; each page contains 512 bytes.
Wait at least 35 ms for the page erase operation to complete
before executing the next I2C command.
OVERVIEW
READ OPERATION (BYTE READ AND BLOCK READ)
The EEPROM controller provides an interface between the
ADP1055 core logic and the built-in Flash/EE. The user can
control data access to and from the EEPROM through this
controller interface. Different I2C commands are available for
the different operations to the EEPROM.
Read from Main Block, Page 0 to Page 5
The main block consists of 16 equivalent pages of 512 bytes each,
numbered Page 0 to Page 15. Page 0 and Page 1 of the main block
are reserved for storing the default settings and user settings,
respectively. Page 2 and Page 3 are reserved for storing the black
box information, and Page 4 and Page 5 are used to store the GUI
settings and factory tracking information. The user cannot perform
a page erase operation to any of Page 0 to Page 5.
Only Page 6 to Page 15 of the main block can be used to store
data. To erase any page from Page 6 to Page 15, the EEPROM
must first be unlocked for access. For instructions on how to
unlock the EEPROM, see the Unlock the EEPROM section.
A
COMMAND
CODE
A
DATA
BYTE
A
In the following example, three bytes from Page 6 are read from
the EEPROM, starting from the fifth byte of that page.
Set the number of return bytes = 3.
7-BIT SLAVE
ADDRESS
2.
0xD2
A
0x03
A
P
0x05
A
P
Set address offset = 5.
S
7-BIT
SLAVE
ADDRESS
W
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
= SLAVE-TO-MASTER
A
= SLAVE-TO-MASTER
P
= MASTER-TO-SLAVE
W
= MASTER-TO-SLAVE
12004-077
W
Before executing this command, the user must program the
number of bytes to read using the EEPROM_NUM_RD_BYTES
command (Register 0xD2). The user can also program the offset
from the page boundary where the first read byte is returned using
the EEPROM_ADDR_OFFSET command (Register 0xD3).
S
For example, to perform a page erase of Page 10, execute the
following command:
7-BIT SLAVE
ADDRESS
Data in Page 6 to Page 15 of the main block is always readable,
even with the EEPROM locked. The data in the EEPROM main
block can be read one byte at a time or in multiple bytes in series
using the EEPROM_PAGE_xx commands (Register 0xB0 to
Register 0xBF).
1.
Page 6 to Page 15 of the main block can be individually erased
using the EEPROM_PAGE_ERASE command (Register 0xD4).
S
Read from Main Block, Page 6 to Page 15
12004-078
PAGE ERASE OPERATION
Page 0 and Page 1 of the main block are reserved for storing the
default settings and user settings, respectively. Page 2 and
Page 3 are reserved for storing the black box information, and
Page 4 and Page 5 are used to store the GUI settings and factory
tracking information. These pages are intended to prevent thirdparty access to this data. To read a page from Page 0 to Page 5,
the user must first unlock the EEPROM (see the Unlock the
EEPROM section). After the EEPROM is unlocked, Page 0 to
Page 5 are readable using the EEPROM_PAGE_xx commands,
as described in the Read from Main Block, Page 6 to Page 15
section. Note that when the EEPROM is locked, a read from
Page 0 to Page 5 returns invalid data.
Figure 82. Example Erase Command
In this example, command code = 0xD4 and data byte = 0x0A.
Rev. A | Page 54 of 140
A
0xD3
A
0x00
A
12004-079
Communication is initiated by the master device sending a
command to the I2C slave device to access data from or send
data to the EEPROM. Using read and write commands, data is
transferred between devices in a byte wide format. Using a read
command, data is received from the EEPROM and transmitted
to the master device. Using a write command, data is received
from the master device and stored in the EEPROM through the
EEPROM controller. Send commands are also supported; a send
command is executed by the slave device upon receiving the stop
bit. The stop bit is the last bit in a complete data transfer, as defined
in the I2C communication protocol. For a complete description
of the I2C protocol, see the Philips I2C Bus Specification, Version 2.1,
dated January 2000.
The EEPROM allows erasing of whole pages only; therefore, to
change the data of any single byte in a page, the entire page
must first be erased (set high) for that byte to be writable.
Subsequent writes to any bytes in that page are allowed as long
as that byte has not been written to a logic low previously.
Data Sheet
S
7-BIT
SLAVE
ADDRESS
W
BYTE
COUNT = 0x03
A
A
0xB6
2.
A
DATA
BYTE 1
A
7-BIT
SLAVE
ADDRESS
Sr
...
DATA
BYTE 3
R
A
NA
P
Write four bytes to Page 9.
S
7-BIT
SLAVE
ADDRESS
W
DATA BYTE 1
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
A
A
0xB9
...
A
DATA BYTE 4
BYTE
COUNT = 4
A
A
P
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
Note that the block read command can read a maximum of
255 bytes for any single transaction.
Note that the block write command can write a maximum of
255 bytes for any single transaction.
WRITE OPERATION (BYTE WRITE AND BLOCK
WRITE)
EEPROM PASSWORD
Write to Main Block, Page 0 and Page 5
Page 0 and Page 1 of the main block are reserved for storing the
default settings and user settings, respectively. Page 2 through
Page 5 of the main block are reserved for storing the black box
information, GUI settings, and factory tracking information. The
user cannot perform a direct write operation to any page from
Page 0 to Page 5 using the EEPROM_PAGE_00 to EEPROM_
PAGE_05 commands. A user write to these pages returns a no
acknowledge. To program the register contents of Page 1 of the
main block, it is recommended that the STORE_USER_ALL
command be used (Register 0x15). See the Save Register
Settings to User Settings section.
12004-082
Read three bytes from Page 6.
12004-080
3.
ADP1055
On power-up, the EEPROM is locked and protected from
accidental writes or erases. Only reads from Page 6 to Page 15 of
the main block are allowed when the EEPROM is locked. Before
any data can be written (programmed) to the EEPROM, the
EEPROM must be unlocked for write access. After it is unlocked,
the EEPROM is opened for reading, writing, and erasing.
Unlock the EEPROM
To unlock the EEPROM, perform two consecutive writes with
the correct password (default = 0xFF) using the EEPROM_
PASSWORD command (Register 0xD5). The EEPROM_
UNLOCKED flag (Register 0xFE93, Bit 15) is set to indicate
that the EEPROM is unlocked for write access.
Write to Main Block, Page 6 to Page 15
Lock the EEPROM
Before performing a write to Page 6 through Page 15 of the
main block, the user must first unlock the EEPROM (see the
Unlock the EEPROM section).
To lock the EEPROM, write any byte other than the correct
password using the EEPROM_PASSWORD command (Register
0xD5). The EEPROM_UNLOCKED flag (Register 0xFE93,
Bit 15) is cleared to indicate that the EEPROM is locked from
write access.
Data in Page 6 to Page 15 of the EEPROM main block can be
programmed (written to) one byte at a time or in multiple bytes
in series using the EEPROM_PAGE_xx commands (Register 0xB6
to Register 0xBF). Before executing this command, the user can
program the offset from the page boundary where the first byte
is written using the EEPROM_ADDR_OFFSET command
(Register 0xD3).
If the targeted page has not yet been erased, the user can erase
the page as described in the Page Erase Operation section.
In the following example, four bytes are written to Page 9,
starting from the 256th byte of that page.
7-BIT
SLAVE
ADDRESS
W A
= MASTER-TO-SLAVE
= SLAVE-TO-MASTER
0xD3
A
0x01
A
0x00
1.
2.
3.
Enter the correct 32-bit key code using the KEY_CODE
command (Register 0xD7).
Write the old password using the EEPROM_PASSWORD
command (Register 0xD5).
Immediately write the new password using the EEPROM_
PASSWORD command (Register 0xD5).
The password is now changed to the new password. Save the new
password to the user settings by executing the STORE_USER_ALL
command (Register 0x15).
Set address offset = 256.
S
To change the EEPROM password, follow these steps:
A P
12004-081
1.
Change the EEPROM Password
Rev. A | Page 55 of 140
ADP1055
Data Sheet
DOWNLOADING EEPROM SETTINGS TO INTERNAL
REGISTERS
Download User Settings to Registers
The user settings are stored in Page 1 of the EEPROM main
block. These settings are downloaded from the EEPROM into
the registers under the following conditions:


On power-up. The user settings are automatically downloaded into the internal registers, powering the ADP1055
up in a state previously saved by the user.
On execution of the RESTORE_USER_ALL command
(Register 0x16). This command allows the user to force a
download of the user settings from Page 1 of the EEPROM
main block into the internal registers.
After the register settings are saved to the user settings, any
subsequent power cycle automatically downloads the latest
stored user information from the EEPROM into the internal
registers.
Note that execution of the STORE_USER_ALL command automatically performs a page erase to Page 1 of the EEPROM main
block, after which the register settings are stored in the EEPROM.
Therefore, it is important to wait at least 35 ms for the operation
to complete before executing the next I2C command.
EEPROM CRC CHECKSUM
As a simple method of checking that the values downloaded from
the EEPROM are consistent with the internal registers, a CRC
checksum is implemented.

Download Factory Default Settings to Registers
The factory default settings are stored in Page 0 of the EEPROM
main block. The factory default settings can be downloaded from
the EEPROM into the internal registers using the RESTORE_
DEFAULT_ALL command (Register 0x12).
Note that when this command is executed, the key code and
EEPROM passwords are also reset to their default factory
settings of 0xFFFFFFFF and 0xFF, respectively.

SAVING REGISTER SETTINGS TO THE EEPROM
The register settings cannot be saved to the factory default settings located in Page 0 of the EEPROM main block. This is to
prevent the user from accidentally overriding the factory trim
settings and default register settings.
Save Register Settings to User Settings
The register settings can be saved to the user settings located in
Page 1 of the EEPROM main block using the STORE_USER_ALL
command (Register 0x15). Before this command can be executed,
the EEPROM must first be unlocked for writing (see the Unlock
the EEPROM section).
When the data from the internal registers is saved to the
EEPROM (Page 1 of the main block), the total number of
1s from all the registers is counted and written into the
EEPROM as the last byte of information. This is called the
CRC checksum.
When the data is downloaded from the EEPROM into the
internal registers, a similar counter that sums all 1s from
the values loaded into the registers is saved. This value is
compared with the CRC checksum from the previous
upload operation.
If the values match, the download operation was successful. If
the values differ, the EEPROM download operation failed, and
the EEPROM CRC fault flag is set (Bit 4 of Register 0x7E).
To read the EEPROM CRC checksum value, execute the
EEPROM_CRC_CHKSUM command (Register 0xD1). This
command returns the CRC checksum accumulated in the
counter during the download operation.
Note that the CRC checksum is an 8-bit cyclical accumulator
that wraps around to 0 when 255 is reached.
Rev. A | Page 56 of 140
Data Sheet
ADP1055
SOFTWARE GUI
A free software GUI is available for programming and configuring
the ADP1055. The GUI is designed to be intuitive to power
supply designers and dramatically reduces power supply design
and development time.
The software includes filter design and power supply PWM
topology windows. The GUI is also an information center,
displaying the status of all readings, monitoring, and flags on
the ADP1055. The GUI takes into account all PMBus conversions;
the user need only enter the voltage and current settings (or
thresholds) in volts and amperes. All PMBus flags and readings
are also displayed in the GUI. For more information about the
GUI, see the ADP1055 product page).
12004-083
Evaluation boards are also available; for more information, see
the ADP1055 product page).
12004-084
Figure 83. Voltage Settings Window of the ADP1055 GUI
Figure 84. Monitor Window of the ADP1055 GUI
Rev. A | Page 57 of 140
ADP1055
Data Sheet
STANDARD PMBUS COMMANDS SUPPORTED BY THE ADP1055
Table 12 lists the standard PMBus commands that are implemented on the ADP1055. Many of these commands are implemented in
registers, which share the same hexadecimal value as the PMBus command code. All commands are maskable with the exceptions noted
in Table 12.
Table 12. PMBus Command List
Command Code
0x01
0x02
0x03
0x10
0x12
0x15
0x16
0x19
0x1B
0x20
0x21
0x22
0x23
0x24
0x27
0x28
0x29
0x2A
0x33
0x35
0x36
0x37
0x38
0x39
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4F
0x50
0x51
0x55
0x56
0x59
0x5A
0x5B
0x5C
0x5E
Command Name
OPERATION
ON_OFF_CONFIG
CLEAR_FAULTS
WRITE_PROTECT
RESTORE_DEFAULT_ALL
STORE_USER_ALL1
RESTORE_USER_ALL1
CAPABILITY
SMBALERT_MASK
VOUT_MODE
VOUT_COMMAND
VOUT_TRIM
VOUT_CAL_OFFSET
VOUT_MAX
VOUT_TRANSITION_RATE
VOUT_DROOP
VOUT_SCALE_LOOP
VOUT_SCALE_MONITOR
FREQUENCY_SWITCH
VIN_ON
VIN_OFF
INTERLEAVE
IOUT_CAL_GAIN
IOUT_CAL_OFFSET
VOUT_OV_FAULT_LIMIT
VOUT_OV_FAULT_RESPONSE
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
VOUT_UV_FAULT_RESPONSE
IOUT_OC_FAULT_LIMIT
IOUT_OC_FAULT_RESPONSE
IOUT_OC_LV_FAULT_LIMIT
IOUT_OC_LV_FAULT_RESPONSE
IOUT_OC_WARN_LIMIT
IOUT_UC_FAULT_LIMIT
IOUT_UC_FAULT_RESPONSE
OT_FAULT_LIMIT
OT_FAULT_RESPONSE
OT_WARN_LIMIT
VIN_OV_FAULT_LIMIT
VIN_OV_FAULT_RESPONSE
VIN_UV_FAULT_LIMIT
VIN_UV_FAULT_RESPONSE
IIN_OC_FAULT_LIMIT
IIN_OC_FAULT_RESPONSE
POWER_GOOD_ON
Command Code
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x68
0x69
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x88
0x89
0x8B
0x8C
0x8D
0x8E
0x8F
0x94
0x95
0x96
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0xAD
0xAE
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
Rev. A | Page 58 of 140
Command Name
POWER_GOOD_OFF
TON_DELAY
TON_RISE
TON_MAX_FAULT_LIMIT
TON_MAX_FAULT_RESPONSE
TOFF_DELAY
TOFF_FALL
TOFF_MAX_WARN_LIMIT
POUT_OP_FAULT_LIMIT
POUT_OP_FAULT_RESPONSE
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
STATUS_IOUT
STATUS_INPUT
STATUS_TEMPERATURE
STATUS_CML
STATUS_OTHER
STATUS_MFR_SPECIFIC
READ_VIN
READ_IIN
READ_VOUT
READ_IOUT
Reserved
READ_TEMPERATURE_2
READ_TEMPERATURE_3
READ_DUTY_CYCLE
READ_FREQUENCY
READ_POUT
PMBUS_REVISION
MFR_ID
MFR_MODEL
MFR_REVISION
MFR_LOCATION
MFR_DATE
MFR_SERIAL
IC_DEVICE_ID
IC_DEVICE_REV
EEPROM_PAGE_00
EEPROM_PAGE_01
EEPROM_PAGE_02
EEPROM_PAGE_03
EEPROM_PAGE_04
EEPROM_PAGE_05
EEPROM_PAGE_06
EEPROM_PAGE_07
EEPROM_PAGE_08
Data Sheet
Command Code
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xD0
0xD1
0xD2
ADP1055
Command Name
EEPROM_PAGE_09
EEPROM_PAGE_10
EEPROM_PAGE_11
EEPROM_PAGE_12
EEPROM_PAGE_13
EEPROM_PAGE_14
EEPROM_PAGE_15
SLV_ADDR_SELECT1
EEPROM_CRC_CHKSUM
EEPROM_NUM_RD_BYTES
Command Code
0xD3
0xD4
0xD5
0xD6
0xD7
0xF1
0xF2
0xF3
0xF4
0xF5
1
Command Name
EEPROM_ADDR_OFFSET
EEPROM_PAGE_ERASE
EEPROM_PASSWORD1
TRIM_PASSWORD
KEY_CODE1
EEPROM_INFO1
READ_BLACKBOX_CURR
READ_BLACKBOX_PREV
CMD_MASK1
EXTCMD_MASK1
This command is not maskable.
Rev. A | Page 59 of 140
ADP1055
Data Sheet
MANUFACTURER SPECIFIC COMMANDS
Table 13 lists the manufacturer-specific PMBus commands that are implemented on the ADP1055. These commands are implemented in
registers, which share the same hexadecimal value as the PMBus command code. All commands are maskable.
Table 13. Manufacturer Specific Command List
Command Code
0xFE00
0xFE01
0xFE02
0xFE03
0xFE04
0xFE05
0xFE06
0xFE07
0xFE08
0xFE09
0xFE0A
0xFE0B
0xFE0C
0xFE0D
0xFE0E
0xFE0F
0xFE10
0xFE11
0xFE12
0xFE13
0xFE14
0xFE15
0xFE16
0xFE17
0xFE18
0xFE19
0xFE1A
0xFE1B
0xFE1C
0xFE1D
0xFE1E
0xFE1F
0xFE20
0xFE21
0xFE22
0xFE23
0xFE24
0xFE25
0xFE26
0xFE27
0xFE28
0xFE29
0xFE2A
0xFE2B
0xFE2C
0xFE2D
0xFE2E
0xFE2F
Command Name
GO_CMD
NM_DIGFILT_LF_GAIN_SETTING
NM_DIGFILT_ZERO_SETTING
NM_DIGFILT_POLE_SETTING
NM_DIGFILT_HF_GAIN_SETTING
LLM_DIGFILT_LF_GAIN_SETTING
LLM_DIGFILT_ZERO_SETTING
LLM_DIGFILT_POLE_SETTING
LLM_DIGFILT_HF_GAIN_SETTING
SS_DIGFILT_LF_GAIN_SETTING
SS_DIGFILT_ZERO_SETTING
SS_DIGFILT_POLE_SETTING
SS_DIGFILT_HF_GAIN_SETTING
OUTA_REDGE_SETTING
OUTA_FEDGE_SETTING
OUTB_REDGE_SETTING
OUTB_FEDGE_SETTING
OUTC_REDGE_SETTING
OUTC_FEDGE_SETTING
OUTD_REDGE_SETTING
OUTD_FEDGE_SETTING
SR1_REDGE_SETTING
SR1_FEDGE_SETTING
SR2_REDGE_SETTING
SR2_FEDGE_SETTING
SR1_REDGE_LLM_SETTING
SR1_FEDGE_LLM_SETTING
SR2_REDGE_LLM_SETTING
SR2_FEDGE_LLM_SETTING
ADT_CONFIG
ADT_THRESHOLD
OUTA_DEAD_TIME
OUTB_DEAD_TIME
OUTC_DEAD_TIME
OUTD_DEAD_TIME
SR1_DEAD_TIME
SR2_DEAD_TIME
VSBAL_SETTING
VSBAL_OUTA_B
VSBAL_OUTC_D
VSBAL_SR1_2
FFWD_SETTING
ISHARE_SETTING
ISHARE_BANDWIDTH
IIN_OC_FAST_SETTING
IOUT_OC_FAST_SETTING
IOUT_UC_FAST_SETTING
VOUT_OV_FAST_SETTING
Command Code
0xFE30
0xFE31
0xFE32
0xFE33
0xFE34
0xFE35
0xFE36
0xFE37
0xFE38
0xFE39
0xFE3A
0xFE3B
0xFE3C
0xFE3D
0xFE3E
0xFE3F
0xFE40
0xFE41
0xFE42
0xFE43
0xFE44
0xFE45
0xFE46
0xFE47
0xFE48
0xFE49
0xFE4A
0xFE4B
0xFE4C
0xFE4D
0xFE4E
0xFE4F
0xFE50
0xFE51
0xFE52
0xFE53
0xFE55
0xFE56
0xFE57
0xFE58
0xFE59
0xFE5A
0xFE5B
0xFE5C
0xFE5D
0xFE5E
0xFE5F
0xFE60
Rev. A | Page 60 of 140
Command Name
DEBOUNCE_SETTING_1
DEBOUNCE_SETTING_2
DEBOUNCE_SETTING_3
DEBOUNCE_SETTING_4
VOUT_OV_FAST_FAULT_RESPONSE
IOUT_OC_FAST_FAULT_RESPONSE
IOUT_UC_FAST_FAULT_RESPONSE
IIN_OC_FAST_FAULT_RESPONSE
ISHARE_FAULT_RESPONSE
GPIO1_FAULT_RESPONSE
GPIO2_FAULT_RESPONSE
GPIO3_FAULT_RESPONSE
GPIO4_FAULT_RESPONSE
PWM_FAULT_MASK
DELAY_TIME_UNIT
WDT_SETTING
GPIO_SETTING
GPIO1_2_KARNAUGH_MAP
GPIO3_4_KARNAUGH_MAP
PGOOD_FAULT_DEB
PGOOD1_FAULT_SELECT
PGOOD2_FAULT_SELECT
SOFT_START_BLANKING
SOFT_STOP_BLANKING
BLACKBOX_SETTING
PWM_DISABLE_SETTING
FILTER_TRANSITION
DEEP_LLM_SETTING
DEEP_LLM_DISABLE_SETTING
OVP_FAULT_CONFIG
CS1_SETTING
CS2_SETTING
PULSE_SKIP_AND_SHUTDOWN
SOFT_START_SETTING
SR_DELAY
MODULATION_LIMIT
SYNC
DUTY_BAL_EDGESEL
DOUBLE_UPD_RATE
VIN_SCALE_MONITOR
IIN_CAL_GAIN
TSNS_SETTING
AUTO_GO_CMD
DIODE_EMULATION
CS2_CONST_CUR_MODE
NL_ERR_GAIN_FACTOR
SR_SETTING
NOMINAL_TEMP_POLE
Data Sheet
Command Code
0xFE61
0xFE62
0xFE63
0xFE64
0xFE65
0xFE66
0xFE67
0xFE80
0xFE81
0xFE82
0xFE86
0xFE87
0xFE88
0xFE89
0xFE8C
0xFE8D
0xFE8E
0xFE8F
ADP1055
Command Name
LOW_TEMP_POLE
LOW_TEMP_SETTING
GPIO3_4_SNUBBER_ON_TIME
GPIO3_4_SNUBBER_DELAY
VOUT_DROOP_SETTING
NL_BURST_MODE
HF_ADC_CONFIG
VS_TRIM
VFF_GAIN_TRIM
CS1_GAIN_TRIM
TSNS_EXTFWD_GAIN_TRIM
TSNS_EXTFWD_OFFSET_TRIM
TSNS_EXTREV_GAIN_TRIM
TSNS_EXTREV_OFFSET_TRIM
FAULT_VOUT
FAULT_IOUT
FAULT_INPUT
FAULT_TEMPERATURE
Command Code
0xFE90
0xFE91
0xFE92
0xFE93
0xFE94
0xFE95
0xFE96
0xFE97
0xFE98
0xFE99
0xFE9A
0xFE9B
0xFE9C
0xFE9D
0xFE9F
0xFEA0
0xFEA3
Rev. A | Page 61 of 140
Command Name
FAULT_CML
FAULT_OTHER
FAULT_MFR_SPECIFIC
FAULT_UNKNOWN
STATUS_UNKNOWN
FIRST_FAULT_ID
VFF_VALUE
VS_VALUE
CS1_VALUE
CS2_VALUE
POUT_VALUE
Reserved
TSNS_EXTFWD_VALUE
TSNS_EXTREV_VALUE
MODULATION_VALUE
ISHARE_VALUE
ADD_ADC_VALUE
ADP1055
Data Sheet
STANDARD PMBUS COMMAND DESCRIPTIONS
STANDARD PMBUS COMMANDS
OPERATION
The OPERATION command, in conjunction with the CTRL pin, is used to turn the device on and off. Illegal values are 11xxxxxx.
Table 14. Register 0x01—OPERATION
Bits
[7:6]
Bit Name
Enable
R/W
R/W
[5:0]
Reserved
R
Description
These bits determine the device response to the OPERATION command.
00 = immediate off (no sequencing).
01 = soft off (power down according to the programmed TOFF_DELAY and TOFF_FALL).
10 = device on.
11 = reserved.
Reserved.
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combination of the CTRL pin input and the OPERATION command needed to turn
the device on and off, including how the device responds when power is applied. Illegal values are xxx100xx.
Table 15. Register 0x02—ON_OFF_CONFIG
Bits
[7:5]
4
Bit Name
Reserved
Power-up control
R/W
R
R/W
3
Command
enable
R/W
2
Pin enable
R/W
1
CTRL pin polarity
R/W
0
CTRL pin powerdown action
R/W
Description
Reserved.
Sets the device power-up response.
0 = device powers up when power is present.
1 = device powers up only when commanded by the CTRL pin and the OPERATION command.
Controls how the device responds to the OPERATION command.
0 = ignores OPERATION command.
1 = the OPERATION command must be set to 1 to enable the device (in addition to setting Bit 2).
Controls how the device responds to the value of the CTRL pin.
0 = ignores the CTRL pin.
1 = CTRL pin must be asserted to enable the device (in addition to setting Bit 3).
Sets the polarity of the CTRL pin.
0 = active low.
1 = active high.
Actions to take on power-down when power-down is activated by the CTRL pin.
0 = uses the TOFF_DELAY and TOFF_FALL values to stop the transfer of energy to the output.
1 = turns off the output and stops energy transfer to the output as quickly as possible.
CLEAR_FAULTS
The CLEAR_FAULTS command is a send byte, no data. This command clears all fault bits in all PMBus status registers simultaneously.
Table 16. Register 0x03—CLEAR_FAULTS
Bits
N/A
Bit Name
CLEAR_FAULTS
Type
Send
Description
Clears all bits in the PMBus status registers (Register 0x78 to Register 0x7E) simultaneously.
WRITE_PROTECT
The WRITE_PROTECT command is used to protect the PMBus device against accidental writes. Reads to the device are allowed
regardless of the setting of this command.
Table 17. Register 0x10—WRITE_PROTECT
Bits
7
6
5
Bit Name
Write Protect 1
Write Protect 2
Write Protect 3
R/W
R/W
R/W
R/W
[4:0]
Reserved
R
Description
Setting this bit disables writes to all commands except WRITE_PROTECT.
Setting this bit disables writes to all commands except WRITE_PROTECT, OPERATION, and PAGE.
Setting this bit disables writes to all commands except WRITE_PROTECT, OPERATION, PAGE,
ON_OFF_CONFIG, and VOUT_COMMAND.
Reserved.
Rev. A | Page 62 of 140
Data Sheet
ADP1055
RESTORE_DEFAULT_ALL
Table 18. Register 0x12—RESTORE_DEFAULT_ALL
Bits
N/A
Bit Name
RESTORE_DEFAULT_ALL
Type
Send
Description
This command downloads the factory default settings from the EEPROM into operating
memory. It also resets the EEPROM password and the key code to their default values.
STORE_USER_ALL
Table 19. Register 0x15—STORE_USER_ALL
Bits
N/A
Bit Name
STORE_USER_ALL
Type
Send
Description
This command copies the entire contents of operating memory into the EEPROM (Page 1 of
the main block) as the user settings.
RESTORE_USER_ALL
Table 20. Register 0x16—RESTORE_USER_ALL
Bits
N/A
Bit Name
RESTORE_USER_ALL
Type
Send
Description
This command downloads the stored user settings from EEPROM into operating memory.
CAPABILITY
This command allows host systems to determine the capabilities of the PMBus device (default value is 0xB0).
Table 21. Register 0x19—CAPABILITY
Bits
7
Bit Name
Packet error checking
R/W
R
[6:5]
Maximum bus speed
R
4
SMBALRT
R
[3:0]
Reserved
R
Description
Checks packet error capability of the device.
1 = supported.
Checks the PMBus speed capability of the device.
01 = maximum bus speed is 400 kHz.
Checks support for the SMBALRT pin and the SMBus Alert Response Address Protocol.
1 = supported.
Reserved.
SMBALERT_MASK
Table 22. Register 0x1B—SMBALERT_MASK
Bits
[15:8]
[7:0]
Bit Name
STATUS_x command code
Mask byte
R/W
W
W
Description
Command code of the STATUS_x mask register to update.
Update mask register with this value.
VOUT_MODE
The VOUT_MODE command sets the data format for output voltage related data. The data byte for the VOUT_MODE command consists
of a 3-bit mode and 5-bit exponent parameter. The 3-bit mode determines whether the device uses linear format or direct format for the
output voltage related commands. The 5-bit parameter sets the exponent value for linear format. VOUT_MODE[7:5] must be equal to 000.
Table 23. Register 0x20—VOUT_MODE
Bits
[7:5]
Bit Name
Mode
R/W
R
[4:0]
Exponent-N
R/W
Description
Returns the output voltage data format. The value is fixed at 000, which means that only
linear data format is supported.
Twos complement N exponent used in the output voltage related commands in linear data
format (V = Y × 2N).
VOUT_COMMAND
The VOUT_COMMAND command sets the output voltage. Exponent N is set using VOUT_MODE[4:0]. Bits[7:5] must be equal to 000.
Table 24. Register 0x21—VOUT_COMMAND (Requires Use of the GO Bit in Register 0xFE00)
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
16-bit unsigned integer Y value for linear data format (V = Y × 2N). N is defined using VOUT_MODE[4:0].
Rev. A | Page 63 of 140
ADP1055
Data Sheet
VOUT_TRIM
The VOUT_TRIM command applies a fixed offset voltage to the VOUT_COMMAND value.
Table 25. Register 0x22—VOUT_TRIM
Bits
[15:0]
Bit Name
Offset trim
R/W
R/W
Description
Twos complement integer used to apply a fixed offset voltage to the VOUT_COMMAND value.
VOUT_CAL_OFFSET
The VOUT_CAL_OFFSET command is used to apply a fixed offset voltage to the VOUT_COMMAND value.
Table 26. Register 0x23—VOUT_CAL_OFFSET
Bits
[15:0]
Bit Name
Offset trim
R/W
R/W
Description
Twos complement integer used to apply a fixed offset voltage to the VOUT_COMMAND value.
VOUT_MAX
The VOUT_MAX command sets an upper limit on the output voltage. Exponent N is set using VOUT_MODE[4:0].
Table 27. Register 0x24—VOUT_MAX
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
Sets the output voltage upper limit. 16-bit unsigned integer Y value for linear data format (V = Y × 2N).
VOUT_TRANSITION_RATE
When the device receives a VOUT_COMMAND or OPERATION command that causes the output voltage to change, this command sets
the output transition rate (or slew rate), in mV/μs, at which the VS± pins change voltage.
Table 28. Register 0x27—VOUT_TRANSITION_RATE
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
VOUT_DROOP
The VOUT_DROOP command sets the rate, in mV/A, at which the output voltage decreases (or increases) with increasing (or
decreasing) output current.
Table 29. Register 0x28—VOUT_DROOP
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
VOUT_SCALE_LOOP
The VOUT_SCALE_LOOP command sets the gain (KR) by which the commanded voltage (VOUT) is scaled to generate the internal
reference voltage (VREF). VREF = VOUT × KR, where KR = Y × 2N.
Table 30. Register 0x29—VOUT_SCALE_LOOP
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
VOUT_SCALE_MONITOR
The VOUT_SCALE_MONITOR command sets the gain (KVOUT) by which the sensed output voltage at the DUT (VOUT_DUT) is scaled to
generate the reading for the READ_VOUT command. READ_VOUT = VOUT_DUT × KVOUT, where KVOUT = Y × 2N.
Table 31. Register 0x2A—VOUT_SCALE_MONITOR
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
Rev. A | Page 64 of 140
Data Sheet
ADP1055
FREQUENCY_SWITCH
The FREQUENCY_SWITCH command sets the switching frequency (in kHz) for the PMBus device. For a list of all supported switching
frequencies, see Table 244.
Table 32. Register 0x33—FREQUENCY_SWITCH (Requires Use of the GO Bit in Register 0xFE00)
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
VIN_ON
The VIN_ON command sets the value of the input voltage (V rms) at which the device starts power conversion. Setting VIN_ON = 0
effectively disables this function.
Table 33. Register 0x35—VIN_ON
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
VIN_OFF
The VIN_OFF command sets the value of the input voltage (V rms) at which the device stops power conversion. VIN_OFF is not checked
until the device reaches the regulation voltage or TON_MAX has expired.
Table 34. Register 0x36—VIN_OFF
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
INTERLEAVE
The INTERLEAVE command is used to arrange multiple devices so that their switching periods can be distributed in time.
Table 35. Register 0x37—INTERLEAVE
Bits
[15:12]
[11:8]
[7:4]
[3:0]
Bit Name
Reserved
Group ID number
Number in group
Interleave order
R/W
R
R/W
R/W
R/W
Description
Reserved.
Group identification number.
Number of units in the group.
Interleave order for this unit.
0000 = 0 × 22.5° (0 × tSW/16).
0001 = 1 × 22.5° (1 × tSW/16).
0010 = 2 × 22.5° (2 × tSW/16).
0011 = 3 × 22.5° (3 × tSW/16).
…
1111 = 15 × 22.5° (15 × tSW/16).
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command sets the ratio of the voltage at the current sense pins to the sensed current (in mΩ).
Table 36. Register 0x38—IOUT_CAL_GAIN
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
Rev. A | Page 65 of 140
ADP1055
Data Sheet
IOUT_CAL_OFFSET
The IOUT_CAL_OFFSET command is used to null any offsets in the output current sensing circuit (in amperes).
Table 37. Register 0x39—IOUT_CAL_OFFSET
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
VOUT_OV_FAULT_LIMIT
The VOUT_OV_FAULT_LIMIT command sets the upper voltage threshold (in volts) measured at the sense/output pin that causes an
overvoltage fault condition. The exponent N is set using VOUT_MODE[4:0].
Table 38. Register 0x40—VOUT_OV_FAULT_LIMIT
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
Unsigned Y-mantissa used in output voltage related commands in linear data format (V = Y × 2N).
VOUT_OV_FAULT_RESPONSE
The VOUT_OV_FAULT_RESPONSE command instructs the device on the actions to take due to an output overvoltage fault. The device
notifies the host and sets the VOUT_OV_FAULT bit in the STATUS_BYTE register, the VOUT bit in the STATUS_WORD register, and
the VOUT_OV_FAULT bit in the STATUS_VOUT register.
Table 39. Register 0x41—VOUT_OV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay time
R/W
Description
Determines the device response to an overvoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
VOUT_OV_WARN_LIMIT
The VOUT_OV_WARN_LIMIT command sets the upper voltage threshold (in volts) measured at the sense/output pin that causes an
overvoltage warning condition. The exponent N is set using VOUT_MODE[4:0]. The device notifies the host and sets the NONE_OF_THE_
ABOVE bit in the STATUS_BYTE register, the VOUT bit in the STATUS_WORD register, and the VOUT_OV_WARNING bit in the
STATUS_VOUT register.
Table 40. Register 0x42—VOUT_OV_WARN_LIMIT
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
Unsigned Y-mantissa used in output voltage related commands in linear data format (V = Y × 2N).
Rev. A | Page 66 of 140
Data Sheet
ADP1055
VOUT_UV_WARN_LIMIT
The VOUT_UV_WARN_LIMIT command sets the lower voltage threshold (in volts) measured at the sense/output pin that causes an
undervoltage warning condition. The exponent N is set using VOUT_MODE[4:0]. The device notifies the host and sets the NONE_OF_
THE_ABOVE bit in the STATUS_BYTE register, the VOUT bit in the STATUS_WORD register, and the VOUT_UV_WARNING bit in
the STATUS_VOUT register.
Table 41. Register 0x43—VOUT_UV_WARN_LIMIT
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
Unsigned Y-mantissa used in output voltage related commands in linear data format (V = Y × 2N).
VOUT_UV_FAULT_LIMIT
The VOUT_UV_FAULT_LIMIT command sets the threshold value (in volts) measured at the sense/output pin that causes an undervoltage fault condition. The exponent N is set using VOUT_MODE[4:0].
Table 42. Register 0x44—VOUT_UV_FAULT_LIMIT
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
Unsigned Y-mantissa used in output voltage related commands in linear data format (V = Y × 2N).
VOUT_UV_FAULT_RESPONSE
The VOUT_UV_FAULT_RESPONSE command instructs the device on actions to take due to an output undervoltage fault condition.
The device notifies the host and sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE register, the VOUT bit in the STATUS_WORD
register, and the VOUT_UV_FAULT bit in the STATUS_VOUT register.
Table 43. Register 0x45—VOUT_UV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to an undervoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
Rev. A | Page 67 of 140
ADP1055
Data Sheet
IOUT_OC_FAULT_LIMIT
The IOUT_OC_FAULT_LIMIT command sets the threshold value (in amperes) measured at the sense pins that causes an overcurrent
fault condition.
Table 44. Register 0x46—IOUT_OC_FAULT_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
IOUT_OC_FAULT_RESPONSE
The IOUT_OC_FAULT_RESPONSE command instructs the device on actions to take due to an output overcurrent fault condition. The
device notifies the host and sets the IOUT_OC_FAULT bit in the STATUS_BYTE register, the IOUT bit in the STATUS_WORD register,
and the IOUT_OC_FAULT bit in the STATUS_IOUT register.
Table 45. Register 0x47—IOUT_OC_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to an overcurrent fault condition.
Bit 7
Bit 6
Response
0
0
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT.
0
1
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT. If VOUT falls below the IOUT_OC_LV_FAULT_LIMIT,
respond as programmed by the retry setting (Bits[5:3]).
1
0
Continue operation in current limiting mode for the delay time (Bits[2:0]). If the
device is still in current limiting mode, respond as programmed by the retry
setting (Bits[5:3]).
1
1
Shut down, disable the output, and respond as programmed by the retry
setting (Bits[5:3]).
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
IOUT_OC_LV_FAULT_LIMIT
The IOUT_OC_LV_FAULT_LIMIT command sets the lower voltage threshold (in volts) measured at the sense/output pin that causes an
undervoltage-in-CLM fault condition. This limit applies only when the device is operating in current limiting mode (CLM).
Table 46. Register 0x48—IOUT_OC_LV_FAULT_LIMIT
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
Unsigned Y-mantissa used in output voltage related commands in linear data format (V = Y × 2N).
N is specified by VOUT_MODE[4:0].
Rev. A | Page 68 of 140
Data Sheet
ADP1055
IOUT_OC_LV_FAULT_RESPONSE
The IOUT_OC_LV_FAULT_RESPONSE command instructs the device on actions to take due to an output undervoltage-in-CLM fault
condition. The device notifies the host and sets the IOUT_OC_FAULT bit in the STATUS_BYTE register, the IOUT bit in the STATUS_
WORD register, and the IOUT_OC_LV_FAULT bit in the STATUS_IOUT register.
Table 47. Register 0x49—IOUT_OC_LV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to an undervoltage-in-CLM fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
IOUT_OC_WARN_LIMIT
The IOUT_OC_WARN_LIMIT command sets the current (in amperes) measured at the sense/output pin that causes an overcurrent
warning condition. The device notifies the host and sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE register, the IOUT bit
in the STATUS_WORD register, and the IOUT_OC_WARNING bit in the STATUS_IOUT register.
Table 48. Register 0x4A—IOUT_OC_WARN_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
Rev. A | Page 69 of 140
ADP1055
Data Sheet
IOUT_UC_FAULT_LIMIT
The IOUT_UC_FAULT_LIMIT command sets the current (in amperes) measured at the sense/output pin that causes an undercurrent
fault condition.
Table 49. Register 0x4B—IOUT_UC_FAULT_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
IOUT_UC_FAULT_RESPONSE
The IOUT_UC_FAULT_RESPONSE command instructs the device on actions to take due to an output undercurrent fault condition. The
device notifies the host and sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE register, the IOUT bit in the STATUS_WORD
register, and the IOUT_UC_FAULT bit in the STATUS_IOUT register.
Table 50. Register 0x4C—IOUT_UC_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to an undercurrent fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT. If VOUT falls below the IOUT_OC_LV_FAULT_LIMIT,
respond as programmed by the retry setting (Bits[5:3]).
1
0
Continue operation in current limiting mode for the delay time (Bits[2:0]). If the
device is still in current limiting mode, respond as programmed by the retry
setting (Bits[5:3]).
1
1
Shut down, disable the output, and respond as programmed by the retry
setting (Bits[5:3]).
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
OT_FAULT_LIMIT
The OT_FAULT_LIMIT command sets the threshold value (in °C) that causes an overtemperature fault condition.
Table 51. Register 0x4F—OT_FAULT_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
Rev. A | Page 70 of 140
Data Sheet
ADP1055
OT_FAULT_RESPONSE
The OT_FAULT_RESPONSE command instructs the device on actions to take due to an overtemperature fault condition. The device notifies the
host and sets the TEMPERATURE bit in the STATUS_BYTE register and the OT_FAULT bit in the STATUS_TEMPERATURE register.
Table 52. Register 0x50—OT_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determine the device response to an overtemperature fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
OT_WARN_LIMIT
The OT_WARN_LIMIT command sets the threshold value (in °C) for an overtemperature warning condition. The device notifies the
host and sets the TEMPERATURE bit in the STATUS_BYTE register and the OT_WARNING bit in the STATUS_TEMPERATURE register.
Table 53. Register 0x51—OT_WARN_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
VIN_OV_FAULT_LIMIT
The VIN_OV_FAULT_LIMIT command sets the upper voltage threshold (in volts) measured at the sense/input pin that causes an
overvoltage fault condition.
Table 54. Register 0x55—VIN_OV_FAULT_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
Rev. A | Page 71 of 140
ADP1055
Data Sheet
VIN_OV_FAULT_RESPONSE
The VIN_OV_FAULT_RESPONSE command instructs the device on the actions to take due to an input overvoltage fault condition. The
device notifies the host and sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE register, the INPUT bit in the STATUS_WORD
register, and the VIN_OV_FAULT bit in the STATUS_INPUT register.
Table 55. Register 0x56—VIN_OV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to an input overvoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
VIN_UV_FAULT_LIMIT
The VIN_UV_FAULT_LIMIT command sets the lower voltage threshold (in volts) measured at the sense/input pin that causes an
undervoltage fault condition.
Table 56. Register 0x59—VIN_UV_FAULT_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
VIN_UV_FAULT_RESPONSE
The VIN_UV_FAULT_RESPONSE command instructs the device on the actions to take due to an input undervoltage fault condition.
The device notifies the host and sets the VIN_UV_FAULT bit in the STATUS_BYTE register, the INPUT bit in the STATUS_WORD
register, and the VIN_UV_FAULT bit in the STATUS_INPUT register.
Table 57. Register 0x5A—VIN_UV_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
Description
Determines the device response to an input undervoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Rev. A | Page 72 of 140
Data Sheet
ADP1055
Bits
[5:3]
Bit Name
Retry setting
R/W
R/W
[2:0]
Delay times
R/W
Description
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
IIN_OC_FAULT_LIMIT
The IIN_OC_FAULT_LIMIT command sets the threshold value (in amperes) measured at the sense/input pin that causes an overcurrent
fault condition.
Table 58. Register 0x5B—IIN_OC_FAULT_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
IIN_OC_FAULT_RESPONSE
The IIN_OC_FAULT_RESPONSE command instructs the device on actions to take due to an input overcurrent fault condition. The
device notifies the host and sets the OTHER bit in the STATUS_BYTE register, the INPUT bit in the STATUS_WORD register, and the
IIN_OC_FAULT bit in the STATUS_INPUT register.
Table 59. Register 0x5C—IIN_OC_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to an input overcurrent fault condition.
Bit 7
Bit 6
Response
0
0
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT.
0
1
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT. If VOUT falls below the IOUT_OC_LV_FAULT_LIMIT,
respond as programmed by the retry setting (Bits[5:3]).
1
0
Continue operation in current limiting mode for the delay time (Bits[2:0]). If the
device is still in current limiting mode, respond as programmed by the retry
setting (Bits[5:3]).
1
1
Shut down, disable the output, and respond as programmed by the retry
setting (Bits[5:3]).
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
Rev. A | Page 73 of 140
ADP1055
Data Sheet
POWER_GOOD_ON
The POWER_GOOD_ON command sets the output voltage (in volts) at which the POWER_GOOD signal is asserted.
Table 60. Register 0x5E—POWER_GOOD_ON
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
Unsigned Y-mantissa used in output voltage related commands in linear data format (V = Y × 2N).
POWER_GOOD_OFF
The POWER_GOOD_OFF command sets the output voltage (in volts) at which the POWER_GOOD signal is deasserted.
Table 61. Register 0x5F—POWER_GOOD_OFF
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R/W
Description
Unsigned Y-mantissa used in output voltage related commands in linear data format (V = Y × 2N).
TON_DELAY
The TON_DELAY command sets the turn-on delay time in milliseconds (ms) from start (ON_OFF_CONFIG) until VOUT starts to rise.
The range is 0 ms to 1023 ms, in steps of 1 ms. The calculated value is rounded down.
Table 62. Register 0x60—TON_DELAY
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
TON_RISE
The TON_RISE command sets the rise time (in ms) from when VOUT starts to rise until the voltage enters the regulation band.
Table 63. Register 0x61—TON_RISE
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
TON_MAX_FAULT_LIMIT
The TON_MAX_FAULT_LIMIT command sets the upper time threshold (in ms) from power-up to the VOUT_UV_FAULT limit.
Table 64. Register 0x62—TON_MAX_FAULT_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
TON_MAX_FAULT_RESPONSE
The TON_MAX_FAULT_RESPONSE command instructs the device on the actions to take due to a TON_MAX fault condition. The
device notifies the host and sets the NONE_OF_THE_ABOVE bit in the STATUS_BYTE register, the VOUT bit in the STATUS_WORD
register, and the TON_MAX_FAULT bit in the STATUS_VOUT register.
Table 65. Register 0x63—TON_MAX_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
Description
Determines the device response to a TON_MAX fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Rev. A | Page 74 of 140
Data Sheet
ADP1055
Bits
[5:3]
Bit Name
Retry setting
R/W
R/W
[2:0]
Delay times
R/W
Description
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
TOFF_DELAY
The TOFF_DELAY command sets the turn-off delay time in milliseconds (ms) from stop (ON_OFF_CONFIG) until the device stops
transferring energy to the output. The range is 0 ms to 1023 ms, in steps of 1 ms. The calculated value is rounded down.
Table 66. Register 0x64—TOFF_DELAY
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
TOFF_FALL
The TOFF_FALL command sets the fall time (in ms) from the end of the turn-off delay time to voltage = 0 V.
Table 67. Register 0x65—TOFF_FALL
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
TOFF_MAX_WARN_LIMIT
The TOFF_MAX_WARN_LIMIT command sets the upper time threshold (in ms) that causes a TOFF_MAX warning condition, that is,
the time it takes to power down the output voltage from VOUT to 12.5% of VOUT. The device notifies the host and sets the NONE_OF_THE_
ABOVE bit in the STATUS_BYTE register, the VOUT bit in the STATUS_WORD register, and the TOFF_MAX_WARNING bit in the
STATUS_VOUT register.
Table 68. Register 0x66—TOFF_MAX_WARN_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
POUT_OP_FAULT_LIMIT
The POUT_OP_FAULT_LIMIT command sets the upper power threshold (in watts) measured at the sense/output pin that causes an
output overpower fault condition.
Table 69. Register 0x68—POUT_OP_FAULT_LIMIT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
Rev. A | Page 75 of 140
ADP1055
Data Sheet
POUT_OP_FAULT_RESPONSE
The POUT_OP_FAULT_RESPONSE command instructs the device on the actions to take due to an output overpower fault condition.
The device notifies the host and sets the IOUT_OC_FAULT bit in the STATUS_BYTE register, the IOUT/POUT bit in the STATUS_WORD
register, and the POUT_OP_FAULT bit in the STATUS_IOUT register.
Table 70. Register 0x69—POUT_OP_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to an overpower fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
STATUS_BYTE
The STATUS_BYTE register returns the lower byte of the STATUS_WORD register. A value of 1 in this command indicates that a fault
has occurred. As per the PMBus standard, the BUSY bit is writable to allow the user to clear that latched bit using a write command with
a 1 to Bit 7, similar to other STATUS_xxx commands. The other bits in this register cannot be cleared with a write to the STATUS_BYTE
command, but should be cleared with a write to the STATUS_VOUT, STATUS_IOUT, STATUS_INPUT, STATUS_TEMP, or
STATUS_CML command.
Table 71. Register 0x78—STATUS_BYTE
Bits
7
6
5
4
3
2
1
0
Bit Name
BUSY
POWER_OFF
VOUT_OV_FAULT
IOUT_OC_FAULT
VIN_UV_FAULT
TEMPERATURE
CML
NONE_OF_THE_ABOVE
R/W
R/W
R
R
R
R
R
R
R
Description
This bit is asserted if the device is busy and unable to respond.
This bit is asserted if the unit is not providing power to the output.
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
An input undervoltage fault has occurred.
A temperature fault or warning has occurred.
A communications, memory, or logic fault has occurred.
A fault or warning not listed in Bits[7:1] has occurred.
Rev. A | Page 76 of 140
Data Sheet
ADP1055
STATUS_WORD
The STATUS_WORD register returns the upper and lower bytes of the STATUS_WORD command. A value of 1 in this command
indicates that a fault has occurred.
Table 72. Register 0x79—STATUS_WORD
Bits
15
14
13
12
11
Bit Name
VOUT
IOUT/POUT
INPUT
MFR
POWER_GOOD
R/W
R
R
R
R
R
10
9
8
7
6
5
4
3
2
1
0
FANS
OTHER
UNKNOWN
BUSY
POWER_OFF
VOUT_OV_FAULT
IOUT_OC_FAULT
VIN_UV_FAULT
TEMPERATURE
CML
NONE_OF_THE_ABOVE
R
R
R
R/W
R
R
R
R
R
R
R
Description
Output voltage fault or warning. A bit in STATUS_VOUT is set.
Output current or output power fault or warning. A bit in STATUS_IOUT is set.
Input voltage, input current, or input power fault or warning. A bit in STATUS_INPUT is set.
Manufacturer-specific fault or warning.
POWER_GOOD is a negation of POWER_GOOD, which means that the output power is not good.
This bit is set when the sensed VOUT is less than the limit programmed in the POWER_GOOD_OFF
command.
Not supported.
A bit in STATUS_OTHER is set.
A fault or warning not listed in STATUS_WORD[15:1].
This bit is asserted if the device is busy and unable to respond.
This bit is asserted if the unit is not providing power to the output.
An output overvoltage fault has occurred.
An output overcurrent fault has occurred.
An input undervoltage fault has occurred.
A temperature fault or warning has occurred.
A communications, memory, or logic fault has occurred.
A fault or warning not listed in Bits[7:1] has occurred.
STATUS_VOUT
The STATUS_VOUT register returns the status of the output voltage. A value of 1 in this command indicates that a fault has occurred.
Table 73. Register 0x7A—STATUS_VOUT
Bits
7
6
5
4
3
2
1
0
Bit Name
VOUT_OV_FAULT
VOUT_OV_WARN
VOUT_UV_WARN
VOUT_UV_FAULT
VOUT_MAX_WARN
TON_MAX_FAULT
TOFF_MAX_WARN
VOUT_TRACKING_ERR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
An output overvoltage fault has occurred.
An output overvoltage warning has occurred.
An output undervoltage warning has occurred.
An output undervoltage fault has occurred.
An attempt was made to set the output voltage to a value greater than the VOUT_MAX command.
The device took too long to power up without reaching the VOUT_UV fault limit.
The device took too long to power down to 12.5% of its output voltage.
Not supported.
STATUS_IOUT
The STATUS_IOUT register returns the status of the output current. A value of 1 in this command indicates that a fault has occurred.
Table 74. Register 0x7B—STATUS_IOUT
Bits
7
6
5
4
3
2
1
0
Bit Name
IOUT_OC_FAULT
IOUT_OC_LV_FAULT
IOUT_OC_WARN
IOUT_UC_FAULT
ISHARE_FAULT
PLIM_MODE
POUT_OP_FAULT
POUT_OP_WARN
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
Description
An output overcurrent fault has occurred.
An output overcurrent fault and a low voltage fault have occurred.
An output overcurrent warning has occurred.
An output undercurrent fault has occurred.
A current sharing fault has occurred.
Not supported.
An output overpower fault has occurred.
Not supported.
Rev. A | Page 77 of 140
ADP1055
Data Sheet
STATUS_INPUT
The STATUS_INPUT register returns the status of the input. A value of 1 in this command indicates that a fault has occurred.
Table 75. Register 0x7C—STATUS_INPUT
Bits
7
6
5
4
3
2
1
0
Bit Name
VIN_OV_FAULT
VIN_OV_WARN
VIN_UV_WARN
VIN_UV_FAULT
VIN_LOW
IIN_OC_FAULT
IIN_OC_WARN
PIN_OP_WARN
R/W
R/W
R
R
R/W
R/W
R/W
R
R
Description
An input overvoltage fault has occurred.
Not supported.
Not supported.
An input undervoltage fault has occurred.
The device is off due to insufficient input voltage; that is, the input voltage is below the turn-off threshold.
An input overcurrent fault has occurred.
Not supported.
Not supported.
STATUS_TEMPERATURE
The STATUS_TEMPERATURE register returns temperature status. A value of 1 in this command indicates that a fault has occurred.
Table 76. Register 0x7D—STATUS_TEMPERATURE
Bits
7
6
5
4
[3:0]
Bit Name
OT_FAULT
OT_WARN
UT_WARN
UT_FAULT
Reserved
R/W
R/W
R/W
R
R
R
Description
An overtemperature fault has occurred.
An overtemperature warning has occurred.
Not supported.
Not supported.
Reserved.
STATUS_CML
The STATUS_CML register returns communications, memory, and logic (CML) status. A value of 1 in this command indicates that a
fault has occurred.
Table 77. Register 0x7E—STATUS_CML
Bits
7
6
5
4
3
2
1
0
Bit Name
CMD_ERR
DATA_ERR
PEC_ERR
CRC_ERR
PROC_ERR
Reserved
COMM_ERR
MEM_ERR
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Description
Invalid or unsupported command received.
Invalid or unsupported data received.
Packet error check failed.
Memory fault detected (for example, a CRC error).
Not supported.
Reserved.
Other communication fault not specified by Bits[7:2].
Other memory or logic fault not specified by Bits[7:2]. This bit is set if the black box record number
has been reached (Register 0xFE48[2]).
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC register returns the status of manufacturer specific faults. A value of 1 in this command indicates that a
fault has occurred.
Table 78. Register 0x80—STATUS_MFR_SPECIFIC
Bits
7
6
5
4
3
2
1
0
Bit Name
GPIO4_FAULT
GPIO3_FAULT
GPIO2_FAULT
GPIO1_FAULT
IIN_OC_FAST_FAULT
IOUT_UC_FAST_FAULT
IOUT_OC_FAST_FAULT
VOUT_OV_FAST_FAULT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
GPIO4 fault received.
GPIO3 fault received.
GPIO2 fault received.
GPIO1 fault received.
Fast input overcurrent fault received.
Fast output reverse current fault received.
Fast output overcurrent current fault received.
Fast output overvoltage fault received.
Rev. A | Page 78 of 140
Data Sheet
ADP1055
READ_VIN
The READ_VIN command returns the input voltage value (V) in linear data format (X = Y × 2N).
Table 79. Register 0x88—READ_VIN
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R
R
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
READ_IIN
The READ_IIN command returns the input current value (A) in linear data format (X = Y × 2N).
Table 80. Register 0x89—READ_IIN
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R
R
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
READ_VOUT
The READ_VOUT command returns the output voltage value (V) in linear data format (V = Y × 2N). Exponent N is set using
VOUT_MODE[4:0].
Table 81. Register 0x8B—READ_VOUT
Bits
[15:0]
Bit Name
Mantissa-Y
R/W
R
Description
Unsigned Y-mantissa used in output voltage related commands in linear data format (V = Y × 2N).
READ_IOUT
The READ_IOUT command returns the output current value (A) in linear data format (V = Y × 2N).
Table 82. Register 0x8C—READ_IOUT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R
R
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
Reserved
This register is reserved.
Table 83. Register 0x8D—Reserved
Bits
[15:0]
Bit Name
Reserved
R/W
R
Description
Reserved.
READ_TEMPERATURE_2
The READ_TEMPERATURE_2 command returns the External 1 (forward diode) temperature (°C) in linear data format (X = Y × 2N).
Table 84. Register 0x8E—READ_TEMPERATURE_2
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R
R
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
READ_TEMPERATURE_3
The READ_TEMPERATURE_3 command returns the External 2 (reverse diode) temperature (°C) in linear data format (X = Y × 2N).
Table 85. Register 0x8F—READ_TEMPERATURE_3
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R
R
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
Rev. A | Page 79 of 140
ADP1055
Data Sheet
READ_DUTY_CYCLE
The READ_DUTY_CYCLE command returns the duty cycle (%) in linear data format (X = Y × 2N).
Table 86. Register 0x94—READ_DUTY_CYCLE
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R
R
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
READ_FREQUENCY
The READ_FREQUENCY command returns the actual switching frequency value (kHz) in linear data format (X = Y × 2N).
Table 87. Register 0x95—READ_FREQUENCY
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R
R
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
READ_POUT
The READ_POUT command returns the output power (W) in linear data format (X = Y × 2N).
Table 88. Register 0x96—READ_POUT
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R
R
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
PMBUS_REVISION
The PMBUS_REVISION command returns the PMBus version information. The ADP1055 is compliant with PMBus Revision 1.2.
Reading this command results in a value of 0x22.
Table 89. Register 0x98—PMBUS_REVISION
Bits
[7:4]
[3:0]
Bit Name
Part 1 revision
Part 2 revision
R/W
R
R
Description
Compliant to PMBus Part 1 specification: 0010 = Revision 1.2.
Compliant to PMBus Part 2 specification: 0010 = Revision 1.2.
MFR_ID
The MFR_ID register stores the manufacturer ID. This register can store 23 bytes.
Table 90. Register 0x99—MFR_ID
Bits
[7:0]
Bit Name
MFR_ID
R/W
Block read/write
Description
Return the manufacturer’s ID.
MFR_MODEL
The MFR_MODEL register stores the manufacturer model number. This register can store 19 bytes.
Table 91. Register 0x9A—MFR_MODEL
Bits
[7:0]
Bit Name
Model
R/W
Block read/write
Description
Return the manufacturer’s model number.
MFR_REVISION
The MFR_REVISION register stores the manufacturer revision number. This register can store 23 bytes.
Table 92. Register 0x9B—MFR_REVISION
Bits
[7:0]
Bit Name
Revision
R/W
Block read/write
Description
Return the manufacturer’s revision number.
Rev. A | Page 80 of 140
Data Sheet
ADP1055
MFR_LOCATION
The MFR_LOCATION register stores the manufacturer location. This register can store nine bytes.
Table 93. Register 0x9C—MFR_LOCATION
Bits
[7:0]
Bit Name
Location
R/W
Block read/write
Description
Return the manufacturer’s location.
MFR_DATE
The MFR_DATE register stores the manufacturer date. This register can store 11 bytes.
Table 94. Register 0x9D—MFR_DATE
Bits
[7:0]
Bit Name
Date
R/W
Block read/write
Description
Return the manufacturer’s date.
MFR_SERIAL
The MFR_SERIAL register stores the manufacturer serial number. This register can store 13 bytes.
Table 95. Register 0x9E—MFR_SERIAL
Bits
[7:0]
Bit Name
Serial No
R/W
Block read/write
Description
Return the manufacturer’s serial number.
IC_DEVICE_ID
The IC_DEVICE_ID register stores the ID and device number of the ADP1055. The default values are 0x02, 0x41, 0x55.
Table 96. Register 0xAD—IC_DEVICE_ID
Bits
[7:0]
Bit Name
Revision
R/W
Block read/write
Description
Return the IC’s ID and device number: 0x02, 0x41, 0x55.
IC_DEVICE_REV
The IC_DEVICE_REV register stores the device revision number of the ADP1055. The default values are 0x01 and 0xREV.
Table 97. Register 0xAE—IC_DEVICE_REV
Bits
[7:0]
Bit Name
Revision
R/W
Block read/write
Description
Device revision number: 0x01 0x11.
EEPROM_PAGE_00 Through EEPROM_PAGE_15 Commands
Register 0xB0 through Register 0xBF are read/write block commands. The EEPROM_PAGE_00 through EEPROM_PAGE_15 commands
are used to read data from the EEPROM (Page 0 through Page 15) and to write data to the EEPROM (Page 6 through Page 15). For example,
EEPROM_PAGE_07 reads from and writes to Page 7 of the EEPROM main block; EEPROM_PAGE_11 reads from and writes to Page 11
of the EEPROM main block. For more information, see the EEPROM section.
EEPROM_PAGE_00
Table 98. Register 0xB0—EEPROM_PAGE_00
Bits
[7:0]
Bit Name
EEPROM_PAGE_00
R/W
Block read
Description
Reserved by manufacturer for storing the default settings.
EEPROM_PAGE_01
Table 99. Register 0xB1—EEPROM_PAGE_01
Bits
[7:0]
Bit Name
EEPROM_PAGE_01
R/W
Block read
Description
Reserved by manufacturer for storing the user settings.
Rev. A | Page 81 of 140
ADP1055
Data Sheet
EEPROM_PAGE_02
Table 100. Register 0xB2—EEPROM_PAGE_02
Bits
[7:0]
Bit Name
EEPROM_PAGE_02
R/W
Block read
Description
Reserved by manufacturer for storing black box information.
EEPROM_PAGE_03
Table 101. Register 0xB3—EEPROM_PAGE_03
Bits
[7:0]
Bit Name
EEPROM_PAGE_03
R/W
Block read
Description
Reserved by manufacturer for storing black box information.
EEPROM_PAGE_04
Table 102. Register 0xB4—EEPROM_PAGE_04
Bits
[7:0]
Bit Name
EEPROM_PAGE_04
R/W
Block read
Description
Reserved by manufacturer for storing GUI settings.
EEPROM_PAGE_05
Table 103. Register 0xB5—EEPROM_PAGE_05
Bits
[7:0]
Bit Name
EEPROM_PAGE_05
R/W
Block read
Description
Reserved by manufacturer for storing factory tracking settings.
EEPROM_PAGE_06
Table 104. Register 0xB6—EEPROM_PAGE_06
Bits
[7:0]
Bit Name
EEPROM_PAGE_06
R/W
Block read/write
Description
Block read/write of Page 6 of the EEPROM main block. The EEPROM must first be unlocked.
EEPROM_PAGE_07
Table 105. Register 0xB7—EEPROM_PAGE_07
Bits
[7:0]
Bit Name
EEPROM_PAGE_07
R/W
Block read/write
Description
Block read/write of Page 7 of the EEPROM main block. The EEPROM must first be unlocked.
EEPROM_PAGE_08
Table 106. Register 0xB8—EEPROM_PAGE_08
Bits
[7:0]
Bit Name
EEPROM_PAGE_08
R/W
Block read/write
Description
Block read/write of Page 8 of the EEPROM main block. The EEPROM must first be unlocked.
EEPROM_PAGE_09
Table 107. Register 0xB9—EEPROM_PAGE_09
Bits
[7:0]
Bit Name
EEPROM_PAGE_09
R/W
Block read/write
Description
Block read/write of Page 9 of the EEPROM main block. The EEPROM must first be unlocked.
Rev. A | Page 82 of 140
Data Sheet
ADP1055
EEPROM_PAGE_10
Table 108. Register 0xBA—EEPROM_PAGE_10
Bits
[7:0]
Bit Name
EEPROM_PAGE_10
R/W
Block read/write
Description
Block read/write of Page 10 of the EEPROM main block. The EEPROM must first be unlocked.
EEPROM_PAGE_11
Table 109. Register 0xBB—EEPROM_PAGE_11
Bits
[7:0]
Bit Name
EEPROM_PAGE_11
R/W
Block read/write
Description
Block read/write of Page 11 of the EEPROM main block. The EEPROM must first be unlocked.
EEPROM_PAGE_12
Table 110. Register 0xBC—EEPROM_PAGE_12
Bits
[7:0]
Bit Name
EEPROM_PAGE_12
R/W
Block read/write
Description
Block read/write of Page 12 of the EEPROM main block. The EEPROM must first be unlocked.
EEPROM_PAGE_13
Table 111. Register 0xBD—EEPROM_PAGE_13
Bits
[7:0]
Bit Name
EEPROM_PAGE_13
R/W
Block read/write
Description
Block read/write of Page 13 of the EEPROM main block. The EEPROM must first be unlocked.
EEPROM_PAGE_14
Table 112. Register 0xBE—EEPROM_PAGE_14
Bits
[7:0]
Bit Name
EEPROM_PAGE_14
R/W
Block read/write
Description
Block read/write of Page 14 of the EEPROM main block. The EEPROM must first be unlocked.
EEPROM_PAGE_15
Table 113. Register 0xBF—EEPROM_PAGE_15
Bits
[7:0]
Bit Name
EEPROM_PAGE_15
R/W
Block read/write
Description
Block read/write of Page 15 of the EEPROM main block. The EEPROM must first be unlocked.
SLV_ADDR_SELECT
On first power-up, a read to this command using the general call address (0x00) returns the I2C slave address of the ADP1055. Any
subsequent writes to this register overwrite this information.
Table 114. Register 0xD0—SLV_ADDR_SELECT
Bits
[7:6]
[5:4]
Bit Name
Reserved
Address, high byte
R/W
R
R/W
[3:0]
Address, low byte
R/W
Description
Returns 01.
00 = 0x40 to 0x4F (default address set by selecting resistor on the ADD pin).
01 = 0x50 to 0x5F.
10 = 0x60 to 0x6F.
11 = 0x70 to 0x7F.
Low byte of slave address (determined by the resistor value on the ADD pin).
Rev. A | Page 83 of 140
ADP1055
Data Sheet
EEPROM_CRC_CHKSUM
Table 115. Register 0xD1—EEPROM_CRC_CHKSUM
Bits
[7:0]
Bit Name
CRC checksum
R/W
R
Description
Return the CRC checksum value from the EEPROM download operation.
EEPROM_NUM_RD_BYTES
Table 116. Register 0xD2—EEPROM_NUM_RD_BYTES
Bits
[7:0]
Bit Name
Number of read bytes returned
R/W
R/W
Description
Set the number of read bytes returned when using the EEPROM_PAGE_xx commands.
EEPROM_ADDR_OFFSET
Table 117. Register 0xD3—EEPROM_ADDR_OFFSET
Bits
[15:0]
Bit Name
Address offset
R/W
R/W
Description
Sets the address offset of the current EEPROM page.
EEPROM_PAGE_ERASE
Table 118. Register 0xD4—EEPROM_PAGE_ERASE
Bits
[7:0]
Bit Name
Page erase
R/W
W
Description
Perform a page erase on the selected EEPROM page (Page 6 to Page 15). Wait 35 ms after each page
erase operation. The EEPROM must first be unlocked. Page 0 to Page 5 are reserved and their
contents must not be erased.
EEPROM_PASSWORD
Table 119. Register 0xD5—EEPROM_PASSWORD
Bits
[7:0]
Bit Name
EEPROM
password
R/W
W
Description
Write the password to this register two consecutive times to unlock the EEPROM and/or to change
the EEPROM password. The factory default password is 0xFF. To lock the EEPROM, type any value
other than the password to this register.
TRIM_PASSWORD
Table 120. Register 0xD6—TRIM_PASSWORD
Bits
[7:0]
Bit Name
Trim password
R/W
W
Description
Write the password to this register to unlock the trim registers for write access. Write the trim
password twice to unlock the register; write any other value to exit. The trim password is the same
as the EEPROM password (0xFF).
KEY_CODE
Table 121. Register 0xD7—KEY_CODE
Bits
[31:0]
Bit Name
Keycode
R/W
Block read/
write
Description
Write the 32-bit keycode to this command to unlock access to Command 0xF4 and Command 0xF5.
Write the key code password twice to unlock the commands; write any other value to lock them.
The factory default password is 0xFFFFFFFF. The procedure includes a block write of four bytes. The
readback returns five bytes; the fifth byte is 0 if locked or 1 if unlocked.
EEPROM_INFO
Table 122. Register 0xF1—EEPROM_INFO
Bits
[7:0]
Bit Name
EEPROM_INFO
R/W
Block read
Description
Block read of the manufacturer data in the EEPROM.
Rev. A | Page 84 of 140
Data Sheet
ADP1055
READ_BLACKBOX_CURR
Table 123. Register 0xF2—READ_BLACKBOX_CURR
Bits
VAR
Bit Name
R/W
Block read
Description
This command returns the data for the current record N (last record saved in the black box). For
information about the contents of the black box record, see the Black Box Contents section.
READ_BLACKBOX_PREV
Table 124. Register 0xF3—READ_BLACKBOX_PREV
Bits
VAR
Bit Name
R/W
Block read
Description
This command returns the data for the previous record N − 1 (next-to-last record saved in the black
box). For information about the contents of the black box record, see the Black Box Contents section.
CMD_MASK
The CMD_MASK command allows any PMBus command to be masked in the ADP1055. If the command is masked, a read or a write to
that command results in a no acknowledge (NACK). The STORE_USER_ALL (Register 0x15) and RESTORE_USER_ALL (Register 0x16)
commands are not maskable.
Table 125. Register 0xF4—CMD_MASK
Bits
VAR
Bit Name
Command
masking
R/W
Block
read/write
Description
This command can be used to disable (mask) any of the standard PMBus commands (Command 0x01
to Command 0xFF). To use this command, the correct key code must be written.
Block count = 0x20 (32 bytes)
Mask[255:0] = Masking status bits.
[0] = Command 0x00.
…
[255] = Command 0xFF.
EXTCMD_MASK
The EXTCMD_MASK command allows any manufacturer specific command to be masked in the ADP1055. If the command is masked,
a read or a write to that command results in a no acknowledge (NACK).
Table 126. Register 0xF5—EXTCMD_MASK
Bits
VAR
Bit Name
Command
masking
R/W
Block
read/write
Description
This command can be used to disable (mask) any of the manufacturer specific PMBus commands
(Command 0xFE00 to Command 0xFEA3). To use this command, the correct key code must be written.
Block count = 0x15 (21 bytes)
Mask[167:0] = Masking status bits.
[0] = Command 0xFE00.
…
[167] = Command 0xFEA7.
Rev. A | Page 85 of 140
ADP1055
Data Sheet
MANUFACTURER SPECIFIC PMBUS COMMAND DESCRIPTIONS
Table 127. Register 0xFE00—GO_CMD
Description
Reserved.
This bit latches Register 0xFE55.
This bit latches Register 0xFE29.
This bit latches Register 0xFE57 and Register 0xFE25.
W
2
Frequency GO
W
1
PWM GO
W
0
Voltage reference GO
W
This bit latches Register 0xFE4A, Register 0xFE01 to Register 0xFE0C, Register 0xFE5E, and
Register 0xFE66.
Update switching frequency programmed by FREQUENCY_SWITCH command
(Register 0x33).
Update Register 0xFE0D to Register 0xFE1C, Register 0xFE1F to Register 0xFE24, and
Register 0xFE15 to Register 0xFE1C
Update reference voltage commanded by the VOUT_COMMAND (Register 0x21).
POLE
20dB
HF GAIN
RANGE
20dB
R/W
R/W
W
W
W
3
Bit Name
Reserved
SYNC
VFF
Double update rate,
VS balance
Filter GO
LF GAIN RANGE
Bits
7
6
5
4
500Hz
1kHz
POLE LOCATION RANGE
5kHz
10kHz
12004-085
100Hz
20dB
ZERO
RANGE
ZERO
Figure 85. Digital Filter Programmability
Table 128. Register 0xFE01—NM_DIGFILT_LF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
LF gain setting
R/W
R/W
Description
This register determines the low frequency gain of the loop response in normal mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Table 129. Register 0xFE02—NM_DIGFILT_ZERO_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
Zero setting
R/W
R/W
Description
This register determines the position of the final zero in normal mode. See Figure 85.
Table 130. Register 0xFE03—NM_DIGFILT_POLE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
Pole setting
R/W
R/W
Description
This register determines the position of the final pole in normal mode. See Figure 85.
Table 131. Register 0xFE04—NM_DIGFILT_HF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
HF gain setting
R/W
R/W
Description
This register determines the high frequency gain of the loop response in normal mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Table 132. Register 0xFE05—LLM_DIGFILT_LF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
LF gain setting
R/W
R/W
Description
This register determines the low frequency gain of the loop response in light load mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Rev. A | Page 86 of 140
Data Sheet
ADP1055
Table 133. Register 0xFE06—LLM_DIGFILT_ZERO_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
Zero setting
R/W
R/W
Description
This register determines the position of the final zero in light load mode. See Figure 85.
Table 134. Register 0xFE07—LLM_DIGFILT_POLE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
Pole setting
R/W
R/W
Description
This register determines the position of the final pole in light load mode. See Figure 85.
Table 135. Register 0xFE08—LLM_DIGFILT_HF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
HF gain setting
R/W
R/W
Description
This register determines the high frequency gain of the loop response in light load mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Table 136. Register 0xFE09—SS_DIGFILT_LF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
LF gain setting
R/W
R/W
Description
This register determines the low frequency gain of the loop response in soft start mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Table 137. Register 0xFE0A—SS_DIGFILT_ZERO_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
Zero setting
R/W
R/W
Description
This register determines the position of the final zero in soft start mode. See Figure 85.
Table 138. Register 0xFE0B—SS_DIGFILT_POLE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
Pole setting
R/W
R/W
Description
This register determines the position of the final pole in soft start mode. See Figure 85.
Table 139. Register 0xFE0C—SS_DIGFILT_HF_GAIN_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:0]
Bit Name
HF gain setting
R/W
R/W
Description
This register determines the high frequency gain of the loop response in soft start mode. It is
programmable over a 20 dB range. Each LSB corresponds to a 0.3 dB increase. See Figure 85.
Table 140. Register 0xFE0D, Register 0xFE0F, Register 0xFE11, Register 0xFE13—OUTA_REDGE_SETTING,
OUTB_REDGE_SETTING, OUTC_REDGE_SETTING, OUTD_REDGE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[15:4]
Bit Name
t1, t3, t5, t7
R/W
R/W
3
Modulate enable
R/W
2
t1, t3, t5, t7 sign
R/W
[1:0]
Reserved
R
Description
This register contains the 12-bit t1, t3, t5, t7 time. Each LSB corresponds to 5 ns resolution.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
1 = PWM modulation acts on the t1, t3, t5, t7 edge.
0 = no PWM modulation of the t1, t3, t5, t7 edge.
1 = negative sign. Increase of PWM modulation moves t1, t3, t5, t7 right.
0 = positive sign. Increase of PWM modulation moves t1, t3, t5, t7 left.
Reserved.
Table 141. Register 0xFE0E, Register 0xFE10, Register 0xFE12, Register 0xFE14—OUTA_FEDGE_SETTING,
OUTB_FEDGE_SETTING, OUTC_FEDGE_SETTING, OUTD_FEDGE_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[15:4]
Bit Name
t2, t4, t6, t8
R/W
R/W
3
Modulate enable
R/W
2
t2, t4, t6, t8 sign
R/W
[1:0]
Reserved
R
Description
This register contains the 12-bit t2, t4, t6, t8 time. Each LSB corresponds to 5 ns resolution.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
1 = PWM modulation acts on the t2, t4, t6, t8 edge.
0 = no PWM modulation of the t2, t4, t6, t8 edge.
1 = negative sign. Increase of PWM modulation moves t2, t4, t6, t8 right.
0 = positive sign. Increase of PWM modulation moves t2, t4, t6, t8 left.
Reserved.
Rev. A | Page 87 of 140
ADP1055
Data Sheet
Table 142. Register 0xFE15, Register 0xFE17—SR1_REDGE_SETTING, SR2_REDGE_SETTING (Requires Use of the GO Bit in
Register 0xFE00)
Bits
[15:4]
Bit Name
t9, t11
R/W
R/W
3
Modulate enable
R/W
2
t9, t11 sign
R/W
[1:0]
Reserved
R
Description
This register contains the 12-bit t9, t11 time. Each LSB corresponds to 5 ns resolution.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
1 = PWM modulation acts on the t9, t11 edge.
0 = no PWM modulation of the t9, t11 edge.
1 = negative sign. Increase of PWM modulation moves t9, t11 right.
0 = positive sign. Increase of PWM modulation moves t9, t11 left.
Reserved.
Table 143. Register 0xFE16, Register 0xFE18—SR1_FEDGE_SETTING, SR2_FEDGE_SETTING (Requires Use of the GO Bit in
Register 0xFE00)
Bits
[15:4]
3
Bit Name
t10, t12
Modulate enable
R/W
R/W
R/W
2
t10, t12 sign
R/W
[1:0]
Reserved
R
Description
This register contains the 12-bit t10, t12 time. Each LSB corresponds to 5 ns resolution.
1 = PWM modulation acts on the t10, t12 edge.
0 = no PWM modulation of the t10, t12 edge.
1 = negative sign. Increase of PWM modulation moves t10, t12 right.
0 = positive sign. Increase of PWM modulation moves t10, t12 left.
Reserved.
Table 144. Register 0xFE19, Register 0xFE1B—SR1_REDGE_LLM_SETTING, SR2_REDGE_LLM_SETTING (Requires Use of the
GO Bit in Register 0xFE00)
Bits
[15:4]
Bit Name
t9, t11
R/W
R/W
3
Modulate enable
R/W
2
t9, t11 sign
R/W
[1:0]
Reserved
R
Description
This register contains the 12-bit t9, t11 time. Each LSB corresponds to 5 ns resolution. This is the
SR setting in light load mode.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
1 = PWM modulation acts on the t9, t11 edge.
0 = no PWM modulation of the t9, t11 edge.
1 = negative sign. Increase of PWM modulation moves t9, t11 right.
0 = positive sign. Increase of PWM modulation moves t9, t11 left.
Reserved.
Table 145. Register 0xFE1A, Register 0xFE1C—SR1_FEDGE_LLM_SETTING, SR2_FEDGE_LLM_SETTING (Requires Use of the
GO Bit in Register 0xFE00)
Bits
[15:4]
Bit Name
t10, t12
R/W
R/W
3
Modulate Enable
R/W
2
t10, t12 sign
R/W
[1:0]
Reserved
R
Description
This register contains the 12-bit t10, t12 time. Each LSB corresponds to 5 ns resolution. This is the
SR setting in light load mode.
The minimum and maximum possible duty cycle is 0% and 100%, respectively.
1 = PWM modulation acts on the t10, t12 edge.
0 = no PWM modulation of the t10, t12 edge.
1 = negative sign. Increase of PWM modulation moves t10, t12 right.
0 = positive sign. Increase of PWM modulation moves t10, t12 left.
Reserved.
Rev. A | Page 88 of 140
Data Sheet
ADP1055
Table 146. Register 0xFE1D—ADT_CONFIG
Bits
7
Bit Name
Averaging period
R/W
R/W
6
ADT reference
R/W
[5:3]
Update rate
R/W
[2:0]
Multiplier
R/W
Description
1 = 9-bit averaging (327 μs).
0 = 12-bit averaging (2.6 ms).
0 = CS1 as reference.
1 = CS2 as reference.
The ADT algorithm adjusts the dead time in steps of 5 ns. These bits are used to program
the number of PWM switching cycles between each step. The number is calculated as 2N + 1,
where N is the 3-bit value specified by these bits. If N = 6 (110), each PWM edge is adjusted
by 5 ns every 26 + 1 = 65 switching cycles.
These bits specify the programming step for Register 0xFE1F to Register 0xFE22, Bits[6:4] and
Bits[2:0].
Bit 2
Bit 1
Bit 0
Multiplier
0
0
0
5
0
0
1
10
0
1
0
15
0
1
1
20
1
0
0
25
1
0
1
30
1
1
0
35
1
1
1
40
Table 147. Register 0xFE1E—ADT_THRESHOLD
Bits
[7:0]
Bit Name
Adaptive dead time
threshold
R/W
R/W
Description
This register sets the ADT threshold. This 8-bit number is compared to the eight MSBs of the
CS1/CS2 value register.
When the current level measured on CS1/CS2 falls below this threshold, the edges of the PWM
signals are affected as a linear function of the CS1/CS2 current, as programmed in Register 0xFE1F
to Register 0xFE24. When this register is programmed to 0x00, the ADT function is disabled.
When CS1 is used as the reference, each LSB in this register corresponds to 1.6 V/28 = 6.25 mV.
When CS2 is used as the reference, each LSB in this register corresponds to 26.25 mV, 52.5 mV,
or 420 mV]/28 = 102.539 μV, 205.078 μV, or 1640.625 μV. Also note that when CS2 is used as the
reference, the maximum allowed value in this register is 224 (0xE0).
Table 148. Register 0xFE1F, Register 0xFE20, Register 0xFE21, Register 0xFE22—OUTA_DEAD_TIME, OUTB_DEAD_TIME,
OUTC_DEAD_TIME, OUTD_DEAD_TIME (Requires Use of the GO Bit in Register 0xFE00)
Bits
7
Bit Name
t1, t3, t5, t7, t9, t11
polarity
R/W
R/W
[6:4]
t1, t3, t5, t7, t9, t11
offset
R/W
3
t2, t4, t6, t8, t10, t12
polarity
R/W
Description
0 = positive polarity.
1 = negative polarity.
This value multiplied by Register 0xFE1D[2:0] determines the offset for t1, t3, t5, t7, t9, t11 from
nominal timing at no load.
Bit 6
Bit 5
Bit 4
Offset (ns)
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
0 = positive polarity.
1 = negative polarity.
Rev. A | Page 89 of 140
ADP1055
Bits
[2:0]
Bit Name
t2, t4, t6, t8, t10, t12
offset
Data Sheet
R/W
R/W
Description
This value multiplied by Register 0xFE1D[2:0] determines the offset for t2, t4, t6, t8, t10, t12 from
nominal timing at no load.
Bit 2
Bit 1
Bit 0
Offset (ns)
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Table 149. Register 0xFE23, Register 0xFE24—SR1_DEAD_TIME, SR2_DEAD_TIME (Requires Use of the GO Bit in Register 0xFE00)
Bits
7
Bit Name
t9, t11 polarity
R/W
R/W
[6:4]
t9, t11 offset
R/W
3
t10, t12 polarity
R/W
[2:0]
t10, t12 offset
R/W
Description
0 = positive polarity.
1 = negative polarity.
This value multiplied by Register 0xFE1D[2:0] determines the offset for t1, t3, t5, t7, t9, t11 from
nominal timing at no load.
Bit 6
Bit 5
Bit 4
Offset (ns)
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
0 = positive polarity.
1 = negative polarity.
This value multiplied by Register 0xFE1D[2:0] determines the offset for t2, t4, t6, t8, t10, t12 from
nominal timing at no load.
Bit 2
Bit 1
Bit 0
Offset (ns)
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Table 150. Register 0xFE25—VSBAL_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
7
6
5
4
3
2
Bit Name
Reserved
Volt-second balance
enable
Reserved
Volt-second disable
during soft start
R/W
R
R/W
Reserved
Reserved
R
R
R
R/W
Description
Reserved.
Setting this bit enables volt-second balance for the main transformer (used for full-bridge
configurations).
Set to 0 for proper operation.
0 = do not blank volt-second balance control during soft start (recommended).
1 = blank volt-second balance control during soft start.
Reserved.
Reserved.
Rev. A | Page 90 of 140
Data Sheet
Bits
[1:0]
Bit Name
Volt-second balance
gain setting
ADP1055
R/W
R/W
Description
These bits set the gain of the volt-second balance circuit. The gain can be changed by a factor
of 64. When these bits are set to 00, it takes approximately 700 ms to achieve volt-second balance.
When these bits are set to 11, it takes approximately 10 ms to achieve volt-second balance.
Bit 1
Bit 0
Volt-Second Balance Gain
0
0
1
0
1
4
1
0
16
1
1
64
Table 151. Register 0xFE26—VSBAL_OUTA_B
Bits
7
6
Bit Name
Modulate enable, t1
t1 sign
R/W
R/W
R/W
5
4
Modulate enable, t2
t2 sign
R/W
R/W
3
2
Modulate enable, t3
t3 sign
R/W
R/W
1
0
Modulate enable, t4
t4 sign
R/W
R/W
Description
Setting this bit enables modulation from balance control on the OUTA rising edge, t1.
0 = positive sign. Increase of balance control modulation moves t1 right.
1 = negative sign. Increase of balance control modulation moves t1 left.
Setting this bit enables modulation from balance control on the OUTA falling edge, t2.
0 = positive sign. Increase of balance control modulation moves t2 right.
1 = negative sign. Increase of balance control modulation moves t2 left.
Setting this bit enables modulation from balance control on the OUTB rising edge, t3.
0 = positive sign. Increase of balance control modulation moves t3 right.
1 = negative sign. Increase of balance control modulation moves t3 left.
Setting this bit enables modulation from balance control on the OUTB falling edge, t4.
0 = positive sign. Increase of balance control modulation moves t4 right.
1 = negative sign. Increase of balance control modulation moves t4 left.
Table 152. Register 0xFE27—VSBAL_OUTC_D
Bits
7
6
Bit Name
Modulate enable, t5
t5 sign
R/W
R/W
R/W
5
4
Modulate enable, t6
t6 sign
R/W
R/W
3
2
Modulate enable, t7
t7 sign
R/W
R/W
1
0
Modulate enable, t8
t8 sign
R/W
R/W
Description
Setting this bit enables modulation from balance control on the OUTC rising edge, t5.
0 = positive sign. Increase of balance control modulation moves t5 right.
1 = negative sign. Increase of balance control modulation moves t5 left.
Setting this bit enables modulation from balance control on the OUTC falling edge, t6.
0 = positive sign. Increase of balance control modulation moves t6 right.
1 = negative sign. Increase of balance control modulation moves t6 left.
Setting this bit enables modulation from balance control on the OUTD rising edge, t7.
0 = positive sign. Increase of balance control modulation moves t7 right.
1 = negative sign. Increase of balance control modulation moves t7 left.
Setting this bit enables modulation from balance control on the OUTD falling edge, t8.
0 = positive sign. Increase of balance control modulation moves t8 right.
1 = negative sign. Increase of balance control modulation moves t8 left.
Table 153. Register 0xFE28—VSBAL_SR1_2
Bits
7
6
Bit Name
Modulate enable, t9
t9 sign
R/W
R/W
R/W
5
4
Modulate enable, t10
t10 sign
R/W
R/W
3
2
Modulate enable, t11
t11 sign
R/W
R/W
1
0
Modulate enable, t12
t12 sign
R/W
R/W
Description
Setting this bit enables modulation from balance control on the SR1 rising edge, t9.
0 = positive sign. Increase of balance control modulation moves t9 right.
1 = negative sign. Increase of balance control modulation moves t9 left.
Setting this bit enables modulation from balance control on the SR1 falling edge, t10.
0 = positive sign. Increase of balance control modulation moves t10 right.
1 = negative sign. Increase of balance control modulation moves t10 left.
Setting this bit enables modulation from balance control on the SR2 rising edge, t11.
0 = positive sign. Increase of balance control modulation moves t11 right.
1 = negative sign. Increase of balance control modulation moves t11 left.
Setting this bit enables modulation from balance control on the SR2 falling edge, t12.
0 = positive sign. Increase of balance control modulation moves t12 right.
1 = negative sign. Increase of balance control modulation moves t12 left.
Rev. A | Page 91 of 140
ADP1055
Data Sheet
Table 154. Register 0xFE29—FFWD_SETTING (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:4]
3
Bit Name
Reserved
Disable feedforward
during soft start
R/W
R/W
R/W
2
Feedforward enable
R/W
1
LF 8× gain increase
R/W
0
Global bit for nonlinear
gain
R/W
Description
Reserved.
If voltage line feedforward is enabled, this bit disables it during the soft start process. This
operation is gated by the filter GO bit (Register 0xFE00).
0 = feedforward enabled during soft start (recommended setting).
1 = feedforward disabled during soft start.
This bit enables the voltage line feedforward loop. This operation is gated by the filter GO bit
(Register 0xFE00]).
0 = feedforward disabled.
1 = feedforward enabled.
0 = default.
1 = 8× LF gain.
0 = 1×/1.25×/1.5×/2× gain.
1 = 1×/2×/3×/4× gain.
Table 155. Register 0xFE2A—ISHARE_SETTING
Bits
[7:4]
Bit Name
Number of bits
dropped by master
R/W
R/W
[3:0]
Bit difference between
master and slave
R/W
Description
These bits determine how much a master device reduces its output voltage to maintain current
sharing. Each LSB corresponds to 1.6 V/216 = 24 μV (at the VS± pins). This LSB is multiplied or
divided by the setting in the share bus bandwidth register.
These bits determine how closely a slave tries to match the current of the master device. The
higher the setting, the larger the voltage difference that satisfies the current sharing criteria.
Table 156. Register 0xFE2B—ISHARE_BANDWIDTH
Bits
[7:5]
4
Bit Name
Reserved
Bitstream
R/W
R
R/W
3
Current share select
R/W
[2:0]
Share bus bandwidth
R/W
Description
Reserved.
1 = the current sense ADC reading is output on the ISHARE pin. This bit stream can be used for
analog current sharing. (recommended setting for standalone power supplies).
0 = the digital share bus signal is output on the ISHARE pin. This signal can be used for digital
current sharing.
1 = CS1 reading used for current share.
0 = CS2 reading used for current share.
These bits determine the amount of bandwidth dedicated to the share bus. The value 000 is the
lowest possible bandwidth, and the value 111 is the highest possible bandwidth.
The slave moves up 1 LSB for every share bus transaction (that is, eight data bits plus the start
and stop bits). The master moves down x LSBs per share bus transaction, where x is the share
bus register setting (Register 0xFE2A[7:4]).
0 = divide LSB by 16 (1 LSB = 24 μV/16).
1 = divide LSB by 8.
2 = divide LSB by 4.
3 = divide LSB by 2.
4 = nominal.
5 = multiply LSB by 2.
6 = multiply LSB by 4.
7 = multiply LSB by 8.
8 = multiply LSB by 16.
Rev. A | Page 92 of 140
Data Sheet
ADP1055
Table 157. Register 0xFE2C—IIN_OC_FAST_SETTING
Bits
[7:3]
2
Bit Name
Reserved
Threshold
R/W
R
R/W
[1:0]
Debounce
R/W
Description
Reserved.
0 = 1.2 V range.
1 = 250 mV range.
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Debounce Time
0 ns
40 ns
80 ns
120 ns
Table 158. Register 0xFE2D—IOUT_OC_FAST_SETTING
Bits
[7:2]
Bit Name
Threshold
R/W
R/W
[1:0]
Debounce
R/W
Description
When the ADC range is 480 mV, LSB = 600/63 = 9.52 mV.
When the ADC range is 30 mV or 60 mV, LSB = 60/63 = 0.952 mV.
Threshold = LSB × Register 0xFE2D[7:2].
Bit 1
Bit 0
Debounce Time
0
0
0 ns
0
1
40 ns
1
0
200 ns
1
1
400 ns
Table 159. Register 0xFE2E—IOUT_UC_FAST_SETTING
Bits
[7:2]
Bit Name
Threshold
R/W
R/W
1
Polarity
R/W
0
Debounce
R/W
Description
|LSB| = 30/63 = 0.476 mV.
Range is +30 mV to −30 mV in 64 steps.
Polarity = 0: Threshold = − 0.477 mV × Register 0xFE2E[7:2].
Polarity = 1: Threshold = + 0.472 mV × Register 0xFE2E [7:2].
Note that the IOUT_UC_FAST fault is set when the CS2 reverse comparator is asserted for the
minimum debounce programmed time. Once set, the IOUT_UC_FAST fault is cleared from
327 μs to 656 μs following the deassertion of the CS2 reverse comparator.
1 = 0 to +30 mV range.
0 = 0 to −30 mV range.
The debounce setting is set by Register 0xFE2D[1:0]. For example, if Register 0xFE2D[1:0] = 10,
the IOUT_OC_FAST_SETTING is 200 ns and the IOUT_UC_FAST_SETTING is 800 ns.
00 = 40 ns.
01 = 200 ns.
10 = 800 ns.
11 = 1200 ns.
Table 160. Register 0xFE2F—VOUT_OV_FAST_SETTING
Bits
[7:2]
[1:0]
Bit Name
Threshold
Debounce
R/W
R/W
R/W
Description
64 steps: Threshold = 0.8 + (Register 0xFE2F[7:2]) × 0.8/63.
These bits set the debounce time.
Bit 1
Bit 0
Typical Debounce Time
0
0
40 ns
0
1
2 μs + 1 μs
1
0
5 μs + 1 μs
1
1
10 μs + 1 μs
Rev. A | Page 93 of 140
ADP1055
Data Sheet
Table 161. Register 0xFE30—DEBOUNCE_SETTING_1
Bits
[15:14]
Bit Name
IOUT_OC_LV_DEB
R/W
R/W
[13:11]
VIN_UV_DEB
R/W
[10:8]
VOUT_UV_DEB
R/W
[7:4]
VIN_OV_DEB
R/W
Description
These bits set the debounce time for the IOUT_OC_LV fault.
Bit 15
Bit 14 Debounce
0
0
0
0
1
1 ms + 10 μs
1
0
10 ms + 100 μs
1
1
100 ms + 1 ms
These bits set the debounce time for the VIN_UV fault.
Bit 13
Bit 12 Bit 11 Debounce
0
0
0
0
0
0
1
1 ms + 10 μs
0
1
0
2.5 ms + 10 μs
0
1
1
5 ms + 10 μs
1
0
0
10 ms + 100 μs
1
0
1
50 ms + 100 μs
1
1
0
100 ms + 1 ms
1
1
1
250 ms + 1 ms
These bits set the debounce time for the VOUT_UV fault.
Bit 10
Bit 9
Bit 8
Debounce
0
0
0
0
0
0
1
1 ms + 10 μs
0
1
0
2.5 ms + 10 μs
0
1
1
5 ms + 10 μs
1
0
0
10 ms + 100 μs
1
0
1
50 ms + 100 μs
1
1
0
100 ms + 1 ms
1
1
1
250 ms + 1 ms
These bits set the debounce time for the VIN_OV fault.
Bit 7
Bit 6
Bit 5
Bit 4
Debounce
0
0
0
0
0
0
0
0
1
100 μs + 1 μs
0
0
1
0
250 μs + 1 μs
0
0
1
1
500 μs + 1 μs
0
1
0
0
750 μs + 10 μs
0
1
0
1
1 ms + 10 μs
0
1
1
0
2.5 ms + 10 μs
0
1
1
1
5 ms + 10 μs
1
0
0
0
7.5 ms + 100 μs
1
0
0
1
10 ms + 100 μs
1
0
1
0
25 ms + 100 μs
1
0
1
1
50 ms + 100 μs
1
1
0
0
75 ms + 1 ms
1
1
0
1
100 ms + 1 ms
1
1
1
0
250 ms + 1 ms
1
1
1
1
500 ms + 1 ms
Rev. A | Page 94 of 140
Data Sheet
Bits
[3:0]
Bit Name
VOUT_OV_DEB
ADP1055
R/W
R/W
Description
These bits set the debounce time for the VOUT_OV fault.
Bit 3
Bit 2
Bit 1 Bit 0 Debounce
0
0
0
0
0
0
0
0
1
100 μs + 1 μs
0
0
1
0
250 μs + 1 μs
0
0
1
1
500 μs + 1 μs
0
1
0
0
750 μs + 10 μs
0
1
0
1
1 ms + 10 μs
0
1
1
0
2.5 ms + 10 μs
0
1
1
1
5 ms + 10 μs
1
0
0
0
7.5 ms + 100 μs
1
0
0
1
10 ms + 100 μs
1
0
1
0
25 ms + 100 μs
1
0
1
1
50 ms + 100 μs
1
1
0
0
75 ms + 1 ms
1
1
0
1
100 ms + 1 ms
1
1
1
0
250 ms + 1 ms
1
1
1
1
500 ms + 1 ms
Table 162. Register 0xFE31—DEBOUNCE_SETTING_2
Bits
[15:12]
Bit Name
ISHARE_DEB
R/W
R/W
Description
These bits set the debounce time for the ISHARE fault.
Bit 15
Bit 14 Bit 13 Bit 12 Debounce
0
0
0
0
0
0
0
0
1
1 ms + 10 μs
0
0
1
0
2.5 ms + 10 μs
0
0
1
1
5 ms + 10 μs
0
1
0
0
7.5 ms + 100 μs
0
1
0
1
10 ms + 100 μs
0
1
1
0
25 ms + 100 μs
0
1
1
1
50 ms + 100 μs
1
0
0
0
75 ms + 1 ms
1
0
0
1
100 ms + 1 ms
1
0
1
0
250 ms + 1 ms
1
0
1
1
500 ms + 1 ms
1
1
0
0
750 ms + 10 ms
1
1
0
1
1 sec + 10 ms
1
1
1
0
2.5 sec + 10 ms
1
1
1
1
5 sec + 10 ms
Rev. A | Page 95 of 140
ADP1055
Data Sheet
Bits
[11:8]
Bit Name
IIN_OC_DEB
R/W
R/W
[7:4]
IOUT_UC_DEB
R/W
Description
These bits set the debounce time for the IIN_OC fault.
Bit 11
Bit 10 Bit 9 Bit 8 Debounce
0
0
0
0
0
0
0
0
1
1 ms + 10 μs
0
0
1
0
2.5 ms + 10 μs
0
0
1
1
5 ms + 10 μs
0
1
0
0
7.5 ms + 100 μs
0
1
0
1
10 ms + 100 μs
0
1
1
0
25 ms + 100 μs
0
1
1
1
50 ms + 100 μs
1
0
0
0
75 ms + 1 ms
1
0
0
1
100 ms + 1 ms
1
0
1
0
250 ms + 1 ms
1
0
1
1
500 ms + 1 ms
1
1
0
0
750 ms + 10 ms
1
1
0
1
1 sec + 10 ms
1
1
1
0
2.5 sec + 10 ms
1
1
1
1
5 sec + 10 ms
These bits set the debounce time for the IOUT_UC fault.
Bit 7
Bit 6
Bit 5 Bit 4 Debounce
0
0
0
0
0
0
0
0
1
1 ms + 10 μs
0
0
1
0
2.5 ms + 10 μs
0
0
1
1
5 ms + 10 μs
0
1
0
0
7.5 ms + 100 μs
0
1
0
1
10 ms + 100 μs
0
1
1
0
25 ms + 100 μs
0
1
1
1
50 ms + 100 μs
1
0
0
0
75 ms + 1 ms
1
0
0
1
100 ms + 1 ms
1
0
1
0
250 ms + 1 ms
1
0
1
1
500 ms + 1 ms
1
1
0
0
750 ms + 10 ms
1
1
0
1
1 sec + 10 ms
1
1
1
0
2.5 sec + 10 ms
1
1
1
1
5 sec + 10 ms
Rev. A | Page 96 of 140
Data Sheet
Bits
[3:0]
Bit Name
IOUT_OC_DEB
ADP1055
R/W
R/W
Description
These bits set the debounce time for the IOUT_OC fault.
Bit 3
Bit 2
Bit 1 Bit 0 Debounce
0
0
0
0
0
0
0
0
1
1 ms + 10 μs
0
0
1
0
2.5 ms + 10 μs
0
0
1
1
5 ms + 10 μs
0
1
0
0
7.5 ms + 100 μs
0
1
0
1
10 ms + 100 μs
0
1
1
0
25 ms + 100 μs
0
1
1
1
50 ms + 100 μs
1
0
0
0
75 ms + 1 ms
1
0
0
1
100 ms + 1 ms
1
0
1
0
250 ms + 1 ms
1
0
1
1
500 ms + 1 ms
1
1
0
0
750 ms + 10 ms
1
1
0
1
1 sec + 10 ms
1
1
1
0
2.5 sec + 10 ms
1
1
1
1
5 sec + 10 ms
Table 163. Register 0xFE32—DEBOUNCE_SETTING_3
Bits
[15:12]
[11:8]
Bit Name
Reserved
POUT_OP_DEB
R/W
R
R/W
Description
Reserved.
These bits set the debounce time for the POUT_OP fault.
Bit 11
Bit 10 Bit 9 Bit 8 Debounce
0
0
0
0
0
0
0
0
1
100 μs + 1 μs
0
0
1
0
250 μs + 1 μs
0
0
1
1
500 μs + 1 μs
0
1
0
0
750 μs + 10 μs
0
1
0
1
1 ms + 10 μs
0
1
1
0
2.5 ms + 10 μs
0
1
1
1
5 ms + 10 μs
1
0
0
0
7.5 ms + 100 μs
1
0
0
1
10 ms + 100 μs
1
0
1
0
25 ms + 100 μs
1
0
1
1
50 ms + 100 μs
1
1
0
0
75 ms + 1 ms
1
1
0
1
100 ms + 1 ms
1
1
1
0
250 ms + 1 ms
1
1
1
1
500 ms + 1 ms
Rev. A | Page 97 of 140
ADP1055
Data Sheet
Bits
[7:4]
Bit Name
TON_MAX_DEB
R/W
R/W
[3:0]
OT_DEB
R/W
Description
These bits set the debounce time for the TON_MAX fault.
Bit 7
Bit 6
Bit 5 Bit 4 Debounce
0
0
0
0
0
0
0
0
1
100 μs + 1 μs
0
0
1
0
250 μs + 1 μs
0
0
1
1
500 μs + 1 μs
0
1
0
0
750 μs + 10 μs
0
1
0
1
1 ms + 10 μs
0
1
1
0
2.5 ms + 10 μs
0
1
1
1
5 ms + 10 μs
1
0
0
0
7.5 ms + 100 μs
1
0
0
1
10 ms + 100 μs
1
0
1
0
25 ms + 100 μs
1
0
1
1
50 ms + 100 μs
1
1
0
0
75 ms + 1 ms
1
1
0
1
100 ms + 1 ms
1
1
1
0
250 ms + 1 ms
1
1
1
1
500 ms + 1 ms
These bits set the debounce time for the overtemperature fault.
Bit 3
Bit 2
Bit 1 Bit 0 Debounce
0
0
0
0
0
0
0
0
1
1 ms + 10 μs
0
0
1
0
2.5 ms + 10 μs
0
0
1
1
5 ms + 10 μs
0
1
0
0
7.5 ms + 100 μs
0
1
0
1
10 ms + 100 μs
0
1
1
0
25 ms + 100 μs
0
1
1
1
50 ms + 100 μs
1
0
0
0
75 ms + 1 ms
1
0
0
1
100 ms + 1 ms
1
0
1
0
250 ms + 1 ms
1
0
1
1
500 ms + 1 ms
1
1
0
0
750 ms + 10 ms
1
1
0
1
1 sec + 10 ms
1
1
1
0
2.5 sec + 10 ms
1
1
1
1
5 sec + 10 ms
Rev. A | Page 98 of 140
Data Sheet
ADP1055
Table 164. Register 0xFE33—DEBOUNCE_SETTING_4
Bits
[15:12]
Bit Name
GPIO4_DEB
R/W
R/W
[11:8]
GPIO3_DEB
R/W
Description
These bits set the debounce time for the GPIO4 fault.
Bit 15
Bit 14 Bit 13 Bit 12 Debounce
0
0
0
0
0
0
0
0
1
80 ns
0
0
1
0
1 μs + 1 μs
0
0
1
1
100 μs + 1 μs
0
1
0
0
500 μs + 1 μs
0
1
0
1
1 ms + 10 μs
0
1
1
0
2.5 ms + 10 μs
0
1
1
1
5 ms + 10 μs
1
0
0
0
7.5 ms + 100 μs
1
0
0
1
10 ms + 100 μs
1
0
1
0
25 ms + 100 μs
1
0
1
1
50 ms + 100 μs
1
1
0
0
75 ms + 1 ms
1
1
0
1
100 ms + 1 ms
1
1
1
0
250 ms + 1 ms
1
1
1
1
500 ms + 1 ms
These bits set the debounce time for the GPIO3 fault.
Bit 11
Bit 10 Bit 9
Bit 8
Debounce
0
0
0
0
0
0
0
0
1
80 ns
0
0
1
0
1 μs + 1 μs
0
0
1
1
100 μs + 1 μs
0
1
0
0
500 μs + 1 μs
0
1
0
1
1 ms + 10 μs
0
1
1
0
2.5 ms + 10 μs
0
1
1
1
5 ms + 10 μs
1
0
0
0
7.5 ms + 100 μs
1
0
0
1
10 ms + 100 μs
1
0
1
0
25 ms + 100 μs
1
0
1
1
50 ms + 100 μs
1
1
0
0
75 ms + 1 ms
1
1
0
1
100 ms + 1 ms
1
1
1
0
250 ms + 1 ms
1
1
1
1
500 ms + 1 ms
Rev. A | Page 99 of 140
ADP1055
Data Sheet
Bits
[7:4]
Bit Name
GPIO2_DEB
R/W
R/W
[3:0]
GPIO1_DEB
R/W
Description
These bits set the debounce time for the GPIO2 fault.
Bit 7
Bit 6
Bit 5 Bit 4 Debounce
0
0
0
0
0
0
0
0
1
80 ns
0
0
1
0
1 μs + 1 μs
0
0
1
1
100 μs + 1 μs
0
1
0
0
500 μs + 1 μs
0
1
0
1
1 ms + 10 μs
0
1
1
0
2.5 ms + 10 μs
0
1
1
1
5 ms + 10 μs
1
0
0
0
7.5 ms + 100 μs
1
0
0
1
10 ms + 100 μs
1
0
1
0
25 ms + 100 μs
1
0
1
1
50 ms + 100 μs
1
1
0
0
75 ms + 1 ms
1
1
0
1
100 ms + 1 ms
1
1
1
0
250 ms + 1 ms
1
1
1
1
500 ms + 1 ms
These bits set the debounce time for the GPIO1 fault.
Bit 3
Bit 2
Bit 1 Bit 0 Debounce
0
0
0
0
0
0
0
0
1
80 ns
0
0
1
0
1 μs + 1 μs
0
0
1
1
100 μs + 1 μs
0
1
0
0
500 μs + 1 μs
0
1
0
1
1 ms + 10 μs
0
1
1
0
2.5 ms + 10 μs
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Rev. A | Page 100 of 140
5 ms + 10 μs
7.5 ms + 100 μs
10 ms + 100 μs
25 ms + 100 μs
50 ms + 100 μs
75 ms + 1 ms
100 ms + 1 ms
250 ms + 1 ms
500 ms + 1 ms
Data Sheet
ADP1055
The VOUT_OV_FAST_FAULT_RESPONSE command instructs the device on the actions to take due to an output fast overvoltage fault
condition. The device notifies the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the MFR_SPECIFIC bit in
STATUS_WORD register, and the VOUT_OV_FAST_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 165. Register 0xFE34—VOUT_OV_FAST_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay time
R/W
Description
Determines the device response to a fast overvoltage fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
The IOUT_OC_FAST_FAULT_RESPONSE command instructs the device on the actions to take due to an output fast overcurrent fault
condition. The device notifies the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the MFR_SPECIFIC bit in
STATUS_WORD register, and the IOUT_OC_FAST_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 166. Register 0xFE35—IOUT_OC_FAST_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry
setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to a fast overcurrent fault condition.
Bit 7
Bit 6
Response
0
0
Operate in current limiting mode, maintaining the output current at IOUT_OC_FAULT_LIMIT.
0
1
Operate in current limiting mode, maintaining the output current at IOUT_OC_FAULT_LIMIT. If
VOUT falls below the IOUT_OC_LV_FAULT_LIMIT, respond as programmed by the retry
setting (Bits[5:3]).
1
0
Continue operation in current limiting mode for the delay time (Bits[2:0]). If the device is
still in current limiting mode, respond as programmed by the retry setting (Bits[5:3]).
1
1
Shut down, disable the output, and respond as programmed by the retry setting (Bits[5:3]).
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
Rev. A | Page 101 of 140
ADP1055
Data Sheet
The IOUT_UC_FAST_FAULT_RESPONSE command instructs the device on the actions to take due to an output fast undercurrent fault
condition. The device notifies the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the MFR_SPECIFIC bit in
STATUS_WORD register, and the IOUT_UC_FAST_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 167. Register 0xFE36—IOUT_UC_FAST_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to a fast undercurrent fault condition.
Bit 7
Bit 6
Response
0
0
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT.
0
1
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT. If VOUT falls below the IOUT_OC_LV_FAULT_LIMIT,
respond as programmed by the retry setting (Bits[5:3]).
1
0
Continue operation in current limiting mode for the delay time (Bits[2:0]). If the
device is still in current limiting mode, respond as programmed by the retry
setting (Bits[5:3]).
1
1
Shut down, disable the output, and respond as programmed by the retry
setting (Bits[5:3]).
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
The IIN_OC_FAST_FAULT_RESPONSE command instructs the device on the actions to take due to an input fast overcurrent fault
condition. The device notifies the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the MFR_SPECIFIC bit in
STATUS_WORD register, and the IIN_OC_FAST_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 168. Register 0xFE37—IIN_OC_FAST_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
Description
Determines the device response to a fast input overcurrent fault condition.
Bit 7
Bit 6
Response
0
0
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT.
0
1
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT. If VOUT falls below the IOUT_OC_LV_FAULT_LIMIT,
respond as programmed by the retry setting (Bits[5:3]).
1
0
Continue operation in current limiting mode for the delay time (Bits[2:0]). If the
device is still in current limiting mode, respond as programmed by the retry
setting (Bits[5:3]).
1
1
Shut down, disable the output, and respond as programmed by the retry
setting (Bits[5:3]).
Rev. A | Page 102 of 140
Data Sheet
ADP1055
Bits
[5:3]
Bit Name
Retry setting
R/W
R/W
[2:0]
Delay times
R/W
Description
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
The ISHARE_FAULT_RESPONSE command instructs the device on the actions to take due to a current sharing fault condition. The
device notifies the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the IOUT bit in STATUS_WORD register,
and the ISHARE_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 169. Register 0xFE38—ISHARE_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay times
R/W
Description
Determines the device response to a current sharing fault condition.
Bit 7
Bit 6
Response
0
0
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT.
0
1
Operate in current limiting mode, maintaining the output current at
IOUT_OC_FAULT_LIMIT. If VOUT falls below the IOUT_OC_LV_FAULT_LIMIT,
respond as programmed by the retry setting (Bits[5:3]).
1
0
Continue operation in current limiting mode for the delay time (Bits[2:0]). If the
device is still in current limiting mode, respond as programmed by the retry
setting (Bits[5:3]).
1
1
Shut down, disable the output, and respond as programmed by the retry
setting (Bits[5:3]).
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
Rev. A | Page 103 of 140
ADP1055
Data Sheet
The GPIO1_FAULT_RESPONSE command instructs the device on the actions to take due to a GPIO1 fault condition. The device notifies
the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the MFR_SPECIFIC bit in STATUS_WORD register, and
the GPIO1_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 170. Register 0xFE39—GPIO1_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay time
R/W
Description
Determines the device response to a GPIO1 fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
The GPIO2_FAULT_RESPONSE command instructs the device on the actions to take due to a GPIO2 fault condition. The device notifies
the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the MFR_SPECIFIC bit in STATUS_WORD register, and
the GPIO2_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 171. Register 0xFE3A—GPIO2_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay time
R/W
Description
Determines the device response to a GPIO2 fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
Rev. A | Page 104 of 140
Data Sheet
ADP1055
The GPIO3_FAULT_RESPONSE command instructs the device on the actions to take due to a GPIO3 fault condition. The device notifies
the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the MFR_SPECIFIC bit in STATUS_WORD register, and
the GPIO3_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 172. Register 0xFE3B—GPIO3_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay time
R/W
Description
Determines the device response to a GPIO3 fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
The GPIO4_FAULT_RESPONSE command instructs the device on the actions to take due to a GPIO4 fault condition. The device notifies
the host and sets the NONE_OF_THE_ABOVE bit in STATUS_BYTE register, the MFR_SPECIFIC bit in STATUS_WORD register, and
the GPIO4_FAULT bit in STATUS_MFR_SPECIFIC register.
Table 173. Register 0xFE3C—GPIO4_FAULT_RESPONSE
Bits
[7:6]
Bit Name
Response
R/W
R/W
[5:3]
Retry setting
R/W
[2:0]
Delay time
R/W
Description
Determines the device response to a GPIO4 fault condition.
Bit 7
Bit 6
Response
0
0
Do nothing.
0
1
Continue operation for the delay time (Bits[2:0]). If the fault persists, retry the
number of times specified by Bits[5:3].
1
0
Shut down, disable the output, and respond as programmed in the retry
setting (Bits[5:3]).
1
1
Disable the output while the fault is present. Operation resumes and the
output is enabled when the fault condition no longer exists.
Number of retry attempts following a fault condition. A fault condition can be cleared by a reset,
a power-off/power-on sequence, or a loss of bias power.
Bit 5
Bit 4
Bit 3
Number of Retries
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Infinite
Number of delay time units (see Register 0xFE3E).
Rev. A | Page 105 of 140
ADP1055
Data Sheet
Register 0xFE3D masks PWM disabling when a fault condition causes the device to disable the output and wait for the fault to clear
(Response[7:6] = 11). Note that this masking register applies only when the ADP1055 is servicing a fault condition that has the fault
response programmed to Bits[7:6] = 11.
Table 174. Register 0xFE3D—PWM_FAULT_MASK
Bits
[7:6]
5
4
3
2
1
0
Bit Name
Reserved
Mask SR2
Mask SR1
Mask OUTD
Mask OUTC
Mask OUTB
Mask OUTA
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved.
0 = SR2 disabled on fault; 1 = SR2 ignores fault.
0 = SR1 disabled on fault; 1 = SR1 ignores fault.
0 = OUTD disabled on fault; 1 = OUTD ignores fault.
0 = OUTC disabled on fault; 1 = OUTC ignores fault.
0 = OUTB disabled on fault; 1 = OUTB ignores fault.
0 = OUTA disabled on fault; 1 = OUTA ignores fault.
Table 175. Register 0xFE3E—DELAY_TIME_UNIT
Bits
7
Bit Name
Current fault delay time
unit
R/W
R/W
[6:4]
Current fault delay time
multiplier
R/W
3
Voltage/other
fault delay time unit
R/W
[2:0]
Voltage/other fault
delay time multiplier
R/W
Description
0 = ms.
1 = μs.
Bit 6
Bit 5
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0 = ms.
1 = μs.
Bit 2
Bit 1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Bit 4
0
1
0
1
0
1
0
1
Multiplier
1
4
16
64
128
256
512
1024
Bit 0
0
1
0
1
0
1
0
1
Multiplier
1
4
16
64
128
256
512
1024
Table 176. Register 0xFE3F—WDT_SETTING
Bits
[7:2]
[1:0]
Bit Name
Reserved
Watchdog timeout
R/W
R
Description
Reserved.
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Timeout
Disable
1 sec
5 sec
10 sec
Rev. A | Page 106 of 140
Data Sheet
ADP1055
Table 177. Register 0xFE40—GPIO_SETTING
Bits
7
6
5
4
3
2
1
0
Bit Name
GPIO4 polarity
GPIO4 direction
GPIO3 polarity
GPIO3 direction
GPIO2 polarity
GPIO2 direction
GPIO1 polarity
GPIO1 direction
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
0 = active high; 1 = active low
0 = input; 1 = output
0 = active high; 1 = active low
0 = input; 1 = output
0 = active high; 1 = active low
0 = input; 1 = output
0 = active high; 1 = active low
0 = input; 1 = output
Table 178. Register 0xFE41—GPIO1_2_KARNAUGH_MAP
Bits
[7:4]
Bit Name
GPIO2 logic function
R/W
R/W
[3:0]
GPIO1 logic function
R/W
Description
0x0 = GND
0x1 = PGOOD1 AND PGOOD2
0x2 = PGOOD1 AND ~PGOOD2
0x3 = PGOOD1
0x4 = ~PGOOD1 AND PGOOD2
0x5 = PGOOD2
0x6 = PGOOD1 XOR PGOOD2
0x7 = PGOOD1 OR PGOOD2
0x8 = PGOOD1 NOR PGOOD2
0x9 = PGOOD1 XNOR PGOOD2
0xA = ~PGOOD2
0xB = PGOOD1 OR ~PGOOD2
0xC = ~PGOOD1
0xD = ~PGOOD1 OR PGOOD2
0xE = PGOOD1 NAND PGOOD2
0xF = VDD
0x0 = GND
0x1 = PGOOD1 AND PGOOD2
0x2 = PGOOD1 AND ~PGOOD2
0x3 = PGOOD1
0x4 = ~PGOOD1 AND PGOOD2
0x5 = PGOOD2
0x6 = PGOOD1 XOR PGOOD2
0x7 = PGOOD1 OR PGOOD2
0x8 = PGOOD1 NOR PGOOD2
0x9 = PGOOD1 XNOR PGOOD2
0xA = ~PGOOD2
0xB = PGOOD1 OR ~PGOOD2
0xC = ~PGOOD1
0xD = ~PGOOD1 OR PGOOD2
0xE = PGOOD1 NAND PGOOD2
0xF = VDD
Rev. A | Page 107 of 140
ADP1055
Data Sheet
Table 179. Register 0xFE42—GPIO3_4_KARNAUGH_MAP
Bits
[7:4]
Bit Name
GPIO4 logic function
R/W
R/W
[3:0]
GPIO3 logic function
R/W
Description
0x0 = GND
0x1 = PGOOD1 AND PGOOD2
0x2 = PGOOD1 AND ~PGOOD2
0x3 = PGOOD1
0x4 = ~PGOOD1 AND PGOOD2
0x5 = PGOOD2
0x6 = PGOOD1 XOR PGOOD2
0x7 = PGOOD1 OR PGOOD2
0x8 = PGOOD1 NOR PGOOD2
0x9 = PGOOD1 XNOR PGOOD2
0xA = ~PGOOD2
0xB = PGOOD1 OR ~PGOOD2
0xC = ~PGOOD1
0xD = ~PGOOD1 OR PGOOD2
0xE = PGOOD1 NAND PGOOD2
0xF = VDD
0x0 = GND
0x1 = PGOOD1 AND PGOOD2
0x2 = PGOOD1 AND ~PGOOD2
0x3 = PGOOD1
0x4 = ~PGOOD1 AND PGOOD2
0x5 = PGOOD2
0x6 = PGOOD1 XOR PGOOD2
0x7 = PGOOD1 OR PGOOD2
0x8 = PGOOD1 NOR PGOOD2
0x9 = PGOOD1 XNOR PGOOD2
0xA = ~PGOOD2
0xB = PGOOD1 OR ~PGOOD2
0xC = ~PGOOD1
0xD = ~PGOOD1 OR PGOOD2
0xE = PGOOD1 NAND PGOOD2
0xF = VDD
Table 180. Register 0xFE43—PGOOD_FAULT_DEB
Bits
[7:6]
Bit Name
PGOOD2_OFF_DEB
R/W
R/W
[5:4]
PGOOD2_ON_DEB
R/W
[3:2]
PGOOD1_OFF_DEB
R/W
Description
Bit 7
Bit 6
0
0
0
1
1
0
1
1
Bit 5
Bit 4
0
0
0
1
1
0
1
1
Bit 3
Bit 2
0
0
0
1
1
0
1
1
Debounce (ms)
0
150 + 10
350 + 10
550 + 10
Debounce (ms)
0
150 + 10
350 + 10
550 + 10
Debounce (ms)
0
150 + 10
350 + 10
550 + 10
Rev. A | Page 108 of 140
Data Sheet
Bits
[1:0]
Bit Name
PGOOD1_ON_DEB
ADP1055
R/W
R/W
Description
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Debounce (ms)
0
150 + 10
350 + 10
550 + 10
Table 181. Register 0xFE44—PGOOD1_FAULT_SELECT
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
TON_MAX_FAULT
IOUT_UC_FAULT
POUT_OP_FAULT
IIN_OC_FAULT
VIN_OV_FAULT
VOUT_UV_FAULT
VOUT_OV_FAULT
IOUT_OC_FAULT
VIN_UV_FAULT
IIN_OC_FAST_FAULT
IOUT_OC_FAST_FAULT
VOUT_OV_FAST
SOFT_START_RAMP
OT_FAULT
SR_OFF
OFF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD1 flag (Bit 6 of STATUS_UNKNOWN)
Table 182. Register 0xFE45—PGOOD2_FAULT_SELECT
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
VOUT (STATUS_WORD[15])
IOUT/POUT (STATUS_WORD[14])
INPUT (STATUS_WORD[13])
TEMPERATURE
(STATUS_WORD[2])
GPIO2/GPIO4
GPIO1/GPIO3
TOFF_MAX_WARN
IOUT_UC_FAST_FAULT
Constant current
IIN_OC_FAST_FAULT
IOUT_OC_FAST_FAULT
VOUT_OV_FAST
SOFT_START_RAMP
SYNC_UNLOCK
Maximum black box record
reached
Soft start filter
R/W
R/W
R/W
R/W
R/W
Description
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
R/W
1 = this flag, if asserted, sets the PGOOD2 flag (Bit 7 of STATUS_UNKNOWN)
Table 183. Register 0xFE46—SOFT_START_BLANKING
Bits
15
14
13
12
11
Bit Name
VOUT_OV_FAULT
GPIO3/GPIO4 snubber
TON_MAX_FAULT
VIN_OV_FAULT
VIN_UV_FAULT
R/W
R/W
R/W
R/W
R/W
R/W
Description
1 = this flag is ignored during soft start
1 = the GPIO3/GPIO4 snubber outputs are disabled during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
Rev. A | Page 109 of 140
ADP1055
Bits
10
9
8
7
6
5
4
3
2
1
0
Data Sheet
Bit Name
IIN_OC_FAULT
IOUT_OC_FAULT
IOUT_UC_FAULT and
IOUT_UC_FAST_FAULT
POUT_OP_FAULT
IIN_OC_FAST_FAULT
IOUT_OC_FAST_FAULT
VOUT_OV_FAST
IOUT_OC_LV_FAULT
GPIO1/GPIO3
GPIO2/GPIO4
OT_FAULT
R/W
R/W
R/W
R/W
Description
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
1 = this flag is ignored during soft start
Table 184. Register 0xFE47—SOFT_STOP_BLANKING
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
VOUT_OV_FAULT
GPIO3/GPIO4 snubber
TOFF_MAX_WARN
VIN_OV_FAULT
VIN_UV_FAULT
IIN_OC_FAULT
IOUT_OC_FAULT
IOUT_UC_FAULT and
IOUT_UC_FAST_FAULT
POUT_OP_FAULT
IIN_OC_FAST_FAULT
IOUT_OC_FAST_FAULT
VOUT_OV_FAST
IOUT_OC_LV_FAULT
GPIO1/GPIO3
GPIO2/GPIO4
OT_FAULT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
1 = this flag is ignored during soft stop
1 = the GPIO3/GPIO4 snubber outputs are disabled during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
1 = this flag is ignored during soft stop
Table 185. Register 0xFE48—BLACKBOX_SETTING
Bits
[7:3]
[2]
Bit Name
Reserved
Maximum record
number
R/W
R
R/W
[1:0]
Recording options
R/W
Description
Reserved.
Sets the maximum record number at which the black box recording feature is disabled.
0 = 150,000. Recommended when operating at <85°C.
1 = 16,000. Recommended when operating at 125°C.
Sets black box recording options before shutting down the power supply. The minimum time for
the black box to write all the status registers into the EEPROM is approximately 1.1 ms. When black
box writing is enabled for the save on every retry shutdown cycle, the minimum retry delay time
must be greater than the time to write to the EEPROM (1.1 ms).
Bit 1
Bit 0 Options
0
0
No recording.
0
1
Record only telemetry just before the final shutdown.
1
0
Record telemetry of final shutdown and all retry attempts.
1
1
Record telemetry of final shutdown, all retry attempts, and normal unit-off per
the CTRL pin and the OPERATION command.
Rev. A | Page 110 of 140
Data Sheet
ADP1055
Table 186. Register 0xFE49—PWM_DISABLE_SETTING
Bits
[7:6]
5
4
3
2
1
0
Bit Name
Reserved
SR2 disable
SR1 disable
OUTD disable
OUTC disable
OUTB disable
OUTA disable
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved.
Setting this bit disables the SR2 output.
Setting this bit disables the SR1 output.
Setting this bit disables the OUTD output.
Setting this bit disables the OUTC output.
Setting this bit disables the OUTB output.
Setting this bit disables the OUTA output.
Table 187. Register 0xFE4A—FILTER_TRANSITION (Requires Use of the GO Bit in Register 0xFE00)
Bits
7
Bit Name
Overshoot
protection
R/W
R/W
6
Overshoot speed
R/W
[5:3]
HF ADC
configuration
R/W
2
Enable soft transition
R/W
[1:0]
Transition speed
R/W
Description
0 = disable setpoint reference tracking.
1 = enable setpoint reference tracking (see the Integrator Windup and Output Voltage Regulation
Loss (Overshoot Protection) section).
0 = if VOUT is out of regulation for 96 out of 128 switching cycles, the reference moves to the last
known value of VOUT (9-bit precision) and tries to return to regulation at a controlled rate given by
the VOUT_TRANSITION_RATE command.
1 = if VOUT is out of regulation for 48 out of 64 switching cycles, VREF tracks VOUT (9-bit precision).
Double update rate affects this register.
000 = autocorrection loop disabled.
001 = autocorrection loop bandwidth set to approximately 9 Hz.
010 = autocorrection loop bandwidth set to approximately 19 Hz.
011 = autocorrection loop bandwidth set to approximately 37 Hz.
100 = autocorrection loop bandwidth set to approximately 75 Hz.
101 = autocorrection loop bandwidth set to approximately 150 Hz.
110 = autocorrection loop bandwidth set to approximately 300 Hz.
111 = autocorrection loop bandwidth set to approximately 600 Hz.
Enables soft transition between filter settings to minimize output transients. All four parameters of
each filter are linearly transitioned to the new value.
The filter changes in 32 steps, with one step applied at the interval specified by these bits.
Bit 1
Bit 0 Speed
0
0
32 × tSW (total transition time = 32 × 32 × tSW = 1024 × tSW)
0
1
8 × tSW (total transition time = 8 × 32 = 256 × tSW)
1
0
2 × tSW (total = 64 × tSW)
1
1
1 × tSW (total = 32 × tSW)
Table 188. Register 0xFE4B—DEEP_LLM_SETTING
Bits
[7:5]
Bit Name
Deep LLM thresholds
R/W
R/W
Description
These bits set the load current limit on the CS2 ADC below which SR1 and SR2 enter deep light
load mode. The averaging time, debounce, and hysteresis are programmed in Register 0xFE4B.
SR outputs are always off in pulse skip mode.
Bit 7
Bit 6
Bit 5
Thresholds (LSBs)
0
0
0
0
0
0
1
4
0
1
0
8
0
1
1
12
1
0
0
16
1
0
1
20
1
1
0
24
1
1
1
28
Rev. A | Page 111 of 140
ADP1055
Data Sheet
Bits
[4:3]
Bit Name
Deep light load mode
averaging speed
R/W
R/W
[2:1]
Deep light load mode
hysteresis
R/W
0
Fast phase-in
R/W
Description
Sets the averaging speed and resolution used for the deep light load mode thresholds. Faster
speed corresponds to lower resolution, and therefore to smaller accuracy of the threshold.
Bit 4
Bit 3
Speed (μs)
0
0
37.5 (six bits)
0
1
82 (seven bits)
1
0
163 (eight bits)
1
1
327 (nine bits)
Sets the amount of hysteresis applied to the deep light load mode thresholds. The size of the
LSB is affected by the speed and resolution selected in Bits[4:3]. For example, if the ADC range
of 30 mV is used with 8-bit resolution, the LSB size is 30 mV/28 = 117.187 μV.
Bit 2
Bit 1
LSBs
0
0
3
0
1
8
1
0
12
1
1
16
0 = SR transition speed is always the value programmed during all transitions, as set by
Register 0xFE5F[7:4].
1 = the SR transition speed is the value programmed in Register 0xFE5F[7:4] for the first
transition process (whenever that occurs after PSON according to the settings), but for every
subsequent transition, the SR outputs transition at the fastest speed, that is, 5 ns/tSW.
Table 189. Register 0xFE4C—DEEP_LLM_DISABLE_SETTING
Bits
7
Bit Name
SR phase-in enable
R/W
R/W
6
OUTD disable
R/W
5
OUTC disable
R/W
4
OUTB disable
R/W
3
OUTA disable
R/W
2
SR2 disable
R/W
1
SRs enable during soft
stop
SRs enable during soft
stop
R/W
0
R/W
Description
0 = disable SR phase-in.
1 = enable SR phase-in.
Setting this bit means that OUTD is disabled if the load current drops below the deep light load
threshold.
Setting this bit means that OUTC is disabled if the load current drops below the deep light load
threshold.
Setting this bit means that OUTB is disabled if the load current drops below the deep light load
threshold.
Setting this bit means that OUTA is disabled if the load current drops below the deep light load
threshold.
Setting this bit means that SR2 are disabled if the load current drops below the deep light load
threshold.
Setting this bit means that SR2 are disabled if the load current drops below the deep light load
threshold.
Setting this bit reenables the SRs during soft stop to facilitate discharging the load. The
recommended setting is 1.
Table 190. Register 0xFE4D—OVP_FAULT_CONFIG
Bits
7
Bit Name
VDD/VCORE OV fault ignore
R/W
R/W
6
VDD/VCORE OV restart
R/W
5
VDD/VCORE OV debounce
R/W
4
VDD UV debounce
R/W
Description
0 = VDD OV and VCORE OV flags are not ignored
1 = VDD OV and VCORE OV flags are ignored
0 = do not download EEPROM again following a fault shutdown
1 = download EEPROM following a fault shutdown
0 = 2 μs + 1 μs debounce
1 = 500 μs + 10 μs debounce
0 = no debounce
1 = 120 ns debounce
Rev. A | Page 112 of 140
Data Sheet
Bits
[3:2]
[1:0]
ADP1055
Bit Name
VOUT_OV sampling
R/W
R/W
Reserved
Description
Bit 3 Bit 2
0
0
0
1
1
0
1
1
Sampling
One sample sets the VOUT_OV flag (80 μs sampling period)
Two consecutive samples that read a value greater than the one set in
VOUT_OV_FAULT_LIMIT set the VOUT_OV flag (160 μs sampling period)
Three consecutive samples that read a value greater than the one set in
VOUT_OV_FAULT_LIMIT set the VOUT_OV flag (240 μs sampling period)
Four consecutive samples that read a value greater than the one set in
VOUT_OV_FAULT_LIMIT set the VOUT_OV flag (320 μs sampling period)
Reserved
Table 191. Register 0xFE4E—CS1_SETTING
Bits
7
[6:4]
Bit Name
Reserved
CS1 fast OCP blanking
R/W
R
R/W
3
[2:0]
CS1 fast OCP bypass
CS1 fast OCP timeout
R/W
R/W
Description
Reserved.
Set the CS1 fast OCP blanking time to 0 ns, 40 ns, 80 ns, 120 ns, 200 ns, 400 ns, 600 ns,
or 800 ns.
Setting this bit means that the GPIO1 pin is used for CS1 fast OCP instead of the CS1 pin.
Set the number of consecutive switching cycles with a CS1 OCP condition before the
IIN_OC_FAST_FAULT flag is set: 1, 4, 16, 128, 256, 384, 512, or 1024.
Table 192. Register 0xFE4F—CS2_SETTING
Bits
7
[6:4]
3
2
[1:0]
Bit Name
CC turbo mode
CS2 fast OCP
timeout
Peak constant
current mode
Average constant
current disable
R/W
R/W
R/W
CS2 range
R/W
R/W
R/W
Description
Reduces the CS2 average time from 328 μs to 41 μs for CC mode.
Sets the number of consecutive switching cycles with a CS2 OCP condition before the
IOUT_OC_FAST_FAULT flag is set: 1, 4, 16, 128, 256, 384, 512, or 1024.
When this bit is set, CS2 fast OCP cycle-by-cycle protection on OUTA to OUTD is disabled. The CS2 fast
OCP timeout is still active.
0 = average constant current mode is enabled/disabled, as defined by PMBus.
Threshold = IOUT_OC_FAULT_LIMIT.
ILIM = IOUT_OC_FAULT_LIMIT × (100 + percentage), where percentage and polarity are defined in
Register 0xFE5D[3:0]. The current fault response is PMBus compliant.
1 = average constant current mode is always on (not PMBus compliant).
Threshold = ILIM = IOUT_OC_FAULT_LIMIT × (100 ± percentage), where percentage and polarity are
defined in Register 0xFE5D[3:0].
Current fault response defaults to these settings (Response Bits[7:6]).
00 = ignore fault.
01 = ignore fault.
10 = ignore fault.
11 = shut down, disable the output, and respond as programmed in retry setting (Bits[5:3]).
Sets the CS2 ADC range.
Bit 1
Bit 0
ADC Range (mV)
0
0
30 (low-side sensing)
0
1
60 (low-side sensing)
1
0
480 (high-side sensing)
1
1
Reserved
Rev. A | Page 113 of 140
ADP1055
Data Sheet
Table 193. Register 0xFE50—PULSE_SKIP_AND_SHUTDOWN
Bits
[7:6]
Bit Name
Addition PS on time after
end of soft stop ramp
R/W
R/W
5
Instant SR transition
R/W
4
Pulse killer mode
R/W
3
End-of-cycle shutdown
R/W
2
R/W
1
Soft stop pulse skipping
enable
Pulse skipping enable
0
Pulse skipping zero PWM
R/W
R/W
Description
To allow any negative current to dissipate, PWM outputs such as the SR outputs are kept active
after the soft stop ramp-down.
Bit 7 Bit 6 LSBs
0
0
No additional on time at the end of soft stop. All PWM outputs are shut off
immediately at end of ramp. The SR PWM outputs continue to increase their
modulation limit and completely turn on for the entire switching cycle after
the maximum limit is reached.
0
1
2 ms of extra on time.
1
0
4 ms of extra on time.
1
1
8 ms of extra on time.
1 = SR outputs move from LLM to normal mode instantly.
0 = SR outputs transition from one mode to another (LLM to CCM or CCM to LLM) at the phase-in
speed (recommended).
Register 0xFE50[0] kills all PWM outputs that are modulated. However, this bit kills all PWM
outputs whether modulated or not (useful for FBPS topology where there are two fixed duty
cycle PWM outputs).
1 = kill all PWM outputs during pulse skip.
0 = do not kill all PWM outputs during pulse skip.
0 = all PWM outputs are disabled immediately on a shutdown condition.
1 = all PWM outputs are disabled at the end of the switching cycle on a shutdown condition.
If set, allow pulse skipping during soft stop (regardless of value of Bit 1). However, SR1 and SR2
never pulse skip during soft stop.
0 = disable.
1 = enable.
0 = pulse skipping drives all modulated PWM outputs to 0 V.
1 = sets all modulated edges to t = 0.
Table 194. Register 0xFE51—SOFT_START_SETTING
Bits
7
Bit Name
Soft stop enable for
current faults
R/W
R/W
6
Soft stop enable for other
faults
R/W
[5:3]
SR phase-in speed up
factor during soft stop
R/W
2
1
Force soft start filter
Disable light load filter
during soft start
R/W
R/W
0
Soft start from precharge
R/W
Description
0 = disable soft stop on a current fault.
1 = enable soft stop on a current fault.
0 = disable soft stop on a voltage fault.
1 = enable soft stop on a voltage and other fault.
During the soft stop process, these bits increase the SR edge transitioning speed that is
specified by Register 0xFE5F[7:4]. The speed-up factor is 2x where x is this 3-bit number. The
maximum speed of the SR edge is 40 ns per tSW.
For example, if Register 0xFE5F specifies 5 ns per 4 tSW, setting these three bits to 2 increases
the SR speed to 5 ns per tSW (5 ns/4tSW × 22). Setting these bits to 3 increases the SR speed to
10 ns per tSW (5 ns/4tSW × 23). Setting these bits to 7 increases the SR speed to 40 ns per tSW (the
maximum rate). A smaller value means slower SR transitioning.
1 = soft start filter is used regardless of whether the low temperature filter is active or not.
0 = allow switching to DCM filter during soft start.
1 = never switch to DCM filter during soft start.
Setting this bit to 1 enables the soft start from precharge function. When this function is
enabled, the soft start ramp starts from the last known value of the voltage detected on VS±.
Rev. A | Page 114 of 140
Data Sheet
ADP1055
Table 195. Register 0xFE52—SR_DELAY
Bits
[7:6]
Bit Name
SR blanking
R/W
R/W
[5:0]
SR driver delay
R/W
Description
These bits add blanking to the reverse current comparator from the falling edges of the SR LLM
edges. Adding dead time to the SR edges effectively gives additional blanking. When the SR
outputs are disabled upon a negative going zero crossing transition, they remain disabled for a
period of 327 μs to 754 μs to ensure that the comparator is not falsely triggered.
Bit 7
Bit 6
Blanking (ns)
0
0
40
0
1
80
1
0
120
1
1
160
These bits specify the 6-bit representation of the SR delay in steps of 5 ns.
000000 = 0 ns.
000001 = 5 ns.
000010 = 10 ns.
…
111111 = 63 × 5 ns = 315 ns.
Table 196. Register 0xFE53—MODULATION_LIMIT
Bits
7
[6:0]
Bit Name
Full bridge mode
Modulation limits
R/W
R/W
R/W
Description
Enable this bit when operating in full bridge mode. It affects the modulation high limit.
This value sets the minimum/maximum modulation limits relative to the nominal edge value. The
resolution depends on the switching frequency range.
Switching Frequency Range (kHz)
Resolution Corresponding to LSB
48.8 to 97.7
Register 0xFE53[6:0] × 32 × 5 ns
97.7 to 195.3
Register 0xFE53[6:0] × 16 × 5 ns
195.3 to 390.6
Register 0xFE53[6:0] × 8 × 5 ns
390.6 to 781
Register 0xFE53[6:0] × 4 × 5 ns
fSW > 781
Register 0xFE53[6:0] × 2 × 5 ns
Table 197. Register 0xFE55—SYNC (Requires Use of the GO Bit in Register 0xFE00)
Bits
7
6
Bit Name
Reserved
PLL disable
R/W
R
R/W
[5:2]
1
0
Reserved
Jitter enable
5 ns resolution
enable
R
R/W
R/W
Description
Reserved.
0 = enable SYNC function.
1 = disable SYNC function.
Reserved.
1 = enable jitter on clock (to randomize frequency components).
0 = tSW varies in multiples of 10 ns (50% point is synchronized with 5 ns; see the External Frequency
Synchronization section).
1 = tSW varies in multiples of 5 ns.
Table 198. Register 0xFE56—DUTY_BAL_EDGESEL
Bits
[7:4]
Bit Name
Positive integration
of PWM outputs
R/W
R/W
[3:0]
Negative integration
of PWM outputs
R/W
Description
1 = selects the PWM outputs to be AND’ed together for positive integration
Bit 7 = OUTA
Bit 6 = OUTB
Bit 5 = OUTC
Bit 4 = OUTD
1 = selects the PWM outputs to be AND’ed together for negative integration
Bit 3 = OUTA
Bit 2 = OUTB
Bit 1 = OUTC
Bit 0 = OUTD
Rev. A | Page 115 of 140
ADP1055
Data Sheet
Table 199. Register 0xFE57—DOUBLE_UPD_RATE (Requires Use of the GO Bit in Register 0xFE00)
Bits
7
Bit Name
Enable duty balance
R/W
R/W
6
Enable OCP duty
equalization
R/W
[5:4]
Duty balance
averaging time
R/W
3
[2:1]
Reserved
Duty balance and VS
balance limit
R/W
R/W
0
Enable double update
rate
R/W
Description
0 = disable.
1 = enable.
1 = enable OCP duty equalization. When OCP occurs, shut down any OUTx that is high and
generate an equalizing OCP to balance the complementary output. Refer to Register 0xFE56
for the selection of PWM outputs.
These bits control how rapidly the misbalance information is used to correct for imbalance.
Bit 5
Bit 4
Time
0
0
Normal value: cycle-by-cycle integral is divided by 8 and applied to OUTx.
0
1
2× faster: cycle-by-cycle integral is divided by 4 and applied to OUTx.
1
0
4× faster: cycle-by-cycle integral is divided by 2 and applied to OUTx.
1
1
8× faster: no averaging; cycle-by-cycle integral is applied on the next cycle
to OUTx.
Set to 0 for proper operation.
To balance OUTA and OUTB, time is added to or subtracted from OUTA and OUTB and added to or
subtracted from OUTC and OUTD, as in VS balance. These bits set the maximum balance value.
Bit 2
Bit 1
Limit (ns)
0
0
±160
0
1
±80
1
0
±40
1
1
±20
0 = disable.
1 = enable.
The VIN_SCALE_MONITOR command sets the gain (KVIN) by which the input sensed voltage at the DUT (VIN_DUT) is scaled to generate
the reading for the READ_VIN command. READ_VIN = VIN_DUT × KVIN, where KVIN = Y × 2N.
Table 200. Register 0xFE58—VIN_SCALE_MONITOR
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
The IIN_CAL_GAIN command sets the ratio of the voltage at the input current sense pins to the sensed current (in ohms).
Table 201. Register 0xFE59—IIN_CAL_GAIN
Bits
[15:11]
[10:0]
Bit Name
Exponent-N
Mantissa-Y
R/W
R/W
R/W
Description
Twos complement N-exponent used in linear data format (X = Y × 2N).
Twos complement Y-mantissa used in linear data format (X = Y × 2N).
The TSNS_SETTING command is the temperature sensor current select.
Table 202. Register 0xFE5A—TSNS_SETTING
Bits
7
[6:5]
Bit Name
Enable reverse diode
Resolution
R/W
R/W
R/W
4
3
Reserved
Temperature sense level
shift disable
R/W
R/W
[2:0]
Temperature sense
current select
R/W
Description
1 = enable external reverse temperature sensor
11 = 11 bit
10 = 12 bit
01 = 13 bit
00 = 14 bit
Set this bit to 0 for proper operation.
0 = enable internal diode level shifter during external TJ sense. This setting is recommended for a
single-ended (PN) diode connected between JTD and AGND.
1 = disable internal diode level shifter during external TJ sense. This setting is recommended for
differential sensing.
Set these bits to 0x04 for proper operation (10 μA).
Rev. A | Page 116 of 140
Data Sheet
ADP1055
Table 203. Register 0xFE5B—AUTO_GO_CMD
Bits
[7:2]
1
Bit Name
Reserved
Frequency auto-go
enable
R/W
R
R/W
0
VREF auto-go enable
R/W
Description
Reserved.
0 = GO_CMD, Bit 2 (Register 0xFE00) is required to latch the programmed frequency in
FREQUENCY_SWITCH into the internal loop frequency.
1 = write to FREQUENCY_SWITCH is automatically latched into the internal loop switching
frequency.
0 = GO_CMD, Bit 0 (Register 0xFE00) is required to latch the programmed reference voltage in
VOUT_COMMAND into the internal loop frequency.
1 = write to any commands affecting the reference voltage is automatically latched into the
internal loop reference voltage.
Commands that affect the reference voltage include VOUT_COMMAND, VOUT_MODE,
VOUT_MAX, VOUT_TRIM, VOUT_CAL_OFFSET, VOUT_SCALE_LOOP, and VOUT_DROOP.
Table 204. Register 0xFE5C—DIODE_EMULATION
Bits
[7:5]
Bit Name
SR debounce
R/W
R/W
[4:2]
1
Reserved
Diode emulation mode
R
R/W
0
SR toggle rate in diode
emulation mode
R/W
Description
These bits delay the onset of LLM or CCM when the light load mode or deep light load mode
threshold is crossed. The device transitions from CCM to LLM based on the debounce time
specified using these bits and the light load mode threshold. The same is true when the device
transitions from LLM to CCM and is also valid for deep light load mode.
For example, if the device is in CCM and the load current step places the device in LLM, the
device physically enters LLM, that is, the SR outputs start phasing after the debounce time set by
these bits. The same debounce time delays the entry to DCM.
Entering deep light load mode is possible only if the ADP1055 is already in DCM (that is, the
device is already below the DCM threshold) and SR transitioning is finished.
Bit 7
Bit 6
Bit 5
Debounce Time (tSW)
0
0
0
0
0
0
1
64
0
1
0
128
0
1
1
256
1
0
0
512
1
0
1
768
1
1
0
1152
1
1
1
2048
Reserved.
0 = disable diode emulation mode (SR LLM and deep LLM are active if the thresholds are
correctly set).
1 = enable diode emulation mode (SR LLM setting is disabled. Only deep LLM is active if the
threshold is correctly set). Once the SR outputs are disabled upon a negative going zero crossing
transition, they are disabled for a period of 327 μs to 754 μs to ensure that the comparator is not
falsely triggered.
0 = SR outputs toggle once in one tSW.
1 = SR outputs toggle twice in one tSW (recommended setting).
Table 205. Register 0xFE5D—CS2_CONST_CUR_MODE
Bits
[7:6]
[5:4]
Bit Name
Reserved
Slew rate during CC mode
(turbo mode only)
R/W
R
R/W
3
CC mode thresholds polarity
R/W
Description
Reserved.
00 = Nominal slew rate of (8 × 1.18) V/sec
Setting 00 provides 2x nominal at VS± pins in CC turbo mode
01 = 16×
10 = 24×
11 = 32×
0 = positive (% above OCP limit)
1 = negative (% below OCP limit)
Rev. A | Page 117 of 140
ADP1055
[2:0]
CC mode thresholds
Data Sheet
R/W
Percentage above or below OCP limit (IOUT_OC_FAULT_LIMIT)
00 = 0%
001 = 3.125%
010 = 6.25%
011 = 12.5%
100 = 25%
101 = 50%
11x = 100%
The NL_ERR_GAIN_FACTOR register applies nonlinear gain. Bits[7:6] apply nonlinear gain to the ±1% to 2% range, where the total
ADC range is 5% of 1 V, that is, ±50 mV. Bits[5:4] apply nonlinear gain to the ±2% to 3.2% range, where the total ADC range is 5% of 1 V,
that is, ±50 mV. Bits[3:2] apply nonlinear gain to the ±3.2% to 3.9% range, where the total ADC range is 5% of 1 V, that is, ±50 mV.
Bits[1:0] apply nonlinear gain to the ±3.9% and greater range, where the total ADC range is 5% of 1 V, that is, ±50 mV.
Table 206. Register 0xFE5E—NL_ERR_GAIN_FACTOR (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:6]
Bit Name
Nonlinear gain,
1% to 2% range
R/W
R/W
[5:4]
Nonlinear gain,
2% to 3.2% range
R/W
[3:2]
Nonlinear gain,
3.2% to 3.9% range
R/W
[1:0]
Nonlinear gain,
3.9% or greater range
R/W
Description
Bit 7
Bit 6
0
0
0
1
1
0
1
1
Bit 5
Bit 4
0
0
0
1
1
0
1
1
Bit 3
Bit 2
0
0
0
1
1
0
1
1
Bit 1
Bit 0
0
0
0
1
1
0
1
1
Gain
1× gain
2× gain or 1.25× (see Register 0xFE29[0])
4× gain or 1.5× (see Register 0xFE29[0])
8× gain or 2× (see Register 0xFE29[0])
Gain
1× gain
2× gain or 1.25× (see Register 0xFE29[0])
4× gain or 1.5× (see Register 0xFE29[0])
8× gain or 2× (see Register 0xFE29[0])
Gain
1× gain
2× gain or 1.25× (see Register 0xFE29[0])
4× gain or 1.5× (see Register 0xFE29[0])
8× gain or 2× (see Register 0xFE29[0])
Gain
1× gain
2× gain or 1.25× (see Register 0xFE29[0])
4× gain or 1.5× (see Register 0xFE29[0])
8× gain or 2× (see Register 0xFE29[0])
Rev. A | Page 118 of 140
Data Sheet
ADP1055
Table 207. Register 0xFE5F—SR_SETTING
Bits
[7:4]
Bit Name
SR phase-in
speed
R/W
R/W
Description
SR edges move by 5 ns every 1/2/4/8/16/32/64/128/256/384/512/640/768/832/960/1024 (total of 16).
SR outputs are always phased in during soft start, soft stop, and all mode transitions; for example, if SR
outputs enter pulse skip or are disabled, they turn on again at the phase-in speed selected by these
bits.
Bit 7
Bit 6
Bit 5
Bit 4
Multiplier
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
0
0
1
1
8
0
1
0
0
16
0
1
0
1
32
0
1
1
0
64
0
1
1
1
1
1
1
[3:1]
0
SR LLM threshold
Blank SR during
soft start
R/W
R/W
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
128
256
384
512
640
768
832
1
1
1
0
960
1
1
1
1
1024
These bits set the load current limit on the CS2 ADC below which SR1 and SR2 enter the light load mode
(SR on during forward conduction only). Averaging time, debounce, and hysteresis are the same
values set in Register 0xFE4B.
Bit 3
Bit 2
Bit 1
Thresholds (LSBs)
0
0
0
0
0
0
1
4
0
1
0
8
0
1
1
12
1
0
0
16
1
0
1
20
1
1
0
24
1
1
1
28
1 = blank SR during soft start.
Table 208. Register 0xFE60—NOMINAL_TEMP_POLE
Bits
[7:0]
Bit Name
ADD_PZ
R/W
R/W
Description
Additional pole/zero setting. A value of 0 disables ADD_PZ.
The analog frequency (in rad/sec) is located at w = ln(reg_val/256)/tSW, where tSW is the switching
period and reg_val is the contents of Register 0xFE60 and Register 0xFE61 in decimal format.
Table 209. Register 0xFE61—LOW_TEMP_POLE
Bits
[7:0]
Bit Name
ADD_PZ
R/W
R/W
Description
Additional pole/zero setting. A value of 0 disables ADD_PZ.
The analog pole frequency in rad/sec is located at w = ln(0xFE61[7:0]/256)/tSW, where tSW is the
switching period.
Rev. A | Page 119 of 140
ADP1055
Data Sheet
Table 210. Register 0xFE62—LOW_TEMP_SETTING
Bits
7
Bit Name
ADD_PZ configuration
R/W
R/W
[6:4]
Low temperature
threshold
R/W
[3:2]
Low temperature
hysteresis
R/W
[1:0]
Low temperature
sensing point
R/W
Description
0 = ADD_PZ is configured as a digital pole.
1 = ADD_PZ is configured as a digital zero.
If non-zero, the filter switches from the NMF (normal mode filter) to the SS filter (soft start filter) in
steps of ±4°C.
000 = regular filter operation independent of temperature unless the sensing point (configured in
Bits[1:0]) is set to GPIO2 (the filter then changes based on the GPIO2 pin).
001 = below −14°C, the soft start filter is used for regulation instead of the normal mode filter.
010 = below −10°C, the soft start filter is used for regulation instead of the normal mode filter.
011 = below −6°C, the soft start filter is used for regulation instead of the normal mode filter.
100 = below −2°C, the soft start filter is used for regulation instead of the normal mode filter.
101 = below +2°C, the soft start filter is used for regulation instead of the normal mode filter.
110 = below +6°C, the soft start filter is used for regulation instead of the normal mode filter.
111 = below +10°C, the soft start filter is used for regulation instead of the normal mode filter.
Each bit is 5°C of hysteresis.
00 = 5°C.
01 = 10°C.
10 = 15°C.
11 = 20°C.
00 = reserved.
01 = external FWD temperature sensing.
10 = external REV temperature sensing.
11 = rising edge of GPIO2.
Table 211. Register 0xFE63—GPIO3_4_SNUBBER_ON_TIME
Bits
[7:0]
Bit Name
Snubber on time
R/W
R/W
Description
Maximum on time of GPIO3/GPIO4 (if SR/OUTC/OUTD goes high, then the GPIO3/GPIO4 output
goes low/high) in units of 20 ns
0x00 = 0 ns
0x01 = 20 ns
…
0xFE = 5.08 μs
0xFF = on until SRx goes high or OUTC or OUTD goes low
Table 212. Register 0xFE64—GPIO3_4_SNUBBER_DELAY
Bits
[7:6]
Bit Name
GPIO4 snubber enable
R/W
R/W
[5:0]
Snubber delay
R/W
Description
00 = disable active snubber on GPIO3/GPIO4.
01 = only GPIO3 is active snubber. GPIO3 goes high after the snubber delay time in
Register 0xFE64[5:0].
10 = only GPIO4 is active snubber. GPIO4 goes high after the snubber delay time in
Register 0xFE64[5:0].
11 = GPIO3 and GPIO4 are active snubber outputs. GPIO3 is the inverse of SR1 or OUTC; GPIO4 is
the inverse of SR2 or OUTC, depending on Register 0xFE65[7].
Dead time delay from fall of SR to rise of GPIO3/GPIO4, in units of 5 ns, regardless of the polarity of
GPIO3/GPIO4.
0x00 = 0 ns.
0x01 = 5 ns.
0x3F = 315 ns.
Rev. A | Page 120 of 140
Data Sheet
ADP1055
Table 213. Register 0xFE65—VOUT_DROOP_SETTING
Bits
7
Bit Name
Snubber selection
R/W
R/W
[6:3]
2
Reserved
Disable VOUT_
TRANSITION_RATE
R
R/W
[1:0]
VOUT_DROOP
sampling rate
R/W
Description
0 = falling edge of SRx is used to activate the snubber.
1 = falling edge of OUTC or OUTD is used to activate the snubber.
Reserved.
1 = disable. The voltage reference immediately jumps to the value set by VOUT_COMMAND.
0 = enable. The output voltage changes from one value to another as programmed by the
VOUT_TRANSITION_RATE command.
For the purposes of VOUT_DROOP, IOUT is sampled at the following intervals:
00 = 7 bits = 82 μs.
01 = 8 bits = 164 μs.
10 = 9 bits = 327 μs.
11 = 10 bits = 655 μs.
Table 214. Register 0xFE66—NC_BURST_MODE (Requires Use of the GO Bit in Register 0xFE00)
Bits
[7:6]
Bit Name
ADC threshold
R/W
R/W
[5:3]
Number of burst
cycles
Enable burst in
LLM/DEM only
R/W
Burst magnitude
R/W
2
[1:0]
R/W
Description
Burst occurs if the ADC error exceeds the specified threshold.
00 = error threshold > |±1%| of 1 V (that is, 10 mV)
01 = error threshold > |±2%| of 1 V (that is, 20 mV)
10 = error threshold > |±3%| of 1 V (that is, 30 mV)
11 = error threshold > |±4%| of 1 V (that is, 40 mV)
Set to 0 for no burst
1 = burst in light load mode and diode emulation mode only (not in CCM)
0 = burst in any mode
Magnitude of burst in percentage of duty cycle that is added to the present duty cycle
00 = 6.25%
01 = 12.5%
10 = 25%
11 = 50%
Table 215. Register 0xFE67—HF_ADC_CONFIG
Bits
[7:4]
Bit Name
HF ADC samples
R/W
R/W
[3:0]
Reserved
R/W
Description
These bits specify the number of samples taken by the flash ADC for loop regulation. The number
of samples ranges from 1 (Bits[7:4] = 0000) to 16 (Bits[7:4] = 1111). Following are suggested values
depending on the frequency range and whether double update rate is enabled.
Frequency Range (kHz)
Double Update Rate Enabled Double Update Rate Disabled
fSW ≤ 250
1111 (16 samples)
1111 (16 samples)
250 < fSW ≤ 300
0111 (8 samples)
1111 (16 samples)
300 < fSW ≤ 724.638
0011 (4 samples)
1111 (16 samples)
724.638 < fSW ≤ 1000
0001 (2 samples)
0111 (8 samples)
Set these bits to 000 for proper operation.
Table 216. Register 0xFE80—VS_TRIM
Bits
7
Bit Name
Gain polarity
R/W
R/W
[6:0]
Gain trim
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
These bits set the amount of gain trim that is applied to the VS ADC reading. This register trims
the voltage at the VS± pins for external resistor tolerances. The VS trim must be performed before
the load OVP and load UVP trims are performed. The total range for these bits is ±6.25%. The
LSB = (6.25%)/128.
Rev. A | Page 121 of 140
ADP1055
Data Sheet
Table 217. Register 0xFE81—VFF_GAIN_TRIM
Bits
7
Bit Name
Gain polarity
R/W
R/W
[6:0]
Gain trim
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
These bits set the gain trim for the VFF ADC. Total range is ±12.5% with 128 steps in the positive direction
and 127 steps in the negative direction, and the LSB = 12.5%/128.
Table 218. Register 0xFE82—CS1_GAIN_TRIM
Bits
7
Bit Name
Gain polarity
R/W
R/W
[6:0]
Gain trim
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
These bits set the gain trim for the primary side current gain. Total range is ±12.5% with 128 steps in the
positive direction and 127 steps in the negative direction, and the LSB = 12.5%/128.
Table 219. Register 0xFE86—TSNS_EXTFWD_GAIN_TRIM
Bits
[7:0]
Bit Name
Gain trim
R/W
R/W
Description
Gain trim in twos complement added to scaling factor (977 for 10-bit resolution set) for external forward
diode temperature measurement. For example,
Register 0xFE5A[6:5] = 00 corresponds to an increase in gain by 1/489%
Register 0xFE86 = 0x01 corresponds to an increase in gain by 1/977%
Register 0xFE86 = 0x02 corresponds to an increase in gain by 2/977%
Table 220. Register 0xFE87—TSNS_EXTFWD_OFFSET_TRIM
Bits
[7:0]
Bit Name
Offset trim
R/W
R/W
Description
Offset trim added to the acquisition result of the forward diode temperature measurement; 1 LSB
corresponds to 0.0156°C, in twos complement format. Maximum correction is 2°C.
Table 221. Register 0xFE88—TSNS_EXTREV_GAIN_TRIM
Bits
[7:0]
Bit Name
Gain trim
R/W
R/W
Description
Gain trim in twos complement added to scaling factor (977 for 10-bit resolution set) for external reverse
diode temperature measurement. For example,
Register 0xFE88 = 0x01 corresponds to an increase in gain by 1/977%
Register 0xFE88 = 0x02 corresponds to an increase in gain by 2/977%
Table 222. Register 0xFE89—TSNS_EXTREV_OFFSET_TRIM
Bits
[7:0]
Bit Name
Offset trim
R/W
R/W
Description
Offset trim added to the acquisition result of the reverse diode temperature measurement; 1 LSB
corresponds to 0.0156°C, in twos complement format. Maximum correction is 2°C.
Table 223. Register 0xFE8C—FAULT_VOUT
Bits
[7:0]
Bit Name
FAULT_VOUT
R/W
R
Description
Unlatched fault conditions after debounce (see STATUS_VOUT for latched version)
Table 224. Register 0xFE8D—FAULT_IOUT
Bits
[7:0]
Bit Name
FAULT_IOUT
R/W
R
Description
Unlatched fault conditions after debounce (see STATUS_IOUT for latched version)
Table 225. Register 0xFE8E—FAULT_INPUT
Bits
[7:0]
Bit Name
FAULT_INPUT
R/W
R
Description
Unlatched fault conditions after debounce (see STATUS_INPUT for latched version)
Rev. A | Page 122 of 140
Data Sheet
ADP1055
Table 226. Register 0xFE8F—FAULT_TEMPERATURE
Bits
[7:0]
Bit Name
FAULT_TEMPERATURE
R/W
R
Description
Unlatched fault conditions after debounce (see STATUS_TEMPERATURE for latched version)
Table 227. Register 0xFE90—FAULT_CML
Bits
[7:0]
Bit Name
FAULT_CML
R/W
R
Description
Unlatched fault conditions after debounce (see STATUS_CML for latched version)
Table 228. Register 0xFE91—FAULT_OTHER
Bits
[7:0]
Bit Name
FAULT_OTHER
R/W
R
Description
Unlatched fault conditions after debounce (see STATUS_OTHER for latched version)
Table 229. Register 0xFE92—FAULT_MFR_SPECIFIC
Bits
[7:0]
Bit Name
FAULT_MFR_SPECIFIC
R/W
R
Description
Unlatched fault conditions after debounce (see STATUS_MFR_SPECIFIC for latched version)
Table 230. Register 0xFE93—FAULT_UNKNOWN
Bits
[15:0]
Bit Name
FAULT_UNKNOWN
R/W
R
Description
Unlatched fault conditions after debounce (see STATUS_UNKNOWN for latched version)
Table 231. Register 0xFE94—STATUS_UNKNOWN
Bits
15
14
13
12
R/W
R/W
R/W
R/W
R/W
Description
The EEPROM is unlocked.
Adaptive dead time threshold has been crossed.
The soft start filter is in use.
The reference is being ramped up (soft start) or ramped down (soft stop).
R/W
R/W
Modulation is at its minimum or maximum limit.
Volt-second balance or duty balance at is the maximum/minimum limit.
9
8
7
6
5
4
Bit Name
EEPROM unlocked
Adaptive dead time
Soft start filter
Soft start ramp
or soft stop ramp
Modulation limit
Volt-second and
duty balance limit
Light load mode
Constant current
PGOOD2 fault
PGOOD1 fault
Sync unlock
SR off
R/W
R/W
R/W
R/W
R/W
R/W
3
2
1
Address warning
VCORE OV
VDD OV
R/W
R/W
R/W
0
VDD UV
R/W
The device is in light load mode.
Power supply is operating in constant current mode (constant current mode is enabled).
PGOOD2 fault. At least one of the flags listed in Register 0xFE45 has been set (see Table 182).
PGOOD1 fault. At least one of the flags listed in Register 0xFE44 has been set (see Table 181).
Sync mode is enabled, but unit not locked to sync input frequency.
Synchronous rectifiers SR1 and SR2 are disabled. This flag is set when one of the following cases
is true: SR1 and SR2 are disabled by the user; the load current has fallen below the threshold in
Register 0xFE4B[7:5]; a fault has been set that was configured to disable the synchronous
rectifiers; or SR outputs are blanked during soft start and during a pulse skip condition.
I2C/PMBus address warning. ADD resistor value out-of-range.
2.5 V VCORE is above limit. Action is set to immediate shutdown.
VDD is above limit. The I2C interface stays functional, but a unit power-off/power-on sequence
is required to restart the power supply. The response to a VDD overvoltage is programmable in
Register 0xFE4D[6].
VDD is below limit. The response to a VDD undervoltage immediate shutdown.
11
10
Rev. A | Page 123 of 140
ADP1055
Data Sheet
Table 232. Register 0xFE95—FIRST_FAULT_ID
Bits
[7:0]
Bit Name
First-fault ID (in hex)
R/W
R
Description
0x00 = no fault
0x01 = VOUT_OV
0x02 = VOUT_OV_FAST
0x03 = VOUT_UV
0x04 = IOUT_OC_LV
0x05 = VIN_OV
0x06 = VIN_UV
0x07 = OT
0x08 = TON_MAX
0x09 = POUT_OP
0x0A = GPIO1
0x0B = GPIO2
0x0C = GPIO3
0x0D = GPIO4
0x0E = IOUT_OC
0x0F = IOUT_OC_FAST
0x10 = IOUT_UC
0x11 = IOUT_UC_FAST
0x12 = IIN_OC
0x13 = IIN_OC_FAST
0x14 = ISHARE
Table 233. Register 0xFE96—VFF_VALUE
Bits
[15:0]
Bit Name
VFF value
R/W
R
Description
This register contains the feedforward information. This value has 12 bits of resolution from
Bit 13 to Bit 2.
Table 234. Register 0xFE97—VS_VALUE
Bits
[15:0]
Bit Name
VS value
(output voltage)
R/W
R
Description
This register contains the output voltage information. This value has 12 bits of resolution from
Bit 13 to Bit 2.
Table 235. Register 0xFE98—CS1_VALUE
Bits
[15:0]
Bit Name
CS1 value
(input current)
R/W
R
Description
This register contains the input current information. This value has 12 bits of resolution from Bit
13 to Bit 2.
Table 236. Register 0xFE99—CS2_VALUE
Bits
[15:0]
Bit Name
CS2 value
(output current)
R/W
R
Description
This register contains the 12-bit output current information. This value is the voltage drop
across the sense resistor. To obtain the current value, divide the value of this register by the
sense resistor value. The CS2± pins have a full-scale input range of 30 mV, 60 mV, or 480 mV (set
in Register 0xFE4F[1:0]).
When the CS2 input range is set to 30 mV, the LSB step size is 7.32 μV. For example, at a 15 mV
input signal on CS2, the value in this register is 15 mV/7.32 μV = 1000 0000 0000.
Table 237. Register 0xFE9A—POUT_VALUE
Bits
[15:0]
Bit Name
CS2 × VS value
(output power)
R/W
R
Description
This register contains the 16-bit output power information. This value is the product of the
remote output voltage value (VS) and the output current reading (CS2).
Rev. A | Page 124 of 140
Data Sheet
ADP1055
Table 238. Register 0xFE9B—Reserved
Bits
[15:0]
Bit Name
Reserved
R/W
R
Description
Reserved.
Table 239. Register 0xFE9C—TSNS_EXTFWD_VALUE
Bits
[15:7]
[6:0]
Bit Name
Integer
Decimal
R/W
R
R
Description
Twos complement integer in the range of −256 to +255
Decimal component of the temperature reading
Table 240. Register 0xFE9D—TSNS_EXTREV_VALUE
Bits
[15:7]
[6:0]
Bit Name
Integer
Decimal
R/W
R
R
Description
Twos complement integer in the range of −256 to +255
Decimal component of the temperature reading
Table 241. Register 0xFE9F—MODULATION_VALUE
Bits
[7:0]
Bit Name
Modulation
value
R/W
R
Description
This register contains the 8-bit modulation information. It outputs the amount of modulation from 0% to
100% that is being placed on the modulating edges.
Table 242. Register 0xFEA0—ISHARE_VALUE
Bits
[7:0]
Bit Name
Share bus
value
R/W
R
Description
This register contains the 8-bit share bus voltage information. If the power supply is the master, this register
outputs 0.
Table 243. Register 0xFEA3—ADD_ADC_VALUE
Bits
[7:0]
Bit Name
ADD ADC
value
R/W
R
Description
This register contains the address information. This value has eight bits of resolution.
LSB = 1.6/28 = 6.25 mV. At 1 V input, the value in this register is 160 (0xA0). It is used in conjunction with
Register 0xD0[5:4].
Rev. A | Page 125 of 140
ADP1055
Data Sheet
SUPPORTED SWITCHING FREQUENCIES
Table 244 lists switching frequencies supported by the ADP1055. For information about setting the switching frequency, see the
FREQUENCY_SWITCH section. For entries with the same exponent and mantissa values, the entry with the lower period value is valid.
Table 244. Supported Switching Frequencies
Period (ns)
20,470
20,460
20,430
20,400
20,380
20,350
20,330
20,300
20,270
20,250
20,220
20,200
20,170
20,150
20,120
20,100
20,070
20,050
20,020
20,000
19,970
19,950
19,920
19,900
19,870
19,850
19,820
19,800
19,770
19,750
19,720
19,700
19,680
19,650
19,630
19,600
19,580
19,550
19,530
19,510
19,480
19,460
19,440
19,410
19,390
19,370
19,340
Frequency (kHz)
48.85197851
48.87585533
48.94762604
49.01960784
49.06771344
49.14004914
49.18839154
49.26108374
49.33399112
49.38271605
49.45598417
49.5049505
49.57858205
49.62779156
49.70178926
49.75124378
49.82561036
49.87531172
49.95004995
50
50.07511267
50.12531328
50.20080321
50.25125628
50.32712632
50.37783375
50.45408678
50.50505051
50.58168943
50.63291139
50.70993915
50.76142132
50.81300813
50.89058524
50.94243505
51.02040816
51.07252298
51.15089514
51.20327701
51.25576627
51.33470226
51.38746146
51.44032922
51.51983514
51.57297576
51.62622612
51.70630817
Exponent
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
Mantissa
782
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
Period (ns)
19,320
19,300
19,270
19,250
19,230
19,200
19,180
19,160
19,130
19,110
19,090
19,070
19,040
19,020
19,000
18,970
18,950
18,930
18,910
18,890
18,860
18,840
18,820
18,800
18,770
18,750
18,730
18,710
18,690
18,660
18,640
18,620
18,600
18,580
18,560
18,530
18,510
18,490
18,470
18,450
18,430
18,410
18,390
18,360
18,340
18,320
18,300
Rev. A | Page 126 of 140
Frequency (kHz)
51.75983437
51.8134715
51.89413596
51.94805195
52.00208008
52.08333333
52.13764338
52.19206681
52.27391532
52.32862376
52.38344683
52.4383849
52.5210084
52.57623554
52.63157895
52.71481286
52.77044855
52.8262018
52.88207298
52.93806247
53.02226935
53.07855626
53.13496281
53.19148936
53.27650506
53.33333333
53.39028297
53.44735436
53.50454789
53.59056806
53.64806867
53.7056928
53.76344086
53.82131324
53.87931034
53.96654074
54.02485143
54.08328826
54.14185165
54.20054201
54.25935974
54.31830527
54.37737901
54.46623094
54.52562704
54.58515284
54.64480874
Exponent
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
Mantissa
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
Data Sheet
Period (ns)
18,280
18,260
18,240
18,220
18,200
18,180
18,160
18,140
18,120
18,090
18,070
18,050
18,030
18,010
17,990
17,970
17,950
17,930
17,910
17,890
17,870
17,850
17,830
17,810
17,790
17,770
17,750
17,730
17,710
17,690
17,670
17,660
17,640
17,620
17,600
17,580
17,560
17,540
17,520
17,500
17,480
17,460
17,440
17,420
17,410
17,390
17,370
17,350
17,330
17,310
17,290
17,270
17,250
Frequency (kHz)
54.70459519
54.7645126
54.8245614
54.88474204
54.94505495
55.00550055
55.0660793
55.12679162
55.18763797
55.27915976
55.34034311
55.40166205
55.46311703
55.5247085
55.58643691
55.64830273
55.71030641
55.77244841
55.8347292
55.89714925
55.95970901
56.02240896
56.08524958
56.14823133
56.21135469
56.27462015
56.33802817
56.40157924
56.46527386
56.52911249
56.59309564
56.62514156
56.6893424
56.75368899
56.81818182
56.88282139
56.9476082
57.01254276
57.07762557
57.14285714
57.20823799
57.27376861
57.33944954
57.40528129
57.43825388
57.50431282
57.57052389
57.63688761
57.7034045
57.7700751
57.83689994
57.90387956
57.97101449
ADP1055
Exponent
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
Mantissa
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
928
Period (ns)
17,240
17,220
17,200
17,180
17,160
17,140
17,130
17,110
17,090
17,070
17,050
17,030
17,020
17,000
16,980
16,960
16,940
16,930
16,910
16,890
16,870
16,850
16,840
16,820
16,800
16,780
16,770
16,750
16,730
16,710
16,700
16,680
16,660
16,640
16,630
16,610
16,590
16,580
16,560
16,540
16,520
16,510
16,490
16,470
16,460
16,440
16,420
16,410
16,390
16,370
16,350
16,340
16,320
Rev. A | Page 127 of 140
Frequency (kHz)
58.00464037
58.07200929
58.13953488
58.20721769
58.27505828
58.34305718
58.37711617
58.44535359
58.51375073
58.58230814
58.65102639
58.71990605
58.75440658
58.82352941
58.89281508
58.96226415
59.03187721
59.06674542
59.13660556
59.20663114
59.27682276
59.34718101
59.3824228
59.4530321
59.52380952
59.59475566
59.63029219
59.70149254
59.77286312
59.84440455
59.88023952
59.95203837
60.0240096
60.09615385
60.13229104
60.20469597
60.27727547
60.31363088
60.38647343
60.45949214
60.53268765
60.56935191
60.64281383
60.71645416
60.75334143
60.82725061
60.90133983
60.93845216
61.01281269
61.08735492
61.16207951
61.1995104
61.2745098
Exponent
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
Mantissa
928
929
930
931
932
933
934
935
936
937
938
940
940
941
942
943
945
945
946
947
948
950
950
951
952
954
954
955
956
958
958
959
960
962
962
963
964
965
966
967
969
969
970
971
972
973
974
975
976
977
979
979
980
ADP1055
Period (ns)
16,300
16,290
16,270
16,260
16,240
16,220
16,210
16,190
16,170
16,160
16,140
16,120
16,110
16,090
16,080
16,060
16,040
16,030
16,010
16,000
15,980
15,960
15,950
15,930
15,920
15,900
15,880
15,870
15,850
15,840
15,820
15,810
15,790
15,770
15,760
15,740
15,730
15,710
15,700
15,680
15,670
15,650
15,640
15,620
15,590
15,560
15,530
15,500
15,470
15,440
15,410
15,380
15,350
Data Sheet
Frequency (kHz)
61.34969325
61.38735421
61.462815
61.50061501
61.57635468
61.65228113
61.69031462
61.76652254
61.84291899
61.88118812
61.95786865
62.03473945
62.07324643
62.15040398
62.18905473
62.26650062
62.34413965
62.38303182
62.4609619
62.5
62.57822278
62.6566416
62.69592476
62.77463905
62.81407035
62.89308176
62.97229219
63.01197227
63.09148265
63.13131313
63.21112516
63.25110689
63.33122229
63.4115409
63.45177665
63.53240152
63.57279085
63.65372374
63.69426752
63.7755102
63.81620932
63.89776358
63.93861893
64.02048656
64.14368185
64.26735219
64.39150032
64.51612903
64.64124111
64.76683938
64.89292667
65.01950585
65.1465798
Exponent
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−4
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
982
982
983
984
985
986
987
988
989
990
991
993
993
994
995
996
998
998
999
1000
1001
1003
1003
1004
1005
1006
1008
1008
1009
1010
1011
1012
1013
1015
1015
1017
1017
1018
1019
1020
1021
1022
1023
512
513
514
515
516
517
518
519
520
521
Period (ns)
15,320
15,290
15,260
15,230
15,200
15,180
15,150
15,120
15,090
15,060
15,030
15,000
14,980
14,950
14,920
14,890
14,860
14,840
14,810
14,780
14,760
14,730
14,700
14,670
14,650
14,620
14,590
14,570
14,540
14,510
14,490
14,460
14,440
14,410
14,380
14,360
14,330
14,310
14,280
14,260
14,230
14,200
14,180
14,150
14,130
14,100
14,080
14,050
14,030
14,010
13,980
13,960
13,930
Rev. A | Page 128 of 140
Frequency (kHz)
65.27415144
65.40222368
65.53079948
65.65988181
65.78947368
65.87615283
66.00660066
66.13756614
66.26905235
66.40106242
66.53359947
66.66666667
66.75567423
66.88963211
67.02412869
67.15916723
67.29475101
67.38544474
67.52194463
67.65899865
67.75067751
67.88866259
68.02721088
68.16632584
68.25938567
68.3994528
68.54009596
68.63417982
68.77579092
68.91798759
69.01311249
69.15629322
69.25207756
69.3962526
69.54102921
69.63788301
69.78367062
69.88120196
70.0280112
70.12622721
70.27406887
70.42253521
70.52186178
70.67137809
70.77140835
70.92198582
71.02272727
71.17437722
71.27583749
71.37758744
71.53075823
71.63323782
71.78750897
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
Data Sheet
Period (ns)
13,910
13,880
13,860
13,840
13,810
13,790
13,760
13,740
13,720
13,690
13,670
13,650
13,620
13,600
13,580
13,550
13,530
13,510
13,490
13,460
13,440
13,420
13,400
13,370
13,350
13,330
13,310
13,280
13,260
13,240
13,220
13,200
13,170
13,150
13,130
13,110
13,090
13,070
13,050
13,020
13,000
12,980
12,960
12,940
12,920
12,900
12,880
12,860
12,840
12,820
12,800
12,770
12,750
Frequency (kHz)
71.8907261
72.04610951
72.15007215
72.25433526
72.41129616
72.51631617
72.6744186
72.78020378
72.88629738
73.04601899
73.15288954
73.26007326
73.42143906
73.52941176
73.6377025
73.80073801
73.90983001
74.019245
74.12898443
74.29420505
74.4047619
74.51564829
74.62686567
74.79431563
74.90636704
75.01875469
75.13148009
75.30120482
75.4147813
75.52870091
75.6429652
75.75757576
75.93014427
76.04562738
76.1614623
76.27765065
76.39419404
76.51109411
76.62835249
76.80491551
76.92307692
77.04160247
77.16049383
77.2797527
77.3993808
77.51937984
77.63975155
77.76049767
77.88161994
78.00312012
78.125
78.30853563
78.43137255
ADP1055
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
Period (ns)
12,730
12,710
12,690
12,670
12,650
12,630
12,610
12,590
12,570
12,550
12,530
12,510
12,500
12,480
12,460
12,440
12,420
12,400
12,380
12,360
12,340
12,320
12,300
12,280
12,260
12,250
12,230
12,210
12,190
12,170
12,150
12,130
12,120
12,100
12,080
12,060
12,040
12,030
12,010
11,990
11,970
11,950
11,940
11,920
11,900
11,880
11,860
11,850
11,830
11,810
11,790
11,780
11,760
Rev. A | Page 129 of 140
Frequency (kHz)
78.55459544
78.67820614
78.80220646
78.92659826
79.0513834
79.17656374
79.30214116
79.42811755
79.55449483
79.6812749
79.8084597
79.93605116
80
80.12820513
80.25682183
80.38585209
80.51529791
80.64516129
80.77544426
80.90614887
81.03727715
81.16883117
81.30081301
81.43322476
81.56606852
81.63265306
81.76614881
81.9000819
82.03445447
82.16926869
82.30452675
82.44023083
82.50825083
82.6446281
82.78145695
82.91873964
83.05647841
83.12551953
83.26394671
83.4028357
83.54218881
83.68200837
83.7520938
83.89261745
84.03361345
84.17508418
84.31703204
84.38818565
84.53085376
84.67400508
84.81764207
84.88964346
85.03401361
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
653
653
654
655
656
657
658
660
660
661
662
663
664
665
666
667
668
669
670
671
672
673
675
675
676
677
679
679
680
ADP1055
Period (ns)
11,740
11,730
11,710
11,690
11,670
11,660
11,640
11,620
11,610
11,590
11,570
11,560
11,540
11,520
11,510
11,490
11,470
11,460
11,440
11,420
11,410
11,390
11,370
11,360
11,340
11,330
11,310
11,290
11,280
11,260
11,250
11,230
11,220
11,200
11,180
11,170
11,150
11,140
11,120
11,110
11,090
11,080
11,060
11,040
11,030
11,010
11,000
10,980
10,970
10,950
10,940
10,920
10,910
Data Sheet
Frequency (kHz)
85.17887564
85.2514919
85.3970965
85.54319932
85.68980291
85.76329331
85.91065292
86.05851979
86.13264427
86.28127696
86.43042351
86.50519031
86.65511265
86.80555556
86.88097307
87.03220191
87.18395815
87.2600349
87.41258741
87.56567426
87.64241893
87.79631255
87.95074758
88.02816901
88.18342152
88.26125331
88.4173298
88.57395926
88.65248227
88.80994671
88.88888889
89.04719501
89.12655971
89.28571429
89.44543828
89.52551477
89.68609865
89.76660682
89.92805755
90.0090009
90.17132552
90.25270758
90.4159132
90.57971014
90.66183137
90.82652134
90.90909091
91.07468124
91.15770283
91.32420091
91.40767824
91.57509158
91.65902841
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
681
682
683
684
686
686
687
688
689
690
691
692
693
694
695
696
697
698
699
701
701
702
704
704
705
706
707
709
709
710
711
712
713
714
716
716
717
718
719
720
721
722
723
725
725
727
727
729
729
731
731
733
733
Period (ns)
10,890
10,880
10,860
10,850
10,840
10,820
10,810
10,790
10,780
10,760
10,750
10,730
10,720
10,700
10,690
10,680
10,660
10,650
10,630
10,620
10,610
10,590
10,580
10,560
10,550
10,540
10,520
10,510
10,490
10,480
10,470
10,450
10,440
10,430
10,410
10,400
10,380
10,370
10,360
10,340
10,330
10,320
10,300
10,290
10,280
10,260
10,250
10,240
10,230
10,210
10,200
10,190
10,170
Rev. A | Page 130 of 140
Frequency (kHz)
91.82736455
91.91176471
92.08103131
92.16589862
92.25092251
92.42144177
92.50693802
92.67840593
92.76437848
92.93680297
93.02325581
93.19664492
93.28358209
93.45794393
93.5453695
93.6329588
93.80863039
93.89671362
94.07337723
94.16195857
94.25070688
94.42870633
94.51795841
94.6969697
94.78672986
94.87666034
95.05703422
95.14747859
95.32888465
95.41984733
95.51098376
95.6937799
95.78544061
95.87727709
96.06147935
96.15384615
96.33911368
96.43201543
96.52509653
96.71179884
96.8054211
96.89922481
97.08737864
97.18172983
97.27626459
97.46588694
97.56097561
97.65625
97.75171065
97.94319295
98.03921569
98.13542689
98.32841691
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
735
735
737
737
738
739
740
741
742
743
744
746
746
748
748
749
750
751
753
753
754
755
756
758
758
759
760
761
763
763
764
766
766
767
768
769
771
771
772
774
774
775
777
777
778
780
780
781
782
784
784
785
787
Data Sheet
Period (ns)
10,160
10,150
10,130
10,120
10,110
10,100
10,080
10,070
10,060
10,050
10,030
10,020
10,010
10,000
9980
9970
9960
9950
9930
9920
9910
9900
9880
9870
9860
9850
9840
9820
9810
9800
9790
9770
9760
9750
9740
9730
9720
9700
9690
9680
9670
9660
9650
9630
9620
9610
9600
9590
9580
9560
9550
9540
9530
Frequency (kHz)
98.42519685
98.52216749
98.71668312
98.81422925
98.91196835
99.00990099
99.20634921
99.30486594
99.40357853
99.50248756
99.70089731
99.8003992
99.9000999
100
100.2004008
100.3009027
100.4016064
100.5025126
100.7049345
100.8064516
100.9081736
101.010101
101.2145749
101.3171226
101.4198783
101.5228426
101.6260163
101.8329939
101.9367992
102.0408163
102.145046
102.3541453
102.4590164
102.5641026
102.6694045
102.7749229
102.8806584
103.0927835
103.1991744
103.3057851
103.4126163
103.5196687
103.626943
103.8421599
103.950104
104.0582726
104.1666667
104.2752868
104.3841336
104.6025105
104.7120419
104.8218029
104.9317943
ADP1055
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
787
788
790
791
791
792
794
794
795
796
798
798
799
800
802
802
803
804
806
806
807
808
810
811
811
812
813
815
815
816
817
819
820
821
821
822
823
825
826
826
827
828
829
831
832
832
833
834
835
837
838
839
839
Period (ns)
9520
9510
9500
9480
9470
9460
9450
9440
9430
9420
9410
9400
9380
9370
9360
9350
9340
9330
9320
9310
9300
9290
9280
9260
9250
9240
9230
9220
9210
9200
9190
9180
9170
9160
9150
9140
9130
9120
9110
9100
9090
9080
9070
9060
9040
9030
9020
9010
9000
8990
8980
8970
8960
Rev. A | Page 131 of 140
Frequency (kHz)
105.0420168
105.1524711
105.2631579
105.4852321
105.5966209
105.7082452
105.8201058
105.9322034
106.0445387
106.1571125
106.2699256
106.3829787
106.6098081
106.7235859
106.8376068
106.9518717
107.0663812
107.1811361
107.2961373
107.4113856
107.5268817
107.6426265
107.7586207
107.9913607
108.1081081
108.2251082
108.3423619
108.4598698
108.577633
108.6956522
108.8139282
108.9324619
109.0512541
109.1703057
109.2896175
109.4091904
109.5290252
109.6491228
109.7694841
109.8901099
110.0110011
110.1321586
110.2535832
110.3752759
110.619469
110.7419712
110.864745
110.9877913
111.1111111
111.2347052
111.3585746
111.4827202
111.6071429
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
840
841
842
844
845
846
847
847
848
849
850
851
853
854
855
856
857
857
858
859
860
861
862
864
865
866
867
868
869
870
871
871
872
873
874
875
876
877
878
879
880
881
882
883
885
886
887
888
889
890
891
892
893
ADP1055
Period (ns)
8950
8940
8930
8920
8910
8900
8890
8880
8870
8860
8850
8840
8830
8820
8810
8800
8790
8780
8770
8760
8750
8740
8730
8720
8710
8700
8690
8680
8670
8660
8650
8640
8630
8620
8610
8600
8590
8580
8570
8560
8550
8540
8530
8520
8510
8500
8490
8480
8470
8460
8450
8440
8430
Data Sheet
Frequency (kHz)
111.7318436
111.8568233
111.9820829
112.1076233
112.2334456
112.3595506
112.4859393
112.6126126
112.7395716
112.8668172
112.9943503
113.1221719
113.2502831
113.3786848
113.507378
113.6363636
113.7656428
113.8952164
114.0250855
114.1552511
114.2857143
114.416476
114.5475372
114.6788991
114.8105626
114.9425287
115.0747986
115.2073733
115.3402537
115.4734411
115.6069364
115.7407407
115.8748552
116.0092807
116.1440186
116.2790698
116.4144354
116.5501166
116.6861144
116.8224299
116.9590643
117.0960187
117.2332943
117.370892
117.5088132
117.6470588
117.7856302
117.9245283
118.0637544
118.2033097
118.3431953
118.4834123
118.623962
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
920
921
922
923
924
925
926
927
928
929
930
931
932
933
935
936
937
938
939
940
941
942
943
945
946
947
948
949
Period (ns)
8420
8410
8400
8390
8380
8370
8360
8350
8340
8330
8320
8310
8300
8290
8280
8270
8260
8250
8240
8230
8220
8210
8200
8190
8180
8170
8160
8150
8140
8130
8120
8110
8100
8090
8080
8070
8060
8050
8040
8030
8020
8010
8000
7990
7980
7970
7960
7950
7940
7930
7920
7910
7900
Rev. A | Page 132 of 140
Frequency (kHz)
118.7648456
118.9060642
119.047619
119.1895113
119.3317422
119.474313
119.6172249
119.760479
119.9040767
120.0480192
120.1923077
120.3369434
120.4819277
120.6272618
120.7729469
120.9189843
121.0653753
121.2121212
121.3592233
121.5066829
121.6545012
121.8026797
121.9512195
122.1001221
122.2493888
122.3990208
122.5490196
122.6993865
122.8501229
123.00123
123.1527094
123.3045623
123.4567901
123.6093943
123.7623762
123.9157373
124.0694789
124.2236025
124.3781095
124.5330012
124.6882793
124.8439451
125
125.1564456
125.3132832
125.4705144
125.6281407
125.7861635
125.9445844
126.1034048
126.2626263
126.4222503
126.5822785
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
−3
Mantissa
950
951
952
954
955
956
957
958
959
960
962
963
964
965
966
967
969
970
971
972
973
974
976
977
978
979
980
982
983
984
985
986
988
989
990
991
993
994
995
996
998
999
1000
1001
1003
1004
1005
1006
1008
1009
1010
1011
1013
Data Sheet
Period (ns)
7890
7880
7870
7860
7850
7840
7830
7820
7810
7790
7780
7760
7750
7730
7720
7700
7690
7670
7660
7640
7630
7610
7600
7590
7570
7560
7540
7530
7510
7500
7490
7470
7460
7440
7430
7420
7400
7390
7380
7360
7350
7330
7320
7310
7290
7280
7270
7250
7240
7230
7220
7200
7190
Frequency (kHz)
126.7427123
126.9035533
127.064803
127.2264631
127.388535
127.5510204
127.7139208
127.8772379
128.0409731
128.3697047
128.5347044
128.8659794
129.0322581
129.3661061
129.5336788
129.8701299
130.0390117
130.3780965
130.5483029
130.8900524
131.061599
131.4060447
131.5789474
131.7523057
132.1003963
132.2751323
132.6259947
132.8021248
133.1557923
133.3333333
133.5113485
133.8688086
134.0482574
134.4086022
134.589502
134.7708895
135.1351351
135.3179973
135.501355
135.8695652
136.0544218
136.425648
136.6120219
136.7989056
137.1742112
137.3626374
137.5515818
137.9310345
138.121547
138.3125864
138.5041551
138.8888889
139.0820584
ADP1055
Exponent
−3
−3
−3
−3
−3
−3
−3
−3
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
Mantissa
1014
1015
1017
1018
1019
1020
1022
1023
512
513
514
515
516
517
518
519
520
522
522
524
524
526
526
527
528
529
531
531
533
533
534
535
536
538
538
539
541
541
542
543
544
546
546
547
549
549
550
552
552
553
554
556
556
Period (ns)
7180
7160
7150
7140
7130
7110
7100
7090
7070
7060
7050
7040
7020
7010
7000
6990
6980
6960
6950
6940
6930
6920
6900
6890
6880
6870
6860
6840
6830
6820
6810
6800
6790
6770
6760
6750
6740
6730
6720
6710
6700
6680
6670
6660
6650
6640
6630
6620
6610
6600
6580
6570
6560
Rev. A | Page 133 of 140
Frequency (kHz)
139.275766
139.6648045
139.8601399
140.0560224
140.2524544
140.6469761
140.8450704
141.0437236
141.4427157
141.6430595
141.8439716
142.0454545
142.4501425
142.6533524
142.8571429
143.0615165
143.2664756
143.6781609
143.8848921
144.092219
144.3001443
144.5086705
144.9275362
145.137881
145.3488372
145.5604076
145.7725948
146.1988304
146.4128843
146.627566
146.8428781
147.0588235
147.275405
147.7104874
147.9289941
148.1481481
148.3679525
148.5884101
148.8095238
149.0312966
149.2537313
149.7005988
149.9250375
150.1501502
150.3759398
150.6024096
150.8295626
151.0574018
151.2859304
151.5151515
151.9756839
152.2070015
152.4390244
Exponent
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
Mantissa
557
559
559
560
561
563
563
564
566
567
567
568
570
571
571
572
573
575
576
576
577
578
580
581
581
582
583
585
586
587
587
588
589
591
592
593
593
594
595
596
597
599
600
601
602
602
603
604
605
606
608
609
610
ADP1055
Period (ns)
6550
6540
6530
6520
6510
6500
6490
6480
6470
6460
6450
6440
6430
6420
6410
6400
6380
6370
6360
6350
6340
6330
6320
6310
6300
6290
6280
6270
6260
6250
6240
6230
6220
6210
6200
6190
6180
6170
6160
6150
6140
6130
6120
6110
6100
6090
6080
6070
6060
6050
6040
6030
6020
Data Sheet
Frequency (kHz)
152.6717557
152.9051988
153.1393568
153.3742331
153.609831
153.8461538
154.0832049
154.3209877
154.5595054
154.7987616
155.0387597
155.2795031
155.5209953
155.7632399
156.0062402
156.25
156.7398119
156.9858713
157.2327044
157.480315
157.7287066
157.9778831
158.2278481
158.4786054
158.7301587
158.9825119
159.2356688
159.4896332
159.7444089
160
160.2564103
160.5136437
160.7717042
161.0305958
161.2903226
161.5508885
161.8122977
162.0745543
162.3376623
162.601626
162.8664495
163.132137
163.3986928
163.6661211
163.9344262
164.2036125
164.4736842
164.7446458
165.0165017
165.2892562
165.5629139
165.8374793
166.1129568
Exponent
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
Mantissa
611
612
613
613
614
615
616
617
618
619
620
621
622
623
624
625
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
653
654
655
656
657
658
659
660
661
662
663
664
Period (ns)
6010
6000
5990
5980
5970
5960
5950
5940
5930
5920
5910
5900
5890
5880
5870
5860
5850
5840
5830
5820
5810
5800
5790
5780
5770
5760
5750
5740
5730
5720
5710
5700
5690
5680
5670
5660
5650
5640
5630
5620
5610
5600
5590
5580
5570
5560
5550
5540
5530
5520
5510
5500
5490
Rev. A | Page 134 of 140
Frequency (kHz)
166.3893511
166.6666667
166.9449082
167.2240803
167.5041876
167.7852349
168.0672269
168.3501684
168.6340641
168.9189189
169.2047377
169.4915254
169.7792869
170.0680272
170.3577513
170.6484642
170.9401709
171.2328767
171.5265866
171.8213058
172.1170396
172.4137931
172.7115717
173.0103806
173.3102253
173.6111111
173.9130435
174.2160279
174.5200698
174.8251748
175.1313485
175.4385965
175.7469244
176.056338
176.366843
176.6784452
176.9911504
177.3049645
177.6198934
177.9359431
178.2531194
178.5714286
178.8908766
179.2114695
179.5332136
179.8561151
180.1801802
180.5054152
180.8318264
181.1594203
181.4882033
181.8181818
182.1493625
Exponent
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
Mantissa
666
667
668
669
670
671
672
673
675
676
677
678
679
680
681
683
684
685
686
687
688
690
691
692
693
694
696
697
698
699
701
702
703
704
705
707
708
709
710
712
713
714
716
717
718
719
721
722
723
725
726
727
729
Data Sheet
Period (ns)
5480
5470
5460
5450
5440
5430
5420
5410
5400
5390
5380
5370
5360
5350
5340
5330
5320
5310
5300
5290
5280
5270
5260
5250
5240
5230
5220
5210
5200
5190
5180
5170
5160
5150
5140
5130
5120
5110
5100
5090
5080
5070
5060
5050
5040
5030
5020
5010
5000
4990
4980
4970
4960
Frequency (kHz)
182.4817518
182.8153565
183.1501832
183.4862385
183.8235294
184.1620626
184.501845
184.8428835
185.1851852
185.528757
185.8736059
186.2197393
186.5671642
186.9158879
187.2659176
187.6172608
187.9699248
188.3239171
188.6792453
189.0359168
189.3939394
189.7533207
190.1140684
190.4761905
190.8396947
191.2045889
191.5708812
191.9385797
192.3076923
192.6782274
193.0501931
193.4235977
193.7984496
194.1747573
194.5525292
194.9317739
195.3125
195.6947162
196.0784314
196.4636542
196.8503937
197.2386588
197.6284585
198.019802
198.4126984
198.8071571
199.2031873
199.6007984
200
200.4008016
200.8032129
201.2072435
201.6129032
ADP1055
Exponent
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
Mantissa
730
731
733
734
735
737
738
739
741
742
743
745
746
748
749
750
752
753
755
756
758
759
760
762
763
765
766
768
769
771
772
774
775
777
778
780
781
783
784
786
787
789
791
792
794
795
797
798
800
802
803
805
806
Period (ns)
4950
4940
4930
4920
4910
4900
4890
4880
4870
4860
4850
4840
4830
4820
4810
4800
4790
4780
4770
4760
4750
4740
4730
4720
4710
4700
4690
4680
4670
4660
4650
4640
4630
4620
4610
4600
4590
4580
4570
4560
4550
4540
4530
4520
4510
4500
4490
4480
4470
4460
4450
4440
4430
Rev. A | Page 135 of 140
Frequency (kHz)
202.020202
202.4291498
202.8397566
203.2520325
203.6659878
204.0816327
204.4989775
204.9180328
205.338809
205.7613169
206.185567
206.6115702
207.0393375
207.4688797
207.9002079
208.3333333
208.7682672
209.2050209
209.6436059
210.0840336
210.5263158
210.9704641
211.4164905
211.8644068
212.3142251
212.7659574
213.2196162
213.6752137
214.1327623
214.5922747
215.0537634
215.5172414
215.9827214
216.4502165
216.9197397
217.3913043
217.8649237
218.3406114
218.8183807
219.2982456
219.7802198
220.2643172
220.7505519
221.2389381
221.72949
222.2222222
222.7171492
223.2142857
223.7136465
224.2152466
224.7191011
225.2252252
225.7336343
Exponent
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
Mantissa
808
810
811
813
815
816
818
820
821
823
825
826
828
830
832
833
835
837
839
840
842
844
846
847
849
851
853
855
857
858
860
862
864
866
868
870
871
873
875
877
879
881
883
885
887
889
891
893
895
897
899
901
903
ADP1055
Period (ns)
4420
4410
4400
4390
4380
4370
4360
4350
4340
4330
4320
4310
4300
4290
4280
4270
4260
4250
4240
4230
4220
4210
4200
4190
4180
4170
4160
4150
4140
4130
4120
4110
4100
4090
4080
4070
4060
4050
4040
4030
4020
4010
4000
3990
3980
3970
3960
3950
3940
3930
3920
3910
3900
Data Sheet
Frequency (kHz)
226.2443439
226.7573696
227.2727273
227.7904328
228.3105023
228.8329519
229.3577982
229.8850575
230.4147465
230.9468822
231.4814815
232.0185615
232.5581395
233.1002331
233.6448598
234.1920375
234.741784
235.2941176
235.8490566
236.4066194
236.9668246
237.5296912
238.0952381
238.6634845
239.2344498
239.8081535
240.3846154
240.9638554
241.5458937
242.1307506
242.7184466
243.3090024
243.902439
244.4987775
245.0980392
245.7002457
246.3054187
246.9135802
247.5247525
248.1389578
248.7562189
249.3765586
250
250.6265664
251.2562814
251.8891688
252.5252525
253.164557
253.8071066
254.4529262
255.1020408
255.7544757
256.4102564
Exponent
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
−1
Mantissa
905
907
909
911
913
915
917
920
922
924
926
928
930
932
935
937
939
941
943
946
948
950
952
955
957
959
962
964
966
969
971
973
976
978
980
983
985
988
990
993
995
998
1000
1003
1005
1008
1010
1013
1015
1018
1020
1023
513
Period (ns)
3890
3880
3870
3860
3850
3840
3830
3820
3810
3800
3790
3780
3770
3760
3750
3740
3730
3720
3710
3700
3690
3680
3670
3660
3650
3640
3630
3620
3610
3600
3590
3580
3570
3560
3550
3540
3530
3520
3510
3500
3490
3480
3470
3460
3450
3440
3430
3420
3410
3400
3390
3380
3370
Rev. A | Page 136 of 140
Frequency (kHz)
257.0694087
257.7319588
258.3979328
259.0673575
259.7402597
260.4166667
261.0966057
261.7801047
262.4671916
263.1578947
263.8522427
264.5502646
265.2519894
265.9574468
266.6666667
267.3796791
268.0965147
268.8172043
269.541779
270.2702703
271.00271
271.7391304
272.479564
273.2240437
273.9726027
274.7252747
275.4820937
276.2430939
277.0083102
277.7777778
278.551532
279.3296089
280.1120448
280.8988764
281.6901408
282.4858757
283.286119
284.0909091
284.9002849
285.7142857
286.5329513
287.3563218
288.184438
289.017341
289.8550725
290.6976744
291.5451895
292.3976608
293.255132
294.1176471
294.9852507
295.8579882
296.735905
Exponent
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
Mantissa
514
515
517
518
519
521
522
524
525
526
528
529
531
532
533
535
536
538
539
541
542
543
545
546
548
549
551
552
554
556
557
559
560
562
563
565
567
568
570
571
573
575
576
578
580
581
583
585
587
588
590
592
593
Data Sheet
Period (ns)
3360
3350
3340
3330
3320
3310
3300
3290
3280
3270
3260
3250
3240
3230
3220
3210
3200
3190
3180
3170
3160
3150
3140
3130
3120
3110
3100
3090
3080
3070
3060
3050
3040
3030
3020
3010
3000
2990
2980
2970
2960
2950
2940
2930
2920
2910
2900
2890
2880
2870
2860
2850
2840
Frequency (kHz)
297.6190476
298.5074627
299.4011976
300.3003003
301.2048193
302.1148036
303.030303
303.9513678
304.8780488
305.8103976
306.7484663
307.6923077
308.6419753
309.5975232
310.5590062
311.5264798
312.5
313.4796238
314.4654088
315.4574132
316.4556962
317.4603175
318.4713376
319.4888179
320.5128205
321.5434084
322.5806452
323.6245955
324.6753247
325.732899
326.7973856
327.8688525
328.9473684
330.0330033
331.1258278
332.2259136
333.3333333
334.4481605
335.5704698
336.7003367
337.8378378
338.9830508
340.1360544
341.2969283
342.4657534
343.6426117
344.8275862
346.0207612
347.2222222
348.4320557
349.6503497
350.877193
352.1126761
ADP1055
Exponent
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
Mantissa
595
597
599
601
602
604
606
608
610
612
613
615
617
619
621
623
625
627
629
631
633
635
637
639
641
643
645
647
649
651
654
656
658
660
662
664
667
669
671
673
676
678
680
683
685
687
690
692
694
697
699
702
704
Period (ns)
2830
2820
2810
2800
2790
2780
2770
2760
2750
2740
2730
2720
2710
2700
2690
2680
2670
2660
2650
2640
2630
2620
2610
2600
2590
2580
2570
2560
2550
2540
2530
2520
2510
2500
2490
2480
2470
2460
2450
2440
2430
2420
2410
2400
2390
2380
2370
2360
2350
2340
2330
2320
2310
Rev. A | Page 137 of 140
Frequency (kHz)
353.3568905
354.6099291
355.8718861
357.1428571
358.4229391
359.7122302
361.0108303
362.3188406
363.6363636
364.9635036
366.3003663
367.6470588
369.00369
370.3703704
371.7472119
373.1343284
374.5318352
375.9398496
377.3584906
378.7878788
380.2281369
381.6793893
383.1417625
384.6153846
386.1003861
387.5968992
389.1050584
390.625
392.1568627
393.7007874
395.256917
396.8253968
398.4063745
400
401.6064257
403.2258065
404.8582996
406.504065
408.1632653
409.8360656
411.5226337
413.2231405
414.9377593
416.6666667
418.4100418
420.1680672
421.9409283
423.7288136
425.5319149
427.3504274
429.1845494
431.0344828
432.9004329
Exponent
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
Mantissa
707
709
712
714
717
719
722
725
727
730
733
735
738
741
743
746
749
752
755
758
760
763
766
769
772
775
778
781
784
787
791
794
797
800
803
806
810
813
816
820
823
826
830
833
837
840
844
847
851
855
858
862
866
ADP1055
Period (ns)
2300
2290
2280
2270
2260
2250
2240
2230
2220
2210
2200
2190
2180
2170
2160
2150
2140
2130
2120
2110
2100
2090
2080
2070
2060
2050
2040
2030
2020
2010
2000
1990
1980
1970
1960
1950
1940
1930
1920
1910
1900
1890
1880
1870
1860
1850
1840
1830
1820
1810
1800
1790
1780
Data Sheet
Frequency (kHz)
434.7826087
436.6812227
438.5964912
440.5286344
442.4778761
444.4444444
446.4285714
448.4304933
450.4504505
452.4886878
454.5454545
456.6210046
458.7155963
460.8294931
462.962963
465.1162791
467.2897196
469.4835681
471.6981132
473.9336493
476.1904762
478.4688995
480.7692308
483.0917874
485.4368932
487.804878
490.1960784
492.6108374
495.049505
497.5124378
500
502.5125628
505.0505051
507.6142132
510.2040816
512.8205128
515.4639175
518.134715
520.8333333
523.5602094
526.3157895
529.1005291
531.9148936
534.7593583
537.6344086
540.5405405
543.4782609
546.4480874
549.4505495
552.4861878
555.5555556
558.6592179
561.7977528
Exponent
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
−1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Mantissa
870
873
877
881
885
889
893
897
901
905
909
913
917
922
926
930
935
939
943
948
952
957
962
966
971
976
980
985
990
995
1000
1005
1010
1015
1020
513
515
518
521
524
526
529
532
535
538
541
543
546
549
552
556
559
562
Period (ns)
1770
1760
1750
1740
1730
1720
1710
1700
1690
1680
1670
1660
1650
1640
1630
1620
1610
1600
1590
1580
1570
1560
1550
1540
1530
1520
1510
1500
1490
1480
1470
1460
1450
1440
1430
1420
1410
1400
1390
1380
1370
1360
1350
1340
1330
1320
1310
1300
1290
1280
1270
1260
1250
Rev. A | Page 138 of 140
Frequency (kHz)
564.9717514
568.1818182
571.4285714
574.7126437
578.0346821
581.3953488
584.7953216
588.2352941
591.7159763
595.2380952
598.8023952
602.4096386
606.0606061
609.7560976
613.4969325
617.2839506
621.1180124
625
628.9308176
632.9113924
636.9426752
641.025641
645.1612903
649.3506494
653.5947712
657.8947368
662.2516556
666.6666667
671.1409396
675.6756757
680.2721088
684.9315068
689.6551724
694.4444444
699.3006993
704.2253521
709.2198582
714.2857143
719.4244604
724.6376812
729.9270073
735.2941176
740.7407407
746.2686567
751.8796992
757.5757576
763.3587786
769.2307692
775.1937984
781.25
787.4015748
793.6507937
800
Exponent
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Mantissa
565
568
571
575
578
581
585
588
592
595
599
602
606
610
613
617
621
625
629
633
637
641
645
649
654
658
662
667
671
676
680
685
690
694
699
704
709
714
719
725
730
735
741
746
752
758
763
769
775
781
787
794
800
Data Sheet
Period (ns)
1240
1230
1220
1210
1200
1190
1180
1170
1160
1150
1140
1130
1120
Frequency (kHz)
806.4516129
813.0081301
819.6721311
826.446281
833.3333333
840.3361345
847.4576271
854.7008547
862.0689655
869.5652174
877.1929825
884.9557522
892.8571429
ADP1055
Exponent
0
0
0
0
0
0
0
0
0
0
0
0
0
Mantissa
806
813
820
826
833
840
847
855
862
870
877
885
893
Period (ns)
1110
1100
1090
1080
1070
1060
1050
1040
1030
1020
1010
1000
Rev. A | Page 139 of 140
Frequency (kHz)
900.9009009
909.0909091
917.4311927
925.9259259
934.5794393
943.3962264
952.3809524
961.5384615
970.8737864
980.3921569
990.0990099
1000
Exponent
0
0
0
0
0
0
0
0
0
0
0
0
Mantissa
901
909
917
926
935
943
952
962
971
980
990
1000
ADP1055
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
*3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
8
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PIN 1
INDICATOR
9
BOTTOM VIEW
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
*COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
08-16-2010-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 86. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP1055ACPZ-RL
ADP1055ACPZ-R7
ADP1055-EVALZ
ADP1055DC1-EVALZ
ADP-I2C-USB-Z
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
ADP1055 Evaluation Board
ADP1055 Daughter Card
USB to I2C Adapter
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12004-0-3/15(A)
Rev. A | Page 140 of 140
Package Option
CP-32-12
CP-32-12