iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 1/24
FEATURES
APPLICATIONS
♦ Resolution of up to 8192 angle steps per sine/cosine period
♦ Binary and decimal resolution settings, e.g. 500, 512, 1000,
1024; programmable angle hysteresis
♦ Conversion time of just 250 ns including amplifier settling
♦ Count-safe vector follower principle, realtime system with
70 MHz sampling rate
♦ Direct sensor connection; selectable input gain
♦ Front-end signal conditioning features offset (8 bit), amplitude
ratio (5 bit) and phase (6 bit) calibration
♦ 250 kHz input frequency
♦ Absolute angle output via fast SSI interface
♦ A QUAD B incremental outputs with selectable minimum
transition distance (e.g. 0.25 µs for 1 MHz at A)
♦ Index signal processing adjustable in position and width
♦ Fault monitoring: frequency, amplitude, configuration (CRC)
♦ Setup via serial EEPROM
♦ ESD protection and TTL-/CMOS-compatible outputs
♦ Interpolator IC for position data
acquisition from analog
sine/cosine sensors
♦ Optical linear/rotary encoders
♦ MR sensor systems
PACKAGES
TSSOP20
BLOCK DIAGRAM
Copyright © 2004, 2011 iC-Haus
http://www.ichaus.com
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 2/24
DESCRIPTION
iC-NQL is a monolithic A/D converter which, by applying a count-safe vector follower principle, converts
sine/cosine sensor signals with a selectable resolution and hysteresis into angle position data. This
absolute value is output via a synchronous-serial
SSI interface and trails a master clock rate of up to
4 Mbit/s.
At the same time any changes in output data are
converted into incremental A QUAD B encoder signals. Here, the minimum transition distance can be
adapted to suit the system on hand (cable length, external counter). A synchronised zero index is generated and output to Z if enabled by the PZERO and
NZERO inputs.
The front-end amplifiers are configured as instrumentation amplifiers, permitting sensor bridges to be di-
rectly connected without the need for external resistors. Various programmable D/A converters are available for the conditioning of sine/cosine sensor signals with regard to offset, amplitude ratio and phase
errors. Front-end gain can be set in stages graded
to suit all common differential sensor signals from
approximately 20 mVpp to 1.5 Vpp, and also singleended sensor signals from 40 mVpp to 3 Vpp respectively.
The device reads its configuration data via the serial
EEPROM interface when cycling power, respectively
following an undervoltage reset. The read in cycle
is repeated up to three times when data correctness
is not confirmed by a CRC validation. A permanent
CRC error as well as the configuration phase itself
is displayed at the error message output NERR by a
low level signal.
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 3/24
CONTENTS
PACKAGES
4
Incremental output to A, B and Z . . . . . . .
14
ABSOLUTE MAXIMUM RATINGS
5
INCREMENTAL SIGNALS
15
THERMAL DATA
5
SIGNAL MONITORING and ERROR
MESSAGES
17
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS: Diagrams
6
8
TEST FUNCTIONS
18
OPERATING REQUIREMENTS: SSI INTERFACE
8
SSI INTERFACE
19
EEPROM INTERFACE and STARTUP
BEHAVIOUR
Example of CRC Calculation Routine . . . . .
20
20
APPLICATION HINTS
Principle Input Circuits . . . . . . . . . . . . .
Basic Circuit . . . . . . . . . . . . . . . . . .
21
21
22
DESIGN REVIEW: Notes On Chip Functions
23
PARAMETERS and REGISTERS
10
SIGNAL CONDITIONING
11
CONVERTER FUNCTIONS
12
MAXIMUM POSSIBLE CONVERTER
FREQUENCY
Serial data output . . . . . . . . . . . . . . .
13
13
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 4/24
PACKAGES TSSOP20 (according to JEDEC Standard)
PIN CONFIGURATION
TSSOP20 4.4 mm, lead pitch 0.65 mm
PIN FUNCTIONS
No. Name Function
1
2
3
4
5
6
PCOS
NCOS
VDDA
GNDA
VREF
A
Input Cosine +
Input Cosine +5 V Supply Voltage (analog)
Ground (analog)
Reference Voltage Output
Incremental Output A
Analog signal COS+ (TMA mode)
PWM signal for Offset Sine (Calib.)
7 B
Incremental Output B
Analog signal COS- (TMA mode)
PWM signal for Offset Cosine (Calib.)
8 Z
Output Index Z
PWM signal for Phase/Ratio (Calib.)
9 GND
Ground
10 VDD
+5 V Supply Voltage (digital)
11 TEST Test Input
12 CLK
SSI interface, clock line
13 DATA
SSI interface, data output
14 SDA
EEPROM interface, data line
Analog signal SIN+ (TMA mode)
15 SCL
EEPROM interface, clock line
Analog signal SIN- (TMA mode)
16 NERR Error Input/Output, active low
17 PZERO Input Zero Signal +
18 NZERO Input Zero Signal 19 PSIN
Input Sine +
20 NSIN
Input Sine External connections linking VDDA to VDD and GND to GNDA are required. The test input may remain unwired
or can be linked to VDD (please note the hints given by chapter Design Review regarding the signal of pin DATA).
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 5/24
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Max.
G001 VDDA
Voltage at VDDA
-0.3
6
V
G002 VDD
G003 Vpin()
Voltage at VDD
-0.3
6
V
-0.3
6
V
Voltage at
PSIN, NSIN, PCOS, NCOS, PZERO,
NZERO, VREF, NERR, SCL,
SDA, CLK, DATA, A, B, Z
G004 Imx(VDDA) Current in VDDA
V() < VDDA + 0.3 V
V() < VDD + 0.3 V
-50
50
mA
G005 Imx(GNDA) Current in GNDA
-50
50
mA
G006 Imx(VDD)
Current in VDD
-50
50
mA
G007 Imx(GND) Current in GND
-50
50
mA
G008 Imx()
Current in
PSIN, NSIN, PCOS, NCOS, PZERO,
NZERO, VREF, NERR, SCL, SDA,
CLK, DATA, A, B, Z
-10
10
mA
G009 Ilu()
Pulse Current in all pins
(Latch-up Strength)
-100
100
mA
according to Jedec Standard No. 78;
Ta = 25 °C, pulse duration to 10 µs,
VCC = VCCmax, VDD = VDDmax,
Vlu() = (-0.5...+1.5) x Vpin()max
G010 Vd()
ESD Susceptibility at all pins
2
kV
G011 Tj
Junction Temperature
HBM 100 pF discharged through 1.5 kΩ
-40
150
°C
G012 Ts
Storage Temperature Range
-40
150
°C
THERMAL DATA
Operating Conditions: VDDA = VDD = 5 V ±10 %
Item
No.
T01
Symbol
Parameter
Conditions
Unit
Min.
Ta
Operating Ambient Temperature Range
(extended temperature range of
-40 to 125 °C available on request)
All voltages are referenced to ground unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
-25
Typ.
Max.
85
°C
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 6/24
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
Functionality and parameters beyond the operating conditions (with reference to independent voltage supplies, for instance)
are to be verified within the individual application using FMEA methods.
001
VDDA,
VDD
Permissible Supply Voltage
002
I(VDDA)
Supply Current in VDDA
003
I(VDD)
Supply Current in VDD
004
Von
Turn-on Threshold VDDA, VDD
3.2
005
006
Vhys
Turn-on Threshold Hysteresis
200
Vc()hi
Clamp Voltage hi at
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF
Vc()hi = V() - VDDA;
I() = 1 mA, other pins open
0.3
1.6
V
007
Vc()lo
Clamp Voltage lo at
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF, NERR,
SCL, SDA, A, B, Z
I() = -1 mA, other pins open
-1.6
-0.3
V
008
Vc()hi
Clamp Voltage hi at
NERR, SCL, SDA,
A, B, Z
Vc()hi = V() - VDD;
I() = 1 mA, other pins open
0.3
1.6
V
-10
-15
10
15
mV
mV
Input Amplifiers PSIN, NSIN, PCOS, NCOS
101 Vos()
Input Offset Voltage
4.5
5.5
V
fin() = 200 kHz; A, B, Z open
15
mA
fin() = 200 kHz; A, B, Z open
20
mA
Vin() and G() in accordance with table GAIN;
G ≥ 20
G < 20
4.4
V
mV
102
TCos
Input Offset Voltage
Temperature Drift
see 101
±10
µV/K
103
Iin()
Input Current
V() = 0 V ... VDDA
-50
50
nA
104
GA
Gain Accuracy
G() in accordance with table GAIN
95
102
%
105
106
GArel
Gain SIN/COS Ratio Accuracy
G() in accordance with table GAIN
97
103
fhc
Cut-off Frequency
G = 80
G = 2.667
150
630
kHz
kHz
107
SR
Slew Rate
G = 80
G = 2.667
2.3
8.0
V/µs
V/µs
%
Sin/D Conversion: Accuracy
201
AAabs
Absolute Angle Accuracy without referred to 360° input signal, G = 2.667,
calibration
Vin = 1.5 Vpp, HYS = 0
-1.0
1.0
DEG
202
AAabs
Absolute Angle Accuracy after
calibration
referred to 360° input signal, HYS = 0, internal
signal amplitude of 2 ... 4 Vpp
-0.5
+0.5
DEG
203
AArel
Relative Angle Accuracy
referred to output signal period of A/B,
G = 2.667, Vin = 1.5 Vpp, SELRES = 1024,
FCTR = 0x0004 ... 0x00FF, fin < finmax
(see table 14)
-10
10
%
Reference Voltage
I(VREF) = -1 mA ... +1 mA
48
52
%
VDDA
Oscillator Frequency
presented at SCL with subdivision
of 2048;
VDDA = VDD = 5 V ±10 %
VDDA = VDD = 5 V
52
60
90
83
MHz
MHz
±0.35
Reference Voltage VREF
801
VREF
Oscillator
A01 fosc()
A02
TCosc
Oscillator Frequency Temperature Drift
A03
VCosc
Oscillator Frequency Power Supply Dependance
VDDA = VDD = 5 V
72
-0.1
%/K
+10.6
%/V
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 7/24
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
Zero Comparator
B01
Vos()
Input Offset Voltage
V() = Vcm()
-20
20
mV
B02
Iin()
Input Current
V() = 0 V ... VDDA
-50
50
nA
B03
Vcm()
Common-Mode Input Voltage
Range
1.4
VDDA1.5
V
0
VDDA
V
V
B04 Vdm()
Differential Input Voltage Range
Incremental Outputs A, B, Z
SSI Interface Output DATA
D01 Vs()hi
Saturation Voltage hi
Vs()hi = VDD - V(); I() = -4 mA
0.4
D02 Vs()lo
Saturation Voltage lo
I() = 4 mA
0.4
V
D03 tr()
Rise Time
CL() = 50 pF
60
ns
D04 tf()
Fall Time
CL() = 50 pF
D05 RL()
Permissible Load at A, B
TMA = 1 (calibration mode)
60
1
ns
MΩ
SSI Interface: Input CLK
E01
Vt()hi
Threshold Voltage hi
E02
Vt()lo
Threshold Voltage lo
2
E03
Vt()hys
Hysteresis
E04
Ipu()
Pull-up Current in CLK
E05
fclk()
Permissible Clock Frequency at
CLK
E06
tp(CLKDATA)
Propagation Delay: CLK edge vs. all modes, RL(SLO) ≥ 1 kΩ
DATA output
E07
E08
tbusy()
Processing Time
ttos()
Timeout
V
0.8
V
Vt()hys = Vt()hi - Vt()lo
300
mV
V() = 0 ... VDD - 1 V
-240
-120
10
-25
µA
4
MHz
50
ns
0
CFGTOS = 0x01 iC-NQL_X3
CFGTOS = 0x01, iC-NQL_3
16
20
µs
µs
EEPROM Interface, Control Logic: Inputs SDA, NERR
F01
Vt()hi
Threshold Voltage hi
2
F02
Vt()lo
Threshold Voltage lo
F03
Vt()hys
Hysteresis
F04
tbusy()cfg
Duration of Startup Configuration error free EEPROM access
Vt()hys = Vt()hi - Vt()lo
V
0.8
V
300
mV
5
7
ms
100
kHz
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR
G01 f()
Write/Read Clock at SCL
G02 Vs()lo
Saturation Voltage lo
I() = 4 mA
G03 Ipu()
Pull-up Current
V() = 0 ... VDD - 1 V
G04 ft()
Fall Time
CL() = 50 pF
G05 tmin()lo
Error Signal Indication Time at
NERR (lo signal)
CLK = hi, no amplitude or frequeny error
G06 Tpwm()
Duty Cycle Of Error Indication at fosc() subdivided by 222
NERR
G07 t()lo
Duty Cycle Of Error Indication at signal duration low to high;
AERR = 0 (amplitude error)
NERR
FERR = 0 (frequency error)
G08 RL()
Permissible Load at SDA, SCL
20
TMA = 1 (calibration mode)
-600
-300
0.45
V
-75
µA
60
10
1
ns
ms
60.7
ms
75
50
%
%
MΩ
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 8/24
ELECTRICAL CHARACTERISTICS: Diagrams
0%
60%
40%
0%
twhi()/T
110%
90%
50%
100%
AArel ±10%
AArel ±10%
Figure 1: Definition of relative angle error.
$ tMTD
Figure 2: Definition of minimum transition distance.
0.15°
0.1°
0.05°
0
-0.05°
-0.1°
-0.15°
0°
90°
180°
270°
Figure 3: Typical residual absolute angle error after calibration.
360°
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 9/24
OPERATING REQUIREMENTS: SSI INTERFACE
Operating Conditions: VDD = 5 V ±10 %, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD
Item
No.
Symbol
Parameter
Conditions
CFGTOS = 0x01
Fig.
Unit
Min.
Max.
I001 TCLK
Permissible Clock Period
4
250
2x ttos
ns
I002 tCLKhi
Clock Signal Hi Level Duration
4
25
ttos
ns
I003 tCLKlo
Clock Signal Lo Level Duration
4
25
ttos
ns
Figure 4: Timing diagram of SSI output.
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 10/24
PARAMETERS and REGISTERS
ZPOS:
CFGZ:
CFGAB:
Register Description . . . . . . . . . . . . . . . . . . . . . . . Page 10
Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . Page 11
GAIN:
Gain Select
SINOFFS:
Offset Calibration Sine
COSOFFS: Offset Calibration Cosine
REFOFFS: Offset Calibration Reference
RATIO:
Amplitude Calibration
PHASE:
Phase Calibration
Zero Signal Position
Zero Signal Length
Zero Signal Logic
Signal Monitoring
and Error Messages . . . . . . . . . . . . . . . . . . . . . . . Page 17
SELAMPL: Amplitude Monitoring, function
AMPL:
Amplitude Monitoring, thresholds
AERR:
Amplitude Error
FERR:
Frequency Error
Converter Function . . . . . . . . . . . . . . . . . . . . . . . . Page 12
SELRES:
Resolution
HYS:
Hysteresis
FCTR:
Max. Permissible Converter Frequency
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 18
TMODE:
Test Mode
TMA:
Analog Test Mode
Incremental Signals . . . . . . . . . . . . . . . . . . . . . . . Page 15
CFGABZ:
Output A, B, Z
ROT:
Direction of Rotation
ENRESDEL: Output Turn-On Delay
SSI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 19
CFGTOS:
Interface Timeout
CFGSSI:
SSI Output Options
OVERVIEW
Adr
Bit 7
Bit 6
Bit 5
0x00
0
0
0
0x01
0x02
Bit 4
Bit 3
HYS(2:0)
ENRESDEL
0x03
Bit 2
Bit 1
Bit 0
SELRES(4:0)
ZPOS(4:0)
1
ROT
CFGSSI(1:0)
0
CFGABZ(1:0)
CFGAB(1:0)
0
0x04
CFGZ(1:0)
0
AERR
FERR
FCTR(7:0)
0x05
0
FCTR(14:8)
0x06
0
0
0x07
0
0
0x08
CFGTOS(1:0)
0
TMODE(2:0)
0
0
TMA
0
GAIN(3:0)
0
0
RATIO(3:0)
0x09
SINOFFS(7:0)
0x0A
COSOFFS(7:0)
0x0B
PHASE(5:0)
REFOFFS
RATIO(4)
0x0C
0
0
0
0
0
SELAMPL
AMPL(1:0)
0x0D
0
0
0
0
0
0
0
0
0x0E
0
0
0
0
0
0
0
0
0x0F
CRC_E2P(7:0) - check value read from the EEPROM for addresses 0x00 to 0x0E
Note
Registers not in use must be set to zero unless otherwise noted.
Table 5: Register layout
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 11/24
SIGNAL CONDITIONING
Input stages SIN and COS are configured as instrumentation amplifiers. The amplifier gain must be selected in accordance with the sensor signal level and
GAIN
programmed to register GAIN according to the following table. Half of the supply voltage is output to VREF
as center voltage to help DC level adaptation.
Adr 0x08, Bit 7:4
Code
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Amplification
80.000
66.667
53.333
40.000
33.333
28.571
26.667
20.000
14.287
10.000
8.000
6.667
5.333
4.000
3.333
2.667
Differential
up to 50 mVpp
up to 60 mVpp
up to 75 mVpp
up to 0.1 Vpp
up to 0.12 Vpp
up to 0.14 Vpp
up to 0.15 Vpp
up to 0.2 Vpp
up to 0.28 Vpp
up to 0.4 Vpp
up to 0.5 Vpp
up to 0.6 Vpp
up to 0.75 Vpp
up to 1 Vpp
up to 1.2 Vpp
up to 1.5 Vpp
Sine/Cosine Input Signal Levels Vin()
Amplitude
Average value (DC)
Single-ended
Differential
Single-ended
up to 100 mVpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 120 mVpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 0.15 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.2 V
up to 0.2 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.24 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.28 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.3 V
up to 0.3 Vpp
1.2 V ... VDDA - 1.2 V
1.3 V ... VDDA - 1.3 V
up to 0.4 Vpp
0.7 V ... VDDA - 1.2 V
0.8 V ... VDDA - 1.3 V
up to 0.56 Vpp
1.2 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.4 V
up to 0.8 Vpp
1.2 V ... VDDA - 1.3 V
1.4 V ... VDDA - 1.5 V
up to 1 Vpp
0.8 V ... VDDA - 1.4 V
1.0 V ... VDDA - 1.6 V
up to 1.2 Vpp
0.8 V ... VDDA - 1.4 V
1.1 V ... VDDA - 1.7 V
up to 1.5 Vpp
0.9 V ... VDDA - 1.5 V
1.3 V ... VDDA - 1.9 V
up to 2 Vpp
1.2 V ... VDDA - 1.6 V
1.7 V ... VDDA - 2.1 V
up to 2.4 Vpp
1.2 V ... VDDA - 1.7 V
1.8 V ... VDDA - 2.3 V
up to 3 Vpp
1.3 V ... VDDA - 1.8 V
2.0 V ... VDDA - 2.6 V
Table 6: Gain Select
SINOFFS
COSOFFS
Code
Adr 0x09, Bit 7:0
Adr 0x0A, Bit 7:0
Output Offset
Input Offset
0x00
0x01
...
0x7F
0V
-7.8125 mV
...
-0.9922 V
0V
-7.8125* mV / GAIN
...
-0.9922 V / GAIN
0x80
0x81
...
0xFF
0V
+7,8125 mV
...
+0.9922 V
0V
+7.8125 mV / GAIN
...
+0.9922 V / GAIN
Notes
*) With REFOFFS = 0x00 und VDDA = 5 V.
Table 7: Offset Calibration Sine/Cosine
REFOFFS
Code
Adr 0x0B, Bit 1
Reference Voltage
0x00
Depending on VDDA
(example of application: MR sensors)
Not depending on VDDA
(example of application: Sin/Cos encoders)
0x01
Table 8: Offset Calibration Reference
RATIO
Code
Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0
COS / SIN
Code
COS / SIN
0x00
0x01
...
0x0F
1.0000
1.0067
...
1.1
0x10
0x11
...
0x1F
1.0000
0.9933
...
0.9000
Table 9: Amplitude Calibration
PHASE
Code
Adr 0x0B, Bit 7:2
Phase Shift
Code
Phase Shift
0x00
0x01
...
0x12
90°
90.703125°
...
102.65625°
0x20
0x21
...
0x32
90°
89.296875°
...
77.34375°
...
0x1F
102.65625°
102.65625°
...
0x3F
77.34375°
77.34375°
Table 10: Phase Calibration
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 12/24
CONVERTER FUNCTIONS
SELRES
Code
Adr 0x00, Bit 4:0
Binary
Examples of Permissible
Resolutions
Input Frequencies finmax
(FCTR 0x0004, 0x4304)
SELRES
Code
Adr 0x00, Bit 4:0
Decimal
Examples of Permissible
Resolutions
Input Frequencies finmax
(FCTR 0x0004, 0x4304)
0x00
0x01
0x02
0x03
0x04
0x05
8192
4096
2048
158 Hz, 635 Hz
317 Hz, 1.27 kHz
634 Hz, 2.54 kHz
0x10
0x11
0x12
0x13
0x14
0x15
2000
1600
1000
800
500
400
650 Hz, 2.6 kHz
812 Hz, 3.3 kHz
1.3 kHz, 5.2 kHz
1.6 kHz, 6.5 kHz
2.6 kHz, 10.4 kHz
3.2 kHz, 13 kHz
0x06
0x07
0x08
0x09
0x0A
0x0B
1024
512
256
128
64
32
1.27 kHz, 5.1 kHz
2.54 kHz, 10.2 kHz
5.1 kHz, 20.3 kHz
10.2 kHz, 40.6 kHz
20.3 kHz, 81.3 kHz
40.6 kHz, 162.5 kHz
0x16
0x17
0x18
0x19
0x1A
0x1B
250 *1
125 *1,2
320
160 *2
80 *4
40 *8
5.2 kHz, 20.8 kHz
5.2 kHz, 20.8 kHz
4.1 kHz, 16.3 kHz
4.1 kHz, 16.3 kHz
4.1 kHz, 16.3 kHz
4.1 kHz, 16.3 kHz
0x0C
0x0D
0x0E
0x0F
16
8
-
81.3 kHz (max. 250 kHz @ 0x4202)
162 kHz (max. 250 kHz @ 0x4102)
0x1C
0x1D
0x1E
0x1F
200
100 *2
50 *1,4
25 *1,8
6.5 kHz, 26 kHz
6.5 kHz, 26 kHz
6.5 kHz, 26 kHz
6.5 kHz, 26 kHz
Notes
*1
Table 11: Binary Resolutions
Not useful with incremental A quad B output.
The internal converter resolution is higher
by a factor of 2, 4 or 8.
*2,4,8
Table 12: Decimal Resolutions
HYS
Code
Adr 0x01, Bit 7:5
Hysteresis in
Hysteresis in
degree
LSB
0x00
0°
0x01
0.0879°
0x02
0.1758°
0x03
0.3516°
0x04
0.7031°
0x05
0x06
1.4063°
5.625°
0x07
45°
Notes
*) The absolute angle error is equivalent to one half
the angle hysteresis
Absolute Angle
Error*
1 LSB @
12 bit
1/2 LSB @
10 bit
1 LSB @
10 bit
0.044°
1/2 LSB @
8 bit
1 LSB @ 8 bit
0.352°
only
recommended
for calibration
22.5°
Table 13: Hysteresis
0.088°
0.176°
0.703°
2.813°
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 13/24
MAXIMUM POSSIBLE CONVERTER FREQUENCY
The converter frequency automatically adjusts to the
value necessary for the input frequency and resolution.
This value ranges from zero to a maximum dependent
on the oscillator frequency which can be set using register FCTR.
feature can be enabled via the FCTR register. Should
the input frequency exceed the frequency limit of the
selected converter resolution, the LSB is kept stable
and not resolved any further; the interpolation resolution halves.
Serial data output
For SSI output the maximum possible converter frequency can be adjusted to suit the maximum input frequency; an automatic converter resolution step-down
If the next frequency limit is overshot, the LSB and the
LSB+1 are kept stable and so on. When the input frequency again sinks below this frequency limit, the fine
resolution automatically returns.
Max. Possible Converter Frequency For Serial Data Output
Resolution
Protocol Max. Input Frequency
Restrictions
Requirements
at high input frequency
FCTR
Min. Res. bin dec SSI
finmax
0x0004
X
X
X
fosc()min / 40 / Resolution
–
0x4102
≥8
X
X
X
fosc()min / 24 / Resolution
Rel. angle error 2x increased
0x4202
≥ 16
X
X
X
2 x fosc()min / 24 / Res.
Rel. angle error 4x increased
0x4304
≥ 32
X
X
X
4 x fosc()min / 40 / Res.
Rel. angle error 8x increased
0x4602
≥ 64
X
X
4 x fosc()min / 24 / Res.
Resolution lowered by factor of 2
0x4A02 ≥ 128
X
X
8 x fosc()min / 24 / Res.
Res. lowered by factor of 2-4
0x4E02 ≥ 256
X
X
16 x fosc()min / 24 / Res.
Res. lowered by factor of 2-8
0x5202
≥ 512
X
X
32 x fosc()min / 24 / Res.
Res. lowered by factor of 2-16
0x5602
≥ 1024
X
X
64 x fosc()min / 24 / Res.
Res. lowered by factor of 2-32
0x5A02 ≥ 2048
X
X
128 x fosc()min / 24 / Res.
Res. lowered by factor of 2-64
0x5E02 ≥ 4096
X
X
256 x fosc()min / 24 / Res.
Res. lowered by factor of 2-128
0x6202
8192
X
X
512 x fosc()min / 24 / Res.
Res. lowered by factor of 2-256
Notes
*) Calculated with fosc()min taken from Electrical Characteristics item A01.
Table 14: Maximum converter frequency for serial data output.
Examples*
finmax [kHz] at resol.
8192 1024 200
0.16
1.27
6.5
0.26
2.1
10.8
0.53
4.2
21.6
0.64
5.1
26.0
1.1
8.5
2.1
16.9
4.2
33.8
8.5
67.7
16.9
135
33.8
250
67.7
135
-
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 14/24
Incremental output to A, B and Z
There are two criteria which must be considered when
setting the maximum possible converter frequency via
the FCTR register:
nals. A digital zero-delay glitch filter then takes care
of a temporal edge-to-edge separation, guaranteeing
spike-free output signals after an ESD impact to the
sensor, for instance.
1. The maximum input frequency
2. System limitations, e.g. due to slow counters or
cable transmission
A serial data output is simultaneously possible at any
time. However, for the transfer of angle data to the
output register the incremental output is halted for one
period of the clock signal applied to pin CLK.
When facing system limitations it is useful to preselect a minimum transition distance for the output sig1. Max. Possible Converter Frequency Defined By The Maximum Input Frequency
Output Frequency Resolution Maximum Input Frequency
Restrictions
fout @ finmax
Requirem.
at high input frequency
FCTR
A, B
bin dec finmax
0x0004
325 kHz
X
X
fosc()min / 40 / Resolution
None
0x4102
542 kHz
X
X
fosc()min / 24 / Resolution
Relative angle error 2x increased
0x4202
1.08 MHz
X
X
2 x fosc()min / 24 Res.
Relative angle error 4x increased
0x4304
1.3 MHz
X
X
4 x fosc()min / 40 / Res.
Relative angle error 8x increased
Notes
*) Calculated with fosc()min taken from Electrical Characteristics item A01.
Examples*
finmax [kHz] at resol.
8192 1024 200
0.16
1.27
6.5
0.26
2.1
10.8
0.53
4.2
21.6
0.64
5.1
26.0
Table 15: Max. converter frequency for incremental A/B/Z output, defined by the max. input frequency
2. Max. Possible Converter Frequency Defined By The Minimum Transition Distance
Output Frequency Resolution Minimum Transition Distance Restrictions
Example*
fout @ tMTD
Requirem. at A, B
at high input frequency
tMTD [µsec]
FCTR
A, B
bin dec tMTD
0x00FF 11 kHz
X
X
2048 / fosc()max
None
22.8
0x00FE 11.03 kHz
X
X
2040 / fosc()max
None
22.7
0x00FD 11.07 kHz
X
X
2032 / fosc()max
None
22.6
...
...
...
...
...
...
...
0x0006
402 kHz
X
X
56 / fosc()max
None
0.62
0x0005
536 kHz
X
X
48 / fosc()max
None
0.53
0x0004
562 kHz
X
X
40 / fosc()max
None
0.44
0x4102
938 kHz
X
X
24 / fosc()max
Relative angle error 2x increased
0.27
0x4202
1.87 MHz
X
X
12 / fosc()max
Relative angle error 4x increased
0.13
0x4304
2.25 MHz
X
X
10 / fosc()max
Relative angle error 8x increased
0.11
Notes
*) Calculated with fosc()max taken from El.Char. item A01; the min. transition distance refers to output A vs. output B
without reversing the sense of rotation.
Table 16: Max. converter frequency for incremental A/B/Z output, defined by the min. transition distance
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 15/24
INCREMENTAL SIGNALS
CFGABZ
Code
Adr 0x02, Bit 3:2
Mode
Pin A
Pin B
Pin Z
0x00
Normal
A
B
Z
0x01
Control signals for
external period counters
CA
CB
CZ
0x02
Calibration mode
Offset+Phase
The following settings
are required additionally:
SELRES = 0x0D
ZPOS = 0x00
HYS = 0x07
ROT = 0x00
CFGAB = 0x00
AERR = 0x00
Figure 5: Offset SIN*
Figure 6: Offs. COS*
Figure 7: Phase*
0x03
Calibration mode
Offset+Amplitude
The following settings
are required additionally:
SELRES = 0x0D
ZPOS = 0x00
HYS = 0x07
ROT = 0x00
CFGAB = 0x00
AERR = 0x00
Figure 8: Offset SIN*
Figure 9: Offs. COS*
Figure 10: Amplit.*
Notes
*) Trimmed accurately when duty cycle is 50 %;
Recommended trimming order (after selecting GAIN): Offset, Phase, Amplitude Ratio, Offset;
Table 17: Outputs A, B, Z
ROT
Code
Adr 0x02, Bit 5
Direction
0x00
0x01
Not inverted
Inverted
Table 18: Direction of Rotation
Code
Adr 0x02, Bit 7
Output*
Function
0x00
immediately
An external counter displays the
absolute angle following power on.
0x01
after 5 ms
An external counter only displays
changes vs. the initial power-on
condition (moving halted to
reapply power is precondition.)
Notes
*) Output delay after device configuration and
internal reset.
ENRESDEL
Table 19: Output Turn-On Delay A, B, Z
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 16/24
ZPOS
Code
Adr 0x01, Bit 4:0
Position
CFGZ
Code
Adr 0x02, Bit 1:0
Length
0x00
0x08
0x10
0x18
0°
90°
180°
270°
0x00
0x01
0x02.. 03
90°
180°
Synchronization
Notes
The zero signal is only output if released by the
input pins (for instance with PZERO = 5 V, NZERO =
VREF).
Table 20: Zero Signal Position
Table 21: Zero Signal Length
CFGAB
Adr 0x03, Bit 5:4
Code
Z = 1 for
0x00
0x01
B = 1, A = 1
B = 0, A = 1
0x02
0x03
B = 1, A = 0
B = 0, A = 0
Table 22: Zero Signal Logic
SIN
COS
A
B
Z (CFGZ= 0)
Z (CFGZ= 1)
Z (CFGZ= 2)
-180°
-90°
0°
90°
180° Angle
Figure 11: Incremental output signals for various length of the zero signal.
Example for a resolution of 64 (SELRES = 0x0A), a zero signal position of 0° (ZPOS = 0x00,
CFGAB = 0x00) and no reversal of the rotational sense (ROT = 0x00, COS leads SIN).
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 17/24
SIGNAL MONITORING and ERROR MESSAGES
Vpp
SELAMPL
AMPL
Adr 0x0C, Bit 2
Adr 0x0C, Bit 1:0
Max ( |Sin| , |Cos| )
Code
Voltage threshold Vth
Output amplitude*
0x00
0x01
0.60 x VDDA
0.64 x VDDA
1.4 Vpp
2.0 Vpp
0x02
0x03
0.68 x VDDA
0.72 x VDDA
2.6 Vpp
3.1 Vpp
Vth
Figure 12: Signal monitoring of minimum amplitude.
Sin2 + Cos2
Code
Vthmin ↔ Vthmax
Output amplitude*
0x04
Design iC-NQL_X3:
(0.48 ↔ 0.68) x VDDA
2.4 Vpp ↔ 3.4 Vpp
0x05
0x06
0x07
(0.56 ↔ 0.76) x VDDA
(0.64 ↔ 0.84) x VDDA
(0.72 ↔ 0.92) x VDDA
2.8 Vpp ↔ 3.8 Vpp
3.2 Vpp ↔ 4.2 Vpp
3.6 Vpp ↔ 4.6 Vpp
0x04
0x05
0x06
0x07
Design iC-NQL_3:
(0.20 ↔ 0.9) x VDDA
(0.30 ↔ 0.9) x VDDA
(0.40 ↔ 0.9) x VDDA
(0.50 ↔ 0.9) x VDDA
1.0 Vss
1.5 Vss
2.0 Vss
2.5 Vss
Notes
*) Entries are calculated with VDDA = 5 V.
Vthmax
↔ 4.5 Vss
↔ 4.5 Vss
↔ 4.5 Vss
↔ 4.5 Vss
Table 23: Signal Amplitude Monitoring
AERR
Code
Adr 0x03, Bit 1
Amplitude error message
0x00
0x01
disabled
enabled
Table 24: Amplitude Error
FERR
Code
Adr 0x03, Bit 0
Excessive frequency error message
0x00
0x01
disabled
enabled
Note
Input frequency monitoring is operational for
resolutions ≥ 16
Table 25: Frequency Error
Configuration Error
Messaging always released
Table 26: Configuration Error
Error Indication at NERR
Failure Mode
Pin signal NERR
No error
Amplitude error
Frequency error
Configuration
HI
LO/HI = 75 %
LO/HI = 50 %
LO
Undervoltage
System error
LO
NERR = low by external error signal
Table 27: Error indication at NERR
Vthmin
Figure 13: Sin2 + Cos2 signal monitoring.
To enable the diagnosis of faults, the various types
of error are signaled at NERR using a PWM code as
given in the key table.
Two error bits are provided to enable communication
via the SSI interface; these bits can decode four different types of error. If NERR is held at low by an external
source, such as an error message from the system, for
example, this can also be verified via the SSI interface.
Error events are stored for the SSI data output and
deleted afterwards. Errors at NERR are displayed for a
minimum of ca. 10 ms, as far as no SSI readout causes
a deletion.
If an error in amplitude occurs the conversion process is terminated and the incremental output signals
halted. An error in amplitude rules out the possibility of
an error in frequency.
Error Messages SSI
Failure Mode
Error bits E1, E0 (actice low)
No error
Amplitude error
Frequency error
1, 1
0, 1
1, 0
Configuration
System error
0, 0
0, 0 (NERR pulled low by external signal)
Line Signal SLO
iC-NQL_3: Data output is deactivated and
SLO permanently high in case of:
configuration phase, invalid configuration,
undervoltage.
Table 28: Error Messages SSI
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 18/24
TEST FUNCTIONS
TMODE
Code
Adr 0x06, Bit 3:1
Signal at Z
Description
0x00
0x01
0x02
0x03
0x04
0x05
Z
A xor B
ENCLK
NLOCK
CLK
DIVC
no test mode
Output A EXOR B
iC-Haus device test
iC-Haus device test
iC-Haus device test
iC-Haus device test
0x06
0x07
PZERO - NZERO
TP
iC-Haus device test
iC-Haus device test
Condition
CFGABZ = 0x00
TMA
Code
Adr 0x06, Bit 0
Pin A
Pin B
Pin SDA
Pin SCL
0x00
0x01
A
COS+
SDA
SIN+
SCL
SIN-
Notes
To permit the verification of GAIN and OFFSET
settings, the input amplifier outputs are available at
the pins. To operate the converter a signal of 4 Vpp
is the ideal here and should not be exceeded. Pin
loads above 1 MΩ are adviceable for accurate
measurements.
B
COS-
Table 30: Analog Test Mode
Table 29: Test Mode
Parameter GAIN ideally adjusts the signal levels to ca.
4 Vpp and should not be touched afterwards.
5V
A: COS+
SDA: Sin+
Both scope display modes are feasible for OFFS (positive values) or RATIO adjustments; regarding the adjustment of PHASE the X/Y mode may be preferred.
For OFFS adjustment towards negative values the test
signals COS- (pin B) and SIN- (pin SCL) are relevant.
0V
Y/T 1 V/Div vert.
X/Y 1 V/Div vert. 1 V/Div hor.
Figure 14: Calibrated signals with TMA mode.
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 19/24
SSI INTERFACE
After each communication cycle the SSI interface returns to its idle state when the monoflop timeout ttos
has elapsed. This temporal condition also determines
up to which clock line pause duration the iC-NQL retains the current data output cycle - the master may
thus not undershoot a minimum clock frequency of
f(CLK)min.
CFGTOS
Code
Adr 0x06, Bit 5:4
Timeout ttos
Ref. clock
counts
Signal Names
Name
Description
Design iC-NQL_X3:
typ. 128 µs
256-259
11 kHz
0x01
0x02
0x03
typ. 16 µs
typ. 4 µs
typ. 1 µs
88 kHz
352 kHz
1.41 MHz
32-35
8-11
2-5
0x00
Design iC-NQL_3:
typ. 20 µs
46-46
50 kHz
0x01
0x02
0x03
typ. 20 µs
typ. 1.5 µs
typ. 1.5 µs
50 kHz
660 kHz
660 MHz
46-47
3-4
3-4
Sensor data (S0 is LSB)
Error messages
Stop
Low signal
Table 32: Signal Names
The angle conversion is halted for a half clock cycle as
soon as the interface receives the first falling edge on
CLK, what is the trigger signal to output updated position data. The halt duration must be taken into consideration when calculating the maximum input frequency.
f(CLK) min*
0x00
S
E
CFGSSI
Adr 0x03, Bit 7:6
Code
Additional bits
Ring register operation
0x00
0x01
E1, E0, zero bit
none
no
no
0x02
0x03
not permissible
none
yes
32
fosc
Notes
A ref. clock count is equal to
(see El. Char.,
A01).
The permissible max. clock frequency is specified
by E05.
*) A low clock frequency can reduce the permissible
maximum input frequency since conversion is
paused after the first falling edge on CLK for a half
clock cycle.
Table 33: SSI Output Options
Cycle
CLK
DATA
Table 31: Monoflop Time (SSI Timeout)
S12
MSB
S0
LSB
Stop
S12
MSB
S0
LSB
Latch
Stop
Timeout
Figure 15: SSI output format during ring register
operation. The example displays the
transmission of a 13-bit angle value; error messages are switched off herein
(SELRES = 0x03, CFGSSI = 0x03)
The iC-NQL position data output contains the angle
value (S) with a bit length of 2 to 13 bits (depending
on SELRES), and up to 3 add-on bits (error messages
E1 and E0 plus a zero bit). Generally, the data output
is in binary format starting with the MSB.
SSI Output Formats
Res
Mode Error CRC
10 bit SSI
X
-
T1
T2
T3
T4... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25
S9
S8
S7
S6 ... S0
E1
E0
Example
13 bit SSI
-
-
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
0
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop
S12 S11 S10 S9 ... S3
S2
S1
S0
S12 S11 S10 S9 ... S3
S2
S1
S0
0
0
0
0
0
0
0
0
0
0
0
*1
Example
SSI-R -
-
0
0
0
*2
Example
0
0
Stop S12 S11 S10 S9
0
Configuration CFGSSI = 0x00; *1) CFGSSI = 0x01; *2) CFGSSI = 0x03
Legend SSI = SSI protocol, SSI-R = SSI ring register operation
Table 34: SSI Output Formats
0
0
0
0
0
0
0
S8
S7
S6
S5
S4
S3
S2
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 20/24
EEPROM INTERFACE and STARTUP BEHAVIOUR
Serial EEPROM components permitting operation
from 3.3 V to 5 V can be connected (such as 24C02, for
example). When the device is switched on the memory
area of bytes 0 to 15 is mapped onto iC-NQL’s registers.
After startup, iC-NQL does not recognize a defined
configuration; the configuration RAM can contain any
values.
After the supply has been turned on (power on reset),
iC-NQL reads the configuration data from the EEPROM and during this phase halts error pin NERR actively on a low signal (open drain output).
unsigned char ucDataStream = 0 ;
i n t iCRCPoly = 0x127 ;
unsigned char ucCRC=0;
int i = 0;
After a successful CRC the data output to SLO is released and the error indication at pin NERR reset;
an external pull-up resistor can supply a high signal.
iC-NQL then switches to normal operation and determines the current angle position, providing that a sensor is connected up to it and there is no amplitude error
(or this is deactivated).
Should the CRC prove unsuccessful due to a data error (disrupted transmission, no EEPROM or the EEPROM is not programmed), the configuration phase is
automatically repeated. After a third failed attempt, the
procedure is aborted and error pin NERR remains active, displaying a permanent low.
Example of CRC Calculation Routine
ucCRC = 0 ; / / s t a r t v a l u e ! ! !
f o r ( iReg = 0 ; iReg <15; iReg ++)
{
ucDataStream = ucGetValue ( iReg ) ;
f o r ( i =0; i <=7; i ++) {
i f ( ( ucCRC & 0x80 ) ! = ( ucDataStream & 0x80 ) )
ucCRC = (ucCRC << 1 ) ^ iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream = ucDataStream << 1 ;
}
}
CRC_E2P
Code
Adr 0x0F, Bit 7:0
Description
0x00
...
0xFF
Check value formed by CRC polynomial 0x127
Table 35: Check value for EEPROM data
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 21/24
APPLICATION HINTS
Principle Input Circuits
Figure 16: Input circuit for voltage signals of 1 Vpp
with no ground reference. When grounds
are not separated the connection NSIN
to VREF must be omitted.
Figure 18: Input circuit for single-sided voltage or
current source signals with ground reference (adaptation via resistors R3, R4).
Figure 20: Input circuit for differential current sink
sensor outputs, eg. using Opto Encoder
iC-WG.
Figure 17: Input circuit for current signals of 11 µA.
This circuit does not permit offset calibration.
Figure 19: Simplified input wiring for single-sided
voltage signals with ground reference.
Figure 21: Combined input circuit for 11 µA, 1 Vpp
(with 120 Ω termination) or TTL encoder
signals. RS3/4 and CS1 serve as protection against ESD and transients.
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 22/24
Basic Circuit
Figure 22: Basic circuit for evaluation of magneto-resistor bridge sensors.
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 23/24
DESIGN REVIEW: Notes On Chip Functions
iC-NQL X3
No.
1
Function, Parameter/Code
Description and Application Hints
ZPOS
Illegal settings:
0x01...0x07, 0x09...0x0F,
0x11...0x17, 0x19...0x1F
Illegal settings of ZPOS delay accurate converter operation following power on.
Depending on the sin/cos input signals (phase angle) the A/B outputs can
provide pulses causing an external counter to alternately count up and down.
This may disturb the startup of a drive if the motion controller tolerates only single
A/B edges during standstill checking.
The converter operation is again accurate when the sin/cos input signals have
changed, by a maximum of 45 angular degrees.
2
Pin DATA
When cycling power pin DATA may show high or low level initially.
With pin TEST = low (e.g. pin open) at least a single low pulse at pin CLK is
required to trigger pin DATA to show a high level after the timeout has elapsed.
When continuing the clock signal after completion of data output, additional zero
bits are output.
With pin TEST = high (e.g. pin wired to VDD) only the timeout needs to elapse to
trigger pin DATA showing high level. When continuing the clock signal after
completion of data output, additional one bits are output.
3
M2S obsolete
Bits 5 to 7 of address 0x00 must be programmed to zero; period counting is not
available.
Table 36: Notes on chip functions iC-NQL_X3
iC-NQL 3
No.
Function, Parameter/Code
Description and Application Hints
1
Pin DATA
When cycling power pin DATA shows high level initially and remains on a
permanent high if CRC verification does not confirm the configuration data.
3
M2S obsolete
Bits 5 to 7 of address 0x00 must be programmed to zero; period counting is not
available.
Table 37: Notes on chip functions iC-NQL_3
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relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
materials.
The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev D2, Page 24/24
ORDERING INFORMATION
Type
Package
Order Designation
iC-NQL
TSSOP20 4.4 mm
iC-NQL TSSOP20
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Tel.: +49 (61 35) 92 92-0
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: [email protected]
Appointed local distributors: http://www.ichaus.com/sales_partners