SN74LVCH16T245-EP www.ti.com........................................................................................................................................................................................... SCES726 – NOVEMBER 2008 16-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS FEATURES 1 • • • • • • • • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage VCC Isolation Feature – If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Ranges (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability DGG OR DGV PACKAGE (TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 VCCB 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCCB 2B5 2B6 GND 2B7 2B8 2DIR 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE 1A1 1A2 GND 1A3 1A4 VCCA 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCCA 2A5 2A6 GND 2A7 2A8 2OE Additional temperature ranges are available – contact factory DESCRIPTION/ORDERING INFORMATION This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. The SN74LVCH16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated SN74LVCH16T245-EP SCES726 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com The SN74LVCH16T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then all outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION (1) PACKAGE (2) TA –55°C to 125°C (1) (2) ORDERABLE PART NUMBER Top-Side Marking TSSOP – DGG Tape and reel CLVCH16T245MDGGREP 8UT245MEP TVSOP – DGV Tape and reel CLVCH16T245MDGVREP LDHT245MEP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. GQL OR ZQL PACKAGE (TOP VIEW) 1 2 3 4 5 6 A B C D E F G H J K 2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVCH16T245-EP SN74LVCH16T245-EP www.ti.com........................................................................................................................................................................................... SCES726 – NOVEMBER 2008 TERMINAL ASSIGNMENTS (1) 1 (1) 2 3 4 5 6 A 1DIR NC NC NC NC 1OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 VCCB VCCA 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 VCCB VCCA 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC 2OE NC – No internal connection FUNCTION TABLE (1) (EACH 16-BIT SECTION) CONTROL INPUTS OE (1) OUTPUT CIRCUITS OPERATION DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B bus H X Hi-Z Hi-Z Isolation Input circuits of the data I/Os are always active. LOGIC DIAGRAM (POSITIVE LOGIC) 1DIR 1 2DIR 48 1A1 25 1OE 47 2A1 2 To Seven Other Channels 24 2OE 36 13 1B1 2B1 To Seven Other Channels Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVCH16T245-EP 3 SN74LVCH16T245-EP SCES726 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCCA VCCB Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state (2) MIN MAX –0.5 6.5 I/O ports (A port) –0.5 6.5 I/O ports (B port) –0.5 6.5 Control inputs –0.5 6.5 A port –0.5 6.5 B port –0.5 6.5 A port –0.5 VCCA + 0.5 B port –0.5 VCCB + 0.5 UNIT V V V VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA Continuous current through each VCCA, VCCB, and GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) 4 ±100 DGV package –65 V mA 58 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVCH16T245-EP SN74LVCH16T245-EP www.ti.com........................................................................................................................................................................................... SCES726 – NOVEMBER 2008 Recommended Operating Conditions (1) (2) (3) VCCI VCCA VCCB VCCO Supply voltage 1.65 V to 1.95 V VIH High-level input voltage MAX 1.65 5.5 1.65 5.5 1.7 3 V to 3.6 V VCCI × 0.7 1.65 V to 1.95 V VIL Data inputs (4) VCCI × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 4.5 V to 5.5 V High-level input voltage Control inputs (referenced to VCCA) (5) VCCA × 0.65 2.3 V to 2.7 V 1.7 3 V to 3.6 V V 2 4.5 V to 5.5 V VCCA × 0.7 1.65 V to 1.95 V VCCA × 0.35 2.3 V to 2.7 V 0.7 3 V to 3.6 V 0.8 VIL Low-level input voltage Control inputs (referenced to VCCA) (5) VI Input voltage Control inputs 0 5.5 Active state 0 VCCO 3-State 0 5.5 4.5 V to 5.5 V VI/O IOH Input/output voltage High-level output current Δt/ Δv TA (1) (2) (3) (4) (5) Low-level output current Input transition rise or fall rate Data inputs V VCCA × 0.3 1.65 V to 1.95 V –4 2.3 V to 2.7 V –8 3 V to 3.6 V –24 4.5 V to 5.5 V –32 1.65 V to 1.95 V IOL V VCCI × 0.3 1.65 V to 1.95 V VIH V V 2 4.5 V to 5.5 V Low-level input voltage UNIT VCCI × 0.65 2.3 V to 2.7 V Data inputs (4) MIN V mA 4 2.3 V to 2.7 V 8 3 V to 3.6 V 24 4.5 V to 5.5 V 32 1.65 V to 1.95 V 20 2.3 V to 2.7 V 20 3 V to 3.6 V 10 4.5 V to 5.5 V 5 Operating free-air temperature V –55 125 mA ns/V °C VCCI is the VCC associated with the data input port. VCCO is the VCC associated with the output port. All unused control inputs of the device must be held at VCCA GND to ensure proper device operation and minimize power consumption. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V. For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVCH16T245-EP 5 SN74LVCH16T245-EP SCES726 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com Electrical Characteristics (1) (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL Control inputs II IBHL (3) IBHH (4) VCCA VCCB IOH = –100 µA, TEST CONDITIONS VI = VIH 1.65 V to 4.5 V 1.65 V to 4.5 V IOH = –4 mA, VI = VIH 1.65 V 1.65 V 1.2 IOH = –8 mA, VI = VIH 2.3 V 2.3 V 1.9 IOH = –24 mA, VI = VIH 3V 3V 2.4 IOH = –32 mA, VI = VIH 4.5 V 4.5 V 3.8 IOL = 100 µA, VI = VIL 1.65 V to 4.5 V 1.65 V to 4.5 V 0.1 IOL = 4 mA, VI = VIL 1.65 V 1.65 V 0.45 IOL = 8 mA, VI = VIL 2.3 V 2.3 V 0.3 IOL = 24 mA, VI = VIL 3V 3V 0.55 IOL = 32 mA, VI = VIL 4.5 V 4.5 V 0.55 1.65 V to 5.5 V 1.65 V to 5.5 V VI = 0.58 V 1.65 V 1.65 V 15 VI = 0.7 V 2.3 V 2.3 V 45 VI = 0.8 V 3V 3V 75 VI = VCCA or GND Ioff A or B port IOZ B port A port ICCA ±1 4.5 V 100 1.65 V –15 VI = 1.7 V 2.3 V 2.3 V –45 3V 3V –75 VI or VO = 0 to 5.5 V VO = VCCO or GND, VI = VCCI or GND OE = VIH OE = don't care VI = VCCI or GND, IO = 0 4.5 V 4.5 V –100 1.95 V 1.95 V 200 2.7 V 2.7 V 300 3.6 V 3.6 V 500 5.5 V 5.5 V 900 1.95 V 1.95 V –200 2.7 V 2.7 V –300 3.6 V 3.6 V –500 µA µA 5.5 V 5.5 V 0V 0 to 5.5 V ±0.5 ±1.5 –900 ±20 0 to 5.5 V 0V ±0.5 ±1.5 ±20 1.65 V to 5.5 V 1.65 V to 5.5 V ±1 ±4 0V 5.5 V ±1 ±4 ±1 ±4 5.5 V 0V 1.65 V to 5.5 V 1.65 V to 5.5 V 20 5V 0V 20 0V 5V –4 1.65 V to 5.5 V 1.65 V to 5.5 V 20 5V 0V –4 0V 5V 20 ICCA + ICCB VI = VCCI or GND, IO = 0 1.65 V to 5.5 V 1.65 V to 5.5 V 30 (5) (6) 6 µA µA VI = VCCI or GND, IO = 0 (4) V µA ICCB (1) (2) (3) UNIT V ±3 4.5 V VI = 0 to VCC B port ±0.5 1.65 V VI = 0 to VCC A port MIN MAX VCCO – 0.1 VI = 1.07 V VI = 3.15 V IBHHO (6) TYP MAX VI = 0.1.35 V VI = 2 V IBHLO (5) MIN µA µA µA µA µA VCCO is the VCC associated with the output port. VCCI is the VCC associated with the input port. The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and then raising it to VIL max. The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and then lowering it to VIH min. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVCH16T245-EP SN74LVCH16T245-EP www.ti.com........................................................................................................................................................................................... SCES726 – NOVEMBER 2008 Electrical Characteristics (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA VCCB 3 V to 5.5 V 3 V to 5.5 V ΔICCA DIR DIR at VCCA – 0.6 V, B port = open, A port at VCCA or GND Ci Control inputs VI = VCCA or GND 3.3 V 3.3 V Cio A or B port VO = VCCA/B or GND 3.3 V 3.3 V MIN TYP MAX MIN MAX UNIT 50 µA 4 5 pF 8.5 10 pF Switching Characteristics over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL FROM (INPUT) TO (OUTPUT) A VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX B 1.7 25.9 1.3 13.2 1 11.4 0.4 11.1 ns B A 0.9 27.8 0.8 27.8 0.7 27.4 0.7 27.4 ns OE A 1.5 33.6 1.5 33.4 1.5 33.3 1.4 33.2 ns OE B 2.4 36.2 1.9 17.1 1.7 16 1.3 14.3 ns OE A 0.4 28 0.4 27.8 0.4 27.7 0.4 27.7 ns OE B 1.8 36 1.5 22 1.2 16.6 0.9 14.8 ns Switching Characteristics over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL FROM (INPUT) TO (OUTPUT) A VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V MIN MAX MIN MAX B 1.5 25.4 1.2 B A 1.2 13.3 OE A 1.4 OE B OE OE VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX 13 0.8 10.2 0.6 8.8 ns 1 13.1 1 12.9 0.9 12.8 ns 13 1.4 13 1.4 13 1.4 13 ns 2.3 33.6 1.8 14 1.7 14.3 0.9 10.9 ns A 1 14.9 1 14.9 1 14.9 1 14.9 ns B 1.7 32.2 1.5 16.9 1.2 13.4 1 10.9 ns Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVCH16T245-EP 7 SN74LVCH16T245-EP SCES726 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com Switching Characteristics over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) A tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX B 1.6 25.2 1.1 12.8 0.8 10.2 0.6 8.4 ns B A 0.8 11.2 0.8 10.2 0.7 10.1 0.6 10 ns OE A 1.6 12.2 1.6 12.2 1.6 12.2 1.6 12.2 ns OE B 2.1 33 1.7 14.3 1.5 12.8 0.8 10.3 ns OE A 0.8 11.8 0.8 12.1 0.8 12.1 0.8 12.1 ns OE B 1.8 3.7 1.4 16.4 1.1 12.5 0.8 10.4 ns Switching Characteristics over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPHZ tPLZ tPHZ tPLZ tPZH tPZL tPZH tPZL FROM (INPUT) TO (OUTPUT) A VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX VCC = 3.3 V ± 0.3 V MIN MAX VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX B 1.5 25.4 1 12.8 0.7 10 0.4 8.2 ns B A 0.7 11 0.4 8.8 0.3 8.5 0.3 8.3 ns OE A 0.3 9.4 0.3 9.4 0.3 9.4 0.3 9.4 ns OE B 2 32.7 1.8 13.7 1.4 12 0.7 9.7 ns OE A 0.7 10.4 0.7 10.4 0.7 10.4 0.7 10.4 ns OE B 1.5 31.6 1.3 15.4 1 12.1 0.9 10 ns Operating Characteristics TA = 25＝C PARAMETER CpdA (1) CpdB (1) (1) 8 TEST CONDITIONS A-port input, B-port output B-port input, A-port output A-port input, B-port output CL = 0, f = 10 MHz, tr = tf = 1 ns B-port input, A-port output VCCA = VCCB = 1.8 V VCCA = VCCB = 2.5 V VCCA = VCCB = 3.3 V VCCA = VCCB = 5 V TYP TYP TYP TYP 2 2 2 3 18 19 19 22 18 19 20 22 2 2 2 2 UNIT pF Power dissipation capacitance per transceiver Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVCH16T245-EP SN74LVCH16T245-EP www.ti.com........................................................................................................................................................................................... SCES726 – NOVEMBER 2008 PARAMETER MEASUREMENT INFORMATION 2 × VCCO S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCO GND RL tw LOAD CIRCUIT VCCI VCCI/2 Input VCCO CL RL VTP 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V 15 pF 15 pF 15 pF 15 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 0.15 V 0.15 V 0.3 V 0.3 V VCCI/2 0V VOLTAGE WAVEFORMS PULSE DURATION VCCA Output Control (low-level enabling) VCCA/2 VCCA/2 0V tPZL VCCI Input VCCI/2 VCCI/2 0V tPLH Output tPHL VOH VCCO/2 VOL VCCO/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCCO Output Waveform 1 S1 at 2 × VCCO (see Note B) VCCO/2 VOL + VTP VOL tPZH tPHZ Output Waveform 2 S1 at GND (see Note B) VCCO/2 VOH − VTP VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns, dv/dt ≥1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. VCCI is the VCC associated with the input port. I. VCCO is the VCC associated with the output port. J. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): SN74LVCH16T245-EP 9 PACKAGE OPTION ADDENDUM www.ti.com 4-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CLVCH16T245MDGGREP ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CLVCH16T245MDGVREP ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/09605-01XE ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/09605-01YE ACTIVE TVSOP DGV 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74LVCH16T245-EP : • Catalog: SN74LVCH16T245 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device CLVCH16T245MDGGRE P Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 CLVCH16T245MDGVREP TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CLVCH16T245MDGGREP TSSOP DGG 48 2000 346.0 346.0 41.0 CLVCH16T245MDGVREP TVSOP DGV 48 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. 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