Holtek HT86BR60 Enhanced voice 8-bit mcu Datasheet

HT86BXX/HT86BRXX
Enhanced Voice 8-Bit MCU
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage: 2.2V~5.5V
· External RC oscillator converter
· System clock: 4MHz~8MHz
· 8 capacitor/resistor sensor input
· Crystal and RC system oscillator
· Watchdog timer function
· 16/20/24 I/O pins
· 8-level subroutine nesting
· 8K´16-bit Program Memory
· Low voltage reset function
· 192´8/384´8-bit Data Memory
· Integrated voice ROM with various capacities
· External interrupt input
· Power-down function and wake-up feature reduce
power consumption
· Three 8-bit programmable Timers with overflow
· Up to 0.5ms instruction cycle with 8MHz system clock
interrupt and 8-stage prescaler
at VDD= 5V
· 12-bit high quality voltage type D/A output
· PWM circuit direct audio output
· 63 powerful instructions
General Description
Device Types
The Voice type series of MCUs are 8-bit high performance microcontrollers which include a voice synthesizer and tone generator. They are designed for
applications which require multiple I/Os and sound effects, such as voice and melody. The devices can provide various sampling rates and beats, tone levels,
tempos for speech synthesizer and melody generator.
They also include an integrated high quality, voltage
type DAC output. The external interrupt can be triggered with falling edges or both falling and rising edges.
Devices which have the letter ²BR² within their part
number, indicate that they are OTP devices offering the
advantages of easy and effective program updates, using the Holtek range of development and programming
tools. These devices provide the designer with the
means for fast and low-cost product development cycles. Devices which have the letter ²B² within their part
number indicate that they are mask version devices.
These devices offer a complementary device for applications that are at a mature state in their design process
and have high volume and low cost demands.
The devices are excellent solutions for versatile voice
and sound effect product applications with their efficient
MCU instructions providing the user with programming
capability for powerful custom applications. The system
frequency can be up to 8MHz at an operating voltage of
2.2V and include a power-down function to reduce
power consumption.
Part numbers including ²R² are OTP devices, all others
are mask version devices.
Fully pin and functionally compatible with their OTP sister devices, the mask version devices provide the ideal
substitute for products which have gone beyond their
development cycle and are facing cost-down demands.
In this datasheet, for convenience, when describing device functions, only the OTP types are mentioned by
name, however the same described functions also apply to the Mask type devices.
Rev. 1.80
1
March 12, 2010
HT86BXX/HT86BRXX
Selection Table
The devices include a comprehensive range of features, with most features common to all devices. The main features
distinguishing them are Program Memory and Data Memory capacity, Voice ROM and Voice capacity, I/O count, stack
size and package types. The functional differences between the devices are shown in the following table.
Part No.
VDD
Program
Data
Memory Memory
2.2V~
5.5V
HT86B03
4K´16
192´8
Timer
Voice
ROM
Voice
Capacity
I/O
96K´8
36sec
12
Audio Output
C/R-F
8-bit
16-bit
3
¾
¾
DAC
PWM
12-bit
¾
Stack
Package
Types
8
16NSOP, 24SSOP
(150/209mil)
24SSOP(209mil),
28SOP, 44QFP
HT86BR10
2.2V~
5.5V
8K´16
192´8
192K´8
72sec
16
3
¾
¾
12-bit
Ö
8
24SSOP
(150/209mil),
28SOP, 44QFP
2.2V~
5.5V
8K´16
192´8
256K´8
96sec
16
3
¾
¾
12-bit
Ö
8
28SOP, 44QFP
2.2V~
5.5V
8K´16
192´8
384K´8
144sec
16
3
¾
¾
12-bit
Ö
8
28SOP, 44QFP
HT86B40
2.2V~
5.5V
8K´16
384´8
512K´8
192sec
20
3
1
Ö
12-bit
Ö
8
28SOP, 44QFP
HT86B50
2.2V~
5.5V
8K´16
384´8
768K´8
288sec
20
3
1
Ö
12-bit
Ö
8
28SOP, 44QFP
2.2V~
5.5V
8K´16
384´8
1024K´8
384sec
20
3
1
Ö
12-bit
Ö
8
HT86B70
2.2V~
5.5V
8K´16
384´8
1536K´8
576sec
24
3
1
Ö
12-bit
Ö
8
44/100QFP
HT86B80
2.2V~
5.5V
8K´16
384´8
2048K´8
768sec
24
3
1
Ö
12-bit
Ö
8
44/100QFP
HT86B90
2.2V~
5.5V
8K´16
384´8
3072K´8
1152sec
24
3
1
Ö
12-bit
Ö
8
100QFP
HT86B10
HT86B20
HT86BR30
HT86B30
HT86BR60
HT86B60
28SOP
28SOP, 44QFP
Note: 1. For devices that exist in more than one package formats, the table reflects the situation for the larger
package.
2. For the HT86B90, the operating voltage is 2.2V~5.5V at fSYS=4MHz/3.3V~5.5V at fSYS=8MHz.
3. Voice length is estimated by 21K-bit data rate
Block Diagram
W a tc h d o g
T im e r
S ta c k
R O M P ro g ra m
M e m o ry
R O M D a ta
M e m o ry
R e s e t
C ir c u it
8 - b it
R IS C
M C U
C o re
R A M D a ta
M e m o ry
In te rru p t
C o n tr o lle r
L o w
V o lta g e
R e s e t
P W M
8 /1 6 - b it
T im e r
W a tc h d o g
T im e r O s c illa to r
R C /C ry s ta l
O s c illa to r
*
A n a lo g
S w itc h
D /A
C o n v e rte rs
R C
O s c illa tio n
N o te : " * " T h e H T 8 6 B 0 3 d o e s n o t c o n ta in a P W M
Rev. 1.80
fu n c tio n .
2
March 12, 2010
HT86BXX/HT86BRXX
Pin Assignment
N C
1
2 4
N C
N C
1
2 4
N C
N C
1
2 4
N C
P A 7
2
2 3
N C
P A 7
2
2 3
N C
P A 7
2
2 3
V S S P
P A 6
3
2 2
N C
P A 6
3
2 2
N C
P A 6
3
2 2
V D D P
V S S
1
1 6
P A 0
P A 5
4
2 1
V D D A
P A 5
4
2 1
V D D A
P A 5
4
2 1
V D D A
V D D /IN T
2
1 5
P A 1
P A 4
5
2 0
A U D
P A 4
5
2 0
A U D
P A 4
5
2 0
A U D
R E S
3
1 4
P A 2
P A 3
6
1 9
V S S A
P A 3
6
1 9
V S S A
P A 3
6
1 9
V S S A
O S C 1
4
1 3
P A 3
P A 2
7
1 8
O S C 2
P A 2
7
1 8
O S C 2
P A 2
7
1 8
O S C 2
O S C 2
5
1 2
P A 4
P A 1
8
O S C 1
P A 1
8
1 7
O S C 1
P A 1
8
1 7
O S C 1
V S S A
6
1 1
P A 5
1 7
P A 0
9
R E S
P A 0
9
1 6
R E S
P A 0
9
1 6
R E S
A U D
7
1 0
P A 6
1 6
P B 4
1 0
V D D /IN T
P B 4
1 0
1 5
IN T
P B 4
1 0
1 5
V D D /IN T
V D D A
8
9
P A 7
1 5
P B 5
1 1
1 4
V S S
P B 5
1 1
1 4
V D D
P B 5
1 1
1 4
V S S
P B 6
1 2
1 3
P B 7
P B 6
1 2
1 3
V S S
P B 6
1 2
1 3
P B 7
H T 8 6 B 0 3
1 6 N S O P -A
H T 8 6 B 0 3
2 4 S S O P -A
V D D P
1
2 8
V D D A
P W M 1
2
2 7
A U D
N C
1
2 8
N C
P W M 2
3
2 6
V S S A
N C
2
2 7
V S S P
V S S P
4
2 5
O S C 2
N C
3
2 6
P W M 2
N C
5
2 4
O S C 1
N C
4
2 5
P W M 1
N C
6
2 3
R E S
P A 7
5
2 4
V D D P
N C
7
2 2
IN T
P A 6
6
2 3
V D D A
N C
8
2 1
V D D
P A 5
7
2 2
A U D
P A 7
9
2 0
V S S
P A 4
8
2 1
V S S A
P A 6
1 0
1 9
P B 2
P A 3
9
2 0
O S C 2
P A 5
1 1
1 8
P B 1
P A 2
1 0
1 9
O S C 1
P A 4
1 2
1 7
P B 0
P A 1
1 1
1 8
N C
P A 3
1 3
1 6
P A 0
P A 0
1 2
1 7
R E S
P A 2
1 4
1 5
P A 1
N C
1 3
1 6
IN T
V S S
1 4
1 5
V D D
H T 8
H T 8
H T 8
H T 8
6 B 1
6 B 2
6 B R
6 B R
0
0 /H T 8 6 B 3 0
1 0
3 0
P -D
P -B
P -B
P -A
3
2 6
N C
N C
4
2 5
N C
N C
4
2 5
N C
P A 7
5
2 4
V S S P
P A 7
5
2 4
N C
P A 6
6
2 3
P W M 2
P A 6
6
2 3
V D D A
P A 5
7
2 2
P W M 1
P A 5
7
2 2
A U D
P A 4
8
2 1
V D D P
P A 4
8
2 1
V S S A
P A 3
9
2 0
O S C 2
P A 3
9
2 0
O S C 2
P A 2
1 0
1 9
O S C 1
P A 2
1 0
1 9
O S C 1
P A 1
1 1
1 8
N C
P A 1
1 1
1 8
N C
P A 0
1 2
1 7
R E S
P A 0
1 2
1 7
R E S
N C
1 3
1 6
IN T
N C
1 3
1 6
IN T
V S S
1 4
1 5
V D D
V S S
1 4
1 5
V D D
H T 8 6 B 6 0
H T 8 6 B R 6 0
2 8 S O P -B
2 8 S O P -A
2 8 S O P -C
2 8 S O P -B
N C
N C
N C
N C
N C
N C
P
P
3 0
T 8 6 B 5 0
T 8 6 B 7 0
8 0
-A
9
2 9
2 8
2 7
2 6
2 5
2 4
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
2 3
P
P
P
P
2
P
1
P
P
P
A
A
1
2
P
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1
8
7
3
7
4
7
5
7
6
7
7
7
8
7
9
7
1 0
7
1 1
7
1 2
6
1 3
6
1 4
6
1 5
H T 8 6 B 7 0 /H T 8 6 B 8 0
6
1 6
H T 8 6 B 9 0
6
1 7
1 0 0 Q F P -A
6
1 8
6
1 9
6
2 0
6
2 1
6
2 2
5
2 3
5
2 4
5
2 5
5
2 6
5
2 7
5
2 8
5
2 9
5
3 0
5
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
1
0
N C
8
N C
2
9
N C
7
N C
6
N C
5
N C
N C
4
3
N C
2
0
N C
1
N C
N C
N C
9
N C
8
N C
7
N C
6
N C
V S
P W
P W
V D
V D
5
4
3
2
1
0
N C
9
8
7
6
5
4
3
2
1
S P
M 2
M 1
D P
D A
N C
A U D
N C
V S S A
N C
N C
N C
O S C 2
O S C 1
N C
R E S
IN T
V D D
V S S
P D 7
P D 6
P D 5
P D 3
P D 2
P D 1
P D 0
P D 4
P B 7
P B 6
P B 5
P B 4
P B 3
P B 2
1 0
V S S
P W M
P W M
V D D
V D D
A U D
V S S
O S C
O S C
R E S
IN T
N C
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
B 0
N C
N C
N C
N C
B 1
N C
N C
N C
N C
N C
1
N C
N C
N C
N C
2
N C
N C
A
N C
N C
N C
N C
N C
N C
A
N C
4
1 1
N C
N C
3 1
8
N C
1
P
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
3 3
3
7
2 6
N C
P W M
V D D
V D D
A U D
V S S
O S C
O S C
N C
R E S
IN T
N C
N C
3 2
0 /H
0 /H
8 6 B
Q F P
3
N C
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
V D D
V S S
N C
N C
N C
N C
P B 7
P B 6
P B 5
P B 4
P B 3
4 0 3 9 3 8 3 7 3 6 3 5 3 4
H T 8 6 B 4
H T 8 6 B 6
H T
4 4
N C
N C
N C
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
3 3
2
6
N C
2 7
N C
1 0
5
2 8
2
N C
9
4 4 4 3 4 2 4 1
1
N C
N C
8
1
N C
N C
H T 8 6 B 6 0
H T 8 6 B R 6 0
P
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 0
P B 1
P B 2
N C
2 7
N C
H T 8 6 B 1 0 /H T 8 6 B 2 0 /H T 8 6 B 3 0
H T 8 6 B R 1 0 /H T 8 6 B R 3 0
4 4 Q F P -B
1 1
2 8
2
N C
4
7
1
N C
N C
3
6
H T 8 6 B 1 0 /H T 8 6 B R 1 0
2 4 S S O P -A
P W M 2
V S S P
N C
4 0 3 9 3 8 3 7 3 6 3 5 3 4
2
5
2 4 S S O P -B
N C
H T 8 6 B 4 0 /H T 8 6 B 5 0 /H T 8 6 B 6 0
2 8 S O P -A
N C
N C
N C
4 4 4 3 4 2 4 1
1
S O
S O
S O
S O
N C
N C
N C
N C
N C
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 0
P B 1
P B 2
2 8
2 8
2 8
2 8
H T 8 6 B 0 3
V D D
V S S
P D 7
P D 6
P D 5
P D 4
P B 7
P B 6
P B 5
P B 4
P B 3
Rev. 1.80
3
March 12, 2010
HT86BXX/HT86BRXX
Pad Assignment
HT86B03
(0 ,0 )
V D D A
2 5
P A 6
1
2
P A 5
P A 7
P A 4
3
8
9
1 0
V S S A
2 2
O S C 2
2 1
O S C 1
1 7 1 8 1 9 2 0
N C
1 6
A U D
2 3
N C
1 5
N C
1 4
N C
1 2 1 3
V S S
P B 5
P B 4
P A 0
1 1
R E S
7
IN T
P A 1
V D D
6
P B 7
P A 2
P B 6
5
4
P A 3
2 4
Chip size: 1975´1930 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
4
March 12, 2010
HT86BXX/HT86BRXX
HT86BR10
P A 7
1
3 4
V S S P
(0 ,0 )
3 3
V S S P
3 2
P W M 2
P A 6
2
P A 5
3
P A 4
4
3 1
P W M 1
P A 3
5
P A 2
6
3 0
V D D P
2 9
V D D A
2 8
A U D
P A 1
P A 0
7
8
P B 0
9
P B 1
1 0
2 7
V S S A
2 6
IN T
V D D
O S C 1
2 4
R E S
N C
V S S
2 0 2 1 2 2 2 3
N C
P B 6
1 9
N C
1 8
N C
1 7
P B 7
1 5 1 6
P B 5
P B 2
P B 3
1 3 1 4
P B 4
1 1 1 2
O S C 2
2 5
Chip size: 3265´4010 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
5
March 12, 2010
HT86BXX/HT86BRXX
HT86B10
(0 ,0 )
3 3
V S S P
3 2
P W M 2
3 1
P W M 1
3 0
V D D P
P A 7
1
P A 6
2
P A 5
3
P A 4
4
2 9
V D D A
P A 3
5
2 8
A U D
P A 2
6
2 7
V S S A
P A 1
7
P A 0
8
1 9
2 0
2 1
2 2
2 3
2 4
N C
1 8
N C
1 7
N C
1 6
N C
1 5
R E S
1 4
IN T
1 3
V D D
1 2
V S S
1 1
P B 7
P B 2
P B 6
1 0
P B 5
P B 1
P B 4
9
P B 3
P B 0
2 6
O S C 2
2 5
O S C 1
Chip size: 1975´2640 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
6
March 12, 2010
HT86BXX/HT86BRXX
HT86BR30
(0 ,0 )
P A 7
1
P A 6
V S S P
3 2
P W M 2
2
3
P A 5
P A 4
4
P A 3
5
P A 2
P A 1
6
7
P A 0
P B 0
3 3
8
3 1
P W M 1
3 0
V D D P
2 9
V D D A
2 8
A U D
2 7
V S S A
9
1 9
2 0
2 1 2 2 2 3 2 4
V S S
V D D
IN T
R E S
N C
2 6
O S C 2
2 5
O S C 1
N C
1 8
N C
1 7
N C
1 5 1 6
P B 7
1 3 1 4
P B 5
1 2
P B 6
1 1
P B 4
1 0
P B 2
P B 3
P B 1
Chip size: 4280´4330 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
7
March 12, 2010
HT86BXX/HT86BRXX
HT86B20/HT86B30
(0 ,0 )
P A 1
7
P A 0
8
P B 0
9
P B 1
1 0
P B 2
1 1
1 5
1 6
1 7
1 8
1 9
2 0
2 1 2 2 2 3 2 4
P W M 2
3 1
P W M 1
3 0
V D D P
2 9
V D D A
2 8
A U D
2 7
V S S A
2 6
O S C 2
2 5
O S C 1
N C
1 4
V S S P
N C
1 3
N C
1 2
N C
6
R E S
P A 2
IN T
5
V D D
4
P A 3
V S S
P A 4
P B 7
3
P B 6
P A 5
P B 5
2
P B 4
1
P A 6
P B 3
P A 7
3 3
3 2
Chip size: 1975´3300 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
8
March 12, 2010
HT86BXX/HT86BRXX
HT86B40
(0 ,0 )
3 7
V S S P
3 6
P W M 2
3 5
P W M 1
3 4
V D D P
P A 7
1
P A 6
2
P A 5
3
P A 4
4
P A 3
5
3 3
V D D A
P A 2
6
3 2
A U D
P A 1
7
3 1
V S S A
P A 0
8
P B 0
9
P B 1
1 0
1 9
2 0
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
P D 4
P D 5
P D 6
P D 7
2 1
2 2
2 3
2 4
2 5 2 6 2 7 2 8
N C
1 8
N C
1 7
N C
1 6
N C
1 5
R E S
1 4
O S C 1
IN T
1 3
2 9
V D D
1 2
O S C 2
V S S
1 1
3 0
Chip size: 1975´3970 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
9
March 12, 2010
HT86BXX/HT86BRXX
HT86BR60
(0 ,0 )
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 0
P B 1
P B 2
1
3 7
V S S P
3 6
P W M 2
3 5
P W M 1
3 4
V D D P
3 3
V D D A
A U D
2
3
4
5
6
3 2
7
V S S A
3 1
8
9
3 0
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 9
2 5 2 6 2 7 2 8
O S C 2
O S C 1
N C
N C
N C
N C
R E S
IN T
V D D
V S S
P D 7
P D 6
P D 5
P D 4
P B 7
P B 6
P B 5
P B 4
P B 3
Chip size: 4290´8835 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
10
March 12, 2010
HT86BXX/HT86BRXX
HT86B50/HT86B60
(0 ,0 )
3 7
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 0
P B 1
1
2
3
4
3 6
V S S P
P W M 2
3 5
P W M 1
3 4
V D D P
3 3
3 2
3 1
V D D A
A U D
V S S A
5
6
7
8
3 0
2 9
9
1 0
N C
N C
R E
IN T
V D
V S
P D
P D
P D
P D
P B
P B
P B
P B
P B
P B
N C
2 5 2 6 2 7 2 8
N C
1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
O S C 2
O S C 1
S
7
6
5
4
3
2
7
6
5
4
S
D
Chip size: 1975´5725 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
11
March 12, 2010
HT86BXX/HT86BRXX
HT86B70/HT86B80
(0 ,0 )
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 0
P B 1
P B 2
4 1
V S S P
2
4 0
P W M 2
4
3 9
P W M 1
5
3 8
V D D P
V D D A
A U D
V S S A
1
3
6
3 7
3 6
7
8
9
1 0
1 1
3 5
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8
2 9 3 0 3 1 3 2
3 4
3 3
O S C 2
O S C 1
N C
N C
N C
N C
R E S
IN T
V D D
V S S
P D 7
P D 6
P D 5
P D 3
P D 2
P D 1
P D 0
P D 4
P B 7
P B 6
P B 5
P B 4
P B 3
Chip size: 3615´4940 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
12
March 12, 2010
HT86BXX/HT86BRXX
HT86B90
(0 ,0 )
1
4 1
V S S P
2
4 0
P W M 2
4
3 9
P W M 1
3 8
V D D P
V D D A
A U D
O S C 2
3
5
6
3 7
3 6
7
8
1 1
3 5
3 4
3 3
V S S A
O S C 1
N C
N C
N C
2 9 3 0 3 1 3 2
R E S
IN T
V D D
V S S
P D 7
P D 6
P D 5
P D 3
P D 2
P D 1
P D 0
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8
N C
9
1 0
P D 4
P B 7
P B 6
P B 5
P B 4
P B 3
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
P B 0
P B 1
P B 2
Chip size: 3620´6700 (mm)2
* The IC substrate should be connected to VSS in the PCB layout artwork.
Rev. 1.80
13
March 12, 2010
HT86BXX/HT86BRXX
Pad Coordinates
Unit: mm
HT86B03
Pad No.
X
Y
Pad No.
X
Y
1
-879.400
-236.700
14
-784.400
-236.700
15
-46.350
51.150
-816.900
2
3
-839.400
-428.200
16
154.150
-816.900
4
-839.400
-523.200
17
294.450
-833.650
5
-839.400
-626.200
18
368.450
-833.650
6
-839.400
-721.200
19
442.450
-833.650
7
-839.400
-824.200
20
516.450
-833.650
8
-632.350
-816.900
21
839.390
-592.550
9
-537.350
-816.900
22
839.390
-488.250
10
-434.350
-816.900
23
839.390
-321.808
11
-339.350
-816.900
24
839.390
-218.358
12
-236.350
-816.900
25
737.790
-116.308
13
-141.350
-816.900
-816.900
Unit: mm
HT86BR10
Pad No.
X
Y
Pad No.
X
Y
1
-1483.900
1900.000
18
-779.500
-1856.400
2
-1483.900
-838.050
19
-682.500
-1856.400
3
-1483.900
-933.050
20
-521.245
-1860.845
4
-1483.900
-1036.050
21
-447.245
-1860.845
5
-1483.900
-1131.050
22
-373.245
-1860.845
6
-1483.900
-1234.050
23
-1860.845
7
-1483.900
-1329.050
24
-299.245
1478.900
8
-1483.900
-1432.050
25
1478.900
-1700.550
9
-1483.900
-1527.050
26
1478.900
-1605.550
10
-1483.900
-1630.050
27
1442.800
-1497.530
11
-1474.850
-1856.400
28
1442.800
-1395.130
12
-1379.850
-1856.400
29
1442.800
-1295.470
13
-1276.850
-1856.400
30
1439.405
-1162.343
14
-1181.850
-1856.400
31
1442.395
-1024.550
15
-1078.850
-1856.400
32
1442.395
-814.050
16
-983.850
-1856.400
33
1442.395
17
-881.645
-1856.400
34
1468.400
-683.200
1879.850
Rev. 1.80
14
-1821.650
March 12, 2010
HT86BXX/HT86BRXX
Unit: mm
HT86B10
Pad No.
X
Y
Pad No.
X
Y
1
-839.400
-189.100
18
-839.400
-284.100
19
-45.150
50.850
-1171.900
2
3
-839.400
-387.100
20
153.850
-1171.900
4
-839.400
-482.100
21
294.450
-1188.650
5
-839.400
-585.100
22
368.450
-1188.650
6
-839.400
-680.100
23
442.450
-1188.650
7
-839.400
-783.100
24
516.450
-1188.650
8
-839.400
-878.100
25
838.940
-945.650
9
-839.400
-981.100
26
838.940
-843.250
10
-839.400
-1076.100
27
802.900
-704.400
11
-839.400
-1179.100
28
802.900
-601.500
12
-632.150
-1171.900
29
802.900
-504.300
13
-537.150
-1171.900
30
792.250
-351.400
14
-434.150
-1171.900
31
803.900
-218.050
15
-339.150
-1171.900
32
803.900
16
-236.150
-1171.900
33
803.900
-7.550
112.000
17
-141.150
-1171.900
-1171.900
Unit: mm
HT86BR30
Pad No.
X
Y
Pad No.
X
Y
1
-1991.400
-1030.120
18
-1152.895
-2016.400
2
-1991.400
-1133.120
19
-1055.695
-2016.400
3
-1991.400
-1228.120
20
-913.745
-2016.400
4
-1991.400
-1331.120
21
-709.506
-2015.810
5
-1991.400
-1426.120
22
-635.506
-2015.810
6
-1991.400
-1529.120
23
-561.506
-2015.810
7
-1991.400
-1624.120
24
-2015.810
8
-1991.400
-1727.120
25
-487.506
1984.750
9
-1991.400
-1822.120
26
1984.750
-1921.500
10
-1991.400
-1925.120
27
1941.835
-1711.230
11
-1991.400
-2020.120
28
1941.835
-1586.960
12
-1771.750
-2016.400
29
1941.835
-1487.300
13
-1668.750
-2016.400
30
1946.850
-1363.920
14
-1573.750
-2016.400
31
1946.850
-1233.070
15
-1470.750
-2016.400
32
1946.850
-1022.570
16
-1375.750
-2016.400
33
1946.850
-891.720
17
-1251.695
-2016.780
Rev. 1.80
15
-2016.500
March 12, 2010
HT86BXX/HT86BRXX
Unit: mm
HT86B20/HT86B30
Pad No.
X
Y
Pad No.
X
Y
1
-839.400
-519.100
18
-839.400
-614.100
19
-45.150
50.850
-1501.900
2
3
-839.400
-717.100
20
153.850
-1501.900
4
-839.400
-812.100
21
294.450
-1518.650
5
-839.400
-915.100
22
368.450
-1518.650
6
-839.400
-1010.100
23
442.450
-1518.650
7
-839.400
-1113.100
24
516.450
-1518.650
8
-839.400
-1208.100
25
838.940
-1275.650
9
-839.400
-1311.100
26
838.940
-1173.250
10
-839.400
-1406.100
27
802.900
-1034.400
-931.500
-1501.900
11
-839.400
-1509.100
28
802.900
12
-632.150
-1501.900
29
802.900
-834.300
13
-537.150
-1501.900
30
792.250
-681.400
14
-434.150
-1501.900
31
803.900
-548.050
15
-339.150
-1501.900
32
803.900
-337.550
16
-236.150
-1501.900
33
803.900
-218.000
17
-141.150
-1501.900
Unit: mm
HT86B40
Pad No.
X
Y
Pad No.
X
Y
1
-839.400
-701.930
20
44.500
-1836.900
2
-839.400
-804.930
21
149.650
-1836.900
3
-839.400
-899.930
22
255.250
-1836.900
4
-839.400
-1002.930
23
359.150
-1836.900
5
-839.400
-1097.930
24
462.150
-1836.900
6
-839.400
-1200.930
25
619.850
-1853.600
7
-839.400
-1295.930
26
693.850
-1853.600
8
-839.400
-1398.930
27
767.850
-1853.600
9
-839.400
-1493.930
28
841.850
-1853.600
10
-839.400
-1596.930
29
839.390
-1551.700
11
-848.700
-1836.900
30
839.390
-1449.300
12
-745.700
-1836.900
31
802.900
-1311.300
13
-650.700
-1836.900
32
802.900
-1207.800
14
-547.700
-1836.900
33
802.900
-1103.500
15
-452.700
-1836.900
34
792.350
-959.450
16
-349.700
-1836.900
35
803.900
-829.350
17
-254.700
-1836.900
36
803.900
-618.850
18
-153.500
-1836.900
37
803.900
-499.300
19
-50.500
-1836.900
Rev. 1.80
16
March 12, 2010
HT86BXX/HT86BRXX
Unit: mm
HT86BR60
Pad No.
X
Y
Pad No.
X
Y
1
-1996.400
-3279.080
20
954.350
-4269.280
2
-1996.400
-3382.080
21
853.150
-4269.280
3
-1996.400
-3477.080
22
753.150
-4268.900
4
-1996.400
-3580.080
23
657.150
-4268.900
5
-1996.400
-3675.080
24
515.200
-4268.900
6
-1996.400
-3778.080
25
345.100
-4268.850
7
-1996.400
-3873.080
26
271.100
-4268.850
8
-1996.400
-3976.080
27
197.100
-4268.850
9
-1996.400
-4074.580
28
123.100
-4268.850
10
-1996.400
-4177.580
29
1991.750
-4269.000
11
-1996.400
-4272.580
30
1991.750
-4174.000
12
-1750.825
-4269.280
31
1948.850
-3963.730
13
-1655.825
-4269.280
32
1948.850
-3839.460
14
-1552.825
-4269.280
33
1948.850
-3739.800
15
-1457.825
-4269.280
34
1953.850
-3616.420
16
-1354.825
-4269.280
35
1953.850
-3485.570
17
-1259.825
-4269.280
36
1953.850
-3275.070
18
-1152.350
-4269.280
37
1953.850
-3144.220
19
-1049.350
-4269.280
Unit: mm
HT86B50/HT86B60
Pad No.
X
Y
Pad No.
X
Y
1
-839.400
-1579.430
20
44.600
-2714.400
2
-839.400
-1682.430
21
149.650
-2714.400
3
-839.400
-1777.430
22
255.250
-2714.400
4
-839.400
-1880.430
23
359.150
-2714.400
5
-839.400
-1975.430
24
462.150
-2714.400
6
-839.400
-2078.430
25
619.850
-2731.100
7
-839.400
-2173.430
26
693.850
-2731.100
8
-839.400
-2276.430
27
767.850
-2731.100
9
-839.400
-2371.430
28
841.850
-2731.100
10
-839.400
-2474.430
29
839.390
-2427.100
11
-848.700
-2714.400
30
839.390
-2326.800
12
-745.700
-2714.400
31
802.900
-2188.800
13
-650.700
-2714.400
32
802.900
-2085.300
14
-547.700
-2714.400
33
802.900
-1981.000
15
-452.700
-2714.400
34
792.350
-1836.950
16
-349.700
-2714.400
35
803.900
-1706.850
17
-254.700
-2714.400
36
803.900
-1496.350
18
-153.400
-2714.400
37
803.900
-1376.800
19
-50.400
-2714.400
Rev. 1.80
17
March 12, 2010
HT86BXX/HT86BRXX
Unit: mm
HT86B70/HT86B80
Pad No.
X
Y
Pad No.
X
Y
1
-1659.400
-1342.900
22
-431.055
-2321.900
2
-1659.400
-1437.900
23
-328.055
-2321.900
3
-1659.400
-1540.900
24
-233.055
-2321.900
4
-1659.400
-1635.900
25
-130.855
-2321.900
5
-1659.400
-1738.900
26
-2321.900
6
-1659.400
-1833.900
27
-32.865
67.140
7
-1659.400
-1936.900
28
170.140
-2321.900
8
-1659.400
-2031.900
29
332.095
-2327.150
9
-1659.400
-2134.900
30
406.095
-2327.150
10
-1659.400
-2229.900
31
480.095
-2327.150
11
-1659.400
-2332.900
32
554.095
-2327.150
12
-1419.255
-2321.900
33
1658.950
-2324.995
13
-1324.255
-2321.900
34
1658.950
-2229.995
14
-1221.255
-2321.900
35
1576.095
-2087.795
15
-1126.255
-2321.900
36
1495.595
-1979.695
16
-1023.255
-2321.900
37
1495.595
-1869.845
17
-928.255
-2321.900
38
1623.910
-1774.245
18
-825.255
-2321.900
39
1623.910
-1640.895
19
-730.255
-2321.900
40
1623.910
-1430.395
20
-627.255
-2321.900
41
1623.910
-1310.845
21
-532.255
-2321.900
-2321.900
Unit: mm
HT86B90
Pad No.
X
Y
Pad No.
X
Y
1
-1661.900
-2222.900
22
-433.555
-3201.900
2
-1661.900
-2317.900
23
-330.555
-3201.900
3
-1661.900
-2420.900
24
-235.555
-3201.900
4
-1661.900
-2515.900
25
-133.355
-3201.900
5
-1661.900
-2618.900
26
-3201.900
6
-1661.900
-2713.900
27
-35.365
64.640
7
-1661.900
-2816.900
28
167.640
-3201.900
8
-1661.900
-2911.900
29
329.595
-3207.150
9
-1661.900
-3014.900
30
403.595
-3207.150
10
-1661.900
-3109.900
31
477.595
-3207.150
11
-1661.900
-3212.900
32
551.595
-3207.150
12
-1421.755
-3201.900
33
1656.900
-3204.995
13
-1326.755
-3201.900
34
1493.095
-2859.695
14
-1223.755
-3201.900
35
1573.595
-2967.795
15
-1128.755
-3201.900
36
1656.900
-3109.995
16
-1025.755
-3201.900
37
1493.095
-2749.845
17
-930.755
-3201.900
38
1621.410
-2654.245
18
-827.755
-3201.900
39
1621.410
-2520.895
19
-732.755
-3201.900
40
1621.410
-2310.395
20
-629.755
-3201.900
41
1621.410
-2190.845
21
-534.755
-3201.900
Rev. 1.80
18
-3201.900
March 12, 2010
HT86BXX/HT86BRXX
Pin Description
HT86B03/HT86B10/HT86B20/HT86B30/HT86BR10/HT86BR30
Pad Name
I/O
Options
Description
PA0~PA7
I/O
Wake-up,
Pull-high
or None
Bidirectional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option).
PB0~PB7
I/O
Pull-high
or None
Bidirectional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option). The
HT86B03 device only has PB4~PB7 port pins.
AUD
O
¾
Audio output for driving an external transistor or for driving HT82V733
PWM1
PWM2
O
¾
Audio PWM outputs.
The HT86B03 has no PWM outputs.
RES
I
¾
Schmitt trigger reset input. Active low.
I
External interrupt Schmitt trigger input without pull-high resistor. A configuraFalling Edge
tion option determines if the interrupt active edge is a falling edge only or both
Trigger or
a falling and rising edge. Falling edge triggered active on a high to low transiFalling/Rising
tion. Rising edge triggered active on a low to high transition. Input voltage is
Edge Trigger
the same as operating voltage.
OSC1
OSC2
¾
OSC1, OSC2 are connected to an external RC network or external crystal,
determined by configuration option, for the internal system clock. If the RC
Crystal or RC
system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.
VDD
¾
¾
Positive digital power supply
VSS
¾
¾
Negative digital power supply, ground.
VDDA
¾
¾
Positive DAC circuit power supply
VSSA
¾
¾
Negative DAC circuit power supply, ground.
VDDP
¾
¾
Positive audio PWM circuit power supply
VSSP
¾
¾
Negative audio PWM circuit power supply, ground.
INT
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have pull-high resistors.
Rev. 1.80
19
March 12, 2010
HT86BXX/HT86BRXX
HT86B40/HT86B50/HT86B60/HT86BR60
Pad Name
I/O
Options
Description
PA0~PA7
I/O
Wake-up,
Pull-high
or None
Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option).
PB0~PB7/
K0~K7
I/O
Pull-high
or None
Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option).
Pins PB0~PB7 are pin-shared with C/R-F input pins K0~K7.
Bi-directional 4-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option).
Pins PD4~PD7 are pin-shared with R/F OSC input pins RR, RC and CC.
RCOUT: Capacitor or resistor connection pin to RC OSC for input.
RR: Oscillation input pin
RC: Reference resistor connection pin for output
CC: Reference capacitor connection pin for output
PD4/RCOUT
PD5/RR
PD6/RC
PD7/CC
I/O
Pull-high
or None
AUD
O
¾
Audio output for driving an external transistor or for driving HT82V733
PWM1
PWM2
O
¾
Audio PWM outputs
RES
I
¾
Schmitt trigger reset input. Active low.
I
INT
External interrupt Schmitt trigger input without pull-high resistor. A configuraFalling Edge
tion option determines if the interrupt active edge is a falling edge only or both
Trigger or
a falling and rising edge. Falling edge triggered active on a high to low transiFalling/Rising
tion. Rising edge triggered active on a low to high transition. Input voltage is
Edge Trigger
the same as operating voltage.
OSC1, OSC2 are connected to an external RC network or external crystal,
determined by configuration option, for the internal system clock. If the RC
system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.
OSC1
OSC2
¾
Crystal or RC
VDD
¾
¾
Positive digital power supply
VSS
¾
¾
Negative digital power supply, ground.
VDDA
¾
¾
Positive DAC circuit power supply
VSSA
¾
¾
Negative DAC circuit power supply, ground.
VDDP
¾
¾
Positive audio PWM circuit power supply
VSSP
¾
¾
Negative audio PWM circuit power supply, ground.
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have pull-high resistors.
Rev. 1.80
20
March 12, 2010
HT86BXX/HT86BRXX
HT86B70/HT86B80/HT86B90
Pad Name
I/O
Options
Description
PA0~PA7
I/O
Wake-up,
Pull-high
or None
Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option).
PB0~PB7/
K0~K7
I/O
Pull-high
or None
Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option).
Pins PB0~PB7 are pin-shared with C/R-F input pins K0~K7.
Bi-directional 8-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by option).
Pins PD4~PD7 are pin-shared with R/F OSC input pins RR, RC and CC.
RCOUT: Capacitor or resistor connection pin to RC OSC for input.
RR: Oscillation input pin
RC: Reference resistor connection pin for output
CC: Reference capacitor connection pin for output
PD0~PD3
PD4/RCOUT
PD5/RR
PD6/RC
PD7/CC
I/O
Pull-high
or None
AUD
O
¾
Audio output for driving an external transistor or for driving HT82V733
PWM1
PWM2
O
¾
Audio PWM outputs
RES
I
¾
Schmitt trigger reset input. Active low.
I
INT
External interrupt Schmitt trigger input without pull-high resistor. A configuraFalling Edge
tion option determines if the interrupt active edge is a falling edge only or both
Trigger or
a falling and rising edge. Falling edge triggered active on a high to low transiFalling/Rising
tion. Rising edge triggered active on a low to high transition. Input voltage is
Edge Trigger
the same as operating voltage.
OSC1, OSC2 are connected to an external RC network or external crystal,
determined by configuration option, for the internal system clock. If the RC
system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.
OSC1
OSC2
¾
Crystal or RC
VDD
¾
¾
Positive digital power supply
VSS
¾
¾
Negative digital power supply, ground.
VDDA
¾
¾
Positive DAC circuit power supply
VSSA
¾
¾
Negative DAC circuit power supply, ground.
VDDP
¾
¾
Positive audio PWM circuit power supply
VSSP
¾
¾
Negative audio PWM circuit power supply, ground.
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have pull-high resistors.
Absolute Maximum Ratings
Supply Voltage ...........................VSS+2.2V to VSS+5.5V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.80
21
March 12, 2010
HT86BXX/HT86BRXX
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
VDD
Operating Voltage
¾
3V
IDD
5V
5V
3V
Standby Current (WDT Off)
5V
ISTB2
Typ.
Max.
Unit
fSYS=4MHz/8MHz
2.2
¾
5.5
V
fSYS=4MHz
for HT86B90 only
2.2
¾
5.5
V
fSYS=8MHz
for HT86B90 only
3.3
¾
5.5
V
¾
¾
1.5
mA
¾
¾
5
mA
¾
¾
3
mA
¾
¾
7
mA
¾
¾
1
mA
¾
¾
2
mA
¾
¾
7
mA
¾
¾
10
mA
No load, fSYS=4MHz,
DAC/PWM disable
Operating Current
3V
ISTB1
Min.
Conditions
3V
No load, fSYS=8MHz,
DAC/PWM disable
No load, system HALT
WDT disable
5V
No load, system HALT
WDT enable
Standby Current (WDT On)
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VIL3
Input Low Voltage for EXT INT
¾
¾
0
¾
0.3VDD
V
VIH3
Input High Voltage for EXT INT
¾
¾
0.7VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
2.1
2.2
2.3
V
IOL1
4
¾
¾
mA
I/O Port Sink Current
10
¾
¾
mA
-2
¾
¾
mA
-5
¾
¾
mA
4
¾
¾
mA
10
¾
¾
mA
-2
¾
¾
mA
-5
¾
¾
mA
50
¾
¾
mA
80
¾
¾
mA
-14.5
¾
¾
mA
-26
¾
¾
mA
-1.5
¾
¾
mA
-3
¾
¾
mA
20
60
100
kW
10
30
50
kW
3V
LVR 2.2V option
VOL=0.1VDD
5V
IOH1
3V
I/O Port Source Current
VOH=0.9VDD
5V
IOL2
3V
RC and CC Sink Current
VOL=0.1VDD
5V
IOH2
3V
RC and CC Source Current
VOH=0.9VDD
5V
IOL3
3V
PWM1/PWM2 Sink Current
VOL=0.1VDD
5V
IOH3
3V
PWM1/PWM2 Source Current
VOH=0.9VDD
5V
IAUD
3V
AUD Source Current
VOH=0.9VDD
5V
RPH
3V
¾
Pull-high Resistance
5V
Rev. 1.80
22
March 12, 2010
HT86BXX/HT86BRXX
A.C. Characteristics
Symbol
Ta=25°C
Test Conditions
Parameter
Conditions
VDD
fSYS
System Clock
(RC OSC, Crystal OSC)
tWDTOSC
Watchdog Oscillator Period
tRES
¾
Min.
Typ.
Max.
Unit
4
¾
8
MHz
2.2V~5.5V
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
*tSYS
tLVR
Low Voltage Reset Time
¾
¾
2
¾
¾
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tMAT
Circumscribe Memory Access
¾
Time
¾
¾
400
ns
Wake-up from HALT
2.2V~5.5V
Note: *tSYS=1/fSYS
Characteristics Curves
HT86BRxx
· R vs. F Chart Characteristics Curves
R v s . F C h a rt
1 0
F re q u e n c y (M H z )
8
3 .0 V
4 .5 V
6
4
2
1 5 0
2 8 5
1 9 5
R
3 7 6
4 4 5
(k W )
· T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .0 6
1 .0 4
V
S C
(2 5 ° C )
0 .9 8
V
D D
= 3 V
-6 0
-4 0
D D
= 5 V
= 5 V
V
0 .9 6
0 .9 4
D D
V
fO
fO
1 .0 0
S C
1 .0 2
-2 0
D D
= 3 V
0
2 0
4 0
6 0
8 0
1 0 0
T (° C )
Rev. 1.80
23
March 12, 2010
HT86BXX/HT86BRXX
· V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
1 0
8 M H z /1 5 0 k W
F re q u e n c y (M H z )
8
6 M H z /1 9 5 k W
6
4 M H z /2 8 5 k W
4
2
2 .2
2 .6
3 .3
3 .0
3 .8
4 .5
4 .2
V
D D
4 .9
5 .2
5 .5
4 .9
5 .2
5 .5
(V )
· V vs. F Chart Characteristics Curves - 4.5V
V v s . F C h a r t (F o r 4 .5 V )
1 0
8 M H z /1 4 5 k W
F re q u e n c y (M H z )
8
6 M H z /1 9 0 k W
6
4 M H z /2 7 4 k W
4
2
2 .2
2 .6
3 .0
3 .3
3 .8
4 .2
V
D D
4 .5
(V )
HT86Bxx
· R vs. F Chart Characteristics Curves
F re q u e n c y (M H z )
R v s . F C h a rt
8
6
3 .0 V
4
4 .5 V
2
6 8
8 8
1 2 7
R
Rev. 1.80
24
1 6 6
2 0 0
(k W )
March 12, 2010
HT86BXX/HT86BRXX
· T vs. F Chart Characteristics Curves
T v s . F C h a rt
1 .0 4
V
1 .0 2
S C
(2 5 ° C )
0 .9 6
V
V
fO
fO
0 .9 8
S C
1 .0 0
0 .9 4
0 .9 2
-6 0
-4 0
D D
D D
V
= 5 V
D D
D D
= 5 V
= 3 V
= 3 V
-2 0
0
2 0
4 0
6 0
8 0
1 0 0
T (° C )
· V vs. F Chart Characteristics Curves - 3.0V
V v s . F C h a r t (F o r 3 .0 V )
8 M H z /6 7 k W
F re q u e n c y (M H z )
8
6 M H z /8 6 k W
6
4 M H z /1 2 5 k W
4
2
2 .2
2 .6
3 .3
3 .0
3 .8
4 .2
V
D D
4 .5
4 .9
5 .2
5 .5
4 .9
5 .2
5 .5
(V )
· V vs. F Chart Characteristics Curves - 4.5V
V v s . F C h a r t (F o r 4 .5 V )
8 M H z /6 8 k W
F re q u e n c y (M H z )
8
6 M H z /8 8 k W
6
4 M H z /1 2 7 k W
2
4
2 .2
2 .6
3 .0
3 .3
3 .8
4 .2
V
Rev. 1.80
25
D D
4 .5
(V )
March 12, 2010
HT86BXX/HT86BRXX
System Architecture
nally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
A key factor in the high-performance features of the
Holtek range of Voice microcontrollers is attributed to
the internal system architecture. The range of devices
take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O, voltage type DAC,
PWM direct drive output, capacitor/resistor sensor input
and external RC oscillator converter with maximum reliability and flexibility.
When the RC oscillator is used, OSC2 is freed for use as
a T1 phase clock synchronizing pin. This T1 phase clock
has a frequency of fSYS/4 with a 1:3 high/low duty cycle.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
Clocking and Pipelining
The main system clock, derived from either a Crystal/
Resonator or RC oscillator is subdivided into four interO s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.80
26
March 12, 2010
HT86BXX/HT86BRXX
Program Counter
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL², that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 8 levels and is neither part of the data nor part
of the program space, and is neither readable nor
writable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writable. At a
subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled by a return instruction, ²RET² or ²RETI², the Program Counter is restored to its previous value from the
stack. After a device reset, the Stack Pointer will point to
the top of the stack.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
P ro g ra m
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be inserted.
C o u n te r
S ta c k L e v e l 1
T o p o f S ta c k
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
P ro g ra m
M e m o ry
S ta c k L e v e l 3
o f S ta c k
S ta c k L e v e l 8
Program Counter
Mode
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
0
1
0
0
Timer 0 Overflow
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer 1 Overflow
0
0
0
0
0
0
0
0
0
1
1
0
0
Timer 2 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
0
Timer 3 Overflow
0
0
0
0
0
0
0
0
1
0
1
0
0
Skip
Program Counter + 2
Loading PCL
*12
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#12
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*12~*0: Program counter bits
S12~S0: Stack register bits
#12~#0: Instruction code bits
@7~@0: PCL bits
The program counter in the HT86B03 is only 12-bits wide therefore the *12 column in the table is not
applicable.
Rev. 1.80
27
March 12, 2010
HT86BXX/HT86BRXX
· Location 000H
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated,
the program will jump to this location and begin execution.
· Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
full.
· Location 008H
Arithmetic and Logic Unit - ALU
This internal vector is used by the 8-bit Timer 0. If a
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
· Location 00CH
This internal vector is used by the 8-bit Timer1. If a
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
· Location 010H
For the HT86B40, HT86B50, HT86B50, HT86B60,
HT86BR60, HT86B70, HT86B80, HT86B90 devices,
this internal vector is used by the 16-bit Timer2. If a
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
· Arithmetic operations ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
· Logic operations AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Location 014H
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
This internal vector is used by the 8-bit Timer3. If a
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
RLC
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
SDZA, CALL, RET, RETI
Program Memory
0 0 0 H
The Program Memory is the location where the user
code or program is stored. By using the appropriate programming tools, this Program memory device offer users the flexibility to conveniently debug and develop
their applications while also offering a means of field
programming.
0 0 4 H
0 0 8 H
0 0 C H
H T
H T 8 6 B 1 0 /H T 8 6 B R 1 0 H T
H T 8 6 B 2 0 /H T 8 6 B 3 0
H T
H T 8 6 B R 3 0
H T
H T 8 6 B 0 3
0 1 4 H
The program memory stores the program instructions
that are to be executed. It also includes data, table and
interrupt entries, addressed by the Program Counter
along with the table pointer. The program memory size
is 8192´16 bits. Certain locations in the program memory are reserved for special usage.
4 0 /H T 8 6 B 5 0
6 0 /H T 8 6 B R 6 0
7 0 /H T 8 6 B 8 0
9 0
In itia lis a tio n
V e c to r
In itia lis a tio n
V e c to r
In itia lis a tio n
V e c to r
E x te rn a l
In te rru p t V e c to r
E x te rn a l
In te rru p t V e c to r
E x te rn a l
In te rru p t V e c to r
T im e r 0
In te rru p t V e c to r
T im e r 0
In te rru p t V e c to r
T im e r 0
In te rru p t V e c to r
T im e r 1
In te rru p t V e c to r
T im e r 1
In te rru p t V e c to r
T im e r 1
In te rru p t V e c to r
0 1 0 H
Organization
8 6 B
8 6 B
8 6 B
8 6 B
T im e r 2
In te rru p t V e c to r
T im e r 3
In te rru p t V e c to r
T im e r 3
In te rru p t V e c to r
T im e r 3
In te rru p t V e c to r
1 6 b its
1 6 b its
0 1 5 H
F F F H
1 6 b its
1 F F F H
Program Memory Structure
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
Rev. 1.80
28
March 12, 2010
HT86BXX/HT86BRXX
Look-up Table
The following diagram illustrates the addressing/data
flow of the look-up table for the devices:
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, table pointers are used to
setup the address of the data that is to be accessed from
the Program Memory. However, as some devices possess only a low byte table pointer and other devices possess both a high and low byte pointer it should be noted
that depending upon which device is used, accessing
look-up table data is implemented in slightly different
ways.
T B H P
T B L H
H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ]
L o w
B y te o f T a b le C o n te n ts
Look-up Table
For the devices, there are two Table Pointer Registers
known as TBLP and TBHP in which the lower order and
higher order address of the look-up data to be retrieved
must be respectively first written. Unlike the other devices in which only the low address byte is defined using
the TBLP register, the additional TBHP register allows
the complete address of the look-up table to be defined
and consequently allow table data from any address
and any page to be directly accessed. For these devices, after setting up both the low and high byte table
pointers, the table data can then be retrieved from any
area of Program Memory using the ²TABRDC [m]² instruction or from the last page of the Program Memory
using the ²TABRDL [m]² instruction. When either of
these instructions are executed, the lower order table
byte from the Program Memory will be transferred to the
user defined Data Memory register [m] as specified in
the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
?
?
P ro g ra m
M e m o ry
T B L P
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the devices.
This example uses raw table data located in the last
page which is stored there using the ORG statement.
The value at this ORG statement is ²1F00H² which refers to the start address of the last page within the Program Memory of the microcontroller. The table pointer is
setup here to have an initial value of ²06H². This will ensure that the first data read from the data table will be at
the Program Memory address ²1F06H² or 6 locations
after the start of the last page. Note that the value for the
table pointer is referenced to the first address of the
present page if the ²TABRDC [m]² instruction is being
used. The high byte of the table data which in this case
is equal to zero will be transferred to the TBLH register
automatically when the ²TABRDL [m]² instruction is executed.
tempreg1
tempreg2
db
db
:
:
; temporary register #1
; temporary register #2
mov
a,06h
; initialise table pointer - note that this address
; is referenced
mov
tblp,a
:
:
; to the last page or present page
tabrdl
tempreg1
;
;
;
;
dec
tblp
; reduce value of table pointer by one
tabrdl
tempreg2
;
;
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²1F06H² transferred to
tempreg1 and TBLH
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²1F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte
register TBLH
:
:
org
1F00h
dc
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.80
; sets initial address of HT86B60 last page
29
March 12, 2010
HT86BXX/HT86BRXX
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
Instruction
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*12~*0: Current Program ROM table
P12~P8: Write P12~P8 to TBHP pointer register
@7~@0: Write @7~@0 to TBLP pointer register
For the HT86B03, the table address location is 12-bits, that is from bit 0 to bit 11.
Data Memory
cated in Bank 0 which is also subdivided into two sections, the Special Purpose Data Memory and the
General Purpose Data Memory. The length of these
sections is dictated by the type of microcontroller chosen. The start address of the RAM Data Memory for all
devices is the address ²00H², and the last Data Memory
address is ²FFH². Registers which are common to all
microcontrollers, such as ACC, PCL, etc., have the
same Data Memory address.
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to directly under program control, however, some remain
protected from user manipulation. The second area of
RAM Data Memory is reserved for general purpose use.
All locations within this area are read and write accessible under program control.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
Organization
The Data Memory is subdivided into two banks, known
as Bank 0 and Bank 1, all of which are implemented in
8-bit wide RAM. Most of the RAM Data Memory is loH T 8
H T 8
H T 8
H T 8
0 0 H
2 D H
6 B 0
6 B 1
6 B 2
6 B R
3
H T 8
H T 8
H T 8
H T 8
0 /H T 8 6 B R 1 0
0 /H T 8 6 B 3 0
3 0
S p e c ia l P u r p o s e
D a ta M e m o ry
6 B 4
6 B 6
6 B 7
6 B 9
0 /H T 8 6 B 5 0
0 /H T 8 6 B R 6 0
0 /H T 8 6 B 8 0
0
0 0 H
S p e c ia l P u r p o s e
D a ta M e m o ry
B a n k 1
M e m o ry
3 9 H
4 0 H
4 0 H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
F F H
F F H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 9 2 B y te s )
B a n k 0
B a n k 1
4 0 H
F F H
: U n k n o w n
RAM Data Memory Structure - Bank 0, Bank1
Note: Most of the RAM Data Memory bits can be directly manipulated using the ²SET [m].i² and ²CLR [m].i² instructions with the exception of a few dedicated bits. The RAM Data Memory can also be accessed through the
Memory Pointer registers MP0 and MP1.
Rev. 1.80
30
March 12, 2010
HT86BXX/HT86BRXX
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
Special Purpose Data Memory
This area of Data Memory, is located in Bank 0, where
registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are
both readable and writable but some are protected and
are readable only, the details of which are located under
the relevant Special Function Register section. Note
that for locations that are unused, any read instruction to
these addresses will return the value ²00H². Although
the Special Purpose Data Memory registers are located
in Bank 0, they will still be accessible even if the Bank
Pointer has selected Bank 1.
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the RAM
Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts,
watchdog, etc., as well as external functions such as I/O
data control. The location of these registers within the
RAM Data Memory begins at the address ²00H². Any
unused Data Memory locations between these special
function registers and the point where the General Purpose Memory begins is reserved for future expansion
purposes, attempting to read data from these locations
will return a value of ²00H².
Indirect Addressing Register - IAR0, IAR1
B 0 3
R 0
P 0
R 1
P 1
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
P A C
P B
P B C
L A
L A
L A
L A
L A
L A
T C
T C
T C
T C
T C
T C
IN T
T B
H 0
H 0
H 0
H 1
H 1
H 1
C H
H P
T M R 3
T M R 3 C
V O IC E C
D A L
D A H
V O L
L A T C H D
H
M
M
L
H
L
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
6 B 1
6 B R
6 B 2
6 B 3
6 B R
IA R 0
M P 0
IA R 1
M P 1
0
1 0
0
0
3 0
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
P A C
P B
P B C
L A
L A
L A
L A
L A
L A
T C
T C
T C
T C
T C
T C
IN T
T B
H 0
H 0
H 0
H 1
H 1
H 1
C H
H P
T M R 3
T M R 3 C
V O IC E C
D A L
D A H
V O L
L A T C H D
P W M C
P W M L
P W M H
H
M
M
L
H
L
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
2 2 H
2 3 H
2 4 H
2 5 H
2 6 H
2 7 H
2 8 H
2 9 H
2 A H
2 B H
2 C H
2 D H
6 B 4 0
6 B 5 0
6 B 6 0
6 B R 6 0
6 B 7 0
6 B 8 0
6 B 9 0
R 0
P 0
R 1
P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
2 E
2 F
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
H
6 B 4
6 B 5
6 B 6
6 B R
6 B 7
6 B 8
6 B 9
P D
P D C
H
H
0
0
0
0
6 0
0
0
H
H
H
H
H
H
H
H
H
R C
T
T
R
A S
O
M
M
C
C R
C C R
R 4 H
R 4 L
O C R
T M R 0
T M R 0 C
T M R 1
T M R 1 C
P A
P A C
P B
P B C
L A
L A
L A
L A
L A
L A
T C H 0
T C H 0
T C H 0
T C H 1
T C H 1
T C H 1
IN T C H
T B H P
T M R 2 H
T M R 2 L
T M R 2 C
T M R 3
T M R 3 C
V O IC E C
D A L
D A H
V O L
L A T C H D
P W M C
P W M L
P W M H
H
M
M
L
H
L
: U n k n o w n
Special Purpose Data Memory Structure
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect
Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indirectly will result in no operation.
Rev. 1.80
H T 8 6
IA
M
IA
M
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
H T 8
IA
M
IA
M
Memory Pointer - MP0, MP1
For all devices, two Memory Pointers, known as MP0
and MP1 are provided. These Memory Pointers are
physically implemented in the Data Memory and can be
manipulated in the same way as normal registers providing a convenient way with which to address and track
data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with
Indirect Addressing Register, IAR0, are used to access
data from Bank 0 only, while MP1 and IAR1 are used to
access data from both Bank 0 and Bank 1.
The following example shows how to clear a section of
four RAM locations already defined as locations adres1
to adres4.
31
March 12, 2010
HT86BXX/HT86BRXX
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block
db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
block,a
a,offset adres1
mp0,a
; setup size of block
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
; Accumulator loaded with first RAM address
; setup memory pointer with first RAM address
loop:
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Bank Pointer - BP
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
The RAM Data Memory is divided into two Banks,
known as Bank 0 and Bank 1. With the exception of the
BP register, all of the Special Purpose Registers and
General Purpose Registers are contained in Bank 0. If
data in Bank 0 is to be accessed, then the BP register
must be loaded with the value "00", while if data in Bank
1 is to be accessed, then the BP register must be loaded
with the value ²01².
Program Counter Low Register - PCL
Using Memory Pointer MP0 and Indirect Addressing
Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank Pointer.
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
The Data Memory is initialised to Bank 0 after a reset,
except for the WDT time-out reset in the Power Down
Mode, in which case, the Data Memory bank remains
unaffected. It should be noted that Special Function
Data Memory is not affected by the bank selection,
which means that the Special Function Registers can be
accessed from within either Bank 0 or Bank 1. Directly
addressing the Data Memory will always result in Bank 0
being accessed irrespective of the value of the Bank
Pointer.
Look-up Table Registers - TBLP, TBLH
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are executed. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
Accumulator - ACC
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
b 7
b 0
B P 0
B a n k P o in te r
B P 0
0
1
D a ta M e m o ry
B a n k 0
B a n k 1
N o t u s e d , m u s t b e re s e t to "0 "
Bank Pointer - BP
Rev. 1.80
32
March 12, 2010
HT86BXX/HT86BRXX
is also affected by a rotate through carry instruction.
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Watchdog Timer Register - WDTS
· Z is set if the result of an arithmetic or logical operation
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128.
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
Interrupt Control Register - INTC, INTCH
Two 8-bit register, known as the INTC and INTCH registers, controls the operation of both external and internal
timer interrupts. By setting various bits within these registers using standard bit manipulation instructions, the
enable/disable function of the external and timer interrupts can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global
enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt
routine is entered to disable further interrupt and is set
by executing the ²RETI² instruction.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Note: In situations where other interrupts may require
servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine
has been entered.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev. 1.80
33
March 12, 2010
HT86BXX/HT86BRXX
Timer Registers
Voice ROM Data Address Latch Counter Registers
Depending upon which device is selected, all devices
contain three or four integrated Timers of either 8-bit or
16-bit size. All devices contain three 8-bit Timers whose
associated registers are known as TMR0, TMR1 and
TMR3, which is the location where the associated
timer's 8-bit value is located. Their associated control
registers, known as TMR0C, TMR1C and TMR3C, contain the setup information for these timers. Some devices also contain an additional 16-bit timer whose
register pair name is known as TMR2L/TMR2H and is
the location where the timer's 16-bit value is located. An
associated control register, known as TMR2C, contains
the setup information for this timer. Note that all timer
registers can be directly written to in order to preload
their contents with fixed data to allow different time intervals to be setup.
These are the LATCH0H/LATCH0M/LATCH0L,
LATCH1H/LATCH1M/LATCH1L and the Voice ROM
data registers. The voice ROM data address latch count e r p r o vi d e s t h e h a n d sh a ki n g b e t w e e n t h e
microcontroller and the voice ROM, where the voice
codes are stored. Eight bits of voice ROM data will be
addressed by using the 22-bit address (except for the
HT86B03 which has only 18-bits) latch counter, which is
composed of LATCH0H/LATCH0M/LATCH0L or
LATCH1H/LATCH1M/LATCH1L. After the 8-bit voice
ROM data is addressed, several instruction cycles of at
least 4us at least, will be required to latch the voice ROM
data, after which the microcontroller can read the voice
data from LATCHD.
Input/Output Ports and Control Registers
The device includes a single 12-bit current type DAC
function for driving an external 8W speaker through an
external NPN transistor. The programmer must write the
voice data to the DAL/DAH registers.
Voice Control and Audio output Registers VOICEC, DAL, DAH, VOL
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PD, etc. These labeled I/O registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory
table, which are used to transfer the appropriate output
or input data on that port. With each I/O port there is an
associated control register labeled PAC, PBC, PDC,
etc., also mapped to specific addresses with the Data
Memory. The control register specifies which pins of that
port are set as inputs and which are set as outputs. To
setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set
low. During program initialisation, it is important to first
setup the control registers to specify which pins are outputs and which are inputs before reading data from or
writing data to the I/O ports. One flexible feature of these
registers is the ability to directly program single bits using the ²SET [m].i² and ²CLR [m].i² instructions. The
ability to change I/O pins from output to input and
vice-versa by manipulating specific bits of the I/O control
registers during normal program operation is a useful
feature of these devices.
Rev. 1.80
Pulse Width Modulator Registers PWMC, PWML, PWMH
Each device contains a single 12-bit PWM function for
driving an external 8W speaker. The programmer must
write the voice data to PWML/PWMH register.
Analog Switch Registers - ASCR
Some devices, include 8 analog switch lines, which
have an associated register, known as ASCR, for their
setup and control.
External RC Oscillation Converter Registers RCOCCR, RCOCR, TMR4L, TMR4H
For the HT86B40/HT86B50/HT86B60/HT86BR60/
HT86B70/ HT86B80/HT86B90 devices, which have two
16-bit programmable timers, the TMR4L and TMR4H
registers are for one of the 16-bit timers. The RCOCCR
and RCOCR registers are the control registers for the
external RC oscillator.
34
March 12, 2010
HT86BXX/HT86BRXX
Input/Output Ports
I/O Port Control Registers
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities.
Depending upon which device or package is chosen,
the microcontroller range provides from 16 to 24
bidirectional input/output lines labeled with port names
PA, PB, PD, etc. These I/O ports are mapped to the Data
Memory with specific addresses as shown in the Special
Purpose Data Memory table. All of these I/O ports can
be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction
²MOV A,[m]², where m denotes the port address. For
output operation, all the data is latched and remains unchanged until the output latch is rewritten.
Each I/O port has its own control register PAC, PBC,
PDC, etc., to control the input/output configuration. With
this control register, each CMOS output or input with or
without pull-high resistor structures can be reconfigured
dynamically under software control. Each pin of the I/O
ports is directly mapped to a bit in its associated port
control register. For the I/O pin to function as an input,
the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the
corresponding bit of the control register is written as a
²0², the I/O pin will be setup as a CMOS output. If the pin
is currently setup as an output, instructions can still be
used to read the output register. However, it should be
noted that the program will in fact only read the status of
the output data latch and not the actual logic status of
the output pin.
Pull-high Resistors
Pin-shared Functions
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have
the capability of being connected to an internal pull-high
resistor. These pull-high resistors are selectable via
configuration options and are implemented using a
weak PMOS transistor. Note that if the pull-high option
is selected, then all I/O pins on that port will be connected to pull-high resistors, individual pins can be selected for pull-high resistor options.
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
· Analog Switch
For the HT86B40, HT86B50, HT86B60, HT86BR60,
HT86B70, HT86B80 and HT86B90 devices, pins
PB0~PB7 are pin-shared with analog switch pins K0
to K7. The choice of which function is used is selected
using configuration options and remains fixed after
the device is programmed.
Port A Wake-up
Each device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port A pins from high to
low. After a ²HALT² instruction forces the microcontroller
into entering a HALT condition, the processor will remain idle or in a low-power state until the logic condition
of the selected wake-up pin on Port A changes from high
to low. This function is especially suitable for applications that can be woken up via external switches. Note
that each pin on Port A can be selected individually to
have this wake-up feature.
Rev. 1.80
· External RC Oscillator Converter
For the HT86B40, HT86B50, HT86B60, HT86BR60,
HT86B70, HT86B80 and HT86B90 devices, pins
PD4~PD7 are pin-shared with external oscillator converter pins RCOUT, RR, RC and CC. The external RC
oscillator converter function is selected via a configuration option and remains fixed after the device is programmed.
· I/O Pin Structures
The following diagrams illustrate the I/O pin internal
structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied
as a guide only to assist with the functional understanding of the I/O pins. Note also that the specified
pins refer to the largest device package, therefore not
all pins specified will exist on all devices.
35
March 12, 2010
HT86BXX/HT86BRXX
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P A 0 ~ P A 7
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
M
U
X
R e a d D a ta R e g is te r
S y s te m
W a k e -u p
W a k e - u p O p tio n
PA Input/Output Port
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P B 0 ~ P B 7
K 0 ~ K 7
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
Q
S
M
P B 0 D a ta B it
K 0 ~ K 7
M
R e a d D a ta R e g is te r
U
X
U
A n a lo g S w itc h O p tio n
X
PB Input/Output Port
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P D 0 ~ P D 7
R C O U T , R R , R C , C C
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
P D 0 D a ta B it
R C O U T , R R , R C , C C
M
R e a d D a ta R e g is te r
U
U
X
E x te rn a l R C
C o n v e r te r O p tio n
X
PD Input/Output Port
Rev. 1.80
36
March 12, 2010
HT86BXX/HT86BRXX
Programming Considerations
MCU series contain either three or four count up timers
of either 8 or 16-bit capacity depending upon which device is selected. The provision of an internal prescaler to
the clock circuitry of some of the timer gives added
range to the timer.
Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data
and port control registers will be set high. This means
that all I/O pins will default to an input state, the level of
which depends on the other connected circuitry and
whether pull-high options have been selected. If the port
control registers, PAC, PBC, PDC, etc., are then programmed to setup some pins as outputs, these output
pins will have an initial high output value unless the associated port data registers, PA, PB, PD, etc., are first
programmed. Selecting which pins are inputs and which
are outputs can be achieved byte-wide by loading the
correct values into the appropriate port control register
or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions.
Note that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then rewrite this data back to the output ports.
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
There is single type of register related to the Timer. The
first is the register that contains the actual value of the
timer and into which an initial value can be preloaded.
Reading from this register retrieves the contents of the
Timer. All devices can have the timer clock configured to
come from the internal clock source. The accompanying
table lists the associated timer register names.
HT86B03
HT86B10
HT86BR10
HT86B20
HT86B30
HT86BR30
HT86B40
HT86B50
HT86B60
HT86BR60
HT86B70
HT86B80
HT86B90
3
3
Timer Register Name
TMR0
TMR1
TMR3
TMR0
TMR1
TMR3
Timer Control Register
TMR0C
TMR1C
TMR3C
TMR0C
TMR1C
TMR3C
No. of 8-bit Timers
T 4
C lo c k
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
No. of 16-bit Timers
¾
1
Port A has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
A pins. Single or multiple pins on Port A can be setup to
have this function.
Timer Register Name
¾
TMR2L
TMR2H
Timer Control Register
¾
TMR2C
Configuring the Timer Input Clock Source
The clock source for the 8-bit timers is the system clock
divided by four while the 16-bit timer has a choice of either the system clock or the system clock divided by
four. The 8-bit timer clock source is also first divided by
the division ratio of which is conditioned by the three
lower bits of the associated timer control register.
Timers
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The devices in the Voice Type
D a ta B u s
T 3 P S C 2 ~ T 3 P S C 0
T 1 P S C 2 ~ T 1 P S C 0
T 0 P S C 2 ~ T 0 P S C 0
fS
Y S
/4
P r e s c a le r
(1 /2 ~ 1 /2 5 6 )
T 3 T M 1
T 1 T M 1
T 0 T M 1
P r e lo a d R e g is te r
T 3 T M 0
T 1 T M 0
T 0 T M 0
T im e r
T im e r M o d e C o n tr o l
T 0 O N
T 1 O N
T 3 O N
R e lo a d
O v e r flo w
to In te rru p t
8 - B it T im e r
8-bit Timer Structure
Rev. 1.80
37
March 12, 2010
HT86BXX/HT86BRXX
D a ta B u s
L o w B y te
B u ffe r
T 2 T M 1
fS
Y S
/4
fS
Y S
1 6 - b it
P r e lo a d R e g is te r
T 2 T M 0
H ig h B y te
T im e r M o d e C o n tr o l
T 2 O N
L o w
1 6 - B it T im e r
B y te
R e lo a d
O v e r flo w
to In te rru p t
16-bit Timer Structure - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90
Timer Registers - TMR0, TMR1, TMR2L/TMR2H,
TMR3
and not directly into the low byte register. The actual
transfer of the data into the low byte register is only carried out when a write to its associated high byte register,
namely TMR2H, is executed. However, using instructions to preload data into the high byte timer register will
result in the data being directly written to the high byte
register. At the same time the data in the low byte buffer
will be transferred into its associated low byte register.
For this reason, when preloading data into the 16-bit
timer registers, the low byte should be written first. It
must also be noted that to read the contents of the low
byte register, a read to the high byte register must first
be executed to latch the contents of the low byte buffer
into its associated low byte register. After this has been
done, the low byte register can be read in the normal
way. Note that reading the low byte timer register will
only result in reading the previously latched contents of
the low byte buffer and not the actual contents of the low
byte timer register.
The timer registers are special function registers located
in the special purpose Data Memory and is the place
where the actual timer value is stored. All devices contain three 8-bit timers, whose registers are known as
TMR0, TMR1 and TMR3. The HT86B40, HT86B50,
HT86B60, HT86BR60, HT86B70, HT86B80 and
HT86B90 devices also contain an additional single
16-bit timer, which has a pair of registers known as
TMR2L and TMR2H. The value in the timer registers increases by one each time an internal clock pulse is received. The timer will count from the initial value loaded
by the preload register to the full count of FFH for the
8-bit timer or FFFFH for the 16-bit timers at which point
the timer overflows and an internal interrupt signal is
generated. The timer value will then be reset with the initial preload register value and continue counting.
Note that to achieve a maximum full range count of FFH
for the 8-bit timer or FFFFH for the 16-bit timers, the
preload registers must first be cleared to all zeros. It
should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the
Timer Counters are in an OFF condition and data is written to their preload registers, this data will be immediately written into the actual counter. However, if the
counter is enabled and counting, any new data written
into the preload data register during this period will remain in the preload register and will only be written into
the actual counter the next time an overflow occurs.
Note also that when the timer registers are read, the
timer clock will be blocked to avoid errors, however, as
this may result in certain timing errors, programmers
must take this into account.
Timer Control Registers - TMR0C, TMR1C, TMR2C,
TMR3C
Each timer has its respective timer control register,
known as TMR0C, TMR1C, TMR2C and TMR3C. It is
the timer control register together with their corresponding timer registers that control the full operation of the
timers. Before the timers can be used, it is essential that
the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during
program initialization. Bits 7 and 6 of the Timer Control
Register, which are known as the bit pair TM1/TM0 respectively, must be set to the required logic levels. The
timer-on bit, which is bit 4 of the Timer Control Register
and known as TON, depending upon which timer is
used, provides the basic on/off control of the respective
timer. setting the bit high allows the timer to run, clearing
the bit stops the timer. For the 8-bit timers, which have
prescalers, bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler.
For devices which have an internal 16-bit Timer, and
which therefore have both low byte and high byte timer
registers, accessing these registers is carried out in a
specific way. It must be noted that when using instructions to preload data into the low byte register, namely
TMR2L, the data will only be placed in a low byte buffer
Rev. 1.80
38
March 12, 2010
HT86BXX/HT86BRXX
b 7
b 0
T M 1
T M 0
T O N
P S C 2
P S C 1
P S C 0
T M R 0 C /T M R 1 C /T M R 3 C
R e g is te r
T im
T 0
T 1
T 3
le c
S C
S C
S C
0
1
0
1
0
1
0
1
e r
P S C
P S C
P S C
0
0
0
0
1
1
1
1
P re s
2 T
2 T
2 T
c a
0
1
3
le r
P S C
P S C
P S C
0
0
1
1
0
0
1
1
R a te
T
1
T
1
T
1
S e
0 P
1 P
3 P
t
0
0
T im e r R a te
0
1 :2
1 :4
1 :8
1 :1
1 :3
1 :6
1 :1
1 :2
6
2
4
2 8
5 6
N o t im p le m e n t e d , r e a d a s " d o n 't c a r e "
T im e r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p
T 0
T 1
T 3
e r
T M
T M
T M
0
0
1
1
a tin g M
T
1
T
1
T
1
o d
0 T
1 T
3 T
1
0
0
1
e S e le c t
M 0
M 0
M 0
n o
n o
tim
n o
m o d
m o d
e r m
m o d
e a v a ila b le
e a v a ila b le
o d e
e a v a ila b le
Timer Control Register - All Devices
b 7
T M 1
b 0
T M 0
T O N
T M R 2 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
T im e r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g M o d e S e le c
T M 2 T M 1 T M 2 T M 0
n o
0
0
n o
1
0
tim
0
1
1
1
n o
t
m o d
m o d
e r m
m o d
e a v a ila b le
e a v a ila b le
o d e
e a v a ila b le
Timer Control Register - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90
Configuring the Timer
Prescaler Rate Select bits, which are bits 0~2 in the
Timer Control Register. After the other bits in the Timer
Control Register have been setup, the enable bit, which
is bit 4 of the Timer Control Register, can be set high to
enable the Timer to run. Each time an internal clock cycle occurs, the Timer increments by one. When it is full
and overflows, an interrupt signal is generated and the
Timer will reload the value already loaded into the
preload register and continue counting. The interrupt
can be disabled by ensuring that the Timer Interrupt Enable bit in the Interrupt Control Register, INTC, is reset
to zero.
The Timer is used to measure fixed time intervals, providing an internal interrupt signal each time the Timer
overflows. To do this the Operating Mode Select bit pair
in the Timer Control Register must be set to the correct
value as shown.
Control Register Operating Mode
Select Bits
Bit7 Bit6
1
0
The internal clock, fSYS, is used as the Timer clock.
However, this clock source is further divided by a
prescaler, the value of which is determined by the
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+ 1
Timer Mode Timing Diagram
Rev. 1.80
39
March 12, 2010
HT86BXX/HT86BRXX
Prescaler
All of the 8-bit timers possess a prescaler. Bits 0~2 of
their associated timer control register, define the
pre-scaling stages of the internal clock source of the
Timer. The Timer overflow signal can be used to generate signals for the Timer interrupt.
important to ensure that an initial value is first loaded into
the timer registers before the timer is switched on; this is
because after power-on the initial values of the timer registers are unknown. After the timer has been initialized
the timer can be turned on and off by controlling the enable bit in the timer control register.
Programming Considerations
Timer Program Example
The internal system clock is used as the timer clock
source and is therefore synchronized with the overall
operation of the microcontroller. In this mode, when the
appropriate timer register is full, the microcontroller will
generate an internal interrupt signal directing the program flow to the respective internal interrupt vector.
The following example program section is based on the
HT86B40, HT86B50, HT86B60, HT86BR60, HT86B70,
HT86B80 and HT86B90 devices, which contain a single
internal 16-bit timer. Programming the timer for other devices is conducted in a very similar way. The program
shows how the timer registers are setup along with how
the interrupts are enabled and managed. Points to note
in the example are how, for the 16-bit timer, the low byte
must be written first, this is because the 16-bit data will
only be written into the actual timer register when the
high byte is loaded. Also note how the timer is turned on
by setting bit 4 of the respective timer control register.
The timer can be turned off in a similar way by clearing
the same bit. This example program sets the timer to be
in the timer mode which uses the internal system clock
as their clock source.
When the Timer is read, the clock is blocked to avoid errors, however as this may result in a counting error, this
should be taken into account by the programmer. Care
must be taken to ensure that the timers are properly initialized before using them for the first time. The associated timer enable bits in the interrupt control register must
be properly set otherwise the internal interrupt associated
with the timer will remain inactive. The edge select, timer
mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also
#include HT86B40.inc
jmp begin
:
org 04h
; external interrupt vectors
reti
org 08h
reti
org 0Ch
reti
org 10h
; timer 2 interrupt vector
jmp tmr2int
; jump here when timer 2 overflows
org 14h
reti
:
; internal timer 2 interrupt routine
tmr2int:
:
; timer 2 main program placed here
:
reti
:
begin:
; setup timer 2 registers
mov a,09bh
; setup timer 2 low byte
mov tmr2l,a
; low byte must be setup before high byte
mov a,0e8h
; setup timer 2 high byte
mov tmr2h,a
; setup timer 2 high byte
mov a,090h
; setup timer 2 control register
mov tmr2c,a
; setup timer mode
; setup interrupt register
mov a,01h
; enable master interrupt
mov intc,a
mov a,01h
; enable timer 2 interrupt
mov intch,a
:
Rev. 1.80
40
March 12, 2010
HT86BXX/HT86BRXX
Interrupts
stack. The Program Counter will then be loaded with a
new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch
its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which
will take program execution to another section of program which is known as the interrupt service routine.
Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated
with a RETI statement, which retrieves the original Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the
point where the interrupt occurred.
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer requires microcontroller attention, their
corresponding interrupt will enforce a temporary susp e n s io n o f t h e m a i n pr o g r am al l ow i n g t h e
microcontroller to direct attention to their respective
needs. Each device contains a single external interrupt
and three or four internal timer interrupt functions. The
external interrupt is controlled by the action of the external INT pin, while the internal interrupt is controlled by
the relevant Timer overflow.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and flag setting, is controlled using two registers, known
as INTC and INTCH, which are located in the Data
Memory. By controlling the appropriate enable bits in
these registers each individual interrupt can be enabled
or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller.
The global enable flag if cleared to zero will disable all
interrupts.
The various interrupt enable bits, together with their associated request flags, are shown in the accompanying
diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A timer overflow or the external interrupt line being
pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropriate
interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the
b 7
b 0
T 1 F
T 0 F
E IF
E T 1 I
E T 0 I
E E I
E M I
IN T C R e g is te r
M a s te r In te r r u p t G lo b a l E n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r 0 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r 1 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r 0 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r 1 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register
Rev. 1.80
41
March 12, 2010
HT86BXX/HT86BRXX
b 7
b 0
T 3 F
T 2 F
E T 3 I
E T 2 I
IN T C H
R e g is te r
T im e r 2 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r 3 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
N o im p le m e n te d , r e a d a s " 0 "
T im e r 2 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r 3 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o im p le m e n te d , r e a d a s " 0 "
INTCH Register
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
P r io r ity
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
T im e r 3
In te r r u p t R e q u e s t F la g T 3 F
E T 3 I
E M I
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure - HT86B03/HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
P r io r ity
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
T im e r 2
In te r r u p t R e q u e s t F la g T 2 F
E T 2 I
T im e r 3
In te r r u p t R e q u e s t F la g T 3 F
E T 3 I
E M I
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure - HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90
Rev. 1.80
42
March 12, 2010
HT86BXX/HT86BRXX
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter
of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the accompanying
table shows the priority that is applied.
Interrupt Vector
HT86B03/HT86B10
HT86BR10/HT86B20
HT86B30/HT86BR30
Priority
HT86B40/HT86B50/HT86B60
HT86BR60/HT86B70/HT86B80
HT86B90
Priority
External Interrupt
04H
1
1
Timer 0 Overflow
08H
2
2
Timer 1 Overflow
0CH
3
3
Timer 2 Overflow
10H
¾
4
Timer 3 Overflow
14H
4
5
Interrupt Source
in the INTC and INTCH registers. Some devices also
contain a 16-bit timer, which has a corresponding timer
interrupt enable bit, ET2I, and a corresponding timer request flag, T2F, which are contained in the INTCH register. When the master interrupt and corresponding timer
interrupt enable bits are enabled, the stack is not full,
and when the corresponding timer overflows a subroutine call to the corresponding timer interrupt vector will
occur. The corresponding Program Memory vector locations for Timer 0, Timer1, Timer 2 and Timer 3 are 08H,
0CH, 10H and 14H. After entering the interrupt execution routine, the corresponding interrupt request flags,
T0F, T1F, T2F or T3F will be reset and the EMI bit will be
cleared to disable other interrupts.
In cases where both external and timer interrupts are
enabled and where an external and timer interrupt occur
simultaneously, the external interrupt will always have
priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the INTC and
INTCH registers can prevent simultaneous occurrences.
External Interrupt
Each device contains a single external interrupt function
controlled by the external pin, INT. For an external interrupt to occur, the corresponding external interrupt enable bit must be first set. This is bit 1 of the INTC register
and known as EEI. An external interrupt is triggered by
an external edge transition on the external interrupt pin
INT, after which the related interrupt request flag, EIF,
which is bit 4 of INTC, will be set. A configuration option
exists for the external interrupt pin to determine the type
of external edge transition which will trigger an external
interrupt. There are two options available, a low going
edge or both high and low going edges. When the master interrupt and external interrupt bits are enabled, the
stack is not full and an active edge transition, as setup in
the configuration options, occurs on the INT pin, a subroutine call to the corresponding external interrupt vector, which is located at 04H, will occur. After entering the
interrupt execution routine, the corresponding interrupt
request flag, EIF, will be reset and the EMI bit will be
cleared to disable other interrupts.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the INTC or INTCH register until the corresponding interrupt is serviced or until the request flag is
cleared by a software instruction.
Timer Interrupt
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
For a timer generated interrupt to occur, the corresponding timer interrupt enable bit must be first set. Each device contains three 8-bit timers whose corresponding
interrupt enable bits are known as ET0I, ET1I and ET3I
and are located in the INTC and INTCH registers. Each
timer also has a corresponding timer interrupt request
flag, which are known as T0F, T1F and T3F, also located
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode. Only the
Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the
interrupt service program, which may corrupt the desired control sequence, then the contents should be
saved in advance.
Rev. 1.80
43
March 12, 2010
HT86BXX/HT86BRXX
Reset and Initialisation
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V D D
0 .9 V
R E S
tR
D D
S T D
S S T T im e - o u t
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
V D D
1 0 0 k W
R E S
0 .1 m F
V S S
Basic Reset Circuit
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
0 .0 1 m F
V D D
1 0 0 k W
Reset Functions
R E S
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
1 0 k W
0 .1 m F
V S S
· Power-on Reset
Enhanced Reset Circuit
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
· RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
D D
D D
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
RES Reset Timing Chart
Rev. 1.80
44
March 12, 2010
HT86BXX/HT86BRXX
· Low Voltage Reset - LVR
Reset Initial Conditions
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device,
which is selected via a configuration option. If the supply
voltage of the device drops to within a range of
0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For
a valid LVR signal, a low voltage, i.e., a voltage in the
range between 0.9V~VLVR must exist for greater than the
value tLVR specified in the A.C. characteristics. If the low
voltage state does not exceed 1ms, the LVR will ignore it
and will not perform a reset function.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
TO PDF
L V R
tR
S T D
S S T T im e - o u t
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
In te rn a l R e s e t
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
Low Voltage Reset Timing Chart
· Watchdog Time-out Reset during Normal Operation
Item
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tR
S T D
S S T T im e - o u t
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer
All Timer will be turned off
Prescaler
The Timer Prescaler will be
cleared
In te rn a l R e s e t
WDT Time-out Reset during Normal Operation
Timing Chart
Input/Output Ports I/O ports will be setup as inputs
Stack Pointer
· Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
Stack Pointer will point to the top
of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure
reliable continuation of normal program execution after
a reset occurs, it is important to know what condition the
microcontroller is in after a particular reset occurs. The
following table describes how each type of reset affects
each of the microcontroller internal registers. Note that
where more than one package type exists the table will
reflect the situation for the larger package type.
W D T T im e - o u t
tS
Condition After RESET
S T
S S T T im e - o u t
WDT Time-out Reset during Power Down
Timing Chart
Rev. 1.80
45
March 12, 2010
HT86BXX/HT86BRXX
HT86B03
Register
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
from HALT
MP0
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 0000
-- 1u uuuu
--uu uuuu
-- 01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 ----
1111 ----
1111 ----
1111 ----
uuuu ----
PBC
1111 ----
1111 ----
1111 ----
1111 ----
uuuu ----
TMR3
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR3C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
INTCH
--0- --0-
--0- --0-
--0- --0-
--0- --0-
--u- --u-
TBHP
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
0000 ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
DAH
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
VOL
000- 0000
000- ----
000- ----
000- ----
uuu- ----
VOICEC
---0 -00-
---0 -00-
---0 -00-
---0 -00-
---u -uu-
LATCH0H
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0M
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0L
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1H
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1M
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1L
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCHD
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note: ²u² stands for unchanged
²x² stands for unknown
²-² stands for undefined
Rev. 1.80
46
March 12, 2010
HT86BXX/HT86BRXX
HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30
Register
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
from HALT
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
-- 1u uuuu
--uu uuuu
-- 01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
TMR3
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR3C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
INTCH
--0- --0-
--0- --0-
--0- --0-
--0- --0-
--u- --u-
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
VOL
xxx- xxxx
uuu- uuuu
uuu- uuuu
uuu- uuuu
uuu- uuuu
VOICEC
---0 -00-
---0 -00-
---0 -00-
---0 -00-
---u -uu-
LATCH0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCHD
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PWMC
0--- 0--0
0--- 0--0
0--- 0--0
0--- 0--0
u--- u--u
PWML
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
PWMH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note: ²u² stands for unchanged
²x² stands for unknown
²-² stands for undefined
Rev. 1.80
47
March 12, 2010
HT86BXX/HT86BRXX
HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90
Register
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
from HALT
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
-- 1u uuuu
--uu uuuu
-- 01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR0
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
TMR2H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR2L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR2C
00-0 ----
00-0 ----
00-0 ----
00-0 ----
uu-u ----
TMR3
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
TMR3C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
INTCH
--00 --00
--00 --00
--00 --00
--00 --00
--uu --uu
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
VOL
xxx- xxxx
uuu- uuuu
uuu- uuuu
uuu- uuuu
uuu- uuuu
VOICEC
---0 -00-
---0 -00-
---0 -00-
---0 -00-
---u -uu-
LATCH0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1M
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCH1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
LATCHD
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
Rev. 1.80
48
March 12, 2010
HT86BXX/HT86BRXX
Register
Reset
(Power-on)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
RES Reset
(HALT)
WDT Time-out
from HALT
PWMC
0--- 0--0
0--- 0--0
0--- 0--0
0--- 0--0
u--- u--u
PWML
xxxx ----
uuuu ----
uuuu ----
uuuu ----
uuuu ----
PWMH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ASCR
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
RCOCCR
0010 ----
0010 ----
0010 ----
0010 ----
uuuu ----
TMR4H
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR4L
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCR
1xxx --00
1xxx --00
1xxx --00
1xxx --00
uuuu --uu
Note: ²u² stands for unchanged
²x² stands for unknown
²-² stands for undefined
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Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application requirements. Two types of system clocks can be selected
while various clock source options for the Watchdog
Timer are provided for maximum flexibility. All oscillator
options are selected through the configuration options.
External RC Oscillator
Using the external system RC oscillator requires that a
resistorco. The mask MCU value between 60kW and
130kW, the OTP MCU value between 150kW and
300kW. They connected between OSC1 and VSS. The
generated system clock divided by 4 will be provided on
OSC2 as an output which can be used for external synchronization purposes. Note that as the OSC2 output is
an NMOS open-drain type, a pull high resistor should be
connected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD,
temperature and process variations and is therefore not
suitable for applications where timing is critical or where
accurate oscillator frequencies are required. Note that it
is the only microcontroller internal circuitry together with
the external resistor, that determine the frequency of the
oscillator. The external capacitor shown on the diagram
does not influence the frequency of oscillation.
The two methods of generating the system clock are:
· External crystal/resonator oscillator
· External RC oscillator
One of these two methods must be selected using the
configuration options.
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
External Crystal/Resonator Oscillator
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most
resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
C 1
R f
fS
In te r n a l
O s c illa to r
C ir c u it
O S C 1
R p
O S C 1
R
C a
Y S
O S C
/4 N M O S O p e n D r a in
O S C 2
External RC Oscillator
Watchdog Timer Oscillator
C b
C 2
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 65ms at 5V
requiring no external components. When the device enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
T o in te r n a l
c ir c u its
O S C 2
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
Ca
Cb
Rf
11~13pF
13~15pF
800kW
Oscillator Internal Component Values
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HT86BXX/HT86BRXX
Power Down Mode and Wake-up
outputs. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled the
Watchdog Timer internal oscillator.
Power Down Mode
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode, also known as the HALT Mode or
Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely
low standby current level. This occurs because when
the device enters the Power Down Mode, the system
oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken
up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power
supply constantly maintained to keep the device in a
known condition but where the power supply capacity is
limited such as in battery applications.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on Port A
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
oscillator. The WDT will stop if its clock source originates from the system clock.
Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased current consumption. Care must also be taken with the
loads, which are connected to I/Os, which are setup as
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source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be
noted that when the system enters the Power Down
Mode, as the system clock is stopped, then the WDT
clock source will also be stopped. Therefore the WDT
will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate
in noisy environments, using the internal WDT oscillator
is therefore the recommended choice.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a
WDT time-out occurs, only the Program Counter and
Stack Pointer will be reset. Three methods can be
adopted to clear the contents of the WDT and the WDT
prescaler. The first is an external hardware reset, which
means a low level on the RES pin, the second is using
the watchdog software instructions and the third is via a
²HALT² instruction.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT
clock is supplied by one of two sources selected by configuration option: its own self-contained dedicated internal WDT oscillator, or the instruction clock which is the
system clock divided by 4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use
the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will
clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed to
successfully clear the WDT. Note that for this second
option, if ²CLR WDT1² is used to clear the WDT, successive executions of this instruction will have no effect,
only the execution of a ²CLR WDT2² instruction will
clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
The internal WDT oscillator has an approximate period
of 65ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal
period of 17ms. Note that this period can vary with VDD,
temperature and process variations. For longer WDT
time-out periods the WDT prescaler can be utilized. By
writing the required value to bits 0, 1 and 2 of the WDTS
register, known as WS0, WS1 and WS2, longer time-out
periods can be achieved. With WS0, WS1 and WS2 all
equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s.
A configuration option can select the instruction clock,
which is the system clock divided by 4, as the WDT clock
b 7
b 0
W S 2
W S 1
W S 0
W D T S R e g is te r
W D T p r e s c a le r r a te s e le c t
W D T R
W S 0
W S 1
W S 2
1 :1
0
0
0
1 :2
1
0
0
1 :4
0
1
0
1 :8
1
1
0
1 :1
0
0
1
1 :3
1
0
1
1 :6
0
1
1
1 :1
1
1
1
a te
6
2
4
2 8
N o t u s e d
Watchdog Timer Register
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HT86BXX/HT86BRXX
C L R W D T 1 F la g
C L R W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
Y S
/4
W D T O s c illa to r
C L R
W D T C lo c k S o u r c e
C o n fig u r a tio n O p tio n
C L R
8 - b it C o u n te r
(¸ 2 5 6 )
7 - b it P r e s c a le r
W D T C lo c k S o u r c e
W S 0 ~ W S 2
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
Voice Output
three registers to store the address. There are two sets
of three registers to store this address, which are
LATCH0H/LATCH0M/LATCH0L and LATCH1H/
LATCH1M/LATCH1L. The 22-bit address (except for
the HT86B03 which has only 10-bits) stored in one set of
these three registers is used to access the 8-bit voice
code data in the Voice ROM. After the 8-bit Voice ROM
data is addressed, a few instruction cycles, of at least
4us duration, are needed to latch the Voice ROM data.
After this the microcontroller can read the voice data
from the LATCHD register.
Voice Control
The voice control register controls the voice ROM circuit
and the DAC circuit and selects the Voice ROM latch
counter. If the DAC circuit is not enabled, any DAH/DAL
outputs will be invalid. Writing a ²1² to the DAC bit will
enable the enable DAC circuit, while writing a ²0² to the
DAC bit will disable the DAC circuit. If the voice ROM circuit is not enabled, then voice ROM data cannot be accessed. Writing a ²1² to the VROMC bit will enable the
voice ROM circuit, while writing a ²0² to the VROMC bit
is will disable the voice ROM circuit. The LATCH bit determines which voice ROM address latch counter will be
used as the voice ROM address latch counter.
b 7
b 0
D 3
D 2
D 1
D 0
D A L R e g is te r
N o t u s e d , re a d a s "0 "
Audio Output and Volume Control - DAL, DAH, VOL
A u d io o u tp u t
D ig ita l to A n a lo g D a ta L o w
The audio output is 12-bits wide whose highest 8-bits
are written into the DAH register and whose lowest four
bits are written into the highest four bits of the DAL register. Bits 0~3 of the DAL register are always read as zero.
There are 8 levels of volume which are setup using the
VOL register. Only the highest 3-bits of this register are
used for volume control, the other bits are not used and
read as zero.
b 7
R e g is te r
b 0
D 1 1
D 1 0
D 9
D 8
D 7
D 6
D 5
D 4
D A H
R e g is te r
A u d io o u tp u t
D ig ita l to A n a lo g D a ta H ig h R e g is te r
b 7
b 0
V O L R e g is te r
V O L 2 V O L 1 V O L 0
U s e d b y P W M
Voice ROM Data Address Latch Counter
o u tp u t
N o t u s e d , re a d a s "0 "
D A v o lu m e c o n tr o l d a ta
The Voice ROM address is 22-bits wide (except for the
HT86B03 which has only 10-bits) and therefore requires
V o lu m e C o n tr o l R e g is te r
b 7
b 0
L A T C H C
V R O M C
D A C
V O IC E C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
D A C E n a b le
1 : e n a b le
0 : d is a b le
V o ic e R O M
1 : e n a b le
0 : d is a b le
E n a b le
N o t im p le m e n te d , r e a d a s " 0 "
V o ic e R O M C o u n te r S e le c t
1 : A d d re s s L a tc h 1
0 : A d d re s s L a tc h 0
N o t im p le m e n te d , r e a d a s " 0 "
VOICE Control Register
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Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0
Set
[26H].2
; Enable voice ROM circuit
mov
A, 07H
;
mov
LATCH0L, A
; Set LATCH0L to 07H
mov
A, 00H
;
mov
LATCH0M, A
; Set LATCH0M to 00H
mov
A, 00H
;
mov
LATCH0H, A
; Set LATCH0H to 00H
call
Delay
; Delay a short period of time
mov
A, LATCHD
; Get voice data at 000007H
Pulse Width Modulation Output
All device include a single 12-bit PWM function. The
PWM output is provided on two complimentary outputs
on the PWM1 and PWM2 pins. These two pins can directly drive a piezo buzzer or an 8 ohm speaker without
requiring any external components. The PWM1 output
can also be used alone to drive a piezo buzzer or an 8
ohm speaker without requiring external components.
When the single PWM1 output is chosen, which is
achieved by setting the Single_PWM bit in the PWMC
register.
P W M 1
P W M 2
0 .0 1 m F *
N o te : " * " F o r r e d u c in g th e d ig ita l n o is e th a t P W M m a y
c a u s e , c a n c o n s id e r in c r e m e n t c a p a c ito r s .
b 7
P 3
b 0
P 2
P 1
P 0
P W M L R e g is te r
N o t u s e d , re a d a s "0 "
The PWM output will initially be at a low level, and if
stopped will also return to a low level. If the PWMCC bit
changes from low to high then the PWM function will
start and latch new data. If the data is not updated then
the old value will remain. If the PWMCC bit changes
from high to low, at the end of the duty cycle, the PWM
output will stop.
b 7
S p e a k e r
0 .0 1 m F *
P W M
o u tp u t
P u ls e W id th M o d u la to r D a ta L o w
b 7
P 1 1
R e g is te r
b 0
P 1 0
P 9
P 8
P 7
P 6
P 5
P 4
P W M H
P W M
R e g is te r
o u tp u t
P u ls e W id th M o d u la to r D a ta H ig h R e g is te r
b 0
V O L 6
V O L 5
V O L 4
V O L 3
V O L R e g is te r
P W M v o lu m e c o n tr o l d a
V O L 6 V O L 5 V O L 4 V
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
1
1
0
1
1
0
x
x
1
ta
O L 3
1
0
1
0
1
0
1
x
P W M
P W M
P W M
P W M
P W M
P W M
P W M
P W M
v o lu
v o lu
v o lu
v o lu
v o lu
v o lu
v o lu
v o lu
m e le
m e le
m e le
m e le
m e le
m e le
m e le
m e le
v e l
v e l
v e l
v e l
v e l
v e l
v e l
v e l
1 fo r th e m in im u m
2
v o lu m e
3
4
7
5
6
8 fo r th e m a x im u m
v o lu m e
N o t u s e d , re a d a s "0 "
U s e d b y D A o u tp u t
Volume Control Register
b 7
b 0
S in g le _ P W M
P W M C C
P W M C
R e g is te r
P W M E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s z e r o
S in g le P W M O u tp u t
1 : s in g le o u tp u t
0 : d u a l o u tp u ts
N o t im p le m e n te d , r e a d a s z e r o
Pulse Width Modulator Control Register
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External RC Oscillation Converter
An external RC oscillation converter is implemented in
certain devices and is a function which allows analog
switch functions to be implemented. When used in conjunction with the Analog Switch function up to eight
C/R-F can be implemented.
TMR4L and RCOCR. The internal timer clock is the input clock source for TMR2H and TMR2L, while the external RC oscillator is the clock source input to TMR4H
and TMR4L. The OVB bit, which is bit 0 of the RCOCR
register, decides whether the timer interrupt is sourced
from either the Timer 2 overflows or Timer 4 overflow.
When a timer overflow occurs, the T2F bit is set and an
external RC oscillation converter interrupt occurs. When
the RC oscillation converter Timer 2 or Timer 4 overflows, the RCOCON bit is automatically reset to zero
and stops counting.
External RC Oscillation Converter Operation
The RC oscillation converter is composed of two 16-bit
count-up programmable timers. One is Timer 2, described in the Timer section and the other is an additional counter known as Timer 4. The RC oscillation
converter is enabled when the RCO bit, which is bit 1 of
the RCOCR register, is set high. The RC oscillation converter will then be composed of four registers, TMR2L,
TMR2H, TMR4L and TMR4H. The Timer 2 clock source
comes from the system clock or from the system
clock/4, the choice of which is determined by bits in the
RCOCCR register. The RC oscillation converter Timer 4
clock source comes from an external RC oscillator. As
the oscillation frequency is dependent upon external capacitance and resistance values, it can therefore be
used to detect the increased capacitance of a analog
switch pad.
The resistor and capacitor form an oscillation circuit and
input to TMR4H and TMR4L. The RCOM0, RCOM1 and
RCOM2 bits of RCOCCR define the clock source of
Timer 2.
When the RCOCON bit, which is bit 4 of the RCOCCR
register, is set high, Timer 2 and Timer 4 will start counting until Timer 2 or Timer 4 overflows. Now the timer
counter will generate an interrupt request flag which is
bit T2F, bit 4 of the INTCH register. Both Timer 2 and
Timer 4 will then stop counting and the RCOCON bit will
automatically be reset to "0" at the same time. Note that
if the RCOCON bit is high, the TMR2H, TMR2L, TMR4H
and TMR4L registers cannot be read or written to.
There are six registers related to the RC oscillation converter. These are, TMR2H, TMR2L, RCOCCR, TMR4H,
b 7
R C O M 2 R C O M 1 R C O M 0
b 0
R C O C O N
R C O C C R
R e g is te r
U n d e fin e d , r e a d a s z e r o
R C O s c illa to r C o n v e r te r E n a b le
1 : E n a b le
0 : D is a b le
T im e r 2 C lo c k S o u r c e S e le c t
R C O M 2
R C O M 1
R C O M 0
0
0
0
0
0
1
0
1
0
:
:
:
1
1
1
fS Y S
fS Y S /4
:
:
U n d e fin e d
RCOCCR Register
b 7
R C O
b 0
O V B
R C O C R
R e g is te r
In te r r u p t S o u r c e S e le c t
1 : T im e r 4 o v e r flo w
0 : T im e r 2 o v e r flo w
R C C o n v e rte r M o d e
1 : E n a b le
0 : D is a b le
U n d e fin e d , r e a d a s z e r o
RCOCR Register
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R C O M O
fS
B it
fS
Y S
Y S
/4
O V B = 0
C lo c k
S e le c t
T im e r 2
R C O C O N
E x te rn a l R C
O V B = 1
T im e r 4
R C
O S C
O s c illa tio n C o n v e r te r In te r r u p t
R e s e t R C O C O N
O u tp u t
the data in the low byte buffer will be transferred into its
associated low byte register. For this reason, when
preloading data into the 16-bit timer registers, the low
byte should be written first. It must also be noted that to
read the contents of the low byte register, a read to the
high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte
register. After this has been done, the low byte register
can be read in the normal way. Note that reading the low
byte timer register will only result in reading the previously latched contents of the low byte buffer and not the
actual contents of the low byte timer register.
Programming Considerations
As the 16-bit Timers have both low byte and high byte
timer registers, accessing these registers is carried out
in a specific way. It must be noted that when using instructions to preload data into the low byte registers,
namely TMR2L or TMR4L, the data will only be placed
into a low byte buffer and not directly into the low byte
register. The actual transfer of the data into the low byte
register is only carried out when a write to its associated
high byte register, namely TMR2H or TMR4H, is executed. However, using instructions to preload data into
the high byte timer register will result in the data being
directly written to the high byte register. At the same time
Program Example
External RC oscillation converter mode example program - Timer 2 overflow:
clr
RCOCCR
mov
a, 00000010b
; Enable External RC oscillation mode and set Timer 2
; overflow interrupt
mov
RCOCR,a
clr
intch.4
; Clear External RC Oscillation Converter interrupt
; request flag
mov
a, low (65536-1000); Give timer 2 initial value
mov
Tmr2l, a
; Timer 2 count 1000 time and then overflow
mov
a, high (65536-1000)
mov
Tmr2h, a
mov
a, 00h
; Give timer 4 initial value
mov
Tmr4l, a
mov
a, 00h
mov
Tmr4h, a
mov
a, 00110000b
; Timer 2 clock source=fSYS/4 and timer on
mov
RCOCCR, a
p10:
clr
Wdt
snz
intch.4
; Polling External RC Oscillation Converter interrupt
; request flag
jmp
p10
clr
intch.4
; Clear External RC Oscillation Converter interrupt
; request flag
; Program continue
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Analog Switch
There are 8 analog switch lines in the microcontroller, labeled as K0 ~ K7, and the Analog Switch control register, which
is mapped to the data memory by option. All of these Analog Switch lines can be used together with the external RC
Oscillation Converter for C/R-F input keys.
b 7
b 0
A S O N 3 A S O N 2 A S O N 1 A S O N 0
A S C R
R e g is te r
A n a lo g S w itc h S e le c t
A S O N 3 A S O N 2 A S O N 1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
1
1
0
1
X
1
X
A S O N 0
0
1
0
1
0
1
0
1
X
K 0 o
K 1 o
K 2 o
K 3 o
K 4 o
K 5 o
K 6 o
K 7 o
A ll o
n , o
n , o
n , o
n , o
n , o
n , o
n , o
n , o
ff, O
th e
th e
th e
th e
th e
th e
th e
th e
S C
rs o
rs o
rs o
rs o
rs o
rs o
rs o
rs o
o ff
ff
ff
ff
ff
ff
ff
ff
ff
U n d e fin e d , r e a d a s z e r o
Analog Switch Control Register - ASCR
A S O N
K 0
T .G .1
K 1
T .G .2
K 2
T .G .3
K 3
T .G .4
K 4
T .G .5
K 5
T .G .6
K 6
T .G .7
K 7
T .G .8
R C O U T
R R
R C
T im e r 4
C C
Analog Switch
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HT86BXX/HT86BRXX
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later by the application software.
No.
HT86B03/HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30 Options
I/O Options
1
PA0~PA7: wake-up enable or disable (bit option)
2
PA0~PA7: pull-high enable or disable (bit option)
3
PB0~PB7: pull-high enable or disable (bit option) - the HT86B03 device only has PB4~PB7
Oscillation Option
4
OSC type selection: RC or crystal
Interrupt Option
5
INT Triggering edge: Falling or both
Watchdog Options
6
WDT: enable or disable
7
WDT clock source: WDROSC or T1
8
CLRWDT instructions: 1 or 2 instructions
Low Voltage Reset Option
9
LVR select: enable or disable
No.
HT86B40/HT86B50/HT86B60/HT86BR60/HT86B70/HT86B80/HT86B90 Options
I/O Options
1
PA0~PA7: wake-up enable or disable
2
PA0~PA7: pull-high enable or disable
3
PB0~PB7: pull-high enable or disable
4
PD0~PD7: pull-high enable or disable
5
PB share pin select: PB0~7 or K0~7
6
PD share pin select: PD4~7 or external RC oscillation converter pin
Oscillation Option
7
OSC type selection: RC or crystal
Interrupt Option
8
INT Triggering edge: Falling or both
Watchdog Options
9
WDT: enable or disable
10
WDT clock source: WDROSC or T1
11
CLRWDT instructions: 1 or 2 instructions
Low Voltage Reset Option
12
LVR select: enable or disable
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HT86BXX/HT86BRXX
Application Circuits
HT86B03
V
T r a n s is to r O u tp u t
D D
1 0 W
V
4 7 m F
0 .1 m F
S P K
(8 W /1 6 W )
0 .1 m F
A U D
V D D A
8 0 5 0
R 1
O S C 2
V
D D
R 2
O S C 1
D D
R
V D D
O S C
P o w e r A m p lifie r O u tp u t
1 0 0 m F
1 0 0 k W
0 .1 m F
1
5
P B 4 ~ P B 7
R E S
V
C E
P A 0 ~ P A 7
A U D
D D
0 .1 m F
2
A u d io In
A U D
3
V S S
V S S A
IN T
1 0 m F
V
O U T N
V D D
H T 8 2 V 7 3 3
V R E F
N C
6
O U T P
7
D D
8
4 7 m F
S P K
(8 W /1 6 W )
4
H T 8 6 B 0 3
V
D D
1 0 W
4 7 m F
0 .1 m F
V D D A
O S C 2
V
O S C 1
D D
V D D
1 0 0 m F
4 M H z ~
8 M H z
P A 0 ~ P A 7
P B 4 ~ P B 7
1 0 0 k W
R E S
0 .1 m F
V
D D
A U D
V S S
V S S A
IN T
H T 8 6 B 0 3
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HT86BXX/HT86BRXX
HT86B10/HT86BR10/HT86B20/HT86B30/HT86BR30
V
T r a n s is to r O u tp u t
D D
1 0 W
V
4 7 m F
0 .1 m F
V D D A
S P K
(8 W /1 6 W )
0 .1 m F
A U D
V D D P
8 0 5 0
R 1
O S C 2
V
D D
R 2
O S C 1
D D
R
V D D
O S C
P o w e r A m p lifie r O u tp u t
1 0 0 m F
1 0 0 k W
V
1
5
P B 0 ~ P B 7
R E S
0 .1 m F
C E
P A 0 ~ P A 7
A U D
D D
0 .1 m F
2
A u d io In
A U D
3
V S S
V S S A
V S S P
IN T
1 0 m F
V
O U T N
V D D
H T 8 2 V 7 3 3
V R E F
N C
6
O U T P
7
D D
8
4 7 m F
S P K
(8 W /1 6 W )
4
H T 8 6 B 1 0 /H T 8 6 B R 1 0
H T 8 6 B 2 0 /H T 8 6 B 3 0 /H T 8 6 B R 3 0
V
D D
4 7 m F
V D D A
V D D P
O S C 2
V
O S C 1
D D
V D D
1 0 0 m F
R E S
V
P A 0 ~ P A 7
P B 0 ~ P B 7
1 0 0 k W
0 .1 m F
4 M H z ~
8 M H z
D D
IN T
V S S
V S S A
V S S P
P W M 1
P W M 2
S P K
(8 W /1 6 W )
H T 8 6 B 1 0 /H T 8 6 B R 1 0
H T 8 6 B 2 0 /H T 8 6 B 3 0 /H T 8 6 B R 3 0
N o te : T h e P W M
Rev. 1.80
a p p lic a tio n r e fe r to th e d e s c r ip tio n o f P u ls e W id th M o d u la tio n O u tp u t.
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HT86BXX/HT86BRXX
HT86B40/HT86B50/HT86B60/HT86BR60
V
T r a n s is to r O u tp u t
D D
1 0 W
V
4 7 m F
0 .1 m F
V D D A
S P K
(8 W /1 6 W )
0 .1 m F
A U D
V D D P
8 0 5 0
R 1
O S C 2
V
D D
R 2
O S C 1
D D
R
V D D
O S C
P o w e r A m p lifie r O u tp u t
1 0 0 m F
P A 0 ~ P A 7
1 0 0 k W
V
0 .1 m F
C E
1
5
P B 0 ~ P B 7
R E S
A U D
P D 4 ~ P D 7
D D
0 .1 m F
A U D
A u d io In
3
V S S
V S S A
V S S P
IN T
2
1 0 m F
V
O U T N
V D D
H T 8 2 V 7 3 3
V R E F
N C
6
O U T P
7
D D
8
4 7 m F
S P K
(8 W /1 6 W )
4
H T 8 6 B 4 0 /H T 8 6 B 5 0 /H T 8 6 B 6 0 /H T 8 6 B R 6 0
V
D D
4 7 m F
V D D A
V D D P
O S C 2
V
O S C 1
D D
V D D
1 0 0 m F
4 M H z ~
8 M H z
P A 0 ~ P A 7
P B 0 ~ P B 7
1 0 0 k W
P D 4 ~ P D 7
R E S
0 .1 m F
V
V S S
V S S A
V S S P
D D
IN T
P W M 1
P W M 2
S P K
(8 W /1 6 W )
H T 8 6 B 4 0 /H T 8 6 B 5 0 /H T 8 6 B 6 0 /H T 8 6 B R 6 0
N o te : T h e P W M
Rev. 1.80
a p p lic a tio n r e fe r to th e d e s c r ip tio n o f P u ls e W id th M o d u la tio n O u tp u t.
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HT86BXX/HT86BRXX
HT86B70/HT86B80/HT86B90
V
T r a n s is to r O u tp u t
D D
1 0 W
V
4 7 m F
0 .1 m F
V D D A
S P K
(8 W /1 6 W )
0 .1 m F
A U D
V D D P
8 0 5 0
R 1
O S C 2
V
D D
R 2
O S C 1
D D
R
V D D
O S C
P o w e r A m p lifie r O u tp u t
1 0 0 m F
P A 0 ~ P A 7
1 0 0 k W
V
0 .1 m F
C E
1
5
P B 0 ~ P B 7
R E S
A U D
P D 0 ~ P D 7
D D
0 .1 m F
A U D
A u d io In
3
V S S
V S S A
V S S P
IN T
2
1 0 m F
V
O U T N
V D D
H T 8 2 V 7 3 3
V R E F
N C
6
O U T P
7
D D
8
4 7 m F
S P K
(8 W /1 6 W )
4
H T 8 6 B 7 0 /H T 8 6 B 8 0 /H T 8 6 B 9 0
V
D D
4 7 m F
V D D A
V D D P
O S C 2
V
O S C 1
D D
V D D
1 0 0 m F
4 M H z ~
8 M H z
P A 0 ~ P A 7
P B 0 ~ P B 7
1 0 0 k W
P D 0 ~ P D 7
R E S
0 .1 m F
V
V S S
V S S A
V S S P
D D
IN T
P W M 1
P W M 2
S P K
(8 W /1 6 W )
H T 8 6 B 7 0 /H T 8 6 B 8 0 /H T 8 6 B 9 0
N o te : T h e P W M
Rev. 1.80
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HT86BXX/HT86BRXX
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.80
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HT86BXX/HT86BRXX
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.80
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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HT86BXX/HT86BRXX
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.80
67
March 12, 2010
HT86BXX/HT86BRXX
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.80
68
March 12, 2010
HT86BXX/HT86BRXX
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.80
69
March 12, 2010
HT86BXX/HT86BRXX
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.80
70
March 12, 2010
HT86BXX/HT86BRXX
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.80
71
March 12, 2010
HT86BXX/HT86BRXX
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.80
72
March 12, 2010
HT86BXX/HT86BRXX
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.80
73
March 12, 2010
HT86BXX/HT86BRXX
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.80
74
March 12, 2010
HT86BXX/HT86BRXX
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.80
75
March 12, 2010
HT86BXX/HT86BRXX
Package Information
24-pin SSOP (150mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.228
¾
0.244
B
0.150
¾
0.157
C
0.008
¾
0.012
C¢
0.335
¾
0.346
D
0.054
¾
0.060
E
¾
0.025
¾
F
0.004
¾
0.010
G
0.022
¾
0.028
H
0.007
¾
0.010
a
0°
¾
8°
Symbol
Dimensions in mm
Min.
Nom.
Max.
5.79
¾
6.20
B
3.81
¾
3.99
C
0.20
¾
0.30
C¢
8.51
¾
8.79
D
1.37
¾
1.52
E
¾
0.64
¾
F
0.10
¾
0.25
G
0.56
¾
0.71
H
0.18
¾
0.25
a
0°
¾
8°
A
Rev. 1.80
a
F
76
March 12, 2010
HT86BXX/HT86BRXX
24-pin SSOP (209mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
a
F
· MO-150
Symbol
A
Min.
Nom.
Max.
0.291
¾
0.323
B
0.197
¾
0.220
C
0.009
¾
0.013
C¢
0.311
¾
0.335
D
¾
¾
0.079
E
¾
0.026
¾
F
0.002
¾
¾
G
0.022
¾
0.037
H
0.004
¾
0.008
a
0°
¾
8°
Symbol
Rev. 1.80
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
7.40
¾
8.20
B
5.00
¾
5.60
C
0.22
¾
0.33
C¢
7.90
¾
8.50
D
¾
E
¾
0.65
2.00
¾
F
0.05
¾
¾
G
0.55
¾
0.95
H
0.09
¾
0.21
a
0°
¾
8°
77
March 12, 2010
HT86BXX/HT86BRXX
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
a
F
· MS-013
Symbol
A
Min.
Nom.
Max.
0.393
¾
0.419
B
0.256
¾
0.300
C
0.012
¾
0.020
C¢
0.697
¾
0.713
D
¾
¾
0.104
E
¾
0.050
¾
F
0.004
¾
0.012
G
0.016
¾
0.050
H
0.008
¾
0.013
a
0°
¾
8°
Symbol
Rev. 1.80
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
9.98
¾
10.64
B
6.50
¾
7.62
C
0.30
¾
0.51
C¢
17.70
¾
18.11
D
¾
¾
2.64
E
¾
1.27
¾
F
0.10
¾
0.30
G
0.41
¾
1.27
H
0.20
¾
0.33
a
0°
¾
8°
78
March 12, 2010
HT86BXX/HT86BRXX
44-pin QFP (10mm´10mm) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
L
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.512
¾
0.528
B
0.390
¾
0.398
C
0.512
¾
0.528
D
0.390
¾
0.398
E
¾
0.031
¾
F
¾
0.012
¾
G
0.075
¾
0.087
H
¾
¾
0.106
I
0.010
¾
0.020
J
0.029
¾
0.037
K
0.004
¾
0.008
L
¾
0.004
¾
a
0°
¾
7°
Symbol
A
Rev. 1.80
1 1
Dimensions in mm
Min.
Nom.
Max.
13.00
¾
13.40
B
9.90
¾
10.10
C
13.00
¾
13.40
D
9.90
¾
10.10
E
¾
0.80
¾
F
¾
0.30
¾
G
1.90
¾
2.20
H
¾
¾
2.70
I
0.25
¾
0.50
J
0.73
¾
0.93
K
0.10
¾
0.20
L
¾
0.10
¾
a
0°
¾
7°
79
March 12, 2010
HT86BXX/HT86BRXX
100-pin QFP (14mm´20mm) Outline Dimensions
C
H
D
8 0
G
5 1
I
5 0
8 1
F
A
B
E
3 1
1 0 0
a
K
J
1
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.728
¾
0.756
B
0.547
¾
0.555
C
0.965
¾
0.992
D
0.783
¾
0.791
E
¾
0.026
¾
F
¾
0.012
¾
G
0.098
¾
0.122
H
¾
¾
0.134
I
¾
0.004
¾
J
0.039
¾
0.055
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
A
Rev. 1.80
3 0
Dimensions in mm
Min.
Nom.
Max.
18.50
¾
19.20
B
13.90
¾
14.10
C
24.50
¾
25.20
D
19.90
¾
20.10
E
¾
0.65
¾
F
¾
0.30
¾
G
2.50
¾
3.10
H
¾
¾
3.40
I
¾
0.1
¾
J
1.00
¾
1.40
K
0.10
¾
0.20
a
0°
¾
7°
80
March 12, 2010
HT86BXX/HT86BRXX
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 24S (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
13.0
+0.5/-0.2
2.0±0.5
16.8
+0.3/-0.2
22.2±0.2
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.80
13.0
+0.5/-0.2
2.0±0.5
24.8
+0.3/-0.2
30.2±0.2
81
March 12, 2010
HT86BXX/HT86BRXX
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SSOP 24S (150mil)
Symbol
Description
W
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
Dimensions in mm
16.0
+0.3/-0.1
8.0±0.1
1.75±0.10
7.5±0.1
1.5
+0.1/-0.0
1.5
+0.25/-0.0
D1
Cavity Hole Diameter
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.5±0.1
K0
Cavity Depth
2.1±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5
D1
Cavity Hole Diameter
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
Rev. 1.80
1.5
+0.1/-0.0
+0.25/-0.0
82
March 12, 2010
HT86BXX/HT86BRXX
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.80
83
March 12, 2010