eorex EM42BM1684RTA 512Mb (8M×4Bank×16) Double DATA RATE SDRAM Features Description • Internal Double-Date-Rate architecture with 2 Accesses per clock cycle. • Single 2.5V ±0.2V Power Supply • 2.5V SSTL-2 compatible I/O • Burst Length (B/L) of 2, 4, 8 • 2,2.5,3 Clock read latency • Bi-directional,intermittent data strobe(DQS) • All inputs except data and DM are sampled at the positive edge of the system clock. • Data Mask (DM) for write data • Sequential & Interleaved Burst type available • Auto Precharge option for each burst accesses • DQS edge-aligned with data for Read cycles • DQS center-aligned with data for Write cycles • DLL aligns DQ & DQS transitions with CLK transition • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms The EM42BM1684RTA is high speed Synchronous graphic RAM fabricated with ultra high performance CMOS process containing 536,870,912 bits which organized as 8Meg words x 4 banks by 16 bits. The 512Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and It transfers the datafor both rising and falling edges of the system clock.It means the doubled data bandwidth can be achieved at the I/O pins. Available packages:TSOPII 66P 400mil. Ordering Information Package Grade Pb EM42BM1684RTA-75F Part No Organization 32M X 16 133MHz @CL25 Max. Freq 66pin TSOP(ll) Commercial Free EM42BM1684RTA-6F 32M X 16 166MHz @CL25 66pin TSOP(ll) Commercial Free EM42BM1684RTA-5F 32M X 16 200MHz @CL3 66pin TSOP(ll) Commercial Free * EOREX reserves the right to change products or specification without notice. Jul. 2006 www.eorex.com 1/19 eorex EM42BM1684RTA Pin Assignment 66pin TSOP-II / (400mil × 875mil) / (0.65mm Pin pitch) Jul. 2006 www.eorex.com 2/19 eorex EM42BM1684RTA Pin Description (Simplified) Pin Name 45,46 CLK,/CLK 24 /CS 44 CKE 28~32,35~42 A0~A12 26, 27 BA0, BA1 23 /RAS 22 /CAS 21 /WE 16/51 LDQS/UDQS 20/47 LDM/UDM 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 1,18,33/ 34,48,66 3, 9, 15, 55.61/ 6, 12, 52, 58,64 14,17,19,25,43, 50,53 49 DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC/RFU VREF Function (System Clock) Clock input active on the Positive rising edge except for DQ and DM are active on both edge of the DQS. CLK and /CLK are differential clock inputs. (Chip Select) /CS enables the command decoder when ”L” and disable the command decoder when “H”.The new command are overLooked when the command decoder is disabled but previous operation will still continue. (Clock Enable) Activates the CLK when “H” and deactivates when “L”. When deactivate the clock,CKE low signifies the power down or self refresh mode. (Address) Row address (A0 to A12) and Calumn address (CA0 to CA8) are multiplexed on the same pin. CA10 defines auto precharge at Calumn address. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output) Data Inputs and Outputs are synchronized with both edge of DQS. (Data Input/Output Mask) DM controls data inputs.LDM corresponds to the data on DQ0~DQ7.UDM corresponds to the data on DQ8~DQ15. (Data Input/Output) Data inputs and outputs are multiplexed on the same pin. (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection/Reserved for Future Use) This pin is recommended to be left No Connection on the device. (Input) SSTL-2 Reference voltage for input buffer. Jul. 2006 www.eorex.com 3/19 eorex EM42BM1684RTA Absolute Maximum Rating Symbol Item VIN, VOUT Input, Output Voltage VDD, VDDQ Power Supply Voltage TOP TSTG Rating Units -0.3 ~ +3.6 V -0.3 ~ +3.6 Commercial 0 ~ +70 Extended N/A -55 ~ +150 Operating Temperature Range Storage Temperature Range V °C °C PD Power Dissipation 1 W IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=2.5V, f=1MHz, TA=25°C) Symbol Parameter Min. CCLK Clock Capacitance(CLK,/CLK) Input Capacitance for CKE, Address, /CS, /RAS, /CAS, /WE DM,Data&DQS Input/Output Capacitance CI CO Typ. Max. Units 2 3 pF 2 3 pF 4 5 pF Recommended DC Operating Conditions (TA=-0°C ~+70°C) Symbol VDD VDDQ VREF VTT Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) I/O Logic high Voltage Min. Typ. Max. Units 2.3 2.3 1.15 2.5 2.5 1.25 2.7 2.7 1.35 V V V VREF+0.04 V I/O Termination Voltage VREF-0.04 VIH Input Logic High Voltage VREF+0.18 VDDQ+0.3 V VIL Input Logic Low Voltage -0.3 VREF-0.18 V Jul. 2006 www.eorex.com 4/19 eorex EM42BM1684RTA Recommended DC Operating Conditions (VDD=2.5V±0.2V, TA=0°C ~ 70°C) Symbol Parameter (Note 1) Max. Test Conditions Burst length=2, tRC≥tRC(min.), IOL=0mA, One bank active -5 -6 -75 110 100 100 Units IDD1 Operating Current IDD2P Precharge Standby Current in Power Down Mode CKE≤VIL(max.), tCK=min 6 mA IDD2N Precharge Standby Current in Non-power Down Mode CKE≥VIL(min.), tCK=min, /CS≥VIH(min.) Input signals are changed one time during 2 clks 30 mA IDD3P Active Standby Current in Power Down Mode CKE≤VIL(max.), tCK=min 15 mA IDD3N Active Standby Current in Non-power Down Mode 50 mA IDD4 Operating Current (Burst (Note 2) Mode) IDD5 Refresh Current IDD6 Self Refresh Current (Note 3) CKE≥VIH(min.), tCK=min, /CS≥VIH(min.) Input signals are changed one time during 2 clks READ tCK ≥ tCK(min.), IOL=0mA, All banks active WRITE 130 mA 140 tRC≥ tRFC (min.), All banks active CKE≤0.2V mA 200 mA 5 mA *All voltages referenced to VSS. Note 1: IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Min. of tRFC (Auto refresh Row Cycle Times) is shown at AC Characteristics. Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions IIL Input Leakage Current IOL Output Leakage Current 0≤VI≤VDDQ, VDDQ=VDD All other pins not under test=0V 0≤VO≤VDDQ, DOUT is disabled VOH High Level Output Voltage IO=-16.8mA VOL Low Level Output Voltage IO=+16.8mA Jul. 2006 Min. Max. Units -5 +5 uA -5 +5 uA VDDQ-0.373 V 0.373 V www.eorex.com 5/19 eorex EM42BM1684RTA Block Diagram Auto/ Self Refresh Counter A0 A1 DM A5 A6 A7 A8 A9 Address Register A4 Row Decoder A3 Row Add. Buffer A2 Memory Array Write DQM Control Data In DOi S/ A & I/ O Gating A10 A11 Data Out Col. Decoder A12 BA0 BA1 Col. Add. Buffer Mode Register Set Col Add. Counter Burst Counter Timing Register /CLK CLK CKE /CS / RAS / CAS Jul. 2006 / WE DM DQS www.eorex.com 6/19 eorex EM42BM1684RTA AC Operating Test Conditions (VDD=2.5V±0.2V, TA=0°C ~70°C) Item Conditions Output Reference Level 1.25V/1.25V Output Load See diagram as below Input Signal Level VREF+0.31V/ VREF-0.31V Transition Time of Input Signals 1ns Input Reference Level VDDQ/2 AC Operating Test Characteristics (VDD=2.5V±0.2V, TA=0°C ~70°C) Symbol -5 Parameter -6 Min. Max. Min. Max. Min. -7.5 Max. Units tDQCK DQ output access from CLK,/CLK -0.65 0.65 -0.7 0.7 -0.75 0.75 ns tDQSCK DQS output access from CLK,/CLK -0.55 0.55 -0.6 0.6 -0.75 0.75 ns tCL,tCH CL low/high level width tCK tDH,tDS tDIPW tHZ,tLZ tDQSQ tDQSS tDSL,tDS Clock Cycle Time 0.45 0.55 0.45 0.55 0.45 0.55 tCK CL=2 - - 7.5 12 10 12 ns CL=2.5 6 12 6 12 7.5 12 ns CL=3 5 12 - - - - ns DQ and DM hold/setup time DQ and DM input pulse width for each input Data out high/low impedance time from CLK,/CLK DQS-DQ skew for associated DQ signal Write command to first latching DQS transition 0.4 0.45 0.5 ns 1.75 1.75 1.75 ns -0.7 0.7 -0.7 0.4 0.7 DQS input valid window 0.7 -0.75 0.45 1.25 0.75 0.75 0.5 1.25 0.75 ns 1.25 tWPRES tWPST tIH,tIS tRPRE Mode Register Set command cycle time Write Preamble setup time Write Preamble Address/control input hold/setup time Read Preamble 0.35 0.35 tCK 2 2 2 tCK 0 0.4 0 0.6 0.4 0.7 0.9 Jul. 2006 tCK 0.35 H tMRD ns 0 0.6 0.8 1.1 0.9 ns 0.4 0.6 1.0 1.1 0.9 tCK ns 1.1 tCK www.eorex.com 7/19 eorex EM42BM1684RTA AC Operating Test Characteristics (Continued) (VDD=2.5V±0.2V, TA=0°C ~70°C) Symbol tRPST Parameter -5 -6 Min. 0.4 Max. 0.6 Min. 0.4 Max. 0.6 Min. 0.4 40 70k 42 70k 45 -75 Max. 0.6 Units tRC Read Postamble Active to Precharge command period Active to Active command period 55 60 65 ns tRFC Auto Refresh Row Cycle Time 70 72 75 ns tRCD Active to Read or Write delay 15 18 20 ns tRP Precharge command period 15 18 20 ns tRRD Active bank A to B command period 10 12 15 ns tCCD Column address to column address delay 1 1 1 tCK tCDLR Last data in to Read command 2.5 tCK- tDQSS 2.5 tCK- tDQSS 2.5 tCK- tDQSS tCK tCDLW Last data in to Write command 0 0 0 tCK 2 2 2 tCK 75 75 75 ns tXSRD Last data in to Precharge command Exit self Refresh to non-read command Exit self Refresh to read command 200 200 200 ns tREFI Average periodic refresh interval tRAS tDPL tXSNR 15.6 Jul. 2006 15.6 70k 15.6 tCK ns us www.eorex.com 8/19 eorex EM42BM1684RTA Simplified State Diagram Jul. 2006 www.eorex.com 9/19 eorex EM42BM1684RTA 1. Command Truth Table Command Symbol Ignore Command DESL CKE n-1 n /CS /RAS /CAS /WE BA0, BA1 A10 A12~A0 H X H X X X X X X No Operation NOP H X L H H H X X X Burst Stop BSTH H X L H H L X X X Read READ H X L H L H V L V Read with Auto Pre-charge READA H X L H L H V H V Write WRIT H X L H L L V L V Write with Auto Pre-charge WRITA H X L L H H V H V Bank Activate ACT H X L L H H V V V Pre-charge Select Bank PRE H X L L H L V L X Pre-charge All Banks PALL H X L L H L X H X Mode Register Set MRS H X L L L L L L V H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. CKE Truth Table Item Command Symbol CKE n-1 n H H Idle CBR Refresh Command REF Idle Self Refresh Entry SELF Self Refresh Self Refresh Exit Idle Power Down Entry Power Down Power Down Exit L /CS /RAS /CAS /WE Addr. L L L H X H L L L L L H X H L H H H X L H H X X X X H L X X X X X H X X X X X Remark H = High level, L = Low level, X = High or Low level (Don't care) Jul. 2006 www.eorex.com 10/19 eorex EM42BM1684RTA 3. Operative Command Table Current State Idle Row Active /CS /R /C /W Addr. Command H X X X X DESL NOP L H H H X NOP NOP L H H L X TERM NOP L H L X BA/CA/A10 READ/WRIT/BW L L H H BA/RA ACT L L H L BA, A10 PRE/PREA L L L H REFA L L L L MRS Mode register H L X H X H X H X Op-Code, Mode-Add X X NOP (Note 4) Auto refresh DESL NOP L H H L BA/CA/A10 READ/READA L H L L BA/CA/A10 WRIT/WRITA NOP NOP Begin read,Latch CA, Determine auto-precharge Begin write,Latch CA, Determine auto-precharge L L H H BA/RA ACT L L H L BA/A10 PRE/PREA L L L H REFA ILLEGAL L L L L MRS ILLEGAL H L L X H H X H H X H L X Op-Code, Mode-Add X X X DESL NOP TERM L H L H BA/CA/A10 READ/READA Read Write Action ILLEGAL (Note 1) Bank active,Latch RA (Note 3) ILLEGAL (Note 1) Precharge/Precharge all NOP(Continue burst to end) NOP(Continue burst to end) Terminal burst Terminate burst,Latch CA, Begin new read, L L H H BA/RA ACT Determine Auto-precharge (Note 1) ILLEGAL L L L L H L L H PRE/PREA REFA Terminate burst, PrecharE ILLEGAL L L L L H L L X H H X H H X H L BA, A10 X Op-Code, Mode-Add X X X L H L H BA/CA/A10 READ/READA L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT L L H L BA, A10 PRE/PREA L L L L L L H L X Op-Code, REFA MRS MRS DESL NOP TERM ILLEGAL NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL Terminate burst with DM=”H”,Latch CA,Begin read,Determine (Note 2) auto-precharge Terminate burst,Latch CA,Begin Jul. 2006 new write, Determine (Note 2) auto-precharge ILLEGAL (Note 1) Terminate burst with DM=”H”, Precharge ILLEGAL ILLEGAL www.eorex.com 11/19 eorex EM42BM1684RTA 3. Operative Command Table (Continued) Current State Read with AP Write with AP Pre-charging Row Activating /CS /R /C /W Addr. Command H L L L X H H H X H H L X H L X X X BA/CA/A10 BA/RA DESL NOP TERM READ/WRITE L L H H BA/A10 ACT ILLEGAL L L L L H L L H PRE/PREA REFA ILLEGAL ILLEGAL L L L L MRS ILLEGAL H L L L X H H H X H H L X H L X X X Op-Code, Mode-Add X X X BA/CA/A10 DESL NOP TERM READ/WRITE L L H H BA/RA ACT ILLEGAL L L L L H L L H PRE/PREA REFA ILLEGAL ILLEGAL L L L L MRS ILLEGAL H L L L X H H H X H H L X H L X BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 DESL NOP TERM READ/WRITE L L H H BA/RA ACT L L L L H L L H PRE/PREA REFA L L L L H L L L X H H H X H H L X H L X BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 DESL NOP TERM READ/WRITE L L H H BA/RA ACT ILLEGAL L L L L H L L H PRE/PREA REFA ILLEGAL ILLEGAL L L L L BA/A10 X Op-Code, Mode-Add MRS ILLEGAL MRS Action NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL (Note 1) (Note 1) NOP(Continue burst to end) NOP(Continue burst to end) ILLEGAL (Note 1) ILLEGAL (Note 1) (Note 1) NOP(idle after tRP) NOP(idle after tRP) NOP (Note 1) ILLEGAL (Note 1) ILLEGAL (Note 3) NOP(idle after tRP) ILLEGAL ILLEGAL NOP(Row active after tRCD) NOP(Row active after tRCD) NOP (Note 1) ILLEGAL (Note 1) (Note 1) Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Jul. 2006 www.eorex.com 12/19 eorex EM42BM1684RTA 3. Operative Command Table (Continued) Current State Write Recovering Refreshing /CS /R /C /W Addr. Command H L L L X H H H X H H L X H L H X X X BA/CA/A10 DESL NOP TERM READ L H L L BA/CA/A10 WRIT/WRITA L L H H BA/RA ACT ILLEGAL L L L L H L L H PRE/PREA REFA ILLEGAL ILLEGAL L L L L MRS ILLEGAL H L L L L L L X H H H L L L X H H L H H L X H L X H L H L L L L BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add DESL NOP TERM READ/WRIT ACT PRE/PREA REFA MRS Action NOP NOP NOP (Note 1) ILLEGAL New write, Determine AP (Note 1) (Note 1) NOP(idle after tRP) NOP(idle after tRP) NOP ILLEGAL ILLEGAL NOP(idle after tRP) ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 1: ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 2: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 3: NOP to bank precharging or in idle state.May precharge bank indicated by BA. Note 4: ILLEGAL of any bank is not idle. Jul. 2006 www.eorex.com 13/19 eorex EM42BM1684RTA 4. Command Truth Table for CKE Current State Self Refresh Both bank precharge power down All Banks Idle Any State Other than Listed above CKE n-1 n H X L H L H L H L H L H L L H X L H L H L H L H L H L L H H H L H L H L H L H L L H L H L H /CS /R /C /W Addr. X H L L L L X X H L L L L X X H X X H H H L X X X H H H L X X X X X H H L X X X X H H L X X X X X X H L X X X X X H L X X X X X X X X X X X X X X X X X X X X X L L L L L L L H H H L L L L H H L H L L L H L X H H L L X X X RA X Op-Code Op-Code Action INVALID Exist Self-Refresh Exist Self-Refresh ILLEGAL ILLEGAL ILLEGAL NOP(Maintain self refresh) INVALID Exist Power down Exist Power down ILLEGAL ILLEGAL ILLEGAL NOP(Maintain Power down) Refer to function true table (Note 3) Enter power down mode (Note 3) Enter power down mode ILLEGAL ILLEGAL Row active/Bank active (Note 3) Enter self-refresh Mode register access Special mode register access L X X X X X X Refer to current state H H X X X X X Refer to command truth table Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 1: After CKE’s low to high transition to exist self refresh mode.And a time of tRC(min) has to be Elapse after CKE’s low to high transition to issue a new command. Notes 2:CKE low to high transition is asynchronous as if restarts internal clock. Notes 3:Power down and self refresh can be entered only from the idle state of all banks. Jul. 2006 www.eorex.com 14/19 eorex EM42BM1684RTA Mode Register Definition Mode Register Set The mode register stores the data for controlling the various operating modes of DDR SDRAM which contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor’s specific opinions. The defaults values of the register is not defined, so the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A7 must be set to low for normal MRS operation. Jul. 2006 www.eorex.com 15/19 eorex EM42BM1684RTA Address input for Mode Register Set ( MRS ) BA1 BA0 A12/11 A10 A9 A8 A7 A6 Operation Mode A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length Burst Length Sequential Interleave A2 A1 A0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 Reserved Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Full Page Reserved 1 1 1 DLL Reset A8 A7 Operation Mode Burst Type A3 NO 0 0 Normal Interleave 1 Yes 1 1 Test Sequential 0 CAS Latency A6 A5 A4 Reserved 0 0 0 Reserved 0 0 1 2 0 1 0 3 0 1 1 Reserved 1 0 0 Reserved 1 0 1 2.5 1 1 0 Reserved 1 1 1 BA0 An ~A0 0 MRS Cycle 1 EMRS Cycle Jul. 2006 www.eorex.com 16/19 eorex EM42BM1684RTA Burst Type (A3) Burst Length 2 4 8 A2 A1 A0 Sequential Addressing X X 0 01 01 X X 0 10 10 X 0 0 0123 0123 X 0 1 1230 1032 X 1 0 2301 2301 X 1 1 3012 3210 0 0 0 01234567 01234567 0 0 1 12345670 10325476 0 1 0 23456701 23016745 0 1 1 34567012 32107654 1 0 0 45670123 45670123 1 0 1 56701234 54761032 1 1 0 67012345 67452301 1 1 1 70123456 *Page length is a function of I/O organization and column addressing Interleave Addressing 76543210 DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disable the DLL for the purpose of debug or evaluation ( upon existing Self Refresh Mode, the DLL is enable automatically. ) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength got all outputs is specified to be SSTL-2, Class II. Some vendors might also support a weak drive strength option, intended for lighter load and/or point to point environments. Jul. 2006 www.eorex.com 17/19 eorex EM42BM1684RTA Extended Mode Register Set ( EMRS ) The Extended mode register stores the data enabling or disabling DLL. The value of the extended mode register is not defined, so the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA0 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. BA1 BA0 0 1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 RFU :Must be set as 0 QFC control A2 Disable 0 0 Enable BA0 MRS Mode 0 MRS 1 EMRS Jul. 2006 A2 A1 A0 /QFC D.I.C DLL 1 DLL Rest A0 Enable 0 Disable 1 Output Driver Impedance Control A1 Normal 0 Weak 1 www.eorex.com 18/19 eorex EM42BM1684RTA Package Description Jul. 2006 www.eorex.com 19/19