Fairchild FAN8035 6-ch motor driver Datasheet

www.fairchildsemi.com
FAN8035
6-CH Motor Driver
Features
Description
•
•
•
•
•
•
•
•
The FAN8035 is a monolithic integrated circuit suitable for
a 6-CH motor driver which drives the tracking actuator,
focus actuator, sled motor, spindle motor, and tray motor of
the CDP/CAR-CD/DVDP systems.
5-CH Balanced Transformerless (BTL) Driver
1-CH (Forward Reverse) Control DC Motor Driver
Operating Supply Voltage (4.5 V ~ 13.2 V)
Built in Thermal Shut Down Circuit (TSD)
Built in Channel Mute Circuit
Built in Power Save Mode Circuit
Built in TSD Monitor Circuit
Built in 2-OP AMPs
Typical Application
•
•
•
•
Compact Disk Player
Video Compact Disk Player
Car Compact Disk Player
Digital Video Disk Player
48-QFPH-1414
Ordering Information
Device
Package
Operating Temperature
FAN8035
48-QFPH-1414
-35°C ~ +85°C
FAN8035L
48-QFPH-1414
-35°C ~ +85°C
48-QFPH-1414
-35°C ~ +85°C
note
FAN8035_NL
Note:
NL : Lead free Type
Rev. 1.0.4
©2003 Fairchild Semiconductor Corporation
FAN8035
40
DO1+
41
PVCC1
42
OPOUT2
43
OPIN2−
44
FIN
(GND)
PS
45
OPIN2+
OPOUT1
OPIN1−
46
VREF
47
SVCC
48
OPIN1+
IN1+
Pin Assignments
39
38
37
IN1−
1
36
DO1−
OUT1
2
35
DO2+
IN2+ 3
34
DO2−
IN2− 4
33
PGND1
OUT2 5
32
DO3+
31
DO3−
IN3+
6
FIN
(GND)
FIN
(GND)
FAN8035
IN3−
7
30
DO4+
OUT3
8
29
DO4−
IN4+
9
28
DO5+
27
DO5−
IN4− 10
OUT4 11
26 PGND2
IN5+ 12
2
21
22
23
24
TSD-M
PVCC2
DO6−
20
MUTE34
19
(GND)
FIN
MUTE12
18
SGND
17
REV
16
FWD
15
CTL
14
OUT5
IN5−
13
MUTE5
25
DO6+
FAN8035
Pin Definitions
Pin Number
Pin Name
I/O
Pin Function Description
1
IN1-
I
CH1 OP-AMP Input (-)
2
OUT1
O
CH1 OP-AMP Output
3
IN2+
I
CH2 OP-AMP Input (+)
4
IN2-
I
CH2 OP-AMP Input (-)
5
OUT2
O
CH2 OP-AMP Output
6
IN3+
I
CH3 OP-AMP Input (+)
7
IN3-
I
CH3 OP-AMP Input (-)
8
OUT3
O
CH3 OP-AMP Output
9
IN4+
I
CH4 OP-AMP Input (+)
10
IN4-
I
CH4 OP-AMP Input (-)
11
OUT4
O
CH4 OP-AMP Output
12
IN5+
I
CH5 OP-AMP Input (+)
13
IN5-
I
CH5 OP-AMP Input (-)
14
OUT5
O
CH5 OP-AMP Output
15
CTL
I
CH6 Motor Speed Control
16
FWD
I
CH6 Forward Input
17
REV
I
CH6 Reverse Input
18
SGND
-
Signal Ground
19
MUTE12
I
Mute For CH1,2
20
MUTE34
I
Mute For CH3,4
21
MUTE5
I
Mute For CH5
22
TSD-M
O
TSD Monitor
23
PVCC2
-
Power Supply Voltage 2 (For CH5, CH6)
24
DO6-
O
CH6 Drive Ouptut (-)
25
DO6+
O
CH6 Drive Output (+)
26
PGND2
-
Power Ground 2 (FOR CH5, CH6)
27
DO5-
O
CH5 Drive Ouptut (-)
28
DO5+
O
CH5 Drive Output (+)
29
DO4-
O
CH4 Drive Ouptut (-)
30
DO4+
O
CH4 Drive Output (+)
31
DO3-
O
CH3 Drive Ouptut (-)
32
DO3+
O
CH3 Drive Output (+)
3
FAN8035
Pin Definitions (Continued)
4
Pin Number
Pin Name
I/O
Pin Function Description
33
PGND1
-
Power Ground 1 (FOR CH1, CH2, CH3, CH4)
34
DO2-
O
CH2 Drive Ouptut (-)
35
DO2+
O
CH2 Drive Output (+)
36
DO1-
O
CH1 Drive Ouptut (-)
37
DO1+
O
CH1 Drive Output (+)
38
PVCC1
-
Power Supply Voltage 1 (FOR CH1, CH2, CH3, CH4)
39
PS
I
Power Save
40
OPOUT2
O
Normal OP-AMP2 output
41
OPIN2-
I
Normal OP-AMP2 Input (-)
42
OPIN2+
I
Normal OP-AMP2 Input (+)
43
VREF
I
Bias Voltage Input
44
SVCC
-
Signal & OPAMPs Supply Voltage
45
OPOUT1
O
Normal OP-AMP1 Output
46
OPIN1-
I
Normal OP-AMP1 Input (-)
47
OPIN1+
I
Normal OP-AMP1 Input (+)
48
IN1+
I
CH1 OP-AMP Intput (+)
FAN8035
Internal Block Diagram
IN1+
48
IN1−
1
OUT1
2
IN2+
3
OPIN1+ OPIN1− OPOUT1 SVCC
47
46
45
FIN
(GND)
VREF
44
43
−
+
OPIN2+ OPIN2− OPOUT2
42
41
40
−
+
− +
PS
PVCC1
39
38
DO1+
37
POWER SAVE
36
DO1−
35
DO2+
−
+
+
−
+
−
34 DO2−
−
IN2−
4
OUT2
5
+
+
−
+
−
33
PGND1
32
DO3+
31
DO3−
−
IN3+
+
6
+
−
+
−
FIN
(GND)
FIN
(GND)
−
T.S.D
IN3−
OUT3
7
+
+
−
30
DO4+
29
DO4−
28
DO5+
27
DO5−
26
PGND2
25
DO6+
+
−
8
−
+
IN4+
9
IN4−
10
OUT4
11
IN5+
12
+
−
M
S
C
S
W
+
D
−
D
MUTE12
13
IN5−
Note.
+
−
14
OUT5
15
CTL
16
FWD
17
18
REV
SGND
19
MUTE34 MUTE5
20
21
TSD-M
22
23
24
(GND) MUTE12 MUTE34 MUTE5 TSD-M PVCC2 DO6−
FIN
Detailed circuit of the output power amp
40K
10K
From input opamp
Vref
10K
Pref
10K
−
+
40K
DO+
40K
+
DO-
−
10K
40K
Pref1 is almost PVCC1 / 2
Pref2 is almost PVCC2 / 2
5
FAN8035
Equivalent Circuits
Description
Pin No
Internal Circuit
VCC
BTL INPUT
&
OP-AMP1 INPUT
1,4,7,10,13,46
3,6,9,12,47,48
VCC
2K
2K
3
6
1
4
9
12
7
10
47
48
13
46
VCC
VCC
5K
OP-AMP2 INPUT
5K
41,42
42
41
VCC
VCC
1K
VREF
43
43
1K
VCC
BTL OP-AMP OUT
&
OP-AMP1 OUT
6
2,5,8,11,14,45
5K
2
5
8
11
14
45
VCC
FAN8035
Equivalent Circuits (Continued)
Description
Pin No
Internal Circuit
VCC
VCC
OP-AMP2 OUT
40
0.05k
40
0.05k
VCC
20K
MUTE12,34,5
19,20,21
19
50K
20
21
50K
VCC
CTL
15
1K
15
39K
TSD-M
22
22
20k
7
FAN8035
Equivalent Circuits (Continued)
Description
Pin No
Internal Circuit
VCC
100k
PS
39
50K
39
50K
VCC
30K
FWD,REV
16,17
30K
17
30K
16
30K
freewheeling diode
vcc VCC
BTL CH1,2,3,4,5
OUTPUT
27,28,29,30,31
32,34,35,36,37
27
28
29
30
40
31
32
34
35
36
37
VCC
40K
7K
parastic diode
freewheeling diode VCC
vcc
BTL CH6
OUTPUT
24,25
24
VCC
25
60K
7K
parastic diode
8
FAN8035
Absolute Maximum Ratings ( Ta=25°C)
Parameter
Maximum Supply Voltage
Symbol
Value
Unit
SVCCMAX
18
V
PVCC1
18
V
PVCC2
18
V
note
W
Power Dissipation
PD
3
Operating Temperature
TOPR
-35 ~ +85
°C
Storge Temperature
TSTG
-55 ~ +150
°C
Maximum Output Current
IOMAX
1
A
Notes:
1. When mounted on 70mm × 70mm × 1.6mm PCB.
2. Power dissipation is derated with the rate of -24mW/°C for TA≥25°C.
3. Do not exceed PD and SOA.
Pd (mW)
3,000
2,000
1,000
0
0
25
50
75
100
125
150
175
Ambient temperature, Ta [°C]
Recommended Operating Conditions ( Ta=25°C)
Parameter
Operating Supply Voltage
Symbol
Min.
Typ.
Max.
Unit
SVCC
4.5
-
13.2
V
PVCC1
4.5
-
13.2
V
PVCC2
4.5
-
13.2
V
9
FAN8035
Electrical Characteristics
(SVCC = 5V, PVCC1 = 5V, PVCC2 = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Quiescent Circuit Current
ICC
note1
Conditions
Min.
Typ.
Max.
Unit
Under no-load
-
30
-
mA
Power Save On Current
IPS
Under no-load
-
-
1
mA
Power Save On Voltage
VPSON
Pin39 = Variation
-
-
0.5
V
Power Save Off Voltage
VPSOFF
Pin39 = Variation
2
-
-
V
Mute12 On Voltage
VMON12
Pin19 = Variation
-
-
0.5
V
Mute12 Off Voltage
VMOFF12
Pin19 = Variation
2
-
-
V
Mute34 On Voltage
VMON34
Pin20 = Variation
-
-
0.5
V
Mute34 Off Voltage
VMOFF34
Pin20 = Variation
2
-
-
V
Mute5 On Voltage
VMON5
Pin21 = Variation
-
-
0.5
V
Mute5 Off Voltage
VMOFF5
Pin21 = Variation
2
-
-
V
-100
-
+100
mV
BTL DRIVER CIRCUIT
Output Offset Voltage
VOO
VIN = 2.5V
Maximum Output Voltage1
VOM1
RL = 10Ω, CH1,2
2.5
3.5
-
V
Maximum Output Voltage2
VOM2
RL = 18Ω, CH3,4,5
8.5
10.0
-
V
Closed-loop Voltage Gain
AVF
VIN = 0.1Vrms
16.8
18
19.2
dB
RR
VIN = 0.1Vrms, f = 120Hz
-
60
-
dB
SR
Square, Vout = 4Vp-p
1
2
-
V/µs
Ripple Rejection Ratio
Slew Rate
note2
note2
INPUT OPAMP CIRCUIT
Input Offset Voltage1
VOF1
-
-10
-
+10
mV
IB1
-
-
-
400
nA
High Level Output Voltage1
VOH1
-
4.4
4.7
-
V
Low Level Output Voltage1
VOL1
-
-
0.2
0.5
V
Output Sink Current1
ISINK1
RL = 50Ω
1
2
-
mA
Output Source Current1
ISOU1
RL = 50Ω
1
2
-
mA
Common Mode Input
Range1note2
Vicm1
-0.3
-
4.0
V
Open Loop Voltage Gain1note2
GVO1
VIN = -75dB
-
80
-
dB
RR1
VIN = -20dB, f = 120Hz
-
65
-
dB
VIN = -20dB
-
80
-
dB
Square, Vout = 3Vp-p
-
1.5
-
V/µs
Input Bias Current1
Ripple Rejection
Ratio1note2
Common Mode Rejection
Ratio1note2
Slew Rate1note2
CMRR1
SR1
-
Note :
1. When the voltage at pin39 goes below 0.5V, the power save circuit makes the main bias current sources stop operating. As a
result, the whole circuits are disable. ( The whole circuits mean the driver circuit, the input Op-amp circuit, and the normal
Op-amp circuit.)
2. Guaranteed field.(No EDS/Final test)
10
FAN8035
Electrical Characteristics (Continued)
(SVCC = 5V, PVCC1 = 5V, PVCC2 = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
VOF2
-
-10
-
+10
mV
IB2
-
-
-
400
nA
High Level Output Voltage2
VOH2
-
4.4
4.7
-
V
Low Level Output Voltage2
VOL2
-
-
0.2
0.5
V
Output Sink Current2
ISINK2
RL= 50Ω
2
4
-
mA
ISOU2
RL= 50Ω
2
4
-
mA
-0.3
-
4.0
V
NORMAL OP AMP CIRCUIT 1
Input Offset Voltage2
Input Bias Current2
Output Source Current2
Common Mode Input
Open Loop Voltage
Range2*note
Gain2*note
Ripple Rejection Ratio2*
Vicm2
GVO2
VIN = -75dB
-
80
-
dB
RR2
VIN = -20dB, f = 120Hz
-
65
-
dB
VIN = -20dB
-
80
-
dB
Square, Vout = 3Vp-p
-
1.5
-
V/µs
note
Common Mode Rejection
Ratio2*note
-
CMRR2
Slew Rate2*note
SR2
NORMAL OP AMP CIRCUIT 2
Input Offset Voltage3
VOF3
-
-15
-
+15
mV
IB3
-
-
-
400
nA
High Level Output Voltage3
VOH3
-
3
3.8
-
V
Low Level Output Voltage3
VOL3
-
-
1.0
1.5
V
Output Sink Current3
ISINK3
RL = 50Ω
10
-
-
mA
ISOU3
RL = 50Ω
10
-
-
mA
GVO3
VIN = -75dB
-
80
-
dB
RR3
VIN = -20dB, f = 120Hz
-
65
-
dB
VIN = -20dB
-
80
-
dB
Square, Vout = 3Vp-p
-
1.5
-
V/µs
Input Bias Current3
Output Source Current3
note
Open Loop Voltage Gain3*
Ripple Rejection
Ratio3*note
Common Mode Rejection
Ratio3*note
CMRR3
Slew Rate3*note
SR3
TRAY DRIVE CIRTUIT
Input High Level Voltage
VIH
-
2
-
-
V
Input Low Level Voltage
VIL
-
-
-
0.5
V
Output Voltage1
VO1
PVCC2 = 11V, VCTL = 3V,
RL= 45Ω
-
6
-
V
Output Voltage2
VO2
PVCC2 = 13V, VCTL = 4.5V,
RL= 45Ω
-
9
-
V
Output Voltage3
VO3
PVCC2 = 11V, VCTL = 1.5V,
RL = 10Ω
2.5
3
3.5
V
Output Load Regulation
∆VRL
VCTL=3V, IL=100mA →
400mA
-
300
700
mV
Output Offset Voltage1
VOO1
VIN = 5V, 5V
-40
-
+40
mV
Output Offset Voltage2
VOO2
VIN = 0V, 0V
-40
-
+40
mV
Note: Guaranteed field.(No EDS/Final test)
11
FAN8035
Application Information
1. Thermal Shutdown
SVCC
• The TSD circuit is activated at the junction temperature of 160°C and
deactivated at 135°C with the hysteresis of 25°C. During the thermal
shutdown, the TSD circuit keeps all the output driver off.
IREF
Output driver
Bias
R1
Q0
R2
Hysteresis
Ihys
R3
2. CH Mute Function
• When the mute pin is high, the TR Q1 is on and Q2 is off, so the bias
circuit is enabled. When the mute pin is low (GND), the TR Q1 is off
and Q2 is on, so the bias circuit is disabled.
• During the mute on state, all the circuit blocks except for the variable
regulator remain off, and the low power quiescent state is established.
• Truth table is as follows;
SVCC
Bias Blocks
(5-CH BTL)
Pin 19, 20, 21
Mute
19
High
Mute-Off
20
Low
Mute-On
21
Q2
Q1
3. Power Save Function
• When the pin39 is high, the TR Q3 becomes on and Q4 off, so the bias
circuit is enabled. When the pin39 is low (GND) , the TR Q3 becomes
off and Q4 is on, so the bias circuit is disabled.
• During the power save on state, this function keeps all the circuit
blocks off, and the low power quiescent state is established.
• Truth table is as follows;
Pin39
Power Save
High
Power Save Off
Low
Power Save On
SVCC
Main Bias
Q4
39
Q3
4. TDS Monitor Function
• Pin22 is TSD monitor pin, which detects the state of the TSD block
and generates the TSD-monitor signal.
• In the normal state Q5 is on, and Q6 is off. When the TSD block is
activated Q5 becomes off, and thus the voltage of pin22 keeps low.
• Truth table is as follows;
12
TSD
Pin22
TSD Off
High
TSD On
Low
SVCC
VCC
R(external)
20K
22
Q6
Q5
FAN8035
5. Focus, Tracking Actuator, Spindle, Sled Motor Drive Part
40K
VREF
10K
43
DO+
10K
IN+
48
3
6
9
12
1
4
7
10
13
2
5
8
11
14
30
32
35
37
27
29
31
34
36
40K
Vin
M
Vp
IN-
28
40K
OUT
10K
PVCC1(PVCC2)
DO-
10K
+
VDP
-
40K
60K
62K
Vp
QP
• The Vref at pin 43 is for eliminating the dc components from the input signals and can set by an exteranl circuit.
• The voltage gain from Vin to output is as follows ;
Vin = Vref + ∆V
DOP = V D + 4 ∆V
DON = V D – 4 ∆V
Vout = DOP – DON = 8 ∆V
Vout
Gain = 20 log ------------- = 20 log 8 = 18dB
∆V
•
•
•
•
Where ∆V means just ac component.
The total input to output voltage gain is the sum of the input OP amp network gain and 18dB.
The output stage is the balanced transformerless (BTL) driver.
The bias voltage Vp is expressed as ;
62k
V P = ( PVCC1 – V DP – V CESAT Q P ) × -------------------------- + V CESAT Q P
60k + 62k
PVCC1 – V DP – V CESAT Q P
= ------------------------------------------------------------------------- + V CESAT Q P
1.97
----------
(1)
13
FAN8035
6. Tray, Changer,panel Motor Drive Part
out 1
out 2
25
M
24
D
D
LEVEL SHIFT
6.5V
M.S.C
CTL
V(out1,out2)
15
S.W
0
IN
IN
FWD
REV
16
17
3.25V
VCTL
• Rotational direction control
The forward and reverse rotational direction is controlled by FWD (pin16) and REV (pin17) and the input conditions are as
follows;
INPUT
OUTPUT
FWD
REV
OUT 1
OUT 2
State
H
H
Vp
Vp
Brake
H
L
H
L
Forward
L
H
L
H
Reverse
L
L
-
-
Hign impedance
• Where Vp(Power reference voltage) is approximately 3.75V at PVCC2=8V according to equation (1).
• Motor speed control (When SVCC=PVCC2=8V)
- The maximum torque is obtained when the pin15(CTL) is open.
- If the voltage of the pin15 (CTL) is 0V, the motor will not operate.
- When the control voltage (pin15) is between 0 and 3.25V, the differential output voltage V(out1,out2) is about two times
of control voltage. The output gain is 6dB.
- When the control voltage is greater than 3.25V, the output voltage is saturated at the 6.5V because of the output swing
limitation.
14
FAN8035
Test Circuits
VCC
50Ω
45
44
43
42
41
40
IN1+
OPIN1+
OPIN1−
OPOUT1
SVCC
VREF
OPIN2+
OPIN2−
OPOUT2
39
38
OP IN (-)
4 IN2-
36 DO1−
DO2+ 35
RL2
DO2- 34
IN2+
3
RL1
37
DO1+
46
PVCC1
47
OP IN (+)
OP IN (+)
OP IN (-)
48
2 OUT1
OP OUT
OP OUT
IN1− 1
OP OUT
RIPPLE
OP IN (+)
OP IN (-)
OP OUT
OP IN (+)
OP IN (-)
OP IN (+)
VREF
2.5V
100µF 2
+
+ 1000µF
PS
1
PGND1 33
5 OUT2
DO3+ 32
6 IN3+
DO3− 31
RL3
FAN8035
OP IN (-)
OP OUT
MUTE5
TSD_M
13
14
15
16
17
18
19
20
21
22
RL4
RL5
PGND2 26
DO6−
MUTE34
IN5+ 12
OP OUT
PVCC2
MUTE12
DO5− 27
SGND
10 IN4−
REV
DO5+ 28
FWD
9 IN4+
11 OUT4
OP IN (+)
OP IN (-)
DO4− 29
CTL
OP OUT
8 OUT3
OUT5
OP IN (-)
DO4+ 30
IN5−
OP IN (+)
7 IN3−
23
25 DO6+
24
RL7
CTL
INA
IL
INB
IL
OP-AMP PART
OPIN(+)
OPIN(−)
A
B
1
VPULSE
2
3
VA
1
2
OPOUT
D
3
VOUT
50Ω
VB
C
1
2
VCC
15
FAN8035
Typical Application Circuits 1
[Voltage control mode]
SVCC
PVCC1
POWER SAVE
46
45
44
43
42
41
40
39
38
OPOUT1
SVCC
VREF
OPIN2+
OPIN2−
OPOUT2
PS
PVCC1
2 OUT1
37
DO1+
47
36
DO2+35
DO2- 34
3 IN2+
DO1−
TRACKING
48
OPIN1−
1
OPIN1+
IN1−
IN1+
FOCUS
PGND1 33
4 IN25 OUT2
DO3+ 32
6 IN3+
DO3− 31
M
SLED
FAN8035
7 IN3−
DO4+ 30
8 OUT3
DO4− 29
9 IN4+
DO5+ 28
10 IN4−
DO5−27
IN5−
OUT5
CTL
FWD
REV
SGND
MUTE12
MUTE34
MUTE5
TSD_M
PVCC2
DO6−
IN5+ 12
PGND2
13
14
15
16
17
18
19
20
21
22
23
24
11 OUT4
M SPINDLE
26
25 DO6+
M TRAY
pvcc2
PVCC2
SPINDLE MUTE
SLED MUTE
FOCUS, TRACKING,
MUTE
TSD MONITOR
VREF
FOCUS TRACKING
INPUT
INPUT
[SERVO PRE AMP]
16
SLED
INPUT
SPINDLE
INPUT
TRAY
TRAY
CONTROL INPUT
[CONTROLLER]
FAN8035
Typical Application Circuits 2
[Differential PWM control mode ]
SVCC
PVCC1
POWER SAVE
4
5
40
39
38
PS
PVCC1
37
DO1+
41
OPOUT2
OPOUT1
42
DO2+
36
DO1−
TRACKING
3
43
OPIN2−
OPIN1−
2 OUT1
44
OPIN2+
45
VREF
46
SVCC
47
OPIN1+
IN1− 1
48
IN1+
FOCUS
35
DO2- 34
IN2+
PGND1 33
IN2-
DO3+ 32
OUT2
DO3− 31
6 IN3+
M
SLED
FAN8035
MUTE34
MUTE5
TSD_M
14
15
16
17
18
19
20
21
22
M SPINDLE
PGND2 26
23
DO6−
MUTE12
13
OUT4
PVCC2
SGND
IN5+ 12
IN4−
DO5−27
REV
11
DO5+ 28
FWD
10
IN4+
CTL
9
DO4− 29
OUT3
OUT5
8
DO4+ 30
IN3−
IN5−
7
25 DO6+
24
M TRAY
PVCC2
pvcc2
SPINDLE MUTE
SLED MUTE
FOCUS, TRACKING
MUTE
TSD MONITOR
VREF FOCUS TRACKING
INPUT INPUT
SLED
INPUT
SPINDLE
INPUT
TRAY
TRAY
CONTROL INPUT
[SERVO PRE AMP]
[CONTROLLER]
Note:
Radiation pin is connected to the internal GND of the package.
17
FAN8035
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/28/03 0.0m 001
Stock#DSxxxxxxxx
 2003 Fairchild Semiconductor Corporation
Similar pages