STMicroelectronics ETC5067 Power amplifier serial interface codec/filterwith receive Datasheet

ETC5064/64-X
ETC5067/67-X
SERIAL INTERFACE CODEC/FILTER WITH RECEIVE
POWER AMPLIFIER
.
..
.
..
.
..
.
..
COMPLETE CODEC AND FILTERING SYSTEM INCLUDING :
- Transmit high-pass and low-pass filtering.
- Receive low-pass filter with sin x/x correction.
- Active RC noise filter.
- µ-law or A-law compatible CODER and DECODER.
- Internal precision voltage reference.
- Serial I/O interface.
- Internal auto-zero circuitry.
- Receive push-pull power amplifiers.
µ-LAW ETC5064
A-LAW ETC5067
MEETS OR EXCEEDS ALL D3/D4 AND CCITT
SPECIFICATIONS.
± 5 V OPERATION.
LOW OPERATING POWER-TYPICALLY 70 mW
POWER-DOWN STANDBY MODE-TYPICALLY
3 mW
AUTOMATIC POWER DOWN
TTL OR CMOS COMPATIBLE DIGITAL INTERFACES
MAXIMIZES LINE INTERFACE CARD CIRCUIT DENSITY
0°C TO 70°C OPERATION: ETC5064/67
–40°C TO 85°C OPERATION: ETC5064-X/67-X
DIP20
(Plastic) N
ORDERING NUMBERS:
ETC5064N
ETC5064N-X
ETC5067N
ETC5067N-X
PL CC20
FN
ORDERING NUMBERS:
ETC5064FN
ETC5064FN-X
ETC5067FN
ETC5067FN-X
DESCRIPTION
The ETC5064 (µ-law), ETC5067 (A-law) are monolithic PCM CODEC/FILTERS utilizing the A/D and
D/A conversion architectureshown in the Block Diagrams and a serial PCM interface. The devices are
fabricated using double-poly CMOS process.
Similar to the ETC505X family, these devices feature an additional Receive Power Amplifier to provide push-pull balanced output drive capability. The
receive gain can be adjusted by means of two external resistors for an output level of up to ± 6.6 V
across a balanced 600Ω load.
Also included is an Analog Loopback switch and
TSX output.
November 1994
SO 20
D
ORDERING NUMBERS:
ETC5064D
ETC5064D-X
ETC5067D
ETC5067D-X
1/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN CONNECTIONS (Top views)
DIP20 &
SO20
PLCC20
BLOCK DIAGRAM (ETC5064 - ETC5064-X - ETC5067 - ETC5067-X)
2/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PIN DESCRIPTION
Pi n
Type (*)
N
VPO
O
1
The Non-inverting Output of the Receive Power Amplifier
GNDA
GND
2
Analog Ground. All signals are referenced to this pin.
VPO
O
3
The Inverting Output of the Receive Power Amplifier
VPI
I
4
Inverting Input to the Receive Power Amplifier. Also powers down both
amplifiers when connected to VBB.
VFRO
O
5
Analog Output of the Receive Filter.
VCC
S
6
Positive Power Supply Pin. VCC = +5V ±5%
FSR
I
7
Receive Frame Sync Pulse which enable BCLKR to shift PCM data into
D R. FSR is an 8KHz pulse train. See figures 1 and 2 for timing details.
DR
I
8
Receive Data Input. PCM data is shifted into DR following the FSR leading
edge
BCLKR/CLKSEL
I
9
The bit Clock which shifts data into DR after the FSR leading edge. May
vary from 64KHz to 2.048MHz.
Alternatively, may be a logic input which selects either 1.536MHz/1.544MHz
or 2.048MHz for master clock in synchronous mode and BCLKX is used
for both transmit and receive directions (see table 1). This input has an
internal pull-up.
MCKLR/PDN
I
10
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKX, but should be synchronous with MCLKX for
best performance. When MCLKR is connected continuously low, MCLKX is
selected for all internal timing. When MCLKR is connected continuously
high, the device is powered down.
MCLKX
I
11
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May
be asynchronous with MCLKR.
BCLKX
I
12
The bit clock which shifts out the PCM data on D X. May vary from 64KHz
to 2.048MHz, but must be synchronous with MCLKX.
Name
+
-
Description
DX
O
13
The TRI-STAT EPCM data output which is enabled by FSX.
FSX
I
14
Transmit frame sync pulse input which enables BCLKX to shift out the
PCM data on DX. FSX is an 8KHz pulse train. See figures 1 and 2 for
timing details.
TSX
O
15
Open drain output which pulses low during the encoder time slot. Must to
be grounded if not used.
ANLB
I
16
Analog Loopback Control Input. Must be set to logic ’0’ for normal
operation. When pulled to logic ’1’, the transmit filter input is disconnected
from the output of the transmit preamplifier and connected to the VPO+
output of the receive power amplifier.
GSX
O
17
Analog output of the transmit input amplifier. Used to set gain externally.
I
18
Inverting input of the transmit input amplifier.
VFXI
VFXI
VBB
-
+
I
19
Non-inverting input of the transmit input amplifier.
S
20
Negative Power Supply Pin. VBB = -5V ±5%
(*) I: Input, O: Output, S: Power Supply.
TRI-STATE is a trademark of National Semiconductor Corp.
3/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
FUNCTIONAL DESCRIPTION
POWER-UP
When power is first applied, power-on reset circuitry
initializes the device and places it into the powerdown mode. All non-essential circuits are deactivated and the DX and VFRO outputs are put in high
impedancestates. To power-upthe device,a logical
low level or clock must be applied to the
MCLKR/PDN pin and FSX and/or FSR pulses must
be present. Thus 2 power-down control modes are
available. The first is to pull the MCLKR/PDN pin
high; the alternative is to hold both FSX and FSR inputs continuously low. The device will power-down
approximately 2 ms after the last FSX pulse. The
TRI-STATE PCM data output, DX, will remain in the
high impedance state until the second FSX pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master clock
and bit clock should be used for both the transmit
and receive directions. In this mode, a clock must be
applied to MCLKX and the MCLKR/PDN pin can be
used as a power-down control. A low level on
MCLKR/PDN powers up the device and a high level
powers down the device. In either case, MCLKX will
be selected as the master clock for both the transmit
and receive circuits. A bit clock must also be applied
to BCLKX and the BCLR/CLKSELcan be used to select the proper internal divider for a master clock of
1.536 MHz, 1.544 MHz or 2.048 MHz. For 1.544
MHz operation, the device automatically compensates for the 193 rd clock pulse each frame.
With a fixed level on the BCLKR/CKSEL pin, BCLKX
will be selected as the bit clock for both the transmit
and receive directions. Table 1 indicates the frequencies of operation which can be selected, depending on the state of BCLKR/CLKSEL. In this synchronous mode, the bit clock, BCLKX, may be from
64 kHz to 2.048 MHz, but must be synchronouswith
MCLKX.
Table 1: Selection of Master Clock Frequencies.
BCLKR/CLKSEL
Clocked
0
1 (or open circuit)
4/18
Master Clock
Frequency Selected
ETC5067
ETC5067-X
ETC5064
ETC5064-X
2.048MHz
1.536MHz or
1.544MHz
1.536MHz or
1.544MHz
2.048MHz
2.048MHz
1.536MHz or
1.544MHz
Each FSX pulse begins the encoding cycle and the
PCM data from the previous encode cycle is shift out
of the enabled DX output on the positive edge of
BCLKX. After 8 bit clock periods, the TRISTATE DX
output is returned to a high impedance state. With an
FSR pulse, PCM data is latched via the DR input on
the negativeedge of BCLKX (or on BCKLR if running).
FSX and FSR must be synchronous with MCLKX/R.
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and
receive clocks may be applied. MCLKX and MCLKR
must be 2.048 MHz for the ETC5067 or 1.536 MHz,
1.544 MHz for the ETC5064, and need not be synchronous. For best transmission performance, however, MCLKR should be synchronouswith MCLKX,
which is easily achieved by applyingonly static logic
levels to theMCLKR/PDN pin. This will automatically
connectMCLKX toall internal MCLKR functions(see
pin description). For 1.544 MHz operation, the device automatically compensates for the 193rd clock
pulse each frame. FSX starts each encoding cycle
and must be synchronous with MCLKX and BCLKX.
FSR starts each decoding cycle and must be synchronous with BCLKR. BCLKR must be a clock, the
logic levels shown in Table 1 are not valid in asynchronous mode. BCLKX and BCLKR may operate
from 64kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse or a long frame sync pulse.Upon power initialization, the device assumes a short frame mode. In
this mode, both frame sync pulses. FSX and FSR,
must be one bit clock period long, with timing relationships specified in figure 2. With FSX high during
a falling edge of BCLKR, the next rising edge of
BCLKX enables the DX TRI-STATE output buffer,
which will output the sign bit. The following sevenrising edges clock out the remaining seven bits, and
the next falling edge disables the DX output. With
FSR high during a falling edge of BCLKR (BCLKX in
synchronous mode), the next falling edge of BCLKR
latches in the sign bit. The following seven falling
edges latch in the seven remaining bits. Both devices may utilize the short frame sync pulse in synchronous or asynchronous operating mode.
LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync
pulses, FSX and FSR, must be three or more bit clock
periods long, with timing relationships specified in
figure 3. Based on the transmit frame sync FSX, the
device will sense whether short or long frame sync
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
pulses are being used. For 64 kHz operation, the
frame sync pulses must be kept low for a minimum
of 160 ns (see Fig 1). The DX TRI-STATE output
buffer is enabled with the rising edge of FSX or the
rising edge of BCLKX, whichever comes later, and
the first bit clocked out is the sign bit. The following
seven BCLKX rising edges clock out the remaining
seven bits. The DX output is disabled by the falling
BCLKX edge following the eighth rising edge, or by
FSX going low, whichever comes later. A rising edge
on the receive frame sync pulse, FSR, will cause the
PCM data at DR to be latched in on the next eight
falling edges of BCLKR (BCLKx in synchronous
mode). Both devices may utilize the long frame sync
pulse in synchronous or asynchronous mode.
TRANSMIT SECTION
The transmit section input is an operational amplifier
with provision for gain adjustmentusing two external
resistors, see figure 4. The low noiseand wide bandwidth allow gains in excess of 20 dB across the
audio passband to be realized. The op amp drives
a unity gain filter consisting of RC active pre-filter,
followed by an eighth order switched-capacitor
bandpass filter directly drives the encoder sampleand-hold circuit. The A/D is of companding type according to A-law (ETC5067 and ETC5067-X) or µlaw (ETC5064 and ETC5064-X) coding conventions. A precision voltage reference is trimmed in
manufacturing to provide an input over load (tMAX)
of nominally 2.5V peak (see table of Transmission
Characteristics). The FSX frame sync pulse controls
the sampling of the filer output,and then the successive-approximationencodingcycle begins.The8-bit
code is then loaded into a buffer and shifted out
throughDX at the next FSX pulse. the total encoding
delay will be approximately 165µs (due to the transmit filter) plus 125µs (due to encoding delay), which
totals 290µs. Any offset voltage due to the filters or
comparator is cancelled by sign bit integration.
RECEIVE SECTION
The receive section consist of an expanding DAC
which drives a fifth order switched-capacitor low
pass filter clocked at 256kHz. The decoder is A-law
(ETC5067 and ETC5067-X) or µ–law (ETC5064
and ETC5064-X) and the 5 th order low pass filter
corrects for the sin x/x attenuation due to the 8kHz
sample and hold. The filter is then followed by a 2
nd order RC active post-filter and power amplifier
capable of driving a 600Ω load to a level of 7.2dBm.
The receive section is unity-gain. Upon the occurence of FSR, the data at the DR input is clocked
in on the falling edge of the next eight BCLKR
(BCKLX) periods.At the endofthe decoder time slot,
the decoding cycle begins, and 10µs later the decoder DAC outputis updated.The total decoder delay is about10µs (decoder up-date) plus 110µs (filter delay) plus 62.5µs (1/2 frame), which gives approximately 180µs.
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided
for directly driving a matched line interface transformer. The gain of the first power amplifier can be
adjusted to boost the ± 2.5V peak output signal from
the receive filter up ± 3.3V peak into an unbalanced
300Ω load, or ±4.0V into an unbalanced15kΩ load.
The second power amplifier is internally connected
in unity-gain inverting mode to give 6dB of signal
gain for balanced loads. Maximum power transfer to
a 600Ω subscriber line termination is obtained by
differientially driving a balanced transformer with a
2 : 1 turns ratio, as shown in figure 4. A total peak
√
power of 15.6dBm can be delivered to the load plus
termination. Both power amplifier can be powered
down independentlyfrom the PDN input by connecting the VPI input to VBB saving approximately 12
mW of power.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Valu e
Un it
VCC
VCC to GNDA
7
V
VBB
VBB to GNDA
-7
V
Voltage at any Analog Input or Output
VCC +0.3 to VBB -0.3
V
Voltage at any Digital Input or Output
VCC +0.3 to GNDA -0.3
V
VIN, VOUT
Toper
Operating Temperature Range: ETC5064/67
ETC5064-X/67-X
-25 to +125
-40 to +125
°C
°C
Tstg
Storage Temperature Range
-65 to +150
°C
300
°C
Lead Temperature (soldering, 10 seconds)
5/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS
VCC = 5.0V ±5%, VBB = -5V ±5%, GNDA = 0V, TA = 0°C to70°C (ETC5064-X/67-X: TA = –40°C to 85°), unless
otherwise noted; typical characteristics specified at VCC = 5.0V, VBB =-5.0V, TA = 25°C; all signals are referenced to GNDA.
DIGITAL INTERFACE (All devices)
Symbol
Parameter
Min.
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IL = 3.2 mA
IL = 3.2 mA, Open Drain
DX
TSX
Output High Voltage
IH = 3.2 mA
DX
VOH
Typ.
Max.
Unit
0.6
V
2.2
V
0.4
0.4
2.4
V
V
V
IIL
Input Low Current (GNDA ≤ VIN ≤ VIL )all digital inputs
Except BCLKR
– 10
10
µA
IIH
Input High Current (VIH ≤ VIN ≤ VCC) Except ANLB
– 10
10
µA
IOZ
Output Current in High Impedance State (TRI-STAT E)
(GNDA ≤ VO ≤ VCC)
– 10
10
µA
Max.
Unit
200
nA
DX
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)
Symbol
Parameter
Min.
+
Typ.
– 200
Input Leakage Current
(– 2.5 V ≤ V ≤ + 2.5 V)
R IXA
Input Resistance
(– 2.5 V ≤ V ≤ + 2.5 V)
R OXA
Output Resistance (closed loop, unity gain)
R LXA
Load Resistance
GSX
C LXA
Load Capacitance
GSX
VOXA
Output Dynamic Range (RL ≥ 10 kΩ)
AVXA
Voltage Gain (VFXI to GSX)
FUXA
Unity Gain Bandwidth
VOSXA
Offset Voltage
– 20
20
Common-mode Voltage
– 2.5
2.5
VCMXA
VFxI or VFxI
–
IIXA
VFXI
+
or VFXI
–
10
MΩ
1
GSX
+
3
10
50
– 2.8
+2.8
5000
1
Ω
kΩ
pF
V
V/V
2
MHz
mV
V
CMRRXA
Common-mode Rejection Ratio
60
dB
PSRRXA
Power Supply Rejection Ratio
60
dB
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
Symbol
Parameter
R ORF
Output Resistance
R LRF
Load Resistance (VFRO = ± 2.5 V)
C LRF
Load Capacitance
VOSRO
6/18
Output DC Offset Voltage
Min.
VFRO
Typ.
Max.
1
3
10
– 200
Unit
Ω
kΩ
25
pF
200
mV
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
ELECTRICAL OPERATING CHARACTERISTICS (Continued)
ANALOG INTERFACE WITH POWER AMPLIFIERS (all devices)
Symbol
Parameter
Min.
Input Leakage Current (– 1.0 V ≤ VPI ≤ 1.0 V)
IPI
RIPI
Input Resistance (– 1.0 ≤ VPI ≤ 1.0 V)
VIOS
Input Offset Voltage
ROP
Output Resistance (inverting unity–gain at VPO + or VPO –)
–
GAp
+
PSRRp
–
+
nA
MΩ
mV
1
Ω
400
kHz
pF
100
500
1000
–
Gain VPO to VPO to GNDA, Level at VPO = 1. 77 Vrms
(+ 3 dBmO)
Power Supply Rejection of VCC or VBB
(VPO– connected to VPI)
0 kHz – 4 kHz
0 kHz – 50 kHz
Unit
100
25
Load Capacitance (VPO + or VPO – to GNDA)
RL ≥ 1500 Ω
RL = 600 Ω
RL = 300 Ω
CLP
Max.
10
– 25
Unity–gain Bandwidth, Open Loop (VPO )
FC
Typ.
– 100
–1
V/V
dB
60
36
POWER DISSIPATION (all devices)
Symbol
Typ.
Max.
Unit
ICC0
Power-down Current at ETC6064/67
ETC5064-X/67-X
Parameter
Min.
0.5
0.5
1.5
mA
mA
IBB0
Power-down Current at ETC6064/67
ETC5064-X/67-X
0.05
0.05
0.3
0.4
mA
mA
ICC1
Active Current at ETC6064/67
ETC5064-X/67-X
7.0
7.0
10.0
12.0
mA
mA
IBB1
Active Current at ETC6064/67
ETC5064-X/67-X
7.0
7.0
10.0
12.0
mA
mA
7/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
All TIMING SPECIFICATIONS
Symbol
1/tPM
Parameter
Min.
Typ.
1.536
2.048
Frequency of master clocks
MCLKX and MCLKR
Depends on the device used and the
BCLKR/CLKSEL Pin
Unit
MHz
1.544
tWMH
Width of Master Clock High
MCLKX and MCLKR
160
tWML
Width of Master Clock Low
MCLKX and MCLKR
160
ns
tRM
Rise Time of Master Clock
MCLKX and MCLKR
50
ns
tFM
Fall Time of Master Clock
MCLKX and MCLK R
50
ns
tPB
15.725
ns
ns
Period of Bit Clock
485
tWBH
Width of Bit Clock High (VIH = 2.2 V)
160
488
ns
tWBL
Width of Bit Clock Low (VIL = 0.6 V)
160
ns
tRB
Rise Time of Bit Clock (tPB = 488 ns)
50
ns
tFB
Fall Time of Bit Clock (tPB = 488 ns)
50
ns
tSBFM
Set-up time from BCLKX high to MCLKX falling edge.
(first bit clock after the leading edge of FSX)
100
ns
tHBF
Holding Time from Bit Clock Low to the Frame Sync
(long frame only)
0
ns
tSFB
Set-up Time from Frame Sync to Bit Clock (long frame only)
80
ns
tHBFI
Hold Time from 3rd Period of Bit Clock
Low to Frame Sync (long frame only)
100
ns
tDZF
Delay Time to valid data from FSX or BCLKX, whichever
comes later and delay time from FSX to data output disabled
(CL = 0 pF to 150 pF)
20
165
ns
tDBD
Delay Time from BCLKX high to data valid
(load = 150 pF plus 2 LSTTL loads)
0
150
ns
tDZC
Delay Time from BCLKX low to data output disabled
50
165
ns
FSX or FSR
tSDB
Set-up Time from DR valid to BCLKR/X low
50
ns
tHBD
Hold Time from BCLKR/X low to DR invalid
50
ns
tHOLD
Holding Time from Bit Clock High to Frame Sync (short frame only)
0
ns
tSF
Set-up Time from FSX/R to BCLKX/R Low
(short frame sync pulse) - Note 1
80
ns
tHF
Hold Time from BCLKX/R Low to FSX/R Low
(short frame sync pulse) - Note 1
100
ns
tXDP
Delay Time to TSX low (load = 150 pF plus 2 LSTTI loads)
tWFL
Minimum Width of the Frame Sync Pulse (low level)
(64 bit/s operating mode)
140
160
Note : 1.For short frame sync timing. FS X and FSR must go high while their respective bit clocks are high.
Figure 1 : 64 k bits/s TIMING DIAGRAM. (see next page for complete timing)
8/18
Max.
ns
ns
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Figure 2 : Short Frame Sync Timing.
9/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Figure 3 : Long Frame Sync Timing.
10/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS
(all devices) TA = 0°C to 70°C (ETC5064-X/67-X: TA = –40°C to 85°), VCC = 5V ± 5%, VBB = – 5V ± 5%,
GNDA = 0V, f = 1.02kHz, VIN = 0dBm0 transmit input amplifier connected forunity–gainnon–inverting.(unless
otherwise specified).
AMPLITUDE RESPONSE
Symbo l
Parameter
Min.
Absolute Levels - Nominal 0 dBm0 is 4 dBm (600Ω).
0 dBm0
tMAX
Max Overload Level
3.14 dBm0
3.17 dBm0
ETC5067
ETC5064
GXA
Transmit Gain, Absolute (TA = 25°C, VCC = 5V, VBB = -5V)
Input at GSX = 0dBm0 at 1020Hz
GXR
Transmit Gain, Relative to GXA
f = 16Hz
f = 50Hz
f = 60Hz
f = 180Hz
f = 200Hz
f = 300Hz -3000Hz
f = 3200Hz (ETC5064-X/67-X)
f = 3300Hz
f = 3400Hz
f = 4000Hz
f = 4600Hz and up, measure response from oHz to 4000Hz
GXAT
Absolute Transmit Gain Variation with Temperature
TA = 0°C to +70°C
TA = –40°C to +85°C (ETC5064-X/67-X)
GXAV
Absolute Transmit Gain Variation with Supply Voltage
(VCC = 5V ±5%, VBB = -5V ±5%)
GXRL
Transmit Gain Variation with Level
Sinusolidal Test Method Reference Level = -10dBm0
VFXI+ = -40dBm0 to +3dBm0
+
VFXI = -50dBm0 to -40dBm0
+
VFXI = -55dBm0 to -50dBm0
GRA
Receive Gain, Absolute (TA = 25°C, VCC = 5V, VBB = -5V)
Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz
GRR
Receive Gain, Relative to GRA
f = 0Hz to 3000Hz
f = 3200Hz (ETC5064-X/67-X)
f = 3300Hz
f = 3400Hz
f = 4000Hz
GRAT
Absolute Receive Gain Variation with Temeperature
TA = 0°C to +70°C
TA = –40°C to +85°C (ETC5064-X/67-X)
T yp.
Max.
Unit
1.2276
Vrms
2.492
2.501
VPK
-0.15
0.15
dB
-2.8
-1.8
-0.15
-0.35
-0.35
-0.7
-40
-30
-26
-0.2
-0.1
0.15
0.20
0.05
0
-14
-32
dB
-0.1
-0.15
0.1
0.15
-0.05
0.05
dB
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
-0.15
0.15
dB
-0.15
-0.35
-0.35
-0.7
0.15
0.20
0.05
0
-14
-0.1
-0.15
0.1
0.15
dB
-0.05
0.05
dB
dB
dB
GRAV
Absolute Receive Gain Variation with Supply Voltage
(VCC = 5V ±5%, VBB = -5V ±5%)
GRRL
Receive Gain Variation with Level
Sinusoidal Test Method; Reference Input PCM code
corresponds to an ideally encoded -10dBm0 signal
PCM level = -40dBm0 to +3dBm0
PCM level = -50dBm0 to -40dBm0
PCM level = -55dBm0 to -50dBm0
-0.2
-0.4
-1.2
0.2
0.4
1.2
dB
Receive Filter Output at VFRO R L = 10KΩ
-2.5
2.5
V
VRO
11/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (continued).
ENVELOPE DELAY DISTORTION WITH FREQUENCY
Symbol
Typ.
Max.
Unit
DXA
Transmit Delay, Absolute (f = 1600 Hz)
Parameter
Min.
290
315
µs
DXR
Transmit Delay, Relative to DXA
f = 500 Hz-600 Hz
f = 600 Hz-800 Hz
f = 800 Hz-1000 Hz
f = 1000 Hz-1600 Hz
f = 1600 Hz-2600Hz
f = 2600 Hz-2800 Hz
f = 2800 Hz-3000 Hz
195
120
50
20
55
80
130
220
145
75
40
75
105
155
DRA
Receive Delay, Absolute (f = 1600 Hz)
180
200
D RR
Receive Delay, Relative to DRA
f = 500 Hz-1000 Hz
f = 1000 Hz-1600 Hz
f = 1600 Hz-2600 Hz
f = 2600 Hz-2800 Hz
f = 2800 Hz-3000 Hz
– 25
– 20
70
100
145
90
125
175
Typ.
Max.
Unit
– 74
– 74
– 69
– 67
dBm0p
dBm0p
– 82
– 79
dBm0p
12
12
15
16
dBrnC0
dBrnC0
8
11
dBrnC0
– 53
dBm0
– 40
– 30
µs
µs
µs
NOISE
Symbol
NXP
Parameter
Transmit Noise, P Message (A-LAW, VFXI
ETC5064
ETC5064-X
NRP
Receive Noise, P Message Weighted
(A-LAW, PCM Code Equals Positive Zero)
NXC
Transmit Noise, C Message Weighted
(µ-LAW, VFxI + = 0 V)
N RC
NRS
Min.
+
= 0 V) Weighted 1)
ETC5064
ETC5064-X
Receive Noise, C Message Weighted
(µ-LAW, PCM Code Equals Alternating Positive and Negative Zero)
Noise, Single Frequency
+
f = 0 kHz to 100 kHz, Loop around Measurement, VFXI = 0 V
PPSRX
Positive Power Supply Rejection, Transmit (note 2)
VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz
40
dBp
NPSRX
Negative Power Supply Rejection, Transmit (note 2)
VBB = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz
40
dBp
PPSRR
Positive Power Supply Rejection, Receive (PCM code equals
positive zero, VCC = 5.0 VDC + 100 mVrms)
f = 0 Hz-4000Hz
A LAW
µ LAW
f = 4 kHz-25 kHz
f = 25 kHz-50 kHz
40
40
40
36
dBp
dBc
dB
dB
Negative Power Supply Rejection, Receive (PCM code equals
positive zero, VBB = – 5.0 VDC + 100 mVrms)
f = 0 Hz-4000Hz
A LAW
µ LAW
f = 4 kHz-25 kHz
f = 25 kHz-50 kHz
40
40
40
36
dBp
dBc
dB
dB
NPSRR
SOS
12/18
Spurious out-of-band Signals at the Channel Output
0 dBm0, 300 Hz-3400 Hz input PCM applied at DR
4600 Hz-7600 Hz
7600 Hz-8400 Hz
8400 Hz-100,000 Hz
–32
–40
–32
dB
dB
dB
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
TRANSMISSION CHARACTERISTICS (continued).
DISTORTION
Symbol
STDX
or
STDR
Parameter
Min.
Typ.
Max.
Unit
Signal to Total Distortion (sinusoidal test method)
Transmit or Receive Half-channel
Level = 3.0 dBm0
= 0 dBm0 to – 30 dBm0
= – 40 dBm0
XMT
RCV
XMT
RCV
= – 55 dBm0
dBp
(ALAW)
33
36
29
30
14
15
dBc
(µLAW)
SFDX
Single Frequency Distortion, Transmit (TA = 25°C)
– 46
dB
SFDR
Single Frequency Distortion, Receive (TA = 25°C)
– 46
dB
Intermodulation Distortion
Loop Around Measurement, VFXI + = – 4 dBm0 to
– 21 dBm0, two Frequencies in the Range 300 Hz-3400 Hz
– 41
dB
Typ.
Max.
Unit
IMD
CROSSTALK
Symbol
Parameter
CTX-R
Transmit to Receive Crosstalk, 0dBm0 Transmit
f = 300 Hz-3400 Hz, DR = Steady PCM Code ETC5064/67
ETC5064-X/67-X
– 90
– 75
– 65
dB
dB
Receive to Transmit Crosstalk, 0dBm0 Receive Level (note 2)
ETC5064/67
f = 300 Hz-3400 Hz, VFXI = 0 V
ETC5064-X/67-X
– 90
– 70
– 65
dB
dB
Typ.
Max.
Unit
CTR-X
Min.
POWER AMPLIFIERS
Symbol
Parameter
VOL
Maximum 0 dBm0 Level for Better than ± 0.1 dB Linearity Over
the Range 10 dBm0 to + 3 dBm0
(balanced load, RL connected between VPO + and VPO –)
RL = 600 Ω
RL = 1200 Ω
RL = 30 kΩ
33
3.5
4.0
Signal/Distortion RL = 600 Ω, 0 dBm0
50
S/DP
Notes :
Min.
Vrms
dB
1. Measured by extrapolation from the distortion test results.
2. PPSRX, NPSRX, CTR–X measured with a –50dBm0 activating signal applied at VFX I+
ENCODING FORMAT AT DX OUTPUT
A-Law
(Including even bit inversion)
µLaw
VIN (at GSX) = + Full-scale
1 0 1 0 1 0 1 0
1 0 0 0 0 0 0 0
VIN (at GSX) = 0 V
1 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1
VIN (at GSX) = – Full-scale
0 0 1 0 1 0 1 0
0 0 0 0 0 0 0 0
13/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
APPLICATION INFORMATION
POWER SUPPLIES
While the pins at the ETC506X family are well protected against electrical misure, it is recommended
that the standard CMOS practice be followed, ensuring that ground is connected to the device before
any other connections are made. In applications
where the printed circuit board may be plugged into
a ”hot” socket with power and clocks already present, an extra long ground pin in the connector
should be used.
All ground connections to each device should meet
at a common point as close as possible to the GNDA
pin. This minimizes the interaction of ground return
currents flowing through a common bus impedance.
0.1µF supply decoupling capacitors should be connected from this common ground point to VCC and
VBB as close to the device as possible.
For best performance, the ground point of each
CODEC/FILTER on a card should be connected to
a common card groundin star formation, rather than
via a ground bus. This common ground point should
be decoupled to VCC and VBB with 10µF capacitors.
For best performance, TSx should be grounded if
not used.
14/18
Figure 4 : Typical Asynchronous Application.
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
SO20 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
a1
inch
MAX.
MIN.
TYP.
2.65
0.1
0.104
0.2
a2
MAX.
0.004
0.008
2.45
0.096
b
0.35
0.49
0.014
0.019
b1
0.23
0.32
0.009
0.013
C
0.5
0.020
c1
45° (typ.)
D
12.6
13.0
0.496
0.510
E
10
10.65
0.394
0.419
e
1.27
0.050
e3
11.43
0.450
F
7.4
7.6
0.291
0.300
L
0.5
1.27
0.020
0.050
M
S
0.75
0.030
8° (max.)
15/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
PLCC20 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
9.78
10.03
0.385
0.395
B
8.89
9.04
0.350
0.356
D
4.2
4.57
0.165
0.180
d1
2.54
0.100
d2
0.56
0.022
E
7.37
8.38
0.290
0.330
e
1.27
0.050
e3
5.08
0.200
F
0.38
0.015
G
16/18
inch
0.101
0.004
M
1.27
0.050
M1
1.14
0.045
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
DIP20 PACKAGE MECHANICAL DATA
mm
DIM.
MIN.
a1
0.254
B
1.39
TYP.
inch
MAX.
MIN.
TYP.
MAX.
0.010
1.65
0.055
0.065
b
0.45
0.018
b1
0.25
0.010
D
25.4
1.000
E
8.5
0.335
e
2.54
0.100
e3
22.86
0.900
F
7.1
0.280
I
3.93
0.155
L
Z
3.3
0.130
1.34
0.053
17/18
ETC5064 - ETC5064-X - ETC5067 - ETC5067-X
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for
the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of SGS-THOMSON Microelectronics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
18/18