AD AD1994 Audio switching amplifier Datasheet

Audio Switching Amplifier
AD1994
GENERAL DESCRIPTION
Integrated stereo modulator and power stage
<0.005% THD + N
105 dB dynamic range (A-weighted)
2 × 25 W output power (6 Ω, 10% THD + N)
1 × 50 W output power (3 Ω, 10% THD + N)
RDS-ON < 0.3 Ω (per transistor)
PSRR > 65 dB
On-off-mute pop noise suppression
EMI optimized modulator
Short-circuit protection
Overtemperature protection
Low cost DMOS process
The AD1994 is a 2-channel, bridge tied load (BTL), switching
audio power amplifier with integrated Σ-Δ modulator. The
modulator accepts a single-ended, analog input signal and
converts it to a switching waveform to drive speakers directly.
One of the two modulators can control both output stages
providing twice the current and almost twice the efficiency for
single-channel applications. Both modulators can also control
external power devices for arbitrarily high output power. A
digital, microprocessor-compatible interface provides control of
reset, mute, and PGA gain, as well as feedback signals for thermal
and overcurrent error conditions. The output stage can operate
over a power supply voltages range of 8 V to 20 V. The analog
modulator and digital logic operate from a 5 V supply.
TE
FEATURES
LE
APPLICATIONS
Advanced televisions
Compact multimedia systems
Minicomponents
NFL–
PGA0
B
SO
PGA1
NFL+
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
FEEDBACK
NETWORK
PVDD
AD1994
AINL
MOD_FILT
ORDER
REDUCER
O
AINR
CLKO
OSCILLATOR
REF_FILT
VOLTAGE
REFERENCE
OUTL+
A2
B1
LEVEL
SHIFTER
AND
DEAD TIME
CONTROL
Σ-Δ
MODULATOR
PGA
CLKI
A1
Σ-Δ
MODULATOR
PGA
OUTL–
B2
H-BRIDGE
C1
OUTR+
C2
MODE CONTROL
LOGIC AND
POP/CLICK
SUPPRESSION
D1
PGND
FEEDBACK
NETWORK
05775-001
DCTRL0
DCTRL1
DCTRL2
NFR–
NFR+
ERR0
ERR1
ERR2
MUTE
RESET
AGND
OUTR–
D2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD1994
TABLE OF CONTENTS
Σ-Δ Modulator............................................................................ 15
Applications....................................................................................... 1
MUTE and RESET ..................................................................... 15
General Description ......................................................................... 1
Mono Mode................................................................................. 16
Functional Block Diagram .............................................................. 1
Modulator Mode ........................................................................ 16
Revision History ............................................................................... 2
Gain Structure............................................................................. 16
Specifications..................................................................................... 3
Power Stage ................................................................................. 17
Absolute Maximum Ratings............................................................ 5
Clocking....................................................................................... 18
ESD Caution.................................................................................. 5
Protection Circuits and Error Reporting ................................ 19
Pin Configuration and Function Descriptions............................. 6
Application Circuits ....................................................................... 20
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 21
Theory of Operation ...................................................................... 15
Ordering Guide .......................................................................... 21
LE
Overview...................................................................................... 15
REVISION HISTORY
O
B
SO
2/06—Revision 0: Initial Version
TE
Features .............................................................................................. 1
Rev. 0 | Page 2 of 24
AD1994
SPECIFICATIONS
Test conditions, unless otherwise specified.
Table 1.
Parameter
SUPPLY VOLTAGES
AVDD
DVDD
PVDD
AMBIENT TEMPERATURE
LOAD IMPEDANCE
CLOCK FREQUENCY
PGA GAIN
MEASUREMENT BANDWIDTH
Ratings
Table 2.
Min
Typ
Max
Unit
Test Conditions/Comments
260
210
5
135
150
120
355
265
mΩ
mΩ
A
°C
°C
°C
T = 25°C
T = 25°C
Peak
Die temperature
Die temperature
Die temperature
B
SO
LE
Parameter
RDS-ON
Per High-Side Transistor
Per Low-Side Transistor
MAXIMUM CURRENT THROUGH OUTx
THERMAL WARNING ACTIVE
THERMAL SHUTDOWN ACTIVE
RESTORE TEMPERATURE AFTER THERMAL SHUTDOWN
TE
5V
5V
12 V
25°C
6Ω
12.288 MHz
0 dB
20 Hz to 20 kHz
Table 3. Performance Specifications
Parameter
TOTAL HARMONIC DISTORTION AND NOISE (THD + N)
O
SIGNAL-TO-NOISE RATIO (SNR)
DYNAMIC RANGE (DNR)
CROSSTALK (LEFT-TO-RIGHT OR RIGHT-TO-LEFT)
Typ
0.003
0.006
0.01
0.02
105
105
−100
Unit
%
%
%
%
dB
dB
dB
Test Conditions/Comments
PGA = 0 dB, PO = 1 W, 1 kHz
PGA = 6 dB, PO = 1 W, 1 kHz
PGA = 12 dB, PO = 1 W, 1 kHz
PGA = 18 dB, PO = 1 W, 1 kHz
1 kHz, A-weighted, 0 dB referred to 1% THD + N output
1 kHz, A-weighted, −60 dB referred to 1% THD + N output
PGA = 0 dB, PO = 5 W, 1 kHz
Table 4. DC Specifications
Parameter
INPUT IMPEDANCE
OUTPUT DC OFFSET
Typ
20
±4
Unit
kΩ
mV
Rev. 0 | Page 3 of 24
Test Conditions/Comments
AINL, AINR input pins
Independent of PGA setting
AD1994
Table 5. Power Supplies
Parameter
ANALOG SUPPLY, AVDD
Min
4.5
Typ
5.0
Max
5.5
Unit
V
DIGITAL SUPPLY, DVDD
4.5
5.0
5.5
V
POWER TRANSISTOR SUPPLY, PVDD
6.5
8 to 20
22.5
V
0.6
7.5
19
1
11
40
μA
μA
μA
20
5.5
30
mA
mA
mA
Table 6. Digital I/O
mA
mA
mA
Min
2.0
Typ
Max
0.8
2.4
0.4
10
Unit
V
V
V
V
μA
Test Conditions/Comments
@ 4 mA
@ 4 mA
B
SO
Parameter
INPUT LOGIC HIGH
INPUT LOGIC LOW
OUTPUT LOGIC HIGH
OUTPUT LOGIC LOW
LEAKAGE CURRENT ON DIGITAL OUTPUTS
27
7
260
LE
20
5.5
218
RESET held low
5V
5V
12 V
Inputs grounded, nonoverlap = minimum
5V
5V
12 V
VIN = 1 V rms, RL = 6 Ω, PO = 1 W
5V
5V
12 V
TE
RESET/POWER-DOWN CURRENT
AVDD
DVDD
PVDD
QUIESCENT CURRENT
AVDD
DVDD
PVDD
OPERATING CURRENT
AVDD
DVDD
PVDD
Test Conditions/Comments
Table 7. Digital Timing
Parameter
tMD
tUD
Typ
10
34
Unit
μs
μs
Test Conditions/Comments
Delay after MUTE is asserted until output stops switching
Delay after MUTE is deasserted until output starts switching
tMD
tUD
05775-002
O
MUTE
OUTx
Figure 2. Mute and Unmute Delay Timing
Rev. 0 | Page 4 of 24
AD1994
ABSOLUTE MAXIMUM RATINGS
Table 8.
19.2°C/W
0.9°C/W
9.7°C/W
Including any induced voltage due to inductive load.
ESD CAUTION
LE
1
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +6.5 V
−0.3 V to +30.0 V
−0.3 V to +0.3 V
−0.5 V to +0.5 V
–40°C to +85°C
–65°C to +150°C
150°C
TE
Parameter
AVDD, DVDD to AGND, DGND
PVDDx to PGNDx 1
AGND to DGND to PGNDx
AVDD, to DVDD
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Thermal Resistance
θJA
θJC (at the Exposed Pad Surface)
θJB (on JEDEC Standard PCB)
O
B
SO
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 24
AD1994
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
MONO_EN
NFL+
NFL–
NC
AINL
NC
MOD_FILT
AVDD
AGND
REF_FILT
NC
AINR
NC
NFR–
NFR+
MOD_EN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PGND2
PGND2
PGND2
OUTR+
OUTR+
OUTR+
PVDD2
PVDD2
PVDD2
PVDD2
OUTR–
OUTR–
OUTR–
PGND2
PGND2
PGND2
TE
AD1994
05775-003
ERR2
ERR1
MODL/ERR0
MODR/DCTRL2
DCTRL1
DCTRL0
DGND
DVDD
DVDD
DGND
CLKI
CLKO
MUTE
RESET
PGA1
PGA0
NC = NO CONNECT
PIN 1
INDICATOR
LE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGND1
PGND1
PGND1
OUTL+
OUTL+
OUTL+
PVDD1
PVDD1
PVDD1
PVDD1
OUTL–
OUTL–
OUTL–
PGND1
PGND1
PGND1
B
SO
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions
Mnemonic
PGND1
OUTL+
PVDD1
OUTL−
PGND1
ERR2
ERR1
MODL/ERR0
MODR/DCTRL2
DCTRL1
DCTRL0
DGND
DVDD
CLKI
CLKO
MUTE
RESET
PGA1
PGA0
PGND2
OUTR−
PVDD2
OUTR+
PGND2
MOD_EN
In/Out
O
O
O
O
O
I/O
I
I
O
Pin No.
1, 2, 3
4, 5, 6
7, 8, 9, 10
11, 12, 13
14, 15, 16
17
18
19
20
21
22
23, 26
24, 25
27
28
29
30
31
32
33, 34, 35
36, 37, 38
39, 40, 41, 42
43, 44, 45
46, 47, 48
49
I
O
I
I
I
I
O
O
I
Description
Negative Power Supply. Used for the A2 and B2 high power transistors.
Output of Transistor Pair A1 and A2.
Positive Power Supply. Used for the A1 and B1 high power transistors.
Output of Transistor Pair B1 and B2.
Negative Power Supply. Used for the A2 and B2 high power transistors.
Active Low Thermal Shutdown.
Active Low Thermal Warning Error Output.
Active Low Overcurrent Error Output/Modulator Output Left.
Nonoverlap Time Setting MSB/Modulator Output Right.
Nonoverlap Time Setting.
Nonoverlap Time Setting LSB.
Negative Power Supply for Low Power Digital Circuitry.
Positive Power Supply for Low Power Digital Circuitry.
Clock Input for 256 × fS Audio Modulator Clock.
Inverted Version of CLKI for Use with an External XTAL Oscillator.
Active Low Mute Input.
Active Low Reset Input.
PGA Gain Control MSB.
PGA Gain Control LSB.
Negative Power Supply for High Power Transistors C2 and D2.
Output of Transistor Pair D1 and D2.
Positive Power Supply for High Power Transistors C1 and D1.
Output of Transistor Pair C1 and C2.
Negative Power Supply for High Power Transistors C2 and D2.
Modulator Mode Enable Pin when Pulled to Logic High.
Rev. 0 | Page 6 of 24
AD1994
In/Out
I
I
I
O
O
O
I
I
I
Description
Right Channel Negative Feedback—Noninverting Input.
Right Channel Negative Feedback—Inverting Input.
No Connection—Should Be Left Floating.
Analog Input for Right Channel.
No Connection—Should Be Left Floating.
Filter Pin for Band Gap Reference—Should Be Bypassed to AGND.
Negative Power Supply for Low Power Analog Circuitry.
Positive Power Supply for Low Power Analog Circuitry.
Modulator Filter Pin—Used to Set Time Constant of Modulator Order Reduction Circuit.
No Connection—Should Be Left Floating.
Analog Input for Left Channel.
No connection—Should Be Left Floating.
Left Channel Negative Feedback—Inverting Input.
Left Channel Negative Feedback—Noninverting Input.
Mono Mode Enable Pin—When Pulled Up to Logic High.
TE
Mnemonic
NFR+
NFR−
NC
AINR
NC
REF_FILT
AGND
AVDD
MOD_FILT
NC
AINL
NC
NFL−
NFL+
MONO_EN
O
B
SO
LE
Pin No.
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Rev. 0 | Page 7 of 24
AD1994
0
–20
–20
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
–120
–140
0
6
8
10
12
14
16
18
20
18
20
18
20
FREQUENCY (kHz)
LE
–60
–120
–140
0
2
4
6
8
10
12
14
16
18
20
–20
–40
–60
–80
–100
–120
–140
–160
05775-005
–100
B
SO
–80
POWER (dBFS: 0dB = Power at which
THD = 1% (10.1W))
–40
FREQUENCY (kHz)
0
O
–20
–40
–60
–80
–100
–120
0
2
4
6
8
10
12
14
16
FREQUENCY (kHz)
18
20
6
8
10
12
14
16
0
05775-006
–140
4
Figure 8. −60 dBFS Output Power into 6 Ω Load
POWER (dBFS: 0dB = Power at which
THD = 1% (7.9W))
0
2
FREQUENCY (kHz)
Figure 5. 1 W Output Power into 6 Ω Load
POWER (dBFS: 0dB = Power at which
THD = 1% (7.9W))
4
0
–20
–160
2
Figure 7. −60 dBFS Output Power into 4 Ω Load
0
POWER (dBFS: 0dB = Power at which
THD = 1% (10.1W))
–100
–160
Figure 4. 1 W Output Power into 4 Ω Load
–160
–80
05775-007
–80
–60
05775-008
–60
–40
05775-009
–40
TE
POWER (dBFS: 0dB = Power at which
THD = 1% (13.8W))
0
05775-004
POWER (dBFS: 0dB = Power at which
THD = 1% (13.8W))
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. 1 W Output Power into 8 Ω Load
–20
–40
–60
–80
–100
–120
–140
–160
0
2
4
6
8
10
12
14
16
FREQUENCY (kHz)
Figure 9. −60 dBFS Output Power into 8 Ω Load
Rev. 0 | Page 8 of 24
AD1994
0
0.1
–70
THD (%)
–40
–60
0.01
–80
–80
–90
0.001
–100
–100
–110
10k
Figure 10. IMD for 19 kHz/20 kHz Twin-Tone Stimulus with
1 W Total Output Power
0.1
PGA GAIN = 0dB
15
10
–70
0.01
–80
–90
100
10k
1k
05775-011
B
SO
0.001
FREQUENCY (Hz)
Figure 11. Amplifier Gain vs. Frequency, 6 Ω Load, PVDD = 12 V
–60
L CHANNEL DRIVEN,
R CHANNEL IDLE
–100
–110
0.0001
100
1k
10k
Figure 14. THD vs. Frequency, 1 W Output Power into 6 Ω Load, PVDD = 12 V
0
–40
–50
0.1
–60
–70
0.01
–80
–90
–80
0.001
–100
–100
–110
L CHANNEL IDLE,
R CHANNEL DRIVEN
100
1k
10k
FREQUENCY (Hz)
Figure 12. Channel Separation vs. Frequency, Driven Channel Has
1 W Output Power into 6 Ω Load
05775-012
–120
–120
FREQUENCY (Hz)
THD (%)
O
–40
–60
THD (dB, Relative to Fundamental)
20
–50
05775-014
PGA GAIN = 6dB
–40
THD (dB, Relative to Fundamental)
25
–120
FREQUENCY (Hz)
THD (%)
PGA GAIN = 12dB
–20
10k
LE
30
0
1k
0
PGA GAIN = 18dB
35
0
100
Figure 13. THD vs. Frequency, 1 W Output Power into 4 Ω Load, PVDD = 12 V
40
5
0.0001
0.0001
100
1k
FREQUENCY (Hz)
10k
–120
05775-015
1k
TE
100
05775-013
–120
FREQUENCY (Hz)
AMPLIFIER GAIN (dB)
–60
THD (dB, Relative to Fundamental)
–50
–20
–140
SIGNAL IN IDLE CHANNEL (dB, Relative to
Driven Channel Signal)
–40
0
05775-010
POWER (dB, Relative to 500mW)
(Output Power in the 19k and 20k Tones)
20
Figure 15. THD vs. Frequency, 1 W Output Power into 8 Ω Load, PVDD = 12 V
Rev. 0 | Page 9 of 24
AD1994
–80
–90
THD
0.001
0.1
10
1
–100
OUTPUT POWER (W)
–90
10
LE
–50
–60
0.1
–70
THD + N
–90
THD
10
1
–100
OUTPUT POWER (W)
Figure 17. THD and THD + N vs. Output Power, 1 kHz Sine, 6 Ω Load, PVDD = 12 V
–30
–40
1
–50
–60
0.1
0.01
–70
THD + N
–80
–90
0.001
0.1
THD
1
OUTPUT POWER (W)
10
–100
–60
–70
–80
–90
THD
1
10
–100
OUTPUT POWER (W)
Figure 20. THD and THD + N vs. Output Power, 1 kHz Sine, 6 Ω Load, PVDD = 15 V
100
0
–10
–20
10
–30
THD or THD + N (%)
–20
O
THD or THD + N (%)
10
THD or THD + N (dB, Relative to Fundamental)
–10
–20
–50
THD + N
0.001
0.1
0
–40
1
–50
–60
0.1
–70
0.01
THD + N
–80
–90
05775-018
100
–10
–40
0.1
0.01
0
–30
1
B
SO
–80
–100
Figure 19. THD and THD + N vs. Output Power, 1 kHz Sine, 4 Ω Load, PVDD = 15 V
THD or THD + N (%)
–40
1
0.001
0.1
10
OUTPUT POWER (W)
05775-017
THD or THD + N (%)
–30
0.01
1
100
THD or THD + N (dB, Relative to Fundamental)
–20
10
THD
0.001
0.1
0
–10
–80
0.01
Figure 16. THD and THD + N vs. Output Power, 1 kHz Sine, 4 Ω Load, PVDD = 12 V
100
–70
THD + N
Figure 18. THD and THD + N vs. Output Power, 1 kHz Sine, 8 Ω Load, PVDD = 12 V
THD or THD + N (dB, Relative to Fundamental)
0.01
THD + N
–60
0.1
05775-019
–70
–50
THD or THD + N (dB, Relative to Fundamental)
–60
0.1
–40
1
05775-020
–50
–30
0.001
0.1
THD
1
OUTPUT POWER (W)
10
–100
THD or THD + N (dB, Relative to Fundamental)
–40
1
–20
10
05775-021
THD or THD + N (%)
–30
TE
–20
10
0
–10
THD or THD + N (%)
–10
100
THD or THD + N (dB, Relative to Fundamental)
0
05775-016
100
Figure 21. THD and THD + N vs. Output Power, 1 kHz Sine, 8 Ω Load, PVDD = 15 V
Rev. 0 | Page 10 of 24
AD1994
–90
THD
0.001
0.1
10
1
–100
OUTPUT POWER (W)
–90
Figure 22. THD and THD + N vs. Output Power, 1 kHz Sine, 4 Ω Load, PVDD = 18 V
0
–10
–20
–50
–60
0.1
–70
THD + N
–80
–90
THD
10
1
–100
OUTPUT POWER (W)
10
–50
–60
0.1
0.01
–70
THD + N
–80
–90
0.001
0.1
THD
1
OUTPUT POWER (W)
10
–100
THD or THD + N (dB, Relative to Fundamental)
–40
1
–20
–50
–60
0.1
–70
–80
–90
THD
0.001
0.1
10
1
–100
OUTPUT POWER (W)
Figure 26. THD and THD + N vs. Output Power, 1 kHz Sine, 6 Ω Load, PVDD = 20 V
100
0
–10
–20
10
–30
–40
1
–50
–60
0.1
–70
0.01
THD + N
–80
–90
05775-024
–30
O
THD or THD + N (%)
10
–20
–10
–40
1
0.01
0
–10
0
–30
THD + N
Figure 23. THD and THD + N vs. Output Power, 1 kHz Sine, 6 Ω Load, PVDD = 18 V
100
Figure 25. THD and THD + N vs. Output Power, 1 kHz Sine, 4 Ω Load, PVDD = 20 V
05775-023
0.001
0.1
–100
OUTPUT POWER (W)
THD or THD + N (%)
–40
1
0.01
10
1
LE
–30
B
SO
THD or THD + N (%)
10
THD
0.001
0.1
100
THD or THD + N (dB, Relative to Fundamental)
100
–80
0.01
Figure 24. THD and THD + N vs. Output Power, 1 kHz Sine, 8 Ω Load, PVDD = 18 V
THD or THD + N (dB, Relative to Fundamental)
–80
–70
THD + N
05775-025
0.01
THD + N
–60
0.1
THD or THD + N (dB, Relative to Fundamental)
–70
–50
05775-026
–60
0.1
–40
1
0.001
0.1
THD
1
OUTPUT POWER (W)
10
–100
THD or THD + N (dB, Relative to Fundamental)
–50
–30
05775-027
–40
1
–20
10
THD or THD + N (%)
THD or THD + N (%)
–30
TE
–20
10
0
–10
THD or THD + N (%)
–10
100
THD or THD + N (dB, Relative to Fundamental)
0
05775-022
100
Figure 27. THD and THD + N vs. Output Power, 1 kHz Sine, 8 Ω Load, PVDD = 20 V
Rev. 0 | Page 11 of 24
50
100
45
90
40
80
THD = 10%
30
25
20
THD = 1%
15
30
10
12
14
16
18
20
0
12
14
16
18
20
Figure 31. Maximum Power vs. PVDD, Mono Mode, 2 Ω Load
50
100
45
90
40
LE
80
OUTPUT POWER (W)
30
THD = 10%
25
20
THD = 1%
5
8
10
12
14
16
18
20
PVDD VOLTAGE (V)
40
O
35
30
25
THD = 10%
20
15
30
THD = 1%
8
10
12
14
16
18
20
PVDD VOLTAGE (V)
Figure 32. Maximum Power vs. PVDD, Mono Mode, 3 Ω Load
100
90
80
THD = 1%
10
THD = 10%
40
0
OUTPUT POWER (W)
45
50
10
Figure 29. Maximum Power vs. PVDD, Stereo Mode, 6 Ω Load
50
60
20
05775-029
10
B
SO
15
70
05775-032
35
70
60
50
40
THD = 10%
30
THD = 1%
20
8
10
12
14
16
18
20
PVDD VOLTAGE (V)
Figure 30. Maximum Power vs. PVDD, Stereo Mode, 8 Ω Load
0
8
10
12
14
16
18
20
PVDD VOLTAGE (V)
Figure 33. Maximum Power vs. PVDD, Mono Mode, 4 Ω Load
Rev. 0 | Page 12 of 24
05775-033
10
05775-030
5
0
10
PVDD VOLTAGE (V)
Figure 28. Maximum Power vs. PVDD, Stereo Mode, 4 Ω Load
0
8
TE
10
THD = 1%
40
5
PVDD VOLTAGE (V)
OUTPUT POWER PER CHANNEL (W)
50
20
8
THD = 10%
60
10
0
OUTPUT POWER PER CHANNEL (W)
70
05775-031
OUTPUT POWER (W)
35
05775-028
OUTPUT POWER PER CHANNEL (W)
AD1994
AD1994
100
100
90
90
2 x8Ω LOAD
2 x4Ω LOAD
60
50
40
30
40
30
10
10
0
0.1
OUTPUT POWER (W)
Figure 34. Power Efficiency vs. Output Power, Stereo Mode, PVDD = 12 V
Figure 37. Power Efficiency vs. Output Power, Mono Mode, PVDD = 12 V
8
3.0
2.5
2.0
2 x6Ω LOAD
1.5
1.0
2
4
6
8
10
1 x2Ω LOAD
12
14
16
18
20
OUTPUT POWER PER CHANNEL (W)
6
5
4
2
0
0
0
–10
–20
–60
–70
–80
–90
15
20
25
30
35
40
250
200
P-TYPE 25°C
N-TYPE 25°C
P-TYPE 130°C
N-TYPE 130°C
150
100
–100
–110
–120
50
50
100
200
500
1k
2k
5k
10k
20k
FREQUENCY (Hz)
05775-039
–130
–140
20
10
Figure 38. On-Chip Power Dissipation vs.
Output Power, Mono Mode, PVDD = 12 V
COUNT
O
–30
–40
–50
5
Figure 36. Power Supply Rejection Ratio (PSRR) vs. Frequency
0
100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400
MOSFET ON-RESISTANCE (mΩ)
Figure 39. Histogram Showing Manufacturing Variation of
RDS-ON of the Output MOSFETS at 25°C and 130°C
Rev. 0 | Page 13 of 24
05775-036
20
1 x4Ω LOAD
OUTPUT POWER (W)
Figure 35. On-Chip Power Dissipation vs.
Output Power, Stereo Mode, PVDD = 12 V
10
1 x3Ω LOAD
3
1
05775-035
0
B
SO
2 x8Ω LOAD
0.5
7
LE
2 x4Ω LOAD
05775-038
3.5
ON-CHIP POWER DISSIPATION (W)
4.0
PSRR (dB)
10
1
TE
10
OUTPUT POWER PER CHANNEL (W)
ON-CHIP POWER DISSIPATION
PER CHANNEL (W)
50
20
1
1 x2Ω LOAD
60
20
0
0.1
1 x3Ω LOAD
70
05775-037
POWER EFFICIENCY (%)
70
0
1 x4Ω LOAD
80
2 x6Ω LOAD
05775-034
POWER EFFICIENCY (%)
80
AD1994
100
20
90
18
ON-CHIP POWER DISSIPATION (W)
2 x8Ω LOAD
2 x6Ω LOAD
70
2 x4Ω LOAD
60
50
40
30
20
10
1 x2Ω LOAD
16
14
12
10
1 x3Ω LOAD
8
6
1 x4Ω LOAD
4
2
OUTPUT POWER PER CHANNEL (W)
0
10
20
30
40
50
60
70
TE
10
1
0
05775-040
0
0.1
80
OUTPUT POWER (W)
Figure 40. Power Efficiency vs. Output Power, Stereo Mode, PVDD = 18 V
05775-043
POWER EFFICIENCY (%)
80
Figure 42. On-Chip Power Dissipation vs.
Output Power, Mono Mode, PVDD = 18 V
10
100
9
90
5
4
2 x6Ω LOAD
3
2 x8Ω LOAD
1
0
0
5
10
15
20
25
30
OUTPUT POWER PER CHANNEL (W)
40
60
1 x2Ω LOAD
50
40
30
20
10
0
0.1
1
OUTPUT POWER (W)
10
Figure 43. Power Efficiency vs. Output Power, Mono Mode, PVDD = 18 V
O
Figure 41. On-Chip Power Dissipation vs.
Output Power, Stereo Mode, PVDD = 18 V
35
05775-041
2
1 x3Ω LOAD
70
05775-042
6
POWER EFFICIENCY (%)
2 x4Ω LOAD
7
LE
80
B
SO
ON-CHIP POWER DISSIPATION
PER CHANNEL (W)
1 x4Ω LOAD
8
Rev. 0 | Page 14 of 24
AD1994
THEORY OF OPERATION
The AD1994 is a 2-channel, high performance, switching, audio
power amplifier. Each of the two Σ-Δ modulators converts a
single-ended analog input into a 2-level pulse stream that
controls the differential, full H-bridge, power output stage. The
combination of an Σ-Δ modulator and a switching power stage
provides an inherently linear and efficient means of amplifying
the entire range of audio frequencies. The AD1994 also offers
warning and protection circuits for overcurrent and overtemperature conditions, as well as silent turn-on and turn-off
transitions.
Σ-Δ MODULATOR
The modulator has a noise shaping effect, and SNR is increased
in the audio band by shifting the quantization noise upward in
frequency. For a nominal input clock frequency of 12.288 MHz,
the noise floor rises sharply above 20 kHz. The actual clock
frequency used in an application circuit can deviate from this
rate by as much as ±10%, and the corner frequency of the noise
scales proportionately. The frequency at which the quantization
noise dominates the output determines the amplifier’s practical
bandwidth.
The expected transition rate at the output of a typical seventhorder, Σ-Δ modulator would be high enough to negate much of
the efficiency benefit of a switching amplifier. However, the
AD1994 incorporates a proprietary, dynamic, switching rate,
reduction scheme that lowers that average switching frequency
by approximately a factor of four. This results in slightly
increased output energy between 450 kHz and 500 kHz and
efficiency on par with other Class-D amplifiers. This low-Q
spectral boost is an artifact of the noise shaping and is in no
way related to the carrier frequency visible in the spectrum of
PWM Class-D amplifiers.
B
SO
LE
The AD1994 is a switching type, also known as a Class-D, audio
power amplifier. This class of amplifiers maximizes efficiency
by only using its power output devices in full-on or full-off
states. While most Class-D amplifiers use some variation of
pulse-width modulation (PWM), the AD1994 uses Σ-Δ
modulation to determine the switching pattern of the output
devices. This provides a number of important benefits. Σ-Δ
modulators do not produce a sharp peak with many harmonics
in the AM frequency band as pulse-width modulators (PWM)
often do. In addition, the 1-bit quantizer produces excellent
linearity across the full amplitude range.
prolonged voltage clipping conditions, enabling stable operation
at full modulation. The dynamic-order reduction circuit uses
the high-order modulator, except during the crests of the highest
waveform peaks. During these peaks, the quantization noise
increases, but the SNR is still quite high. These modulator order
transitions are fast and smooth enough to avoid audible artifacts.
TE
OVERVIEW
Σ-Δ modulators require feedback to generate an error signal
with respect to the input. The feedback voltages for the AD1994
modulators come from the outputs of the power devices and
before the passive low-pass filters (see Figure 45). This compensates
for nonlinear behavior in the power stage, such as nonoverlap
time, mismatched rise and fall times, and propagation delays. It
also reduces sensitivity to both dc and transient changes of the
power supply voltage.
O
Σ-Δ modulators operate in discrete time. As with all timequantized systems, the Nyquist frequency is equal to half of
the sampling frequency and input signals above that point
aliases back into the base band. The AD1994 sampling frequency
(master clock) is equal to half the frequency of the input clock,
approximately 6 MHz, so images only alias for input frequencies
above approximately 3 MHz. This is far enough above the audio
band that bandwidth and aliasing are not a problem in real
applications.
The AD1994 implements a seventh-order, Σ-Δ modulator with
a 1-bit quantizer. Traditionally, higher-order designs such as
this are not suitable for driving a Class-D amplifier because of
stability problems at higher modulation factors. The modulator
design of the AD1994 is unusual in that it is stable to 90%
modulation. To allow the amplifier to drive even further, the
AD1994 dynamically reverts from seventh order to second
order above a fixed modulation threshold. The second-order
modulator is unconditionally stable, including during
MUTE AND RESET
When power is applied and the RESET pin remains asserted,
the AD1994 is in its lowest power consumption mode. The
analog modulator is not running, and the power stage is tristated. On deasserting the RESET pin, the modulator begins a
start-up sequence that includes initialization of the modulator,
the protection circuits, and other functions.
Once the start-up sequence is complete, the amplifier is in a
state in which the modulator is running, but the output stage is
not driven. When MUTE is deasserted, the output is started
using a soft-start sequence that avoids any audible pop or click
noise in the output signal.
The output power transistors do not switch while MUTE
remains asserted. Unlike the analog mute circuits found on
some amplifiers that can be limited in their attenuation by the
control logic or crosstalk, the mute attenuation on the AD1994
is greater than its dynamic range. The noise floor of the output
signal also drops while in MUTE because the output transistors
are not switching.
Rev. 0 | Page 15 of 24
AD1994
Careful power-up is necessary when using the AD1994 to
ensure correct operation and to avoid possible latch-up issues.
The AD1994 should be powered up with RESET and MUTE
held low until all the power supplies have stabilized. Once the
supplies have stabilized, bring the AD1994 out of RESET by
bringing RESET high.
For reactive loads, the impedance can only be below the
recommended threshold over a small portion of the amplifier’s
bandwidth. In these cases, the amplifier can enter overcurrent
shutdown in response to even small input signals in those
frequency bands. When designing a system, use the minimum
load impedance over the entire range of amplified frequencies
when calculating current output rather than the average or
nominal load impedance ratings often cited by loudspeaker
driver manufacturers.
MODULATOR MODE
LE
Begin the soft unmute sequence by bringing MUTE high at
least 1 sec after the RESET rising edge. The amplifier produces
audio using a shorter start-up sequence (as shown in Table 7),
but the amplifier can produce an audible pop or click noise as
the output starts switching. This is because the ac coupling
capacitors at the analog input have a long time constant. If
MUTE is deasserted substantially less than 1 sec after deasserting
RESET, then these capacitors may not have charged to a steady
state. They need ample time to settle at a bias voltage of VREF,
the reference voltage for the single-ended inputs, or the
amplifier starts with a slight dc offset.
When the load impedance is substantially less than 4 Ω, the
system would be current limited if configured for normal stereo
operation, and the amplifier would enter the overcurrent error
state when a nominal input signal is applied. Under these
conditions, the amount of real power delivered to the load
increases in mono mode. The minimum recommended
impedance in mono mode is 2 Ω (as compared to 4 Ω for stereo
operation), so the effective power delivered to a single channel
can be as much as twice the maximum achievable in stereo mode.
TE
Power-Up Sequencing
MONO MODE
The AD1994 is capable of operating as a modulator for controlling
external power devices. When MOD_EN (Pin 49) is logic level
high at the rising edge of RESET, both the left and right internal
power stages are disabled. The error output flags (ERR2, ERR1,
and ERR0) and the nonoverlap delay inputs (DCNTL2, DCNTL1,
and DCNTL0) no longer have meaning because they apply only
to the internal power stages. The logic level outputs from the
two modulators appear on Pin 19 (MODL) and Pin 20 (MODR).
B
SO
The power supply voltage and the limited current that the
output transistors can source combine to dictate that maximum
total output power of the AD1994. For higher impedance loads,
the system is voltage limited, and for lower impedance loads,
the system is current limited. In normal stereo operation, each
output is driven by four MOSFET devices arranged in a full
H-bridge configuration, also known as bridge-tied load (BTL).
This provides the maximum differential output voltage swing,
equal to twice the voltage of the power supply. However,
operating in mono mode doubles the maximum achievable
output current.
Analog Input Levels
The AD1994 has single-ended inputs for the left and right
channels. The analog input section uses an internal amplifier to
bias the input signal to the reference level, VREF, which is nominally
equal to AVDD/2. A dc-blocking capacitor, as shown in Figure 44,
prevents this bias voltage from affecting the signal source. In
combination with the nominal 20 kΩ input impedance, the value
of this capacitor should be large enough to produce a flat
frequency response at the lowest input frequency of interest.
Note that the amplifier is capable of dc-coupled operation if the
circuit includes some means to account for this bias voltage.
Note that the practical effect of mono mode depends greatly on
the load impedance. If the load is 4 Ω or greater, the efficiency
of the amplifier increases due to the reduced effective resistance
of power FETs, and the amplifier dissipates less heat. However,
the amount of real power delivered to the load does not increase
because the system is voltage limited (that is, the output
waveform voltage clips before current limiting occurs).
Rev. 0 | Page 16 of 24
0V
+
AINL/
AINR
05775-044
O
When MONO_EN (Pin 64) is logic level high at the rising edge
of RESET, the right channel modulator is disabled, and the left
channel modulator is used to drive both the left and right
output stages in parallel. When using mono mode, connect
OUTL+ directly to OUTR+, connect OUTL− directly to
OUTR−, and use the combined differential pair to a drive a
single load. Connect the feedback pair to the positive and
negative feedback input of the left modulator. The right
channel feedback pins are unused in mono mode. The RDS-ON
of the power FETs drops to half of its value in stereo operation
because the devices are in parallel, and the AD1994 delivers its
full current capability to a single channel.
GAIN STRUCTURE
Figure 44. AC-Coupled Input Signal
AD1994
Setting the Modulator Gain
Programmable Gain Amplifier (PGA)
The AD1994 modulator uses a combination of the input signal
and feedback from the power output stage to calculate its twostate output pattern. The feedback input nodes are part of the
internal analog circuit that operates from the AVDD (nominal
5 V) power supply. Because the voltage measured at the power
outputs is nominally between 0 V and PVDD, and thus beyond
the 0 V to AVDD range, a voltage divider is required to scale the
feedback to an appropriate level.
The Σ-Δ modulator itself requires a fixed gain for a given value
of PVDD to maintain optimal stability. This gain can be appropriate,
but many applications require more gain to account for low
source signal levels. The AD1994 includes a programmable gain
amplifier (PGA) to boost the overall amplifier gain. PGA1 (Pin
31) and PGA0 (Pin 32) select one of four PGA gain values, as
shown in Table 11.
Table 11. PGA Gain Settings
Resistor voltage dividers should sense the voltage on each side
of the differential output and provide these feedback signals to
the modulator, as shown in Figure 45.
PVDD
EXTERNAL COMPONENTS
D1
L
RL
OUTx+
D2
R1
C
D3
L
OUTx–
C
R3
D4
PGND
NFx–
R2
R4
Figure 45. H-Bridge Configuration
05775-045
NFx+
The H-Bridge
B
SO
R1 + R2 R3 + R 4 PVDD
=
=
3.635
R2
R4
The AD1994 incorporates a single-ended-to-differential
converter for each channel in the analog front-end section.
The PGA is also part of this analog front-end, and it affects the
analog input signal before it enters the Σ-Δ modulator. The
PGA1 and PGA0 pins are continuously monitored and allow
the gain to be changed at any time.
POWER STAGE
The resistor values should satisfy the following equation to
maintain modulator stability.
Gain =
Selecting a gain that meets this criterion ensures that the
modulator remains in a stable operating condition.
The ratio of the resistances sets the gain rather than the absolute
values. However, the dividers provide a path from the high
voltage supply to ground; therefore, the values should be large
enough to produce negligible loss due to quiescent current.
O
The chip contains a calibration circuit to minimize voltage
offsets at the speaker, which helps to minimize clicks and pops
when muting or unmuting. Optimal performance is achieved
for the offset calibration circuit when the feedback divider resistors
sum to 6 kΩ, that is, (R1 + R2) = 6 kΩ, and (R3 + R4) = 6 kΩ.
The output stage of the AD1994 includes four integrated
MOSFET devices arranged in a full H-bridge, as shown in
Figure 45. The P-Type, high-side transistor of one leg and the
N-Type, low-side transistor of the opposite leg switch on and off
as a pair producing a total voltage swing across the load of
−PVDD to +PVDD. The drive is floating and differential, and it is
important that neither output terminal be shorted to ground.
The power supply for the output stage of the AD1994, PVDD,
should be in the 8 V to 20 V range and should be capable of
supplying enough current to drive the load. Connect the power
supply across the PVDD and PGND pins. The feedback pins,
NFR+, NFR−, NFL+, and NFL−, supply negative feedback to
the modulator as described in the Setting the Modulator Gain
section.
Table 10. Recommended Feedback Resistor Values
PVDD (V)
12
15
18
20
R1 (kΩ)
4.2
4.55
4.8
4.91
R2 (kΩ)
1.8
1.45
1.2
1.09
PGA Gain (dB)
0
6
12
18
LE
PGND
PGA0
0
1
0
1
TE
PVDD
PGA1
0
0
1
1
Gain
3.3 (+10.4 dB)
4.1 (+12.3 dB)
5.0 (+14.0 dB)
5.5 (+14.8 dB)
Rev. 0 | Page 17 of 24
AD1994
The AD1994 allows the user to select from one of eight different
nonoverlap times, as shown in Figure 46. Nonoverlap time
prevents or minimizes the period during which both the highside and low-side devices are on simultaneously due to propagation
delays and nonzero rise and fall times. If both the upper and
lower portions of a half-bridge conduct simultaneously, there is a
path directly from the power supply to ground and an induced
current flow known as shoot-through. However, introducing
this delay increases distortion by pushing the switching pattern
further from an ideal two-state waveform. Selecting the
nonoverlap delay requires a compromise between distortion
and efficiency. The logic levels on the three delay control pins,
DCTRL2, DCTRL1, and DCTRL0, set the nonoverlap time
according to Table 12. The state of DCTRL[2:0] is read on the
rising edge of RESET and should not be changed while RESET
is logic high.
Table 12. Nonoverlap Time Settings
DCTRL1
DCTRL0
Nonoverlap Time (ns)1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
62
49
37
24
15
13.5
12
9
Using a Crystal Oscillator
The AD1994 can use a crystal connected to the CLKI and
CLKO pins as a master clock source, as shown in Figure 47. The
CLKI and CLKO pins connect to an internal inverter to create a
full resonator. The typical values shown work in many applications,
but the crystal manufacturer should provide the exact type and
value of the capacitors and the resistor.
B
SO
22pF
XTAL
22pF
47Ω
tNOL
tNOL
05775-046
LOW-SIDE
GATE DRIVE
05775-047
HIGH-SIDE
GATE DRIVE
CLKO
Values are typical and are not production tested.
CLKI
1
The clock frequency does not have to be exactly equal to
12.288 kHz and can vary by up to ±10%. For other rates, the
noise corner scales linearly with frequency. When the modulator
runs at a rate lower than nominal, the average power stage
switching frequency decreases, the efficiency increases slightly,
and the noise floor begins to rise at a slightly lower frequency.
Likewise, a faster clock gives slightly increased bandwidth and
slightly lower efficiency.
LE
DCTRL2
As mentioned in the Σ-Δ Modulator section, the modulator has
a noise-shaping effect such that SNR is increased within the
audio band by shifting modulator quantization noise upward in
frequency. For external clock frequency of 12.288 MHz, the
modulator’s noise-shaping works in a manner that results in a
flat noise floor at the amplifier output for frequencies 20 kHz
and below. Above 20 kHz, the amplifier noise rises due to the
spectral shaping of the modulator quantization noise. At very
high frequencies, the noise floor levels off and decreases due to
poles in the modulator noise-transfer function and in the
external LC filter.
TE
Output Transistor Nonoverlap Time
Figure 47. Crystal Connection
Using an External Clock Source
O
Figure 46. Half-Bridge Nonoverlap Delay Timing
The shortest setting (DCTRL[2:0] = 111) or the second shortest
setting (DCTRL[2:0] = 111) is recommended for most applications.
These two settings allow a small trade-off between efficiency
and distortion. Longer nonoverlap times generally increase
distortion while providing little or no decrease in shootthrough current.
CLOCKING
The AD1994 Σ-Δ modulator requires an external clock source
with a nominal frequency of 12.288 MHz. This clock can come
from a crystal or from an existing clock signal in the application
circuit. The discrete time portions of the modulator run internally
at 6.144 MHz, corresponding to 128 × fS, where fS = 48 kHz.
If a clock signal of the appropriate frequency already exists in
the application circuit, connect it directly to CLKI and leave
CLKO floating. The logic levels of the square wave should be
compatible with those defined in Specifications section.
Large amounts of jitter on the clock input degrade performance.
Whenever possible, avoid passing the clock signal though
programmable logic and other circuits with unknown or variable
propagation delay. In general, clock signals suitable for audio ADCs
or DACs are also appropriate for use with the AD1994.
Rev. 0 | Page 18 of 24
AD1994
Clocking Multiple Amplifiers in Parallel
Overcurrent Protection
If there are multiple AD199x family amplifiers connected to the
same PVDD supply, use the same clock source (or synchronous
derivatives) for each amplifier as previously described. Avoid
clocking amplifiers from similar but asynchronous clocks if
they use the same power supply because this can result in beat
frequencies.
The AD1994 features over current or short-circuit protection. If
the current through any power transistors exceeds approximately
4 A, the part enters a mute state and the overcurrent error
output (ERR0) is asserted. This is a latched error and does not
clear automatically. Restore normal operation and clear the
error condition by either asserting and then negating RESET or
by asserting and then negating MUTE.
PROTECTION CIRCUITS AND ERROR REPORTING
O
B
SO
LE
The AD1994 features thermal protection. When the die
temperature exceeds approximately 135°C, the thermal warning
error output (ERR1) is asserted. If the die temperature exceeds
approximately 150°C, the thermal shutdown error output
(ERR2) is asserted. If this occurs, the part shuts down to
prevent damage to the part. When the die temperature drops
below approximately 120°C, the part returns to normal
operation automatically and negates both error outputs.
TE
Thermal Protection
Rev. 0 | Page 19 of 24
AD1994
APPLICATION CIRCUITS
DVDD
PVDD
+
0.1µF
+
47µF
0.1µF
1000µF
AVDD
PVDD
+
0.1µF
+
0.1µF
47µF
PVDD2
PVDD
TE
+
PVDD1
10µF
DVDD
AVDD
1000µF
L
AINL
OUTL+
C
R1
NFL+
10µF
+
R2
AINL
LE
R2
NFL–
6.8µF
+
MOD_FILT
10kΩ
PVDD
R1
OUTL–
L
AD1994
PVDD
REF_FILT
4.7µF
+
0.1µF
C
L
B
SO
OUTR+
PGA0
C
R1
NFR+
R2
PGA1
DCTRL2
DIGITAL
INPUTS
DCTRL1
R2
NFR–
DCTRL0
MUTE
R1
OUTR–
RESET
ERR2
THERMAL WARNING
ERR1
L
C
R1 = 4.2kΩ
R2 = 1.8kΩ
L = 18µH
C = 1µF
LOAD = 6Ω
ERR0
05775-048
PGND2
CLKO
PGND1
CLKI
DGND
OVERCURRENT
AGND
O
THERMAL SHUTDOWN
PVDD
Figure 48. Typical Stereo Circuit
Rev. 0 | Page 20 of 24
AD1994
OUTLINE DIMENSIONS
9.00
BSC SQ
0.30
0.25
0.18
0.60 MAX
0.60 MAX
64 1
48 49
PIN 1
INDICATOR
PIN 1
INDICATOR
8.75
BSC SQ
(BOTTOM VIEW)
12° MAX
SEATING
PLANE
17 16
32
7.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.50 BSC
33
0.20 REF
0.25 MIN
LE
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
122105-0
0.45
0.40
0.35
1.00
0.85
0.80
7.25
7.10 SQ
6.95
EXPOSED PAD
TE
TOP
VIEW
Figure 49. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimension shown in millimeters
B
SO
ORDERING GUIDE
Model
AD1994ACPZ 1
AD1994ACPZRL1
AD1994ACPZRL71
EVAL-AD1994EB
Package Description
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ), 13” Tape and Reel
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ), 7” Tape and Reel
Evaluation Board
Z = Pb-free part.
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1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
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Package Option
CP-64-3
CP-64-3
CP-64-3
AD1994
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NOTES
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AD1994
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AD1994
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©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05775-0-2/06(0)
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