ACSL-7210 Dual-Channel (Bidirectional) 25 MBd CMOS Buffered Input Digital Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The ACSL-7210 is a dual-channel bidirectional 25 MBd digital optocoupler utilizes CMOS IC technology and patented packaging technologies to achieve high isolation voltage 3750 VRMS in a < 2 mm low profile narrow-body SOIC-8 package. The device optimizes for bidirectional industrial communication networks such as Fieldbus (PROFIBUS) and Serial Peripheral Interface (SPI) applications. • Dual-Channel (Opposite direction orientation) The main building blocks of the ACSL-7210 for each channel are a CMOS LED driver IC that is controlled by a CMOS logic input signal, a high speed LED, and a CMOS detector IC. These building blocks allow fast propagation delay of 40 ns and short pulse width distortion of 10 ns maximum. • Guaranteed AC and DC performance over wide temperature: –40 °C to +105 °C The ACSL-7210 has common-mode noise immunity of typical 35 kV/μs at 1000 VCM, with UL recognized with isolation voltage of 3750 VRMS for 1 minute, and IEC/EN/ DIN EN 60747-5-5 working insulation voltage VIORM of 567 VPEAK with reinforced insulation. - IEC/EN/DIN EN 60747-5-5 for Reinforced Insulation – 567 VPEAK Applications Functional Diagram • Multiplexed Data Transmission VDD 1 1 8 VDD 2 VO A 2 7 VI A • High Speed: DC to 25 MBd • 3.3 V and 5 V CMOS Compatibility • CMOS input and output • 25 kV/μs minimum Common Mode Rejection (CMR) at VCM = 1000 V • Safety and Regulatory Approvals: (pending): - UL 1577 – 3750 Vrms for 1 minute • Digital Fieldbus DeviceNet, SDS Isolation: PROFIBUS, CC-Link, • General Instrument and Data Acquisition • Computer Peripheral Interface • Microprocessor System Interface TRUTH TABLE (POSITIVE LOGIC) VI B 3 GND 1 4 6 VOB Shield 5 GND 2 ACSL-7210 * A 0.1 µF bypass capacitor must be connected between pins VDD1 and GND1, and VDD2 and GND2 Input side VDD state Output side VDD state Power Supplied No Power VI LED VO Power Supplied HIGH OFF HIGH LOW ON LOW Power Supplied X OFF HIGH CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. The components featured in this datasheet are not to be used in military or aerospace applications or environments. Ordering Information ACSL-7210 is UL Recognized with 3750 VRMS for 1 minute per UL1577. Option Part number RoHS Compliant Package Surface Mount ACSL-7210 -00RE SO-8 X Tape & Reel IEC/EN/DIN EN 60747-5-5 Quantity 100 per tube -06RE X X -50RE X X -56RE X X 100 per tube 1500 per reel X 1500 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACSL-7210-50RE to order RoHS-compliant Surface Mount 8-pin package in Tape-and-Reel packaging. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Package Outline Drawings ACSL-7210 SO-8 Package 0.189 (4.80) 0.197 (5.00) 8 7 6 A NNNN • YYWW EEE AVAGO 0.228 (5.80) 0.244 (6.20) LEAD FREE 1 2 LAND PATTERN RECOMMENDATION 5 0.150 (3.80) 0.157 (4.00) 0.286 (7.27) DATE CODE 4 3 DEVICE PART NUMBER 0.085 (2.16) LOT ID 0.025 (0.64 ) 0.013 (0.33) 0.020 (0.51) 0.010 (0.25) 0.020 (0.50) 0.008 (0.19) 0.010 (0.25) x 45° 0.004 (0.10) 0.010 (0.25) 0.054 (1.37) 0.069 (1.75) 0° 8° 0.040 (1.016) 0.060 (1.524) DIMENSIONS: INCHES (MILLIMETERS) 2 0.016 (0.40) 0.050 (1.27) MIN MAX Solder Reflow Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACSL-7210 will be approved by the following organizations: UL Approval under UL 1577, component recognition program up to VISO = 3750 VRMS. CSA Approval under CSA Component Acceptance Notice #5. IEC/EN/DIN EN 60747-5-5 (Option 06RE only) Insulation and Safety Related Specifications Parameter Symbol ACSL-7210 Units Conditions Minimum External Air Gap (Clearance) L(101) 4.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (Creepage) L(102) 4.3 mm Measured from input terminals to output terminals, shortest distance path along body. 0.08 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. 175 V DIN IEC 112/VDE 0303 Part 1 Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1) IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 06RE) Characteristic Description Symbol Installation classification per DIN VDE 0110/39, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms ACSL-7210 Unit I – IV I – IV I – III Climatic Classification 40/105/21 Pollution Degree (DIN VDE 0110/39) 2 Maximum Working Insulation Voltage VIORM 567 Vpeak Input to Output Test Voltage, Method b* VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC VPR 1063 Vpeak Input to Output Test Voltage, Method a* VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC VPR 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 6000 Vpeak Safety-limiting values – maximum values allowed in the event of a failure. Case Temperature Input Current Output Power TS IS, INPUT PS, OUTPUT 175 75 600 °C mA mW Insulation Resistance at TS, VIO = 500 V RS 109 Ω * 3 Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/ DIN EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles. Absolute Maximum Ratings Parameter Symbol Min Max Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 105 °C Supply Voltage VDD1, VDD2 0 6.5 V Input Voltage VIA, VIB -0.5 VDD + 0.5 V Output Voltage VOA, VOB -0.5 VDD + 0.5 V Average Output Current IO 10 mA Input Power Dissipation [1] PI 72 mW Output Power Dissipation [1] PO 62 mW Lead Solder Temperature TLS 260 °C for 10 sec, 1.6 mm below seating plane Parameter Symbol Min Max Units Operating Temperature TA -40 105 °C Supply Voltage (3.3V) VDD1, VDD2 3.0 3.6 V Supply Voltage (5V) VDD1, VDD2 4.5 5.5 V Logic High Input Voltage VIH 0.7 × VDD VDD V Logic Low Input Voltage VIL 0 0.3 × VDD V Input Signal Rise and Fall Times tr, tf 1 ms Recommended Operating Conditions Electrical Specifications (DC) Over recommended temperature (TA = –40 °C to 105 °C) and supply voltage (4.5 V≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V), (3 V≤ VDD1 ≤ 3.6 V, 3 V ≤ VDD2 ≤ 3.6 V), (4.5 V ≤ VDD1 ≤ 5.5V, 3 V ≤ VDD2 ≤ 3.6 V) and (3 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤5.5 V). All typical specifications are at VDD1 = VDD2 = +3.3 V, TA = 25 °C, unless otherwise specified. Parameter Symbol Typ. Max. Units Test Conditions Logic Low Supply Current [2] IDD1L, IDD2L 9 15 mA VI = 0 V Figure 1 Logic High Supply Current [2] IDD1H, IDD2H 1.9 5 mA VI = VDD Figure 2 Input Current IIA, IIB -10 10 µA Logic High Output Voltage VOH VDD - 0.1 3.3 VDD - 1.0 3.1 Logic Low Output Voltage VOL 4 Min. V IO = –20 µA, VI = VIH V IO = –4 mA, VI = VIH 0 0.1 V IO = 20 µA, VI = VIL 0.14 1.0 V IO = 4 mA, VI = VIL Switching Specifications (AC) Over recommended temperature (TA = –40 °C to 105 °C) and supply voltage (4.5 V≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V), (3 V≤ VDD1 ≤ 3.6 V, 3 V ≤ VDD2 ≤ 3.6 V), (4.5 V ≤ VDD1 ≤ 5.5V, 3 V ≤ VDD2 ≤ 3.6 V) and (3 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤5.5 V). All typical specifications are at VDD1 = VDD2 = +3.3 V, TA = 25 °C, unless otherwise specified. Parameter Symbol Propagation Delay Time to Logic Low Output [3] Typ. Max. Units Test Conditions tPHL 27 40 ns CL= 15 pF, CMOS Signal Levels Figures 3,4 Propagation Delay Time to Logic High Output [3] tPLH 25 40 ns CL= 15 pF, CMOS Signal Levels Figures 3,4 Pulse Width tPW ns CL= 15 pF, CMOS Signal Levels Pulse Width Distortion [4] PWD 8 ns 3 V ≤ VDD ≤ 3.6 V CL= 15 pF, CMOS Signal Levels Figures 5, 6 10 ns CL= 15 pF, CMOS Signal Levels Propagation Delay Skew [5] tPSK 20 ns CL= 15 pF, CMOS Signal Levels Output Rise Time (10% – 90%) tR 5.1 ns Output Fall Time (90% - 10%) tF 3.8 ns CL= 15 pF, CMOS Signal Levels Figure 7 Common Mode Transient Immunity at Logic High Output [6] |CMH| 25 35 kV/µs VCM = 1000 V, TA = 25 °C VI = VDD1, VO > 0.8 × VDD2 Common Mode Transient Immunity at Logic Low Output [6] |CML| 25 35 kV/µs VCM = 1000 V, TA = 25 °C VI = 0 V, VO < 0.8 V Parameter Symbol Min. Typ. Units Test Conditions Input-Output Insulation [7,8,9] VISO 3750 |tPHL - tPLH| Min. 40 1.8 Package Characteristics All typical at TA = 25 °C Input-Output Resistance [7] Input-Output Capacitance Input Capacitance [10] Max. VRMS RH < 50% for 1 min. TA = 25 °C RI-O 1012 Ω VI-O = 500 V CI-O 1 pF f=1 MHz, TA = 25 °C CI 6 pF Notes: 1. Per channel. 2. LED is ON when VI is low and OFF when VI is high. 3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 4. PWD is defined as |tPHL - tPLH|. 5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 7. Device is considered a two-terminal device: pins 1, 2, 3, and 4 are shorted together and pins 5, 6, 7, and 8 are shorted together. 8. In accordance with UL1577, ACSL-7210 is proof-tested by applying an insulation test voltage ≥ 4500 VRMS for 1 second (leakage detection current limit, II-O ≤ 5 μA). 9. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or Avago Technologies Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.” 10. CI is the capacitance measured at pin 3 or pin 7 (VI). 5 13 11 9 7 5 5.0 V 3.3 V - 40 - 20 0 20 40 TA (°C) 60 80 100 Figure 1.Typical Logic Low Supply Current vs. temperature IDD1H, IDD2H - LOGIC HIGH SUPPLY CURRENT (mA) IDD1L, IDD2L - LOGIC LOW SUPPLY CURRENT (mA) 15 2 1 32 30 Tphl, Tplh (ns) Tphl, Tplh (ns) 3 32 28 26 24 20 - 40 Tplh Tphl - 20 0 20 40 TA (°C) 60 80 20 100 6 5 5 PWD (ns) 6 4 3 1 1 TA (°C) 60 80 100 80 Tplh Tphl 100 Figure 5. Typical pulse width distortion vs. temperature at 3.3 V supply voltage 15 25 35 CL (pF) 45 55 3 2 40 60 4 2 20 40 TA (°C) Figure 4. Typical propagation delay vs. load capacitance at 3.3 V supply voltage 7 0 20 24 7 - 20 0 26 8 - 40 - 20 28 8 0 - 40 22 Figure 3. Typical propagation delay vs. temperature at 3.3 V supply voltage PWD (ns) 4 34 22 5.0V 3.3V Figure 2. Typical Logic High Supply Current vs. temperature 30 6 5 0 15 25 35 CL (pF) 45 55 Figure 6. Typical pulse width distortion vs. load capacitance at 3.3 V supply voltage 8 7 Tr, Tf (ns) 6 5 4 3 Rise Time Fall Time 2 1 -40 -20 0 20 40 T A ( O C) 60 80 100 Figure 7. Typical rise and fall time vs. temperature at 3.3 V supply voltage Application Information Bypassing and PC Board Layout The ACSL-7210 optocoupler is extremely easy to use. No external interface circuitry is required because ACSL-7210 uses high-speed CMOS IC technology, allowing CMOS logic to be directly connected to the inputs and outputs. The only external components required for proper operation are two bypass capacitors. Capacitor value should be between 0.01 µF and 0.1 µF. For each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. Figure 8 shows the typical application diagram for 25 MBd bidirectional ACSL-7210 and 10 MBd ultra low-power ACPLM61L, providing isolation in PROFIBUS (RS485) communication. ACSL-7210 isolates the transmitting and receiving data channels while ACPL-M61L isolates the transmit enable signal. VDD1 C4 100 nF U1 Isolation 1 VDD1 2 VOA 3 VIB 4 GND1 Rx Tx VDD2 8 VDD2 7 VIA 6 VOB 5 GND2 Rx Tx ACSL-7210 VDD1 Isolation R1 Tx Enable U3 U2 1 AN 510 R2 3 360 VDD2 VDD2 CA 1 VDD 6 5 VO 4 GND Tx Enable RO 2 RE_ 3 DE 4 DI ACPL-M61L Figure 8. Isolated PROFIBUS (RS485) communication with ACSL-7210 and ACPL-M61L 7 VCC 8 7 B A 6 5 GND RS485 Fieldbus Network (Twisted Cable) For the SPI interface, the ACSL-7210 is used for serial data in/out isolation (2 channels bidirectional). The third channel - clock signal isolation is provided by ACPL-077L, 25 MBd CMOS digital optocoupler. Figure 9 shows the SPI isolated communication between master and slave devices using ACSL-7210 and ACPL-077L. VDD2 VDD1 C6 100 nF U4 1 2 To master device 3 4 VDD1 VDD2 V1 NC NC VO GND1 GND2 8 VDD2 VDD1 C5 100 nF C4 100 nF 7 6 To slave device U1 1 2 To master device 5 3 4 ACPL-077L VDD1 VOA VIA VIB VOB GND1 ACSL-7210 Figure 9. Isolated SPI between master and slave devices using ACSL-7210 and ACPL-077L For product information and a complete list of distributors, please go to our web site: VDD2 www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2015 Avago Technologies. All rights reserved. AV02-4235EN - February 11, 2015 GND2 8 C1 100 nF 7 6 To slave device 5