Freescale MC68HC05P9ACP Hcmos microcontroller unit Datasheet

Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MC68HC05P9A/D
HC 5
MC68HC05P9A
HCMOS Microcontroller Unit
TECHNICAL DATA
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Freescale Semiconductor, Inc.
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List of Sections
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . 5
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Central Processor Unit (CPU) . . . . . . . . . . . . . . . 27
Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . 49
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . 59
Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . 65
Computer Operating Properly
Watchdog (COP) . . . . . . . . . . . . . . . . . . . . . . 79
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Serial Input/Output Port (SIOP). . . . . . . . . . . . . 103
Analog-to-Digital Converter (ADC). . . . . . . . . 117
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Literature Updates . . . . . . . . . . . . . . . . . . . . . . . 153
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List of Sections
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List of Sections
4
List of Sections
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Freescale Semiconductor, Inc...
Table of Contents
Introduction
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . .12
Mask Selectable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pin Descriptions
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Memory
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ROM Security Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CPU
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Arithmetic/Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
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Table of Contents
Resets
and Interrupts
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Low-Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Low-Power Modes
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
COP
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Timer
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
6
Table of Contents
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Table of Contents
SIOP
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
ADC
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Timing and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .121
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Specifications
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
5.0 V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .130
3.3 V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .132
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Typical Supply Current vs. Internal Clock Frequency . . . . . . . . . . . .135
Maximum Supply Current vs. Internal Clock Frequency . . . . . . . . . .136
5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
3.3 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
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Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Literature Updates
Literature Distribution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Mfax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Motorola SPS World Marketing World Wide Web Server . . . . . . . . .154
CSIC Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . .154
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Index
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Table of Contents
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Introduction
Contents
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . .12
Mask Selectable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1-mc68hc05p9a
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Introduction
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Introduction
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Features
•
Four Peripheral Modules
– 16-Bit Input Capture/Output Compare Timer
– Synchronous Serial I/O Port (SIOP)
– 4-Channel, 8-Bit Analog-to-Digital Converter (ADC)
– Computer Operating Properly (COP) Watchdog
•
20 Bidirectional I/O Port Pins and One Input-Only Port Pin
– High Current Source Sink on PC0 and PC1
– Mask Programmable Pullups/Interrupts on PA0–PA7, a
Keyboard Scan Feature
•
On-Chip Oscillator with Connections for:
– Crystal
– Ceramic Resonator
– External Clock
– Resistor Capacitor (RC) Oscillator
•
2112 Bytes of ROM
– 48 Bytes of Page Zero ROM
– Eight Locations for User Vectors
– ROM Security
•
128 Bytes of User RAM
•
Selfcheck ROM
•
Memory-Mapped Input/Output (I/O) Registers
•
Fully Static Operation with No Minimum Clock Speed
•
Power-Saving Stop and Wait Modes
2-mc68hc05p9a
10
Introduction
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Introduction
Structure
Structure
PA7
RESET
ACCUMULATOR
M68HC05
MCU
SDI
SDO
INDEX REGISTER
RESET
VRH
STACK POINTER
0 0 0 0 0 0 0 0 1 1
AN0
PROGRAM COUNTER
0 0 0
AN1
AN2
CONDITION CODE REGISTER
1 1 1 H I N C Z
AN3
PORT A
PA5
DIVIDE
BY 2
INTERNAL CLOCK
COP
WATCHDOG
VDD
VSS
PB7/SCK
PB6/SDI
PB5/SDO
PC7/VRH
PC6/AN0
PC5/AN1
PC4/AN2
PC3/AN3
PC2
PC1
PORT D
INTERNAL
OSCILLATOR
PA2
PC0
TO ADC
AND
SIOP
DATA DIRECTION
REGISTER D
OSC2
PA3
PA0
CPU CLOCK
OSC1
PA4
PA1
PORT B
SIOP
SCK
IRQ
PA6
PORT C
ARITHMETIC/LOGIC
UNIT
CPU CONTROL
DATA DIRECTION REGISTER C
RAM — 128 BYTES x 8
ADC
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SELFCHECK ROM — 240 BYTES x 8
DATA DIRECTION
REGISTER B
DATA DIRECTION REGISTER A
ROM — 2112 BYTES x 8
PD5
PD7/TCAP
TCAP
POWER
DIVIDE
BY 4
CAPTURE/COMPARE
TIMER
TCMP
Figure 1. MC68HC05P9A Block Diagram
3-mc68hc05p9a
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Introduction
Package Types and Order Numbers
Table 1. Order Numbers
Package
Type
Case
Outline
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Plastic DIP(1)
Pin
Count
Operating
Temperature
28
0 to +70 °C
–40 to +85 °C
–40 to +105 °C
–40 to +125 °C
MC68HC05P9AP
MC68HC05P9ACP
MC68HC05P9AVP
MC68HC05P9AMP
28
0 to +70 °C
–40 to +85 °C
–40 to +105 °C
–40 to +125 °C
MC68HC05P9ADW
MC68HC05P9ACDW
MC68HC05P9AVDW
MC68HC05P9AMDW
710
SOIC(2)
751F
Order Number
1. DIP = dual in-line package
2. SOIC = small outline integrated circuit
Mask Selectable Options
The options in Table 2 are user selectable mask options.
Table 2. User Selectable Mask Options
Feature
Option
COP Watchdog
Enabled
or
Disabled
External Interrupt Pin Triggering
Negative-Edge Triggering Only
or
Negative-Edge and Low-Level Triggering
SIOP Data Format
MSB First
or
LSB First
Enabled Pin-by-Pin
Keyscan Pullups/Interrupts on Port A or
Disabled Pin-by-Pin
STOP Instruction
Enabled
or
Disabled (Convert to HALT)
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Pin Descriptions
Contents
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Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . .16
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PB7/SCK–PB5/SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PC7/VRH–PC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PD7/TCAP and PD5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
5-mc68hc05p9a
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Pin Descriptions
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Pin Descriptions
Pin Assignments
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RESET
VDD
IRQ
OSC1
PA7
OSC2
PA6
PD7/TCAP
PA5
TCMP
PA4
PD5
PA3
PC0
PA2
PC1
PA1
PC2
PA0
PC3/AN3
PB5/SDO
PC4/AN2
PB6/SDI
PC5/AN1
PB7/SCK
PC6/AN0
VSS
PC7/VRH
Figure 2. Pin Assignments
6-mc68hc05p9a
14
Pin Descriptions
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Pin Descriptions
Pin Functions
Pin Functions
VDD and VSS are the power supply and ground pins. The MCU operates
from a single 5-V power supply.
OSC1 and OSC2
MCU
C1
0.1 µF
VSS
Very fast signal transitions occur
on the MCU pins, placing high
short-duration current demands
on the power supply. To prevent
noise problems, take special
care to provide good power
supply bypassing at the MCU as
Figure 3 shows. Place the
bypass capacitors as close as
possible to the MCU. C2 is an
optional bulk current bypass
capacitor for use in applications
that require the port pins to
source high current levels.
VDD
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VDD and VSS
C2
+
VDD
Figure 3. Bypassing
Recommendation
The OSC1 and OSC2 pins are the connections for the on-chip oscillator.
The oscillator can be driven by any of the following:
•
Crystal
•
Ceramic resonator
•
RC Oscillator
•
External clock signal
The frequency of the on-chip oscillator is fOSC. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fOP.
7-mc68hc05p9a
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Pin Descriptions
Ceramic
Resonator
Connections
10 MΩ
OSC2
OSC1
MCU
XTAL
27 pF
27 pF
Figure 4. Crystal Connections
Use an AT-cut crystal. Do not use a strip or tuning fork crystal. The MCU
may overdrive or have the incorrect characteristic impedance for a strip
or tuning fork crystal.
To reduce cost, use a ceramic
resonator in place of the crystal.
Figure 5 shows a ceramic
resonator circuit. For the values
of any external components,
follow the recommendations of
the resonator manufacturer. The
load capacitance values used in
the oscillator circuit design
should include all stray layout
capacitances. To minimize
output distortion, mount the
resonator and capacitors as
close as possible to the pins.
MCU
CERAMIC
RESONATOR
OSC2
NOTE:
The circuit in Figure 4 shows a
typical crystal oscillator circuit
for an AT-cut, parallel resonant
crystal. Follow the crystal
supplier’s recommendations, as
the crystal parameters
determine the external
component values required to
provide reliable startup and
maximum stability. The load
capacitance values used in the
oscillator circuit design should
include all stray layout
capacitances. To minimize
output distortion, mount the
crystal and capacitors as close
as possible to the pins.
OSC1
Freescale Semiconductor, Inc...
Crystal
Connections
Figure 5. Ceramic Resonator
Connections
8-mc68hc05p9a
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Freescale Semiconductor, Inc.
Pin Descriptions
Pin Functions
External Clock
Connections
The lowest cost oscillator is the
RC oscillator configuration
where a resistor is connected
between the two oscillator pins
as shown in Figure 6. The
internal startup resistor of
approximately 2 MΩ is not
recommended between OSC1
and OSC2 for the RC-type
oscillator.
MCU
OSC1
OSC2
R
Figure 6. RC Oscillator
Connections
An external clock from another
CMOS-compatible device can
drive the OSC1 input, with the
OSC2 pin unconnected, as
Figure 7 shows.
MCU
OSC2
Freescale Semiconductor, Inc...
RC Oscillator
Because the frequency stability of ceramic resonators is not as high as
that of crystal oscillators, using a ceramic resonator may degrade the
performance of the ADC.
OSC1
NOTE:
UNCONNECTED
RESET
IRQ
A logic 0 on the RESET pin
forces the MCU to a known
startup state. The RESET pin
input circuit contains an internal
Schmitt trigger to improve noise
immunity.
EXTERNAL
CMOS CLOCK
Figure 7. External Clock
Connections
The IRQ pin has the following functions:
•
Applying asynchronous external interrupt signals
•
Applying VTST, the mode detection voltage
9-mc68hc05p9a
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Pin Descriptions
PA7–PA0
PA7–PA0 are general-purpose bidirectional I/O port pins. Use data
direction register A to configure port A pins as inputs or outputs.
PA7–PA0 also have mask selectable interrupt/pullup options.
PB7/SCK–
PB5/SDO
Port B is a 3-pin bidirectional I/O port that shares its pins with the SIOP.
Use data direction register B to configure port B pins as inputs or
outputs.
PC7/VRH–PC0
Port C is an 8-pin bidirectional I/O port that shares five of its pins with the
ADC. Use data direction register C to configure port C pins as inputs or
outputs.
PD7/TCAP and PD5
Port D is a 2-pin I/O port that shares one of its pins with the
capture/compare timer. Use data direction register D to configure port D
pins as inputs or outputs.
TCMP
The TCMP pin is the output compare pin for the capture/compare timer.
10-mc68hc05p9a
18
Pin Descriptions
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Freescale Semiconductor, Inc.
Memory
Freescale Semiconductor, Inc...
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ROM Security Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Features
•
2104 Bytes of ROM
– 48 Bytes of Page Zero ROM
– Eight Locations for User Vectors
•
128 Bytes of User RAM
•
240 Selfcheck ROM
5-mc68hc05p9a
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Memory
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19
Freescale Semiconductor, Inc.
Memory
Freescale Semiconductor, Inc...
Memory Map
$0000
↓
$001F
I/O Registers (32 Bytes)
$0020
↓
$004F
Page Zero User ROM (48 Bytes)
$0050
↓
$007F
Unimplemented (48 Bytes)
Port A Data Register (PORTA)
Port B Data Register (PORTB)
Port C Data Register (PORTC)
Port D Data Register (PORTD)
Data Direction Register A (DDRA)
Data Direction Register B (DDRB)
Data Direction Register C (DDRC)
Data Direction Register D (DDRD)
Timer Control Register (TCR)
Timer Status Register (TSR)
Input Capture Register High (ICRH)
Input Capture Register Low (ICRL)
Output Compare Register High (OCRH)
Output Compare Register Low (OCRL)
Timer Register High (TRH)
Timer Register Low (TRL)
Alternate Timer Register High (ATRH)
Alternate Timer Register Low (ATRL)
Unimplemented
ADC Data Register (ADDR)
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
ADC Status/Control Register (ADSCR)
$001E
Reserved
$001F
Timer Interrupt Vector High
$1FF8
Unimplemented
$0080
↓
$00FF
RAM (128 Bytes)
$0100
↓
$08FF
User ROM (2048 Bytes)
SIOP Control Register (SCR)
SIOP Status Register (SSR)
SIOP Data Register (SDR)
Unimplemented
$0900
↓
$1EFF
Unimplemented (5632 Bytes)
$1F00
↓
$1FEF
Self Check ROM (240 Bytes)
$1FF0
COP Control Register
$1FF1
↓
$1FF7
Reserved
$1FF8
↓
$1FFF
User Vector (8 Bytes)
Timer Interrupt Vector Low
$1FF9
External Interrupt Vector High
$1FFA
External Interrupt Vector Low
$1FFB
Software Interrupt Vector High
$1FFC
Software Interrupt Vector Low
$1FFD
Reset Vector High
$1FFE
Reset Vector Low
$1FFF
Figure 8. Memory Map
6-mc68hc05p9a
20
Memory
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Freescale Semiconductor, Inc.
Memory
Input/Output Register Summary
Input/Output Register Summary
Addr.
$0000
Freescale Semiconductor, Inc...
$0001
$0002
$0003
Name
R/W Bit 7
Read:
PA7
Port A Data Register (PORTA)
Write:
Reset:
Port B Data Register (PORTB)
Port C Data Register (PORTC)
Port D Data Register (PORTD)
$0004
Data Direction Register A (DDRA)
$0005
Data Direction Register B (DDRB)
$0006
Data Direction Register C (DDRC)
$0007
Data Direction Register D (DDRD)
$0008
Unimplemented
$0009
Unimplemented
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PB7
6
5
4
3
2
1
Bit 0
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
0
0
PC2
PC1
PC0
0
0
0
Unaffected by reset
PB6
0
PB5
0
Unaffected by reset
PC7
PC6
PC5
PC4
PC3
Unaffected by reset
PD7
0
1
PD5
0
Unaffected by reset
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
0
0
0
0
0
0
0
0
Reset:
Read:
DDRB7 DDRB6 DDRB5
Write:
0
0
0
Reset:
0
0
0
0
0
0
0
0
0
0
Read:
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
0
0
0
0
0
0
0
0
Reset:
Read:
Write:
Reset:
0
0
0
0
DDRD5
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
U = Unaffected
Figure 9. I/O Register Summary
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Freescale Semiconductor, Inc.
Memory
Addr.
$000A
$000B
Freescale Semiconductor, Inc...
$000C
Name
R/W Bit 7
0
Read:
SIOP Control Register (SCR)
Write:
0
Reset:
Read: SPIF
Write:
0
Reset:
Read:
Bit 7
SIOP Data Register (SDR)
Write:
Reset:
SIOP Status Register (SSR)
$000D
Unimplemented
$000E
Unimplemented
$000F
Unimplemented
$0010
Unimplemented
$0011
Unimplemented
$0012
Timer Control Register (TCR)
$0013
$0014
$0015
$0016
Timer Status Register (TSR)
Input Capture Register High (ICRH)
Input Capture Register Low (ICRL)
Output Compare Register High (OCRH)
Read:
Write:
Reset:
Read:
Write:
Reset:
6
SPE
5
4
0
MSTR
1
Bit 0
0
0
0
0
0
0
0
0
0
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
Bit 0
IEDG
OLVL
Unaffected by reset
0
0
0
0
0
0
0
U
0
TOF
0
0
0
0
0
0
0
0
0
0
12
11
10
9
Bit 8
2
1
Bit 0
10
9
Bit 8
OCIE
TOIE
0
0
ICF
OCF
Unaffected by reset
Read: Bit 15
Write:
Reset:
14
Read:
Write:
Reset:
6
Read:
Bit 15
Write:
Reset:
2
0
0
ICIE
Bit 7
3
13
Unaffected by reset
5
4
3
Unaffected by reset
14
13
12
11
Unaffected by reset
= Unimplemented
R = Reserved
U = Unaffected
Figure 9. I/O Register Summary (Continued)
8-mc68hc05p9a
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Freescale Semiconductor, Inc.
Memory
Input/Output Register Summary
Addr.
$0017
Name
R/W Bit 7
Read:
Bit 7
Output Compare Register Low (OCRL) Write:
Reset:
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
Read: Bit 15
Write:
Reset:
14
10
9
Bit 8
Read:
Write:
Reset:
6
1
Bit 0
9
Bit 8
1
Bit 0
2
1
Bit 0
CH2
CH1
CH0
Timer Register High (TRH)
$0018
Timer Register Low (TRL)
Freescale Semiconductor, Inc...
$0019
$001A
$001B
Alternate Timer Register High (ATRH)
Alternate Timer Register Low (ATRL)
Unimplemented
$001C
ADC Data Register (ADDR)
$001D
$001E
ADC Status/Control Register (ADSCR)
$001F
Reserved
$1FF0
COP Register (COPR)
Bit 7
Unaffected by reset
13
5
4
3
2
Reset initializes TRL to $FC
14
Read:
Write:
Reset:
6
Bit 7
13
12
11
10
Reset initializes ATRH to $FF
5
4
3
2
Reset initializes ATRL to $FC
Read:
Write:
Reset:
Unaffected by reset
Read:
Write:
Reset:
Bit 7
Read:
Write:
Reset:
CCF
Read:
Write:
Reset:
11
Reset initializes TRH to $FF
Read: Bit 15
Write:
Reset:
Read:
Write:
Reset:
12
6
5
4
3
Unaffected by reset
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
COPC
ADRC
ADON
0
0
R
R
Unaffected by reset
= Unimplemented
R = Reserved
U = Unaffected
Figure 9. I/O Register Summary (Continued)
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Memory
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Freescale Semiconductor, Inc.
Memory
RAM
Freescale Semiconductor, Inc...
The 128 addresses from $0080–$00FF are RAM locations. The CPU
uses the top 64 RAM addresses, $00C0–$00FF, as the stack. Before
processing an interrupt, the CPU uses five bytes of the stack to save the
contents of the CPU registers. During a subroutine call, the CPU uses
two bytes of the stack to store the return address. The stack pointer
decrements when the CPU stores a byte on the stack and increments
when the CPU retrieves a byte from the stack.
NOTE:
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
ROM
The following addresses are mask programmable ROM locations:
•
$0020–$004F
•
$0100–$08FF
•
$1FF8–$1FFF (reserved for user-defined interrupt and reset
vectors)
ROM Security Feature
A security1 feature has been incorporated into the MC68HC05P9A to
help prevent externally reading of code in the ROM. This feature aids in
keeping customer developed software proprietary.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
10-mc68hc05p9a
24
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Memory
Self-Check Mode
Self-Check Mode
The self-check program resides at mask ROM locations $1F00 to
$1FEF. This program is designed to check the part’s functionality with a
minimum of support hardware. The COP subsystem is disabled in the
self-check mode so that routines that feed the COP do not exist in the
self-check program.
Freescale Semiconductor, Inc...
The self-check mode is entered on the rising edge of RESET if the IRQ
pin is driven to double the supply voltage and the TCAP/PD7 pin is at
logic 1. RESET must be held low for 4064 cycles after POR or for a time,
tRL, for any other reset. After reset, the I/O, RAM, ROM, timer, and SIOP
are tested. Self-check results (using LEDs as monitors) are shown in
Table 3. It is not recommended that the user code use any of the
self-check code. The self-check code is subject to change at any time to
improve testability or manufacturability.
Table 3. Self-Check Results
PC2
PC1
PC0
0
0
1
Bad I/O
0
1
0
Bad RAM
0
1
1
Bad Timer
1
0
0
Bad ROM
1
0
1
Bad Serial
Flashing
All Others
Remarks
Good Device
Bad Device
0 indicates LED is on; 1 indicates LED is off.
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Memory
VDD
VTST
10 KΩ
4.7 kΩ
VDD
RESET
1 µF
IRQ
PA7
PA6
PA5
1
28
2
27
3
26
4
25
5
24
PA4
Freescale Semiconductor, Inc...
6
23
PA3
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
PA2
PA1
PA0
SDO/PB5
SDI/PB6
SCK/PB7
VSS
VDD
10 KΩ
OSC1
4 MHz
OSC2
TCAP/PD7
TCMP
10 MΩ
PD5
20 pF
20 pF
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
470 Ω
VDD = 5.0 V
VDD
10 KΩ
VTST = 10.0 V
Figure 10. Self-Check Circuit
12-mc68hc05p9a
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Central Processor Unit
CPU
Contents
Freescale Semiconductor, Inc...
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Arithmetic/Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
CPU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Indexed,
8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .37
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . .38
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5-hc05cpu
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CPU
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Freescale Semiconductor, Inc.
CPU
Freescale Semiconductor, Inc...
Features
•
2.1-MHz Bus Frequency
•
8-Bit Accumulator
•
8-Bit Index Register
•
13-Bit Program Counter
•
6-Bit Stack Pointer
•
Condition Code Register with Five Status Flags
•
62 Instructions
•
Eight Addressing Modes
•
Power-Saving Stop and Wait Modes
Introduction
The central processor unit (CPU) consists of a CPU control unit, an
arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit
fetches and decodes instructions. The ALU executes the instructions.
The CPU registers contain data, addresses, and status bits that reflect
the results of CPU operations.
6-hc05cpu
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CPU
Introduction
ARITHMETIC/LOGIC UNIT
CPU CONTROL UNIT
7
6
5
4
3
2
1
0
ACCUMULATOR (A)
7
6
5
4
3
2
1
0
Freescale Semiconductor, Inc...
INDEX REGISTER (X)
15 14 13 12 11 10
9
8
7
6
0
0
0
1
1
15 14 13 12 11 10
9
8
7
6
0
0
0
0
0
0
0
5
4
3
2
1
0
STACK POINTER (SP)
5
4
3
2
1
0
0
PROGRAM COUNTER (PC)
7
6
5
4
3
2
1
0
1
1
1
H
I
N
Z
C
CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 11. CPU Programming Model
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Freescale Semiconductor, Inc.
CPU
CPU Control Unit
The CPU control unit fetches and decodes instructions during program
operation. The control unit selects the memory locations to read and
write and coordinates the timing of all CPU operations.
Freescale Semiconductor, Inc...
Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic, logic, and
manipulation operations decoded from the instruction set by the CPU
control unit. The ALU produces the results called for by the program and
sets or clears status and control bits in the condition code register
(CCR).
CPU Registers
The M68HC05 CPU contains five registers that control and monitor MCU
operation:
•
Accumulator
•
Index register
•
Stack pointer
•
Program counter
•
Condition code register
CPU registers are not memory mapped.
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CPU
CPU Registers
Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic and logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
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Reset:
Unaffected by reset
Figure 12. Accumulator (A)
Index Register
The index register can be used for data storage or as a counter. In the
indexed addressing modes, the CPU uses the byte in the index register
to determine the effective address of the operand.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 13. Index Register (X)
Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
stack location to be used. During a reset or after the reset stack pointer
instruction (RSP), the stack pointer is preset to $00FF. The address in
the stack pointer decrements after a byte is stacked and increments
before a byte is unstacked.
Read:
Bit
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
5
4
3
2
1
Bit
0
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
Figure 14. Stack Pointer (SP)
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The 10 most significant bits of the stack pointer are permanently fixed at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations;
an interrupt uses five locations.
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Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched. The three most significant bits
of the program counter are ignored internally and appear as 000.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit
15
14
13
0
0
0
12
11
10
9
8
7
6
5
4
3
2
Bit
0
1
Read:
Write:
Reset:
Loaded with vector from $1FFE and $1FFF
Figure 15. Program Counter (PC)
Condition Code
Register
The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed.
Read:
Bit 7
6
5
1
1
1
4
3
2
1
Bit 0
H
I
N
Z
C
U
1
U
U
U
Write:
Reset:
1
1
1
= Unimplemented
U = Unaffected
Figure 16. Condition Code Register (CCR)
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CPU
CPU Registers
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The
half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations.
I — Interrupt Mask
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Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic zero, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is set, the interrupt request is latched. Normally, the CPU processes
the latched interrupt as soon as the interrupt mask is cleared again.
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After any
reset, the interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result.
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
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Instruction Set
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The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
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CPU
Instruction Set
Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
Indexed,
No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
Indexed,
8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
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Indexed,
16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
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Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
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Instruction Set
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Instruction Types
Register/
Memory
Instructions
The MCU instructions fall into the following five categories:
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 4. Register/Memory Instructions
Instruction
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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Read-ModifyWrite Instructions
NOTE:
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
Do not use read-modify-write operations on write-only registers.
Table 5. Read-Modify-Write Instructions
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Instruction
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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Instruction Set
Jump/Branch
Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
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The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Table 6. Jump and Branch Instructions
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Instruction
Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
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CPU
Instruction Set
Bit Manipulation
Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 7. Bit Manipulation Instructions
Instruction
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Bit Clear
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Bit Set
Control
Instructions
Mnemonic
BSET
These instructions act on CPU registers and control CPU operation
during program execution.
Table 8. Control Instructions
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
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Instruction Set
Summary
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
↕ —
A ← (A) + (M)
Add without Carry
↕ —
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left (Same as LSL)
C
C
b7
BCLR n opr
Clear Bit n
BCS rel
BEQ rel
BHCC rel
BHCS rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
— — ↕
↕
↕
↕
↕
↕ —
↕
↕
b0
Arithmetic Shift Right
Branch if Carry Bit Clear
↕
— — ↕
0
b7
↕
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
— — — — —
Mn ← 0
— — — — —
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
REL
REL
REL
A9
B9
C9
D9
E9
F9
AB
BB
CB
DB
EB
FB
A4
B4
C4
D4
E4
F4
38
48
58
68
78
37
47
57
67
77
24
11
13
15
17
19
1B
1D
1F
25
27
28
29
ii
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
dd
ff
dd
ff
rr
dd
dd
dd
dd
dd
dd
dd
dd
rr
rr
rr
rr
Cycles
Description
Operand
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
BCC rel
Operation
Effect on
CCR
Opcode
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 9. Instruction Set Summary
2
3
4
5
4
3
2
3
4
5
4
3
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
3
5
5
5
5
5
5
5
5
3
3
3
3
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Instruction Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Bit Test Accumulator with Memory Byte
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
PC ← (PC) + 2 + rel ? C ∨ Z = 0
PC ← (PC) + 2 + rel ? C = 0
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? C ∨ Z = 1
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— — ↕
↕ —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PC ← (PC) + 2 + rel ? Mn = 0
— — — — ↕
PC ← (PC) + 2 + rel ? 1 = 0
— — — — —
PC ← (PC) + 2 + rel ? Mn = 1
— — — — ↕
Mn ← 1
— — — — —
REL
REL
REL
REL
IMM
DIR
EXT
IX2
IX1
IX
REL
REL
REL
REL
REL
REL
REL
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
22
24
2F
2E
A5
B5
C5
D5
E5
F5
25
23
2C
2B
2D
26
2A
20
01
03
05
07
09
0B
0D
0F
21
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
rr
rr
rr
rr
ii
dd
hh ll
ee ff
ff
rr
rr
rr
rr
rr
rr
rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
Cycles
H I N Z C
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Description
Operand
BHI rel
BHS rel
BIH rel
BIL rel
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Operation
Effect on
CCR
Opcode
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 9. Instruction Set Summary (Continued)
3
3
3
3
2
3
4
5
4
3
3
3
3
3
3
3
3
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
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Table 9. Instruction Set Summary (Continued)
Operand
Cycles
Description
Opcode
Operation
Effect on
CCR
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
— — — — —
REL
AD
rr
6
— — — — 0
— 0 — — —
INH
INH
DIR
INH
INH
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
98
9A
3F
4F
5F
6F
7F
A1
B1
C1
D1
E1
F1
33
43
53
63
73
A3
B3
C3
D3
E3
F3
3A
4A
5A
6A
7A
A8
B8
C8
D8
E8
F8
3C
4C
5C
6C
7C
H I N Z C
BSR rel
Branch to Subroutine
CLC
CLI
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
Clear Carry Bit
Clear Interrupt Mask
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
C←0
I←0
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
EXCLUSIVE OR Accumulator with Memory Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
— — 0 1 —
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
↕
↕
↕
↕
1
↕
↕ —
↕ —
↕ —
dd
ff
ii
dd
hh ll
ee ff
ff
dd
ff
ii
dd
hh ll
ee ff
ff
dd
ff
ii
dd
hh ll
ee ff
ff
dd
ff
2
2
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
22-hc05cpu
44
CPU
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MOTOROLA
Freescale Semiconductor, Inc.
CPU
Instruction Set
H I N Z C
Unconditional Jump
PC ← Jump Address
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
A ← (M)
Load Accumulator with Memory Byte
— — ↕
C
0
b7
C
b7
Unsigned Multiply
Negate Byte (Two’s Complement)
— — ↕
↕ —
↕ —
↕
↕
b0
0
Logical Shift Right
— — — — —
— — ↕
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — — — —
— — 0 ↕
↕
b0
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
No Operation
0 — — — 0
— — ↕
↕
↕
— — — — —
Logical OR Accumulator with Memory
A ← (A) ∨ (M)
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
INH
DIR
INH
INH
IX1
IX
INH
IMM
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
BD
CD
DD
ED
FD
A6
B6
C6
D6
E6
F6
AE
BE
CE
DE
EE
FE
38
48
58
68
78
34
44
54
64
74
42
30
40
50
60
70
9D
AA
BA
CA
DA
EA
FA
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
dd
ff
dd
ff
dd
ff
ii
dd
hh ll
ee ff
ff
Cycles
Description
Operand
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Operation
Effect on
CCR
Opcode
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 9. Instruction Set Summary (Continued)
2
3
4
3
2
5
6
7
6
5
2
3
4
5
4
3
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
11
5
3
3
6
5
2
2
3
4
5
4
3
23-hc05cpu
MOTOROLA
CPU
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45
Freescale Semiconductor, Inc.
CPU
Table 9. Instruction Set Summary (Continued)
39
49
59
69
79
36
46
56
66
76
9C
dd
Rotate Byte Left through Carry Bit
C
↕
INH
80
9
— — — — —
INH
81
6
IMM
DIR
EXT
IX2
IX1
IX
INH
INH
DIR
EXT
IX2
IX1
IX
INH
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
99
9B
B7
C7
D7
E7
F7
8E
BF
CF
DF
EF
FF
A0
B0
C0
D0
E0
F0
— — ↕
b7
C
Rotate Byte Right through Carry Bit
b7
Return from Interrupt
RTS
Return from Subroutine
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
C←1
I←1
Set Carry Bit
Set Interrupt Mask
Store Accumulator in Memory
M ← (A)
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
Subtract Memory Byte from Accumulator
↕
— — ↕
↕
↕
b0
SP ← $00FF
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
Reset Stack Pointer
↕
b0
— — — — —
↕
↕
↕
— — ↕
↕
↕
↕
— — — — 1
— 1 — — —
— — ↕
↕ —
— 0 — — —
M ← (X)
A ← (A) – (M)
— — ↕
— — ↕
↕ —
↕
↕
ff
dd
ff
ii
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
Cycles
Operand
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
INH
Description
H I N Z C
RTI
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SEC
SEI
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STOP
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Opcode
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
RSP
Operation
Effect on
CCR
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
5
3
3
6
5
5
3
3
6
5
2
2
3
4
5
4
3
2
2
4
5
6
5
4
2
4
5
6
5
4
2
3
4
5
4
3
24-hc05cpu
46
CPU
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MOTOROLA
Freescale Semiconductor, Inc.
CPU
Instruction Set
Freescale Semiconductor, Inc...
SWI
H I N Z C
Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
X ← (A)
— — — — —
TAX
Transfer Accumulator to Index Register
TST opr
TSTA
TSTX
Test Memory Byte for Negative or Zero
TST opr,X
TST ,X
TXA
Transfer Index Register to Accumulator
WAIT
Stop CPU Clock and Enable Interrupts
A
Accumulator
C
Carry/borrow flag
CCR Condition code register
dd
Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
ff
Offset byte in indexed, 8-bit offset addressing
H
Half-carry flag
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
IMM Immediate addressing mode
INH Inherent addressing mode
IX
Indexed, no offset addressing mode
IX1
Indexed, 8-bit offset addressing mode
IX2
Indexed, 16-bit offset addressing mode
M
Memory location
N
Negative flag
n
Any bit
Opcode Map
(M) – $00
A ← (X)
— — ↕
↕ —
INH
83
INH
DIR
INH
INH
IX1
IX
INH
INH
97
3D
4D
5D
6D
7D
9F
8F
— — — — —
— 0 — — —
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
Relative program counter offset byte
rr
Relative program counter offset byte
SP Stack pointer
X
Index register
Z
Zero flag
#
Immediate value
∧
Logical AND
∨
Logical OR
⊕
Logical EXCLUSIVE OR
()
Contents of
–( ) Negation (two’s complement)
←
Loaded with
?
If
:
Concatenated with
↕
Set or cleared
—
Not affected
Cycles
Description
Operand
Operation
Effect on
CCR
Opcode
Source
Form
Address
Mode
Table 9. Instruction Set Summary (Continued)
10
dd
ff
2
4
3
3
5
4
2
2
The opcode map is provided in Table 10.
25-hc05cpu
MOTOROLA
CPU
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48
CPU
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
2
Branch
REL
3
DIR
4
5
6
Read-Modify-Write
INH
INH
IX1
7
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
MSB
0
LSB
0
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
Register/Memory
EXT
IX2
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
9
2
STOP
INH
2
2
WAIT
TXA
INH 1
INH
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
Control
INH
INH
LSB of Opcode in Hexadecimal
5
5
3
5
3
3
6
5
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BCLR0
BRN
3
DIR 2
DIR 2
REL
1
5
5
3
11
BRSET1
BSET1
BHI
MUL
3
DIR 2
DIR 2
REL
1
INH
5
5
3
5
3
3
6
5
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BCLR5
BMI
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BSET7
BIL
3
DIR 2
DIR 2
REL
1
5
5
3
5
3
3
6
5
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
0
Bit Manipulation
DIR
DIR
Table 10. Opcode Map
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
CPU
26-hc05cpu
MOTOROLA
Freescale Semiconductor, Inc.
Resets and Interrupts
Contents
Freescale Semiconductor, Inc...
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Low-Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5-mc68hc05p9a
MOTOROLA
Resets and Interrupts
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Resets and Interrupts
Resets
Freescale Semiconductor, Inc...
A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. The following sources can
generate resets:
•
Power-on reset (POR) circuit
•
RESET pin
•
COP watchdog
VDD
POWER-ON RESET
COP WATCHDOG
(MASK OPTION)
RESET
S
D
INTERNAL CLOCK
Q
RST
TO CPU AND
SUBSYSTEMS
CK
RESET
LATCH
Figure 17. Reset Sources
Power-On Reset
NOTE:
A positive transition on the VDD pin generates a power-on reset.
The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064 tCYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at logic
0 at the end of 4064 tCYC, the MCU remains in the reset condition until
the signal on the RESET pin goes to logic 1.
6-mc68hc05p9a
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Resets and Interrupts
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MOTOROLA
Freescale Semiconductor, Inc.
Resets and Interrupts
Resets
VDD
(NOTE 1)
4064 tCYC
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
1FFE
Freescale Semiconductor, Inc...
INTERNAL
DATA BUS
1FFE
1FFF
NEW
PCH
NEW
PCL
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 18. Power-On Reset Timing
External Reset
A logic 0 applied to the RESET pin for one and one-half tCYC generates
an external reset. A Schmitt trigger senses the logic level at the RESET
pin.
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
INTERNAL
DATA BUS
1FFE
1FFE
1FFE
NEW
PCH
1FFF
NEW
PCL
NEW PC
NEW PC
DUMMY
OP
CODE
tRL
RESET
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 19. External Reset Timing
Table 11. External Reset Timing
Characteristic
RESET Pulse Width
Symbol
Min
Max
Unit
tRL
1.5
—
tCYC
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Resets and Interrupts
COP Watchdog
Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $1FF0.
Low-Voltage Protection
Freescale Semiconductor, Inc...
A drop in power supply voltage below the minimum operating VDD
voltage is called a brownout condition. A brownout while the MCU is in a
non-reset state can corrupt MCU operation and necessitate a power-on
reset to resume operation.
The best protection against brownout is an undervoltage sensing circuit
that pulls the RESET pin low when it detects a low-power supply voltage.
The undervoltage sensing circuit may be made of discrete components
or an integrated circuit can be used.
For information about brownout and the COP watchdog, see the
Computer Operating Properly Watchdog section.
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Resets and Interrupts
Interrupts
Interrupts
Freescale Semiconductor, Inc...
The following sources can generate interrupts:
•
SWI instruction
•
IRQ pin
•
Capture/compare timer
An interrupt temporarily stops normal program execution to process a
particular event. An interrupt does not stop the operation of the
instruction being executed, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a
user-defined interrupt vector address.
Software
Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
External
Interrupt
An interrupt signal on the IRQ pin latches an external interrupt request.
When the CPU completes its current instruction, it tests the IRQ latch. If
the IRQ latch is set, the CPU then tests the I bit in the condition code
register. If the I bit is clear, the CPU then begins the interrupt sequence.
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is
cleared during the return from interrupt, the CPU can recognize the new
interrupt request. Figure 20 shows the IRQ pin interrupt logic.
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Resets and Interrupts
EDGE ONLY
MASK OPTION
EDGE AND LEVEL
VDD
Freescale Semiconductor, Inc...
FROM OTHER
PORT B PINS
D
Q
C
Q
R
EXTERNAL
INTERRUPT
REQUEST
I BIT
(FROM CCR)
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 20. External Interrupt Logic
Setting the I bit in the condition code register disables external interrupts.
Interrupt triggering sensitivity of the IRQ pin is a mask option. The IRQ
pin can be negative-edge triggered or negative-edge- and low-level
triggered. The level-sensitive triggering option allows multiple external
interrupt sources to be wire-ORed to the IRQ pin. An external interrupt
request, shown in Figure 21, is latched as long as any source is holding
the IRQ pin low.
tILIL
IRQ/VPP PIN
IRQ1
.
.
.
IRQn
tILIH
tILIH
IRQ (INTERNAL)
Figure 21. External Interrupt Timing
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Resets and Interrupts
Interrupts
Table 12. External Interrupt Timing (VDD = 5.0 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note(2)
—
tCYC
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
2. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tCYC.
Freescale Semiconductor, Inc...
Table 13. External Interrupt Timing (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
Note(2)
—
tCYC
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
2. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tCYC.
Timer Interrupts
The capture/compare timer can generate the following interrupts:
•
Input capture interrupt
•
Output compare interrupt
•
Timer overflow interrupt
Setting the I bit in the condition code register disables timer interrupts.
Input Capture
Interrupt
An input capture interrupt request occurs if the input capture flag, ICF,
becomes set while the input capture interrupt enable bit, ICIE, is also set.
ICF is in the timer status register, and ICIE is in the timer control register.
Output Compare
Interrupt
An output compare interrupt request occurs if the output compare flag,
OCF, becomes set while the output compare interrupt enable bit, OCIE,
is also set. OCF is in the timer status register, and OCIE is in the timer
control register.
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Resets and Interrupts
A timer overflow interrupt request occurs if the timer overflow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF is in the timer status register, and TOIE is in the timer control
register.
Interrupt
Processing
The CPU takes the following actions to begin servicing an interrupt:
Freescale Semiconductor, Inc...
Timer Overflow
Interrupt
•
Stores the CPU registers on the stack in the order shown in
Figure 22
•
Sets the I bit in the condition code register to prevent further
interrupts
•
Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $1FFC and $1FFD (software interrupt vector)
– $1FFA and $1FFB (external interrupt vector)
– $1FF8 and $1FF9 (timer interrupt vector)
The return from interrupt (RTI) instruction causes the CPU to recover the
CPU registers from the stack as shown in Figure 22.
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Resets and Interrupts
Interrupts
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
Freescale Semiconductor, Inc...
UNSTACKING
ORDER
•
•
•
•
•
•
5
1
4
2
ACCUMULATOR
3
3
INDEX REGISTER
2
4
PROGRAM COUNTER (HIGH BYTE)
1
5
PROGRAM COUNTER (LOW BYTE)
CONDITION CODE REGISTER
STACKING
ORDER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 22. Interrupt Stacking Order
Table 14. Reset/Interrupt Vector Addresses
Function
Source
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector
Address
Reset
Power-On
RESET Pin
COP Watchdog(1)
None
None
None
None
1
1
1
$1FFE–$1FFF
Software
Interrupt
(SWI)
User Code
None
None
External
Interrupt
IRQ Pin
None
I Bit
2
$1FFA–$1FFB
Timer
Interrupts
ICF Bit
OCF Bit
TOF Bit
ICIE Bit
OCIE Bit
TOIE Bit
I Bit
3
$1FF8–$1FF9
Same Priority as
$1FFC–$1FFD
Instruction
1. The COP watchdog is a mask option.
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Resets and Interrupts
FROM RESET
YES
I BIT SET?
NO
Freescale Semiconductor, Inc...
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH.
NO
TIMER
INTERRUPT?
YES
STACK PC, X, A, CCR.
SET I BIT.
LOAD PC WITH INTERRUPT VECTOR.
NO
FETCH NEXT
INSTRUCTION.
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
NO
YES
UNSTACK CCR, A, X, PC.
EXECUTE INSTRUCTION.
Figure 23. Interrupt Flowchart
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Low-Power Modes
Freescale Semiconductor, Inc...
Contents
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Stop Mode
The STOP instruction puts the MCU in its lowest power-consumption
mode and has the following effects on the MCU:
•
Stops the internal oscillator, the CPU clock, and the internal clock,
turning off the capture/compare timer, the COP watchdog, the
SIOP, and the ADC
•
Clears the I bit in the condition code register, enabling external
interrupts
•
Clears the ICIE, OCIE, and TOIE bits in the timer control register,
disabling further timer interrupts
The STOP instruction does not affect any other registers or any I/O lines.
The following events bring the MCU out of stop mode:
•
An external interrupt signal on the IRQ pin or a high-to-low
transition on the IRQ pin loads the program counter with the
contents of locations $1FFA and $1FFB. The timer resumes
counting from the last value before the STOP instruction.
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Low-Power Modes
•
External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $1FFE
and $1FFF. The timer begins counting from $FFFC.
When the MCU exits stop mode, processing resumes after a
stabilization delay of 4064 oscillator cycles.
Freescale Semiconductor, Inc...
An active edge on the PD7/TCAP pin during stop mode sets the ICF flag
when an external interrupt brings the MCU out of stop mode. An external
interrupt also latches the value in the timer registers into the input
capture registers.
If a reset brings the MCU out of stop mode, then an active edge on the
PD7/TCAP pin during stop mode has no effect on the ICF flag or the
input capture registers.
See Figure 24 for stop recovery timing information.
OSC
(NOTE 1)
tRL
RESET
IRQ/VPP
(NOTE 2)
tILIH
4064 tCYC
IRQ/VPP
(NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
1FFE
(NOTE 4)
1FFE
1FFE
1FFE
NOTES:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
1FFE
1FFF
RESET OR INTERRUPT
VECTOR FETCH
Figure 24. Stop Recovery Timing
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Low-Power Modes
Halt Mode
Halt Mode
NOTE:
Halt mode is NOT designed for intentional use. Halt mode is only
provided to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently. This mode of operation is usually
achieved by invoking wait mode.
Freescale Semiconductor, Inc...
Execution of the STOP instruction when STOP is disabled mask option
is selected placing the MCU in this low-power mode. Halt mode
consumes the same amount of power as wait mode (both halt and wait
modes consume more power than stop mode).
In halt mode, the internal clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the IRQ external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
the halt mode and resume normal operation. The halt mode also can be
exited when an IRQ external interrupt or external RESET occurs. When
exiting the halt mode, the internal clock will resume after a delay of one
to 4064 internal clock cycles. This varied delay time is the result of the
halt mode exit circuitry testing the oscillator stabilization delay timer (a
feature of the stop mode), which has been free-running (a feature of the
wait mode).
Figure 25 shows the sequence of events caused by the STOP/HALT
instruction.
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Low-Power Modes
STOP
HALT
MOR
SWAIT
BIT SET?
EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
Y
N
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET STARTUP DELAY
Y
Freescale Semiconductor, Inc...
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I BIT IN CCR
EXTERNAL
RESET?
N
EXTERNAL
RESET?
Y
Y
IRQ
EXTERNAL
INTERRUPT?
N
N
IRQ
EXTERNAL
INTERRUPT?
N
Y
Y
TIMER
INTERNAL
INTERRUPT?
RESTART EXTERNAL OSCILLATOR,
START STABILIZATION DELAY
N
Y
END
OF STABILIZATION
DELAY?
COP
INTERNAL
RESET?
Y
N
N
RESTART
INTERNAL PROCESSOR CLOCK
1.
2.
FETCH RESET VECTOR
OR
SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
Figure 25. STOP/HALT Flowcharts
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Low-Power Modes
Wait Mode
Wait Mode
The WAIT instruction puts the MCU in an intermediate
power-consumption mode and has the following effects on the MCU:
•
Clears the I bit in the condition code register, enabling interrupts
•
Stops the CPU clock, but allows the internal clock to drive the
capture/compare timer, the COP watchdog, and the ADC
Freescale Semiconductor, Inc...
The WAIT instruction does not affect any other registers or any I/O lines.
The following conditions restart the CPU clock and bring the MCU out of
wait mode:
•
External interrupt — A high-to-low transition on the IRQ pin loads
the program counter with the contents of locations $1FFA and
$1FFB.
•
Timer interrupt — Input capture, output compare, and timer
overflow interrupt requests load the program counter with the
contents of locations $1FF8 and $1FF9.
•
COP watchdog reset — A timeout of the COP watchdog resets the
MCU and loads the program counter with the contents of locations
$1FFE and $1FFF. Software can enable timer interrupts so that
the MCU can periodically exit wait mode to reset the COP
watchdog.
•
External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $1FFE
and $1FFF.
Figure 26 shows the sequence of events caused by the WAIT
instruction.
Figure 27 shows the effect of the STOP and WAIT instructions on the
CPU clock and the timer clock.
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Low-Power Modes
WAIT
CLEAR I BIT IN CCR
STOP CPU CLOCK
NO
Freescale Semiconductor, Inc...
RESET?
YES
EXTERNAL
INTERRUPT?
NO
YES
TIMER
INTERRUPT?
NO
YES
OTHER ON-CHIP
INTERRUPT
SOURCES?
NO
RESTART CPU CLOCK
(1) FETCH RESET VECTOR
OR
(2) SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. VECTOR TO INTERRUPT SERVICE ROUTINE
Figure 26. WAIT Instruction Flowchart
WAIT
STOP
OSC1
OSC2
INTERNAL
OSCILLATOR
÷2
INTERNAL CLOCK
÷2
CPU CLOCK
TIMER CLOCK
ADC CLOCK
Figure 27. STOP/WAIT Clock Logic
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Parallel I/O Ports
Contents
Freescale Semiconductor, Inc...
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Port A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . .68
Port A I/O Pin Interrupts/Pullups . . . . . . . . . . . . . . . . . . . . . . . . . .70
Port B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . .71
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . .74
PC0–PC1 High Current Sink/Source Capability . . . . . . . . . . . . . . .75
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . .77
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Parallel I/O Ports
Introduction
Twenty bidirectional pins and one input-only pin form four parallel
input/output (I/O) ports. All the bidirectional port pins are programmable
as inputs or outputs.
Freescale Semiconductor, Inc...
NOTE:
Addr.
$0000
$0001
$0002
$0003
Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Name:
R/W Bit 7
Read:
Port A Data Register (PORTA)
PA7
Write:
Reset:
Port B Data Register (PORTB)
Port C Data Register (PORTC)
Port D Data Register (PORTD)
$0004 Data Direction Register A (DDRA)
$0005 Data Direction Register B (DDRB)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
PB7
6
5
4
3
2
1
Bit 0
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
0
0
PC2
PC1
PC0
0
0
0
Unaffected by reset
PB6
0
PB5
0
Unaffected by reset
PC7
PC6
PC5
PC4
PC3
Unaffected by reset
PD7
0
1
PD5
0
Unaffected by reset
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:
0
0
0
0
0
0
0
0
Read:
DDRB7 DDRB6 DDRB5
Write:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 28. Parallel I/O Port Register Summary
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Parallel I/O Ports
Port A
Addr.
Name:
R/W Bit 7
6
5
4
3
2
1
Bit 0
Read:
$0006 Data Direction Register C (DDRC)
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Reset:
0
0
0
0
0
0
0
0
$0007 Data Direction Register D (DDRD)
Read:
Write:
Reset:
0
0
0
0
DDRD5
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
Freescale Semiconductor, Inc...
Figure 28. Parallel I/O Port Register Summary (Continued)
Port A
Port A is an 8-bit general-purpose I/O port.
Port A Data
Register (PORTA)
The port A data register contains a latch for each of the eight port A pins.
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Unaffected by reset
Figure 29. Port A Data Register (PORTA)
PA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
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Parallel I/O Ports
Data Direction
Register A (DDRA)
Data direction register A determines whether each port A pin is an input
or an output.
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Freescale Semiconductor, Inc...
Figure 30. Data Direction Register A (DDRA)
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all eight port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 31 shows the I/O logic of port A.
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port A pins.
Table 15. Port A Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
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Parallel I/O Ports
Port A
VDD
VDD
DISABLED
PORT A EXTERNAL INTERRUPT
MASK OPTION
ENABLED
READ $0004
INTERNAL DATA BUS
Freescale Semiconductor, Inc...
WRITE $0004
RESET
WRITE $0000
DATA DIRECTION
REGISTER A
BIT DDRA7
PORT A DATA
REGISTER
BIT PA7
PAX
READ $0000
EDGE ONLY
SOFTWARE CONTROLLED OPTION
EDGE AND LEVEL
VDD
FROM OTHER
PORT A PINS
D
Q
C
Q
R
EXTERNAL
INTERRUPT
REQUEST
I BIT
(FROM CCR)
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 31. Port A I/O Logic
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Parallel I/O Ports
Port A I/O Pin
Interrupts/Pullups
If the port A interrupt/pullup enabled mask option is selected the
PA0–PA7 pins will function as external interrupt pins when configured as
inputs. (See External Interrupt on page 53.)
Port B
Freescale Semiconductor, Inc...
Port B is a 3-bit I/O port that shares its pins with the serial I/O port
(SIOP).
NOTE:
Port B Data
Register (PORTB)
Do not use port B for general-purpose I/O while the SIOP is enabled.
The port B data register contains a latch for each of the three port B pins.
$0001
Bit 7
6
5
PB7
PB6
PB5
Read:
4
3
2
1
Bit 0
0
0
0
0
0
Write:
Reset:
Alternate
Function:
Unaffected by reset
SCK
SDI
SDO
= Unimplemented
Figure 32. Port B Data Register (PORTB)
PB[7:5] — Port B Data Bits
These read/write bits are software programmable bits. Data direction
of each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
NOTE:
Writing to data direction register B does not affect the data direction of
port B pins that are being used by the SIOP. However, data direction
register B always determines whether reading port B returns the states
of the latches or the states of the pins.
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Parallel I/O Ports
Port B
SCK — Serial Clock
When the SIOP is enabled, SCK is the SIOP clock output (in master
mode) or the SIOP clock input (in slave mode).
SDI — Serial Data Input
When the SIOP is enabled, SDI is the SIOP data input.
SDO — Serial Data Output
Freescale Semiconductor, Inc...
When the SIOP is enabled, SDO is the SIOP data output.
Data Direction
Register B (DDRB)
NOTE:
Data direction register B determines whether each port B pin is an input
or an output.
Enabling and then disabling the SIOP configures data direction register
B for SIOP operation and can also change the port B data register. After
disabling the SIOP, initialize data direction register B and the port B data
register as your application requires.
$0005
Bit 7
6
5
DDRB7
DDRB6
DDRB5
0
0
0
Read:
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 33. Data Direction Register B (DDRB)
DDRB[7:5] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:5], configuring all three port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 34 shows the I/O logic of port B.
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Parallel I/O Ports
READ DATA DIRECTION REGISTER B ($0005)
INTERNAL DATA BUS
WRITE DATA DIRECTION REGISTER B ($0005)
RESET
WRITE PORT B DATA REGISTER ($0001)
DDRBx
PBx
PBx
Freescale Semiconductor, Inc...
READ PORT B DATA REGISTER ($0001)
Figure 34. Port B I/O Logic
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port B pins.
Table 16. Port B Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
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Parallel I/O Ports
Port C
Port C
Port C is an 8-bit I/O port that shares five of its pins with the A/D
converter (ADC). The five shared pins are available for general-purpose
I/O functions when the ADC is disabled.
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Port C Data
Register (PORTC)
The port C data register contains a latch for each of the eight port C pins.
$0002
Bit 7
6
5
4
3
2
1
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Read:
Write:
Reset:
Alternate
Function:
Unaffected by reset
VRH
AN0
AN1
AN2
AN3
Figure 35. Port C Data Register (PORTC)
PC[7:0] — Port C Data Bits
These read/write bits are software programmable. Data direction of
each port C pin is under the control of the corresponding bit in data
direction register C. Reset has no effect on port C data.
VRH — Voltage Reference High Bit
When the ADC is turned on, the PC7/VRH pin is configured as an input
and is the positive ADC reference voltage.
AN[3:0] — Analog Input Bits
When the ADC is turned on, the AN0–AN3 pin that is selected as the
analog input is configured as an input. Unused analog inputs can be
used as digital inputs, but pins PC3/AN3, PC4/AN2, PC5/AN1, and
PC6/AN0 cannot be used as digital outputs while the ADC is on. Only
pins PC0, PC1, and PC2 can be used as digital outputs when the
ADC is on.
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Parallel I/O Ports
The port C data register reads normally while the ADC is on, except
that the bit corresponding to the currently selected ADC input pin
reads as logic 0.
Writing to bits PC7–PC3 while the ADC is on can produce
unpredictable ADC results.
Freescale Semiconductor, Inc...
Data Direction
Register C (DDRC)
Data direction register C determines whether each port C pin is an input
or an output.
$0006
Bit 7
6
5
4
3
2
1
Bit 0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 36. Data Direction Register C (DDRC)
DDRC[7:0] — Data Direction Register C Bits
These read/write bits control port C data direction. Reset clears
DDRC[7:0], configuring all port C pins as inputs.
1 = Corresponding port C pin configured as output
0 = Corresponding port C pin configured as input
NOTE:
Avoid glitches on port C pins by writing to the port C data register before
changing data direction register C bits from 0 to 1.
Writing to bits DDRC7–DDRC3 while the ADC is on can produce
unpredictable ADC results.
Figure 37 shows the I/O logic of port C.
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Parallel I/O Ports
Port C
READ DATA DIRECTION REGISTER C ($0006)
INTERNAL DATA BUS
WRITE DATA DIRECTION REGISTER C ($0006)
RESET
WRITE PORT C DATA REGISTER ($0002)
DDRCx
HIGH CURRENT SOURCE/SINK
CAPABILITY (PINS PA0–PA1 ONLY)
PCx
PCx
Freescale Semiconductor, Inc...
READ PORT C DATA REGISTER ($0002)
Figure 37. Port C I/O Logic
Writing a logic 1 to a DDRC bit enables the output buffer for the
corresponding port C pin; a logic 0 disables the output buffer.
When bit DDRCx is a logic 1, reading address $0002 reads the PCx data
latch. When bit DDRCx is a logic 0, reading address $0002 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port C pins.
Table 17. Port C Pin Operation
Accesses to Data Bit
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
PC0–PC1 High
Current
Sink/Source
Capability
The outputs for the lower two bits of port C (PC0–PC1) can source/sink
relatively high current. (See 5.0 V DC Electrical Characteristics on
page 130 and 3.3 V DC Electrical Characteristics on page 132 for
details.)
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Port D
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Port D is a 2-bit port with one I/O pin and one input-only pin. Port D
shares the input-only pin, PD7/TCAP, with the capture/compare timer.
PD7/TCAP is the timer input capture pin. The PD7/TCAP pin can always
be a general-purpose input, even if input capture interrupts are enabled.
Port D Data
Register (PORTD)
The port D data register contains a latch for each of the two port D pins.
$0003
Bit 7
6
Read:
PD7
0
5
4
3
2
1
Bit 0
1
0
0
0
0
PD5
Write:
Reset:
Alternate
Function:
Unaffected by reset
TCAP
= Unimplemented
Figure 38. Port D Data Register (PORTD)
PD7 and PD5 — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
TCAP — Timer Capture
TCAP is the input capture pin for the timer.
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Parallel I/O Ports
Port D
Data Direction
Register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output.
$0007
Bit 7
6
Read:
0
0
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
DDRD5
Write:
Reset:
0
0
0
= Unimplemented
Freescale Semiconductor, Inc...
Figure 39. Data Direction Register D (DDRD)
DDRD5 — Data Direction Register D Bit
This read/write bit controls the data direction of pin PD5. Reset clears
DDRD5, configuring PD5 as an input.
1 = PD5 configured as output
0 = PD5 configured as input
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 40 shows the I/O logic of port D.
READ DATA DIRECTION REGISTER D ($0007)
INTERNAL DATA BUS
WRITE DATA DIRECTION REGISTER D ($0007)
RESET
WRITE PORT D DATA REGISTER ($0003)
DDRDx
PDx
PDx
READ PORT D DATA REGISTER ($0003)
Figure 40. Port D I/O Logic
Writing a logic 1 to a DDRD bit enables the output buffer for the
corresponding port D pin; a logic 0 disables the output buffer.
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When bit DDRDx is a logic 1, reading address $0003 reads the PDx data
latch. When bit DDRDx is a logic 0, reading address $0003 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 16 summarizes the operation
of the port D pins.
Table 18. Port D Pin Operation
Accesses to Data Bit
Freescale Semiconductor, Inc...
Data Direction Bit
I/O Pin Mode
Read
Write
0
Input, Hi-Z(1)
Pin
Latch(2)
1
Output
Latch
Latch
1. Hi-Z = high impedance
2. Writing affects data register, but does not affect input.
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Computer Operating Properly Watchdog
COP
Freescale Semiconductor, Inc...
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Features
•
Protection from runaway software
•
131,072/fop timeout period
•
Wait mode operation
•
Halt mode operation
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COP
Introduction
Freescale Semiconductor, Inc...
The purpose of the computer operating properly (COP) watchdog is to
reset the MCU in case of software failure. Software that is operating
properly periodically services the COP watchdog and prevents the reset
from occurring. The COP watchdog function is selectable with a mask
option.
Operation
COP Watchdog
Timeout
NOTE:
The COP watchdog is a 16-bit counter that generates a reset if allowed
to time out. Periodically clearing the counter starts a new timeout period
and prevents the COP from resetting the MCU. A COP watchdog
timeout indicates that the software is not executing instructions in the
correct sequence.
The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
The COP watchdog also depends on a power supply voltage at or above
a minimum specification and is not guaranteed to protect against
brownout. For information about brownout protection, see the Resets
and Interrupts section.
COP Watchdog
Timeout Period
Use the following formula to calculate the COP timeout period:
131 ,072 cycles
COP Timeout Period = --------------------------------------f BUS
where
crystal frequency
f BUS = --------------------------------------------2
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COP
Interrupts
Clearing the COP
Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $1FF0.
If the main program executes within the COP timeout period, the clearing
routine needs to be executed only once. If the main program takes
longer than the COP timeout period, the clearing routine must be
executed more than once.
Freescale Semiconductor, Inc...
NOTE:
Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even though the main program is not operating
properly.
Interrupts
The COP watchdog does not generate interrupts.
COP Register
The COP register is a write-only register that returns the contents of
EPROM location $1FF0 when read.
$1FF0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
D7
D6
D5
D4
D3
D2
D1
D0
Write:
Reset:
COPC
U
U
U
= Unimplemented
U
U
U
U
0
U = Unaffected
Figure 41. COP Register (COPR)
COPC — COP Clear
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU. Reset clears the
COPC bit.
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COP
Low-Power Modes
The STOP, HALT, and WAIT instructions put the MCU in low-power
consumption standby modes.
Freescale Semiconductor, Inc...
Stop Mode
The STOP instruction clears the COP watchdog counter. Upon exit from
stop mode by external reset:
•
The COP counter begins counting from $0000.
•
The COP counter is cleared again after the 4064-cycle oscillator
stabilization delay.
Upon exit from stop mode by external interrupt:
•
The COP counter begins counting from $0000.
•
The COP counter is not cleared again after the oscillator
stabilization delay and has a count of 4064 when the program
resumes.
Halt Mode
NOTE:
Halt mode is NOT designed for intentional use. Halt mode is only
provided to keep the COP watchdog timer active in the event a STOP
instruction is executed inadvertently. This mode of operation is usually
achieved by invoking wait mode.
Execution of the STOP instruction when STOP is disabled mask option
is selected placing the MCU in this low-power mode. Halt mode
consumes the same amount of power as wait mode (both halt and wait
modes consume more power than stop mode).
Upon exit from halt mode by COP reset or external reset:
•
The COP counter begins counting from $0000
•
the COP counter resumes counting after a delay of one to 4064
cycles
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COP
Low-Power Modes
The COP watchdog continues to operate normally after a WAIT
instruction. Software should periodically take the MCU out of wait mode
and write to the COPC bit to prevent a COP watchdog timeout.
Freescale Semiconductor, Inc...
Wait Mode
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COP
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COP
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COP
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Timer
Contents
Freescale Semiconductor, Inc...
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Alternate Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
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Timer
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Features
•
Programmable Polarity of Input Capture Edge
•
Programmable Polarity of Output Compare Signal
•
Alternate Counter Registers
•
16-Bit Counter
•
Interrupt-Driven Operation with Three Maskable Interrupt Flags:
– Input Capture
– Output Compare
– Timer Overflow
Introduction
The timer provides a timing reference for MCU operations. The input
capture and output compare functions provide a means to latch the
times at which external events occur, to measure input waveforms, and
to generate output waveforms and timing delays. Figure 42 shows the
structure of the timer module.
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Timer
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Timer
Introduction
EDGE
SELECT/
DETECT
LOGIC
TCAP
IEDG
ICRH
ICRL
TRH
TRL
ATRH
ATRL
Freescale Semiconductor, Inc...
INTERNAL
CLOCK
(XTAL ÷ 2)
÷4
16-BIT COUNTER
16-BIT COMPARATOR
OCRH
PIN
CONTROL
LOGIC
TCMP
OCRL
OLVL
INTERNAL
DATA BUS
TIMER OVERFLOW
OCIE
OCF
TOIE
TOF
TIMER
INTERRUPT
REQUEST
ICIE
ICF
Figure 42. Timer Block Diagram
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Timer
Addr.
$0012
$0013
Freescale Semiconductor, Inc...
$0014
$0015
Name
R/W Bit 7
Read:
Timer Control Register (TCR)
ICIE
Write:
Reset:
0
Timer Status Register (TSR)
Input Capture Register High (ICRH)
Input Capture Register Low (ICRL)
$0016 Output Compare Register High (OCRH)
$0017
$0018
$0019
$001A
$001B
Output Compare Register Low (OCRL)
Timer Register High (TRH)
Timer Register Low (TRL)
Alternate Timer Register High (ATRH)
Alternate Timer Register Low (ATRL)
6
5
4
3
2
1
Bit 0
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
U
0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Read: Bit 15
Write:
Reset:
14
13
12
11
10
9
Bit 8
Read:
Write:
Reset:
6
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
10
9
Bit 8
1
Bit 0
Read:
Write:
Reset:
Bit 7
5
4
3
Unaffected by reset
Read:
Bit 15
Write:
Reset:
Read:
Write:
Reset:
Unaffected by reset
Bit 7
14
13
12
11
Unaffected by reset
6
5
4
3
Unaffected by reset
Read: Bit 15
Write:
Reset:
14
Read:
Write:
Reset:
6
Bit 7
13
12
11
Reset initializes TRH to $FF
5
4
3
Reset initializes TRL to $FC
Read: Bit 15
Write:
Reset:
14
Read:
Write:
Reset:
6
Bit 7
13
12
11
Reset initializes ATRH to $FF
5
4
3
2
Reset initializes ATRL to $FC
= Unimplemented
U = Unaffected
Figure 43. Timer I/O Register Summary
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Timer
Operation
Operation
Freescale Semiconductor, Inc...
The timing reference for the input capture and output compare functions
is a 16-bit free-running counter. The counter is preceded by a divide-byfour prescaler and rolls over every 218 cycles. Timer resolution with a 4MHz crystal is 2 µs. Software can read the value in the counter at any
time without affecting the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
Pin Functions
The timer uses two pins.
PD7/TCAP
PD7/TCAP is the input capture pin. When an active edge occurs on
PD7/TCAP, the timer transfers the current counter value to the input
capture registers. PD7/TCAP is also an I/O port pin.
TCMP
TCMP is the output-only output compare pin. When the counter value
matches the value written in the output compare registers, the timer
transfers the output level bit, OLVL, to the TCMP pin.
Input Capture
The input capture function is a means to record the time at which an
external event occurs. When the input capture circuitry detects an active
edge on the PD7/TCAP pin, it latches the contents of the timer registers
into the input capture registers. The polarity of the active edge is
programmable.
Latching values into the input capture registers at successive edges of
the same polarity measures the period of the input signal on the
PD7/TCAP pin. Latching the counter values at successive edges of
opposite polarity measures the pulse width of the signal. Figure 44
shows the logic of the input capture function.
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Timer
EDGE
SELECT/
DETECT
LOGIC
TCAP
IEDG
ICRH
ICRL
TRH
TRL
ICF
TIMER
INTERRUPT
REQUEST
Freescale Semiconductor, Inc...
ICIE
Figure 44. Input Capture Operation
Output Compare
The output compare function is a means of generating an output signal
when the 16-bit counter reaches a selected value. Software writes the
selected value into the output compare registers. On every fourth
internal clock cycle the output compare circuitry compares the value of
the counter to the value written in the output compare registers. When a
match occurs, the timer transfers the programmable output level bit
(OLVL) from the timer control register to the TCMP pin.
Software can use the output compare register to measure time periods,
to generate timing delays, or to generate a pulse of specific duration or
a pulse train of specific frequency and duty cycle on the TCMP pin.
Figure 45 shows the logic of the output compare function.
16-BIT COUNTER
PIN
CONTROL
LOGIC
16-BIT COMPARATOR
OCRH ($0016)
TCMP
OCRL ($0017)
OLVL
OCF
OCIE
TIMER
INTERRUPT
REQUEST
Figure 45. Output Compare Operation
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Timer
Timing
Timing
Table 19. Timer Characteristics (VDD = 5.0 Vdc)(1)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Timer Resolution(2)
tRESL
4.0
—
tCYC
Input Capture Pulse Width
tH, tL
125
—
ns
Input Capture Pulse Period
tTLTL
—
tCYC
Note
(3)
1. VDD = 5.0 Vdc ± 10%, TA = TL to TH unless otherwise noted.
2. A 2-bit prescaler in the timer is the limiting factor as it counts 4 tCYC.
3. The minimum tTLTL should not be less than the number of interrupt service routine cycles
plus 19 tCYC.
Table 20. Timer Characteristics (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Timer Resolution(2)
tRESL
4.0
—
tCYC
Input Capture Pulse Width
tH, tL
250
—
ns
Input Capture Pulse Period
tTLTL
—
tCYC
Note
(3)
1. VDD = 3.3 Vdc ± 10%, TA = TL to TH unless otherwise noted.
2. A 2-bit prescaler in the timer is the limiting factor as it counts 4 tCYC.
3. The minimum tTLTL should not be less than the number of interrupt service routine cycles
plus 19 tCYC.
tTLTL
tTH
tTL
Figure 46. Input Capture Characteristics
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Timer
INTERNAL
BUS CLOCK
INTERNAL
RESET
Freescale Semiconductor, Inc...






TIMER 
CLOCKS 





T00
T01
T10
T11
16-BIT
COUNTER
$FFFC
$FFFE
$FFFD
$FFFF
RESET (EXTERNAL
OR END OF POR)
Figure 47. Timer Reset Timing
INTERNAL
BUS CLOCK

 T00


 T01

TIMER 
CLOCKS 
 T10


 T11

16-BIT
COUNTER $FFEB
$FFEC
$FFED
$FFEE
$FFEF
INPUT CAPTURE
EDGE
INPUT CAPTURE
LATCH
INPUT CAPTURE
REGISTER
PREVIOUSLY CAPTURED VALUE
$FFED
INPUT CAPTURE
FLAG
NOTE:
If the input capture edge occurs in the shaded area between T10 states, then the input capture
flag becomes set during the next T11 state.
Figure 48. Input Capture Timing
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Timer
Timing
INTERNAL
BUS CLOCK

 T00


 T01

TIMER 
CLOCKS 
 T10


 T11

Freescale Semiconductor, Inc...
16-BIT
COUNTER
OUTPUT COMPARE
REGISTERS
$FFEB
$FFEC
$FFED
$FFEF
$FFEE
$FFED
CPU WRITES $FFED
COMPARE
REGISTER LATCH
OUTPUT COMPARE
FLAG AND TCMP
NOTES:
1. A write to the output compare registers may occur at any time, but a compare only occurs at
timer state T01. Therefore, the compare may follow the write by up to four cycles.
2. The output compare flag is set at the timer state T11 that follows the comparison latch.
Figure 49. Output Compare Timing
INTERNAL
BUS CLOCK

 T00


 T01

TIMER 
CLOCKS 
 T10


 T11

16-BIT
COUNTER
$FFFF
$0000
$0001
$0002
OVERFLOW
FLAG (TOF)
Figure 50. Timer Overflow Timing
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Timer
Interrupts
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The following timer sources can generate interrupts:
•
Input capture flag (ICF) — The ICF bit is set when an edge of the
selected polarity occurs on the input capture pin. The input
capture interrupt enable bit, ICIE, enables ICF interrupt requests.
•
Output compare flag (OCF) — The OCF bit is set when the
counter value matches the value written in the output compare
registers. The output compare interrupt enable bit, OCIE, enables
OCF interrupt requests.
•
Timer overflow flag (TOF) — The TOF bit is set when the counter
value rolls over from $FFFF to $0000. The timer overflow enable
bit (TOIE) enables timer overflow interrupt requests.
Table 21 summarizes the timer interrupt sources.
Table 21. Timer Interrupt Sources
Source
Local Mask
Global
Mask
Priority
(1 = Highest)
ICF Bit
OCF Bit
TOF Bit
ICIE Bit
OCIE Bit
TOIE Bit
I Bit
3
I/O Registers
The following registers control and monitor the operation of the timer:
•
Timer control register (TCR)
•
Timer status register (TSR)
•
Timer registers (TRH and TRL)
•
Alternate timer registers (ATRH and ATRL)
•
Input capture registers (ICRH and ICRL)
•
Output compare registers (OCRH and OCRL)
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Timer
I/O Registers
Freescale Semiconductor, Inc...
Timer Control
Register
The timer control register (TCR) performs the following functions:
•
Enables input capture interrupts
•
Enables output compare interrupts
•
Enables timer overflow interrupts
•
Controls the active edge polarity of the TCAP signal
•
Controls the active level of the TCMP output
$0012
Bit 7
6
5
4
3
2
1
Bit 0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
Read:
Write:
Reset:
U = Unaffected
Figure 51. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the PD7/TCAP pin. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Reset clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
Bits 4–2 — Unused
These are read/write bits that always read as logic 0s.
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Timer
IEDG — Input Edge
The state of this read/write bit determines whether a positive or
negative transition on the PD7/TCAP pin triggers a transfer of the
contents of the timer registers to the input capture registers. Reset
has no effect on the IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
Freescale Semiconductor, Inc...
OLVL — Output Level
The state of this read/write bit determines whether a logic 1 or a logic
0 appears on the TCMP pin when a successful output compare
occurs. Reset clears the OLVL bit.
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Timer Status
Register
The timer status register (TSR) contains flags for the following events:
•
An active signal on the PD7/TCAP pin, transferring the contents of
the timer registers to the input capture registers
•
A match between the 16-bit counter and the output compare
registers, transferring the OLVL bit to the TCMP pin
•
A timer rollover from $FFFF to $0000
$0013
Bit 7
6
5
4
3
2
1
Bit 0
Read:
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Write:
Reset:
= Unimplemented
U = Unaffected
Figure 52. Timer Status Register (TSR)
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Timer
I/O Registers
ICF — Input Capture Flag
The ICF bit is automatically set when an edge of the selected polarity
occurs on the PD7/TCAP pin. Clear the ICF bit by reading the timer
status register with ICF set, and then reading the low byte of the input
capture registers. Reset has no effect on ICF.
1 = Input capture
0 = No input capture
OCF — Output Compare Flag
Freescale Semiconductor, Inc...
The OCF bit is automatically set when the value of the timer registers
matches the contents of the output compare registers. Clear the OCF
bit by reading the timer status register with OCF set, and then reading
the low byte of the output compare registers. Reset has no effect on
OCF.
1 = Output compare
0 = No output compare
TOF — Timer Overflow Flag
The TOF bit is automatically set when the 16-bit counter rolls over
from $FFFF to $0000. Clear the TOF bit by reading the timer status
register with TOF set, and then reading the low byte of the timer
registers. Reset has no effect on TOF.
1 = Timer overflow
0 = No timer overflow
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Timer
Timer Registers
The read-only timer registers (TRH and TRL) contain the current high
and low bytes of the 16-bit counter. Reading TRH before reading TRL
causes TRL to be latched until TRL is read. Reading TRL after reading
the timer status register clears the timer overflow flag (TOF). Writing to
the timer registers has no effect.
$0018
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Freescale Semiconductor, Inc...
Write:
Reset:
Reset initializes TRH to $FF
$0019
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Reset initializes TRL to $FC
= Unimplemented
Figure 53. Timer Registers (TRH and TRL)
Reading TRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer. The buffer value
remains fixed even if the high byte is read more than once. Reading TRL
reads the transparent low byte buffer and completes the read sequence
of the timer registers.
INTERNAL
DATA BUS
LATCH
READ TRH
BUFFER
TRH ($0018)
TRL ($0019)
Figure 54. Timer Register Reads
NOTE:
To prevent interrupts from occurring between readings of TRH and TRL,
set the interrupt mask (I bit) in the condition code register before reading
TRH, and clear the mask after reading TRL.
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Timer
I/O Registers
Alternate Timer
Registers
The read-only alternate timer registers (ATRH and ATRL) contain the
current high and low bytes of the 16-bit counter. Reading ATRH before
reading ATRL causes ATRL to be latched until ATRL is read. Reading
does not affect the timer overflow flag (TOF). Writing to the alternate
timer registers has no effect.
$001A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Freescale Semiconductor, Inc...
Write:
Reset:
Reset initializes ATRH to $FF
$001B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Reset initializes ATRL to $FC
= Unimplemented
Figure 55. Alternate Timer Registers (ATRH and ATRL)
Reading ATRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer.
INTERNAL
DATA BUS
LATCH
READ ATRH
ATRH ($001A)
BUFFER
ATRL ($001B)
Figure 56. Alternate Timer Register Reads
NOTE:
To prevent interrupts between readings of ATRH and ATRL, set the
interrupt mask (I bit) in the condition code register before reading ATRH,
and clear the mask after reading ATRL.
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Timer
Freescale Semiconductor, Inc...
Input Capture
Registers
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the read-only input capture
registers (ICRH and ICRL). Reading ICRH before reading ICRL inhibits
further captures until ICRL is read. Reading ICRL after reading the timer
status register clears the input capture flag (ICF). Writing to the input
capture registers has no effect.
$0014
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Unaffected by reset
$0015
7
6
5
4
3
2
1
0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 57. Input Capture Registers (ICRH and ICRL)
NOTE:
To prevent interrupts between readings of ICRH and ICRL, set the
interrupt mask (I bit) in the condition code register before reading ICRH,
and clear the mask after reading ICRL.
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Timer
I/O Registers
Output Compare
Registers
When the value of the 16-bit counter matches the value in the read/write
output compare registers (OCRH and OCRL), the planned TCMP pin
action takes place. Writing to OCRH before writing to OCRL inhibits
timer compares until OCRL is written. Reading or writing to OCRL after
reading the timer status register clears the output compare flag (OCF).
$0016
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Freescale Semiconductor, Inc...
Write:
Reset:
$0017
Unaffected by reset
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 58. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use the following procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading the timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code
register.
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Timer
Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power
consumption standby modes.
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Stop Mode
The STOP instruction suspends the timer counter. Upon exit from stop
mode by external reset:
•
The timer counter resumes counting from $FFFC.
•
An input capture edge during stop mode does not affect the ICF
bit or the input capture registers.
Upon exit from stop mode by external interrupt:
Wait Mode
•
The counter resumes counting from the suspended value.
•
An input capture edge during stop mode sets the ICF bit and
transfers the suspended timer counter value to the input capture
registers.
The timer remains active after a WAIT instruction. Any enabled timer
interrupt request can bring the MCU out of wait mode.
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Serial Input/Output Port
SIOP
Contents
Freescale Semiconductor, Inc...
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PB7/SCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
PB5/SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
PB6/SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
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SIOP
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SIOP
Freescale Semiconductor, Inc...
Features
•
Master or Slave Operation
•
Programmable MSB-First or LSB-First Operation
•
Interrupt-Driven Operation with Transfer Complete Flag
•
Data Collision Flag
•
Master Mode Frequency = Bus Frequency ÷ 4
•
Maximum Slave Mode Frequency = Bus Frequency ÷ 4
•
No Minimum Slave Mode Frequency
Introduction
The serial input/output port (SIOP) is a 3-wire master/slave
communication port with serial clock, data input, and data output
connections. The SIOP enables high-speed synchronous serial data
transfer between the MCU and peripheral devices. Shift registers used
with the SIOP can increase the number of parallel I/O pins controlled by
the MCU. More powerful peripherals such as analog-to-digital
converters and real-time clocks are also compatible with the SIOP.
Figure 59 shows the structure of the SIOP module.
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SIOP
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SIOP
Introduction
INTERNAL BUS
SIOP DATA REGISTER
7
6
5
4
3
2
1
PB5/SDO
0
PB7/SCK
LSB OR MSB
SHIFT CLOCK
SPIF/DCOL
MASK OPTION
PB6/SDI
Freescale Semiconductor, Inc...
SIOP
CONTROL
PIN
CONTROL
LOGIC
AND
DDR
SPE
MSTR
M
S
SPIF
DCOL
INTERNAL
CLOCK
(fOSC ÷ 2)
DIVIDE
BY 4
CLOCK
LOGIC
Figure 59. SIOP Block Diagram
Addr.
$000A
$000B
$000C
Name
SIOP Control Register (SCR)
SIOP Status Register (SSR)
SIOP Data Register (SDR)
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 7
0
6
SPE
5
0
4
MSTR
3
0
2
0
1
0
Bit 0
0
0
0
0
0
0
0
0
0
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Unaffected by reset
= Unimplemented
Figure 60. SIOP I/O Register Summary
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SIOP
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SIOP
Operation
The master MCU initiates and controls the transfer of data to and from
one or more slave peripheral devices. In master mode, a transmission is
initiated by writing to the SIOP data register (SDR). Data written to the
SDR is parallel-loaded and shifted out serially to the slave device(s).
Freescale Semiconductor, Inc...
Many simple slave devices are designed to only receive data from a
master or to only supply data to a master. For example, when a
serial-to-parallel shift register is used as an 8-bit port, the master MCU
initiates transfers of 8-bit data values to the shift register. Since the
serial-to-parallel shift register does not send any data to the master, the
MCU ignores whatever it receives as a result of the transmission.
The SIOP is simpler than the serial peripheral interface (SPI) on some
other Motorola MCUs in that:
•
The polarity of the serial clock is fixed.
•
There is no slave select pin.
•
The direction of serial data does not automatically switch as on the
SPI because the SIOP is not intended for use in multimaster
systems. Most applications use one MCU as the master to initiate
and control data transfer between one or more slave peripheral
devices.
A mask option allows the SIOP to transfer data MSB first or LSB first.
8-mc68hc05p9a
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SIOP
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SIOP
Operation
Pin Functions
Freescale Semiconductor, Inc...
NOTE:
The SIOP uses three pins and shares them with port B:
•
PB7/SCK
•
PB6/SDI
•
PB5/SDO
Do not use the PB7/SCK, PB6/SDI, or PB5/SDO pins for
general-purpose I/O while the SIOP is enabled.
When bit 6 (SPE) of the SIOP control register (SCR) is set, the SIOP is
enabled and the PB7/SCK, PB5/SDO, and PB6/SDI pins are dedicated
to SIOP functions. Clearing SPE disables the SIOP and the SIOP pins
become standard I/O port pins.
NOTE:
PB7/SCK
Enabling and then disabling the SIOP configures the data direction
register bits associated with the SIOP pins for SIOP operation and can
also change the associated port data register. After disabling the SIOP,
initialize the data direction register and the port data register as the
application requires.
The PB7/SCK pin synchronizes the movement of data into and out of the
MCU through the PB6/SDI and PB5/SDO pins.
In master mode, the PB7/SCK pin is an output. The serial clock
frequency in master mode is one-fourth the internal clock frequency.
In slave mode, the PB7/SCK pin is an input. The maximum serial clock
frequency in slave mode is one-fourth the internal clock rate. Slave
mode has no minimum serial clock frequency.
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SIOP
Freescale Semiconductor, Inc...
Figure 61 shows the timing relationships among the serial clock, data
input, and data output. The state of the serial clock between
transmissions is a logic 1. The first falling edge on the PB7/SCK pin
signals the beginning of a transmission, and data appears at the
PB5/SDO pin. Data is captured at the PB6/SDI pin on the rising edge of
the serial clock, and the transmission ends on the eighth rising edge of
the serial clock.
SERIAL CLOCK
SAMPLE INPUT
DATA OUTPUT
(MSB-FIRST OPTION)
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
DATA OUTPUT
(LSB-FIRST OPTION)
LSB
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
MSB
Figure 61. SIOP Data/Clock Timing
PB5/SDO
The PB5/SDO pin is the SIOP data output. Between transfers, the state
of the PB5/SDO pin reflects the value of the last bit shifted out on the
previous transmission, if there was one. To preset the beginning state,
write to the corresponding port data bit before enabling the SIOP. On the
first falling edge on the PB7/SCK pin, the first data bit to be shifted out
appears at the PB5/SDO pin.
PB6/SDI
The PB6/SDI pin is the SIOP data input. Valid SDI data must be present
for an SDI setup time, tS, before the rising edge of the serial clock and
must remain valid for an SDI hold time, tH, after the rising edge of the
serial clock. (See Table 22 and Table 23.)
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SIOP
Operation
Freescale Semiconductor, Inc...
Data Movement
Connecting the SIOP data register of a master MCU with the SIOP of a
slave MCU forms a 16-bit circular shift register. During an SIOP transfer,
the master shifts out the contents of its SIOP data register on its
PB5/SDO pin. At the same time, the slave MCU shifts out the contents
of its SIOP data register on its PB5/SDO pin. Figure 62 shows how the
master and slave exchange the contents of their data registers.
SIOP SHIFT REGISTER
SDO
SDO
SDI
SDI
SIOP SHIFT REGISTER
SIOP IN
SLAVE MODE
SIOP IN
MASTER MODE
SCK
SCK
Figure 62. Master/Slave SIOP Shift Register Operation
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SIOP
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Freescale Semiconductor, Inc.
SIOP
Timing
tSCK
tSCKL
SCK
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tV
tHO
SDO
MSB
BIT 1
LSB
tH
tS
SDI
VALID
DATA
MSB
LSB
Figure 63. SIOP Timing
Table 22. SIOP Timing (VDD = 5.0 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Master
Slave
fSIOP(M)
fSIOP(S)
fOSC/8d
c
fOSC/8
fOSC/8
MHz
kHz
Cycle Time
Master
Slave
tSCK(M)
tSCK(S)
4.0
—
4.0
1920
tCYC(2)
ns
tSCKL
932
—
ns
SDO Data Valid Time
tV
—
200
ns
SDO Hold Time
tHO
0
—
ns
SDI Setup Time
tS
100
—
ns
SDI Hold Time
tH
100
—
ns
Clock (SCK) Low Time (fOP = 2.1 MHz)(3)(4)
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted.
2. tCYC = 1 ÷ fOP
3. fOSC = crystal frequency; fOP = fOSC ÷ 2 = 2.1 MHz maximum
4. In master mode, the frequency of SCK is fOP ÷ 4.
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SIOP
Interrupts
Table 23. SIOP Timing (VDD = 3.3 Vdc)(1)
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Master
Slave
fSIOP (M)
fSIOP(S)
fOSC/8
dc
fOSC/8
fOSC/8
MHz
kHz
Cycle Time
Master
Slave
tSCK(M)
tSCK(S)
4.0
—
4.0
4000
tCYC(2)
tSCKL
1980
—
ns
SDO Data Valid Time
tV
—
400
ns
SDO Hold Time
tHO
0
—
ns
SDI Setup Time
tS
200
—
ns
SDI Hold Time
tH
200
—
ns
Freescale Semiconductor, Inc...
Clock (SCK) Low Time (fOP = 1.0 MHz)(3) (4)
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted
2. tCYC = 1 ÷ fOP
3. fOSC = crystal frequency; fOP = fOSC ÷ 2 = 1.0 MHz maximum
4. In master mode, the frequency of SCK is fOP ÷ 4.
Interrupts
The SIOP does not generate interrupt requests.
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SIOP
I/O Registers
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The following registers control and monitor SIOP operation:
SIOP Control
Register
•
SIOP control register (SCR)
•
SIOP status register (SSR)
•
SIOP data register (SDR)
The read/write SIOP control register (SCR) contains two bits. One bit
enables the SIOP, and the other configures the SIOP for master mode
or for slave mode.
$000A
Bit 7
Read:
0
6
5
4
0
SPE
3
2
1
Bit 0
0
0
0
0
0
0
0
0
MSTR
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 64. SIOP Control Register (SCR)
SPE — SIOP Enable
This read/write bit enables the SIOP. Setting SPE initializes the data
direction register as follows:
•
The PB6/SDI pin is an input.
•
The PB5/SDO pin is an output.
•
The PB7/SCK pin is an input in slave mode and an output in
master mode.
Clearing SPE disables the SIOP and returns the port to its normal I/O
functions. The data direction register and the port data register remain
in their SIOP-initialized state.
NOTE:
After clearing SPE, be sure to initialize the port for its intended I/O use.
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SIOP
I/O Registers
Clearing SPE during a transmission aborts the transmission, resets
the bit counter, and returns the port to its normal I/O function. Reset
clears SPE.
1 = SIOP enabled
0 = SIOP disabled
MSTR — Master Mode Select
Freescale Semiconductor, Inc...
This read/write bit configures the SIOP for master mode. Setting
MSTR initializes the PB7/SCK pin as the serial clock output. Clearing
MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can
be set at any time regardless of the state of SPE. Reset clears MSTR.
1 = Master mode selected
0 = Slave mode selected
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SIOP
SIOP Status
Register
The read-only SIOP status register (SSR) contains two bits. One bit
indicates that a SIOP transfer is complete, and the other indicates that
an invalid access of the SIOP data register occurred while a transfer was
in progress.
$000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Freescale Semiconductor, Inc...
Reset:
= Unimplemented
Figure 65. SIOP Status Register (SSR)
SPIF — Serial Peripheral Interface Flag
This clearable, read-only bit is set automatically on the eighth rising
edge on the PB7/SCK pin and indicates that a data transmission took
place. SPIF does not inhibit further transmissions. Clear SPIF by
reading the SIOP status register while SPIF is set and then reading or
writing the SIOP data register. Reset clears SPIF.
1 = Transmission complete
0 = Transmission not complete
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SIOP
I/O Registers
DCOL — Data Collision Flag
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This clearable, read-only bit is automatically set if the SIOP data
register is accessed while a data transfer is in progress. Reading or
writing the SIOP data register while a transmission is in progress
causes invalid data to be transmitted or read. Clear DCOL by reading
the SIOP status register with SPIF set and then accessing the SIOP
data register. Because the clearing sequence accesses the SIOP
data register, the sequence has to be completed before another
transmission starts or DCOL is set again.
To clear DCOL when SPIF is not set, turn off the SIOP by writing a 0
to SPE and then turn it back on by writing a 1 to SPE. Reset clears
DCOL.
1 = Invalid access of SDR
0 = Valid access of SDR
SIOP Data Register
The SIOP data register (SDR) is both the transmit data register and the
receive data register. To read or write the SIOP data register, the SPE
bit in the SIOP control register must be set.
$000C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 66. SIOP Data Register (SDR)
With the SIOP configured for master mode, writing to the SIOP data
register initiates a serial transfer. This register is not buffered. Writing to
the SIOP data register overwrites the previous contents. Reading or
writing to the SIOP data register while a transmission is in progress can
cause invalid data to be transmitted or received.
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SIOP
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SIOP
Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
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Stop Mode
The STOP instruction suspends the clock to the SIOP. When the MCU
exits stop mode, processing resumes after the internal oscillator
stabilization delay of 4064 oscillator cycles.
A STOP instruction in a master SIOP does not suspend the clock to
slave SIOPs.
Wait Mode
The WAIT instruction suspends the clock to the SIOP. When the MCU
exits wait mode, processing resumes immediately.
A WAIT instruction in a master SIOP does not suspend the clock to slave
SIOPs.
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Analog-to-Digital Converter
ADC
Freescale Semiconductor, Inc...
Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
PC7/VRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
PC6/AN0–PC3/AN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Timing and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .121
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . .122
ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Features
•
8-Bit Conversions with ± 1.5-LSB Precision
•
Four External and Three Internal Analog Input Channels
•
Wait Mode Operation
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ADC
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ADC
Introduction
The ADC consists of a single successive-approximation A/D converter,
an input multiplexer to select one of four external or two internal
channels, and control circuitry. Figure 67 shows the structure of the
ADC module.
AN3
COMPARATOR
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AN2
INPUT
MULTIPLEXER
AN1
AN1
CH2
CH1
CH0
VSS
CCF
ADON
CONTROL
LOGIC
INTERNAL CLOCK
(XTAL ÷ 2)
ADRC
INTERNAL DATA BUS
DIGITALTO-ANALOG
CONVERTER
VRH
INTERNAL
RC
OSCILLATOR
Figure 67. ADC Block Diagram
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ADC
Operation
Table 24. ADC I/O Register Summary
Addr.
Name
R/W Bit 7
Read: Bit 7
Write:
Reset:
$001D ADC Data Register (ADDR)
Freescale Semiconductor, Inc...
$001E ADC Status/Control Register (ADSCR)
Read:
Write:
Reset:
CCF
0
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
CH2
CH1
CH0
0
0
0
Unaffected by reset
ADRC
ADON
0
0
0
0
0
0
= Unimplemented
Operation
The A/D conversion process is ratiometric, using two reference voltages,
VRH and VSS. Conversion accuracy is guaranteed only if VRH is equal to
VDD.
Pin Functions
PC7/VRH
The ADC uses five pins and shares them with port C:
•
PC7/VRH
•
PC6/AN0, PC5/AN1, PC4/AN2, and PC3/AN3
The voltage reference high pin (PC7/VRH) supplies the high reference
voltage for the ratiometric conversion process. For ratiometric
conversion, the supply voltage of the analog source should be the same
as VRH and be referenced to VSS.
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ADC
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PC6/AN0–
PC3/AN3
The multiplexer can select one of four external analog input channels
(AN0, AN1, AN2, or AN3) for sampling. The conversion takes 32 cycles.
The first 12 cycles sample the voltage on the selected input pin by
charging an internal capacitor. In the last 20 cycles, a comparator
successively compares the output of an internal D/A converter to the
sampled analog input. Control logic changes the D/A converter input one
bit at a time, starting with the MSB, until the D/A converter output
matches the sampled analog input. The conversion is monotonic and
has no missing codes. At the end of the conversion, the conversion
complete flag (CCF) becomes set, and the CPU takes two cycles to
move the result to the ADC data register.
NOTE:
To prevent excess power dissipation, do not simultaneously use an I/O
port pin as a digital input and an analog input.
While the ADC is on, the selected analog input reads as logic 0. The port
C pins that are not selected read normally.
An analog input voltage equal to VRH converts to digital $FF; an input
voltage greater than VRH converts to $FF with no overflow. An analog
input voltage less than VSS converts to digital $00. For ratiometric
conversion, the source of each analog input should use VRH as the
supply voltage and be referenced to VSS.
The clock frequency must be equal to or greater than 1 MHz. If the
internal clock frequency is less than 1MHz, the internal RC oscillator
(nominally 1.5 MHz) must be used for the ADC conversion clock. Make
this selection by setting the ADRC bit to logic 1 in the ADC status and
control register.
Interrupts
The ADC cannot generate interrupt requests.
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ADC
Timing and Electrical Characteristics
Timing and Electrical Characteristics
Table 25. ADC Characteristics (VDD = 5.0 Vdc)(1)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Resolution
—
8
8
Bit
Absolute Accuracy (4.0 > VRH > VDD)(2)
—
—
±1.5
LSB
Conversion Range (PC7/VRH)
—
VSS
VDD
V
Conversion Time (Includes Sampling Time)
External Clock
Internal RC Oscillator (ADRC = 1)
—
32
32
32
32
tAD(3)
µs
Monotonicity
—
Analog Input Voltage
VIN
VSS
VRH
V
Zero Input Reading (VIN = 0 V)
—
00
01
Hex
Full-Scale Reading (VIN = VRH)
—
FE
FF
Hex
Sample Acquisition Time(4)
External Clock
Internal RC Oscillator (ADRC = 1)
—
12
—
12
12
tAD(5)
µs
Input Capacitance
PC6/AN0, PC5/AN1, PC4/AN2, PC3/AN3
CIN
—
12
pF
Input Leakage(6)
PC6/AN0, PC5/AN1, PC4/AN2, PC3/AN3
PC7/VRH
—
—
—
±1
±1
µA
ADC On Current Stabilization Time
tADON
—
100
µs
ADC RC Stabilization Time (ADRC = 1)
tADRC
—
100
µs
Inherent (Within Total Error)
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc
2. ADC accuracy may decrease proportionately as VRH is reduced below 4.0 V.
3. tAD = cycle time of the A/D converter
4. Source impedances more than 10 kΩ adversely affect internal RC charging time during input
sampling.
5. tAD = tCYC (1 ÷ fOP) if MCU clock is clock source
6. External system error caused by input leakage approximately equals R source times input
current.
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ADC
I/O Registers
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The following registers control and monitor operation of the ADC:
ADC Status and
Control Register
•
ADC status and control register (ADSCR)
•
ADC data register (ADDR)
The ADC status and control register (ADSCR) contains a conversion
complete flag and four writable control bits. Writing to ADSCR clears the
conversion complete flag and starts a new conversion sequence.
$001E
Bit 7
Read:
CCF
6
5
ADRC
ADON
0
0
4
3
0
0
2
1
Bit 0
CH2
CH1
CH0
0
0
0
Write:
Reset:
0
0
0
= Unimplemented
Figure 68. ADC Status and Control Register (ADSCR)
CCF — Conversion Complete Flag
This read-only bit is automatically set when an analog-to-digital
conversion is complete, and a new result can be read from the ADC
data register. Clear the CCF bit by writing to the ADC status and
control register or by reading the ADC data register. Resets clear the
CCF bit.
1 = Conversion complete
0 = Conversion not complete
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ADC
I/O Registers
ADRC — ADC RC (Oscillator)
This read/write bit turns on the internal RC oscillator to drive the ADC.
If the internal clock frequency (fOP) is less than 1 MHz, ADRC must be
set. When the RC oscillator is turned on, it requires a time, tADRC, to
stabilize, and results can be inaccurate during this time. Resets clear
the ADRC bit.
1 = Internal RC oscillator drives ADC
0 = Internal clock drives ADC
Freescale Semiconductor, Inc...
When the internal RC oscillator is being used as the ADC clock, two
limitations apply:
•
Because of the frequency tolerance of the RC oscillator and its
asynchronism with the internal clock, the conversion complete flag
must be used to determine when a conversion sequence is
complete.
•
The conversion process runs at the nominal 1.5-MHz rate, but the
conversion results must be transferred to the ADC data register
synchronously with the internal clock; therefore, the conversion
process is limited to a maximum of one channel every internal
clock cycle.
ADON — ADC On
This read/write bit turns on the ADC. When the ADC is on, it requires
a time, tADON, for the current sources to stabilize. During this time,
results can be inaccurate. Resets clear the ADON bit.
1 = ADC turned on
0 = ADC turned off
Bits 4 and 3 — Not used
Bits 4 and 3 always read as logic 0s.
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ADC
CH[2:0] — Channel Select Bits
These read/write bits select one of eight ADC input channels as
shown in Table 26. Channels 0–3 are the input pins, PC3/AN3,
PC4/AN2, PC5/AN1, and PC6/AN0. Channels 4–6 can be used for
reference measurements. Channel 7 is reserved for factory testing.
Freescale Semiconductor, Inc...
Table 26. ADC Input Channel Selection
CH[2:1:0]
Channel
Signal
000
0
AN0
001
1
AN1
010
2
AN2
011
3
AN3
100
4
VRH (see Note 1)
101
5
(VRH + VSS) / 2
(see Note 1)
110
6
VSS (see Note 1)
111
7
Reserved
NOTE:
1. The accuracy of these measurements are
untested and not guaranteed.
To prevent excess power dissipation, do not use an ADC pin as an
analog input and a digital input at the same time.
Using one of the port pins as the ADC input does not affect the ability to
use the remaining port pins as digital inputs.
Reading a port pin that is selected as an analog input returns a logic 0.
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ADC
Low-Power Modes
ADC Data Register
The ADC data register (ADDR) is a read-only register that contains the
result of the most recent analog-to-digital conversion.
$001D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Freescale Semiconductor, Inc...
Reset:
Unaffected by reset
Figure 69. ADC Data Register (ADDR)
Low-Power Modes
Stop Mode
The STOP instruction turns off the ADC and aborts any current and
pending conversions.
Wait Mode
The ADC continues to operate normally after the WAIT instruction. To
reduce power consumption in wait mode:
•
If the ADC is not being used, clear both the ADON and ADRC bits
before entering wait mode.
•
If the ADC is being used and the internal clock rate is above
1 MHz, clear the ADRC bit before entering wait mode.
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Freescale Semiconductor, Inc...
ADC
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ADC
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Specifications
Contents
Freescale Semiconductor, Inc...
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
5.0 V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .130
3.3 V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .131
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Typical Supply Current vs. Internal Clock Frequency . . . . . . . . . . . .135
Maximum Supply Current vs. Internal Clock Frequency . . . . . . . . . .136
5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
3.3 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
28-Pin PDIP — Case #710 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
28-Pin SOIC — Case #751F . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
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Specifications
Maximum Ratings
Freescale Semiconductor, Inc...
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in Table 27. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Table 27. Maximum Ratings
Rating
Symbol
Value
Unit
VDD
–0.3 to +7.0
V
I
25
mA
Input Voltage
VIN
VSS – 0.3 to VDD + 0.3
V
EPROM Programming Voltage
VPP
16.75
V
Storage Temperature Range
TSTG
–65 to +150
°C
Supply Voltage
Current Drain per Pin
(Excluding VDD and VSS)
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 5.0 V DC Electrical Characteristics on page 130 and
3.3 V DC Electrical Characteristics on page 132 for guaranteed
operating conditions.
Operating Temperature Range
Table 28. Operating Temperature Range
Package Type
Symbol
Value
Unit
TA
0 to 70
–40 to +85
–40 to +105
–40 to +125
°C
MC68HC05P9P(1), DW(2) (Standard)
MC68HC05P9C(3)P, CDW (Extended)
MC68HC05P9V(4)P, VDW (Automotive)
MC68HC05P9M(5)P, MDW (Automotive)
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
3. C = Extended temperature range (–40 to +85 °C)
4. V = Automotive temperature range (–40 to +105 °C)
5. M = Automotive temperature range (–40 to +125 °C)
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Specifications
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Specifications
Thermal Characteristics
Thermal Characteristics
Table 29. Thermal Characteristics
Characteristic
Symbol
Value
Unit
θJA
60
60
°C/W
Freescale Semiconductor, Inc...
Thermal Resistance
Plastic Dual In-Line Package (PDIP)
Small Outline Integrated Circuit (SOIC)
Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
T J = T A + (P D × θ JA )
(1)
where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O
PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
P D = ---------------------------------T J + 273 °C
Solving equations (1) and (2) for K gives:
K = PD × ( TA + 273 °C) + θ JA × ( PD )2
(2)
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
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Specifications
5.0 V DC Electrical Characteristics
Table 30. DC Electrical Characteristics (VDD = 5.0 Vdc)(1)
Symbol
Min
Typ(2)
Max
Unit
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output High Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC2, PD5,
TCMP (ILoad = –0.8 mA)
PC1–PC0 (ILoad = –5.0 mA)
VOH
VDD – 0.8
—
—
V
Output Low Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC2, PD5,
TCMP (ILoad = 1.6 mA)
PC1–PC0 (ILoad = 10 mA)
VOL
—
—
0.4
V
Input High Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
PD7/TCAP, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input Low Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
PD7/TCAP, IRQ, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
—
4.0
2.0
1.3
7.0
4.0
2.0
mA
mA
mA
—
—
—
2
—
—
30
50
100
µA
µA
µA
Characteristic
Freescale Semiconductor, Inc...
Output Voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Supply Current(3) (4) (5)
Run Mode
Wait Mode (ADC On)
Wait Mode (ADC Off)
Stop Mode
25 °C
0 to 70 °C (Standard)
–40 to 125 °C
IDD
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5
IIL
—
—
±10
µA
ADC Ports Hi-Z Leakage Current
IOZ
—
—
±1
µA
Input Current
RESET, IRQ, OSC1, PD7/TCAP
IIN
—
—
±1
µA
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Specifications
5.0 V DC Electrical Characteristics
Table 30. DC Electrical Characteristics (VDD = 5.0 Vdc)(1) (Continued)
Symbol
Min
Typ(2)
Max
Unit
Input Pullup Current(6)
PA7–PA0 with Pullup Enabled)
IINPU
175
385
750
µA
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ
COUT
CIN
—
—
—
—
12
8
pF
Freescale Semiconductor, Inc...
Characteristic
1. VDD = 5.0 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all
other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected
linearly by the OSC2 capacitance.
5. Stop mode IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V,
VIH = VDD –0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
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Specifications
3.3 V DC Electrical Characteristics
Table 31. DC Electrical Characteristics (VDD = 3.3 Vdc)(1)
Symbol
Min
Typ(2)
Max
Unit
Output Voltage (ILOAD ≤ 10.0 µA)
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output High Voltage (ILOAD = –0.2 mA)
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC2, PD5,
TCMP (ILoad = –0.2 mA)
PC1–PC0 (ILoad = 1.2 mA)
VOH
VDD – 0.3
—
—
V
Output Low Voltage (ILOAD = 0.4 mA)
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC2, PD5,
TCMP (ILoad = 0.4 mA)
PC1–PC0 (ILoad = 2.5 mA)
VOL
—
—
0.3
V
Input High Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
PD7/TCAP, IRQ, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input Low Voltage
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5,
PD7/TCAP, IRQ, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
Data-Retention Mode Supply Voltage
VRM
2.0
—
—
V
—
—
—
1.3
1.0
0.6
2.5
1.4
1.0
mA
mA
mA
—
—
—
2.0
—
—
20
40
50
µA
µA
µA
Freescale Semiconductor, Inc...
Characteristic
Supply Current(3) (4) (5)
Run Mode
Wait Mode (ADC On)
Wait Mode (ADC Off)
Stop Mode
25 °C
0 to 70 °C (Standard)
–40 to 125 °C
IDD
I/O Ports Hi-Z Leakage Current
PA7–PA0, PB7/SCK–PB5/SDO, PC7/VRH–PC0, PD5
IIL
—
—
±10
µA
Input Current
RESET, IRQ, OSC1, PD7/TCAP
IIN
—
—
±1
µA
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Specifications
3.3 V DC Electrical Characteristics
Table 31. DC Electrical Characteristics (VDD = 3.3 Vdc)(1) (Continued)
Symbol
Min
Typ(2)
Max
Unit
Input Pullup Current(6)
PA7–PA0 with Pullup Enabled)
IINPU
75
175
350
µA
Capacitance
Ports (As Inputs or Outputs)
RESET, IRQ
COUT
CIN
—
—
—
—
12
8
pF
Freescale Semiconductor, Inc...
Characteristic
1. VDD = 3.3 Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25 °C only
3. Run (operating) IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all
other inputs VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source; all I/O pins configured as inputs, port B = VDD, all other inputs
VIL = 0.2 V, VIH = VDD –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. Wait IDD is affected linearly
by the OSC2 capacitance.
5. Stop mode IDD measured with OSC1 = 0.2 V; all I/O pins configured as inputs, port B = VDD, all other inputs VIL = 0.2 V,
VIH = VDD –0.2 V.
6. Input pullup current measured with VIL = 0.2 V.
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Specifications
Driver Characteristics
VDD = 5.0 V
VDD = 3.3 V
0.8
0.8
0.7
0.6
0.6
VDD – VOH (V)
Freescale Semiconductor, Inc...
VDD – VOH (V)
(NOTE 2)
0.7
0.5
0.4
0.3
0.5
0.4
(NOTE 3)
0.3
0.2
0.2
0.1
0.1
0
0
0
–1.0
–2.0
–3.0
–4.0
–5.0
0
–1.0
–2.0
IOH (mA)
–3.0
–4.0
–5.0
IOH (mA)
NOTES:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V versus I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 800 mV @ IOL = –0.8 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = –0.2 mA.
Figure 70. Typical High-Side Driver Characteristics
VDD = 5.0 V
VDD = 3.3 V
0.40
0.40
0.35
0.30
0.30
0.25
0.25
VOL (V)
VOL (V)
(NOTE 2)
0.35
0.20
0.15
0.20
0.15
0.10
0.10
0.05
0.05
0
(NOTE 3)
0
0
2.0
4.0
6.0
8.0
10.0
0
2.0
4.0
IOL (mA)
6.0
8.0
10.0
IOL (mA)
NOTES:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V versus I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 1.6 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 0.4 mA.
Figure 71. Typical Low-Side Driver Characteristics
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Specifications
Typical Supply Current vs. Internal Clock Frequency
Typical Supply Current vs. Internal Clock Frequency
5.0
RUN MODE
25 °C
5.5 V
4.0
SUPPLY CURRENT (mA)
3.6 V
3.0
3.0 V
2.0
1.0
0
0.5
0
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
2.0
1.2
1.0
WAIT MODE
25 °C
ADC OFF
5.5 V
0.8
4.5 V
1.0
RUN MODE
25 °C
ADC ON
5.5 V
0.5
4.5 V
SUPPLY CURRENT (mA)
1.5
SUPPLY CURRENT (mA)
Freescale Semiconductor, Inc...
4.5 V
3.6 V
3.6 V
3.0 V
0.6
0.4
0.2
3.0 V
0
0
0
0.5
1.0
1.5
INTERNAL CLOCK FREQUENCY (MHz)
2.0
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 72. Typical Supply Current vs. Internal Clock Frequency
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Maximum Supply Current vs. Internal Clock Frequency
7.0
2.5
VDD = 5 V ±10%
–40 to +125 °C
6.0
Run Mode
Run Mode
2.0
Wait Mode (ADC On)
Wait Mode (ADC Off)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
Wait Mode (ADC On)
Wait Mode (ADC Off)
5.0
Freescale Semiconductor, Inc...
VDD = 3.3 V ±10%
–40 to +125 °C
4.0
3.0
2.0
1.5
1.0
0.5
1.0
0
0
0
0.5
1.0
1.5
INTERNAL CLOCK FREQUENCY (MHz)
2.0
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 73. Maximum Supply Current vs. Internal Clock Frequency
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Specifications
5.0 V Control Timing
5.0 V Control Timing
Table 32. Control Timing (VDD = 5.0 Vdc)(1)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fOSC
—
dc
4.2
4.2
MHz
Internal Operating Frequency (fOSC ÷ 2)
Crystal
External Clock
fOP
—
dc
2.1
2.1
MHz
Cycle Time (1 ÷ fOP)
tCYC
480
—
ns
Crystal Oscillator Startup Time
tOXOV
—
100
ms
Stop Recovery Startup Time (Crystal
Oscillator)
tILCH
—
100
ms
tRL
1.5
—
tCYC
Timer
Resolution(2)
Input Capture Pulse Width
Input Capture Pulse Period
tRESL
tH, tL
tTLTL
4.0
125
Note(3)
—
—
—
tCYC
ns
tCYC
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note(4)
—
tCYC
tOH, tOL
90
—
ns
RC Oscillator Stabilization Time
tRCON
—
5
µs
ADC On Current Stabilization Time
tADON
—
100
µs
RESET Pulse Width
OSC1 Pulse Width
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted
2. A 2-bit prescaler in the timer is the limiting factor as it counts 4 tCYC
3. The minimum tTLTL should not be less than the number of interrupt service routine cycles
plus 19 tCYC
4. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tCYC
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Specifications
3.3 V Control Timing
Table 33. Control Timing (VDD = 3.3 Vdc)(1)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal
External Clock
fOSC
—
dc
2.0
2.0
MHz
Internal Operating Frequency (fOSC ÷ 2)
Crystal
External Clock
fOP
—
dc
1.0
1.0
MHz
Cycle Time (1 ÷ fOP)
tCYC
1
—
ms
Crystal Oscillator Startup Time
tOXOV
—
100
ms
Stop Recovery Startup Time (Crystal
Oscillator)
tILCH
—
100
ms
tRL
1.5
—
tCYC
Timer
Resolution(2)
Input Capture Pulse Width
Input Capture Pulse Period
tRESL
tH, tL
tTLTL
4.0
250
Note(3)
—
—
—
tCYC
ns
tCYC
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
Interrupt Pulse Period
tILIL
Note(4)
—
tCYC
tOH, tOL
200
—
ns
RESET Pulse Width
OSC1 Pulse Width
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH unless otherwise noted
2. A 2-bit prescaler in the timer is the limiting factor as it counts 4 tCYC
3. The minimum tTLTL should not be less than the number of interrupt service routine cycles
plus 19 tCYC
4. The minimum tILIL should not be less than the number of interrupt service routine cycles
plus 19 tCYC
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Specifications
Test Load
Test Load
VDD
PINS
R2
R2
C
3.26 kΩ
2.38 kΩ
50 pF
PA7–PA0
TEST POINT
PB7/SCK–PB5/SDO
C
Freescale Semiconductor, Inc...
R1
R1
PC7/VRH–PC0
Figure 74. Test Load
Mechanical Specifications
The MC68HC05P9A is available in the following packages:
•
710 — Plastic dual in-line package (PDIP)
•
751F — Small outline integrated circuit (SOIC)
The following figures show the latest packages at the time of this
publication. To make sure that you have the latest package
specifications, contact one of the following:
•
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
•
Worldwide Web (wwweb) at http://design-net.com
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
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Specifications
28-Pin PDIP —
Case #710
28
! ! ! #! %% !
$" ! ! ! ! ! !
! ! # ! "
15
B
1
14
Freescale Semiconductor, Inc...
A
L
C
N
H
G
M
K
D
F
J
°
°
°
°
28-Pin SOIC —
Case #751F
-A28
! ! % ! !
! " !" $" !" ! "
!" #
!" !! $ ! $" !
!
15
14X
-B1
P
14
28X D
!
M
R X 45°
C
-T26X
-T-
G
K
F
J
°
°
°
°
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Index
Freescale Semiconductor, Inc...
A
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 37
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 117
ADC (analog-to-digital converter)
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
ADC data register (ADDR) . . . . . . . . . . . . . . . . . . . 120, 122–123, 125
ADC status and control register (ADSCR) . . . . . . . . . . . . . . . 120, 122
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ADON bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, 125
ADRC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 123, 125
alternate timer registers (ATRH/L) . . . . . . . . . . . . . . . . . . . . . . . . . . 99
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AN[3:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
B
brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 80
bypass capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Freescale Semiconductor, Inc...
C
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
case outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 140
CCF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 122
central processor unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ceramic resonator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CH[2:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
computer operating properly watchdog . . . . . . . . . . . . . . . . . . . . . . 79
condition code register (CCR) . . . . . . . . . . 30, 39, 53, 55–56, 98–101
COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
COP register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 81
COP watchdog
COP in halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
COP in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
COP in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
COP register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
COP watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 80–81
COPC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 81, 83
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27–28
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28, 30
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
instructions set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 34, 37, 41, 56
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 37
condition code register (CCR) . . . . . . . . 30, 39, 53, 55–56, 98–101
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34–37
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . 36, 39, 50, 56
stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
142
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MOTOROLA
Freescale Semiconductor, Inc.
Index
crystal
AT-cut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
strip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
tuning fork . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
16
16
Freescale Semiconductor, Inc...
D
data direction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, 112
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . 18, 68
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . 18, 71
data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 18, 74
data direction register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 18, 77
DCOL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DDRA[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DDRB[7:5] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DDRC[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DDRD5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
E
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.3 V DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 132
5.0 V DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 130
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137–138
current versus internal clock frequency . . . . . . . . . . . . . . . 135–136
driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
electrostatic damage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 53–54, 82, 102
external interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51, 82, 102
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Index
H
halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
halt instruction flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Freescale Semiconductor, Inc...
I
I bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53, 55–56, 98–101
I/O bits
ADON bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123, 125
ADRC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 123, 125
AN[3:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
CCF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 122
CH[2:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
COPC bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 81, 83
DCOL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DDRA[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DDRB[7:5] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DDRC[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DDRD5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53, 55–56, 98–101
ICF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94, 97, 100, 102
ICIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94–95
IEDG bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
MSTR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
OCF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94, 97, 101
OCIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94–95
OLVL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, 96
PA[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
PB[7:5] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PC[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, 112, 115
SPIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
TOF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56, 94, 97–99
TOIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56, 94–95
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Freescale Semiconductor, Inc...
I/O pins
IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 53
IRQ/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PB5/SDO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, 112
PB6/SDI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, 112
PB7/SCK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, 112
PC3/AN0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PC3/AN3 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119
PC4/AN2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119, 124
PC5/AN1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119, 124
PC6/AN0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119, 124
PC7/VRH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , 119
PD7/TCAP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 89, 96–97
RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 50–52
TCMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 89–90, 96, 101
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
I/O port pin termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
I/O registers
ADC data register (ADDR) . . . . . . . . . . . . . . . . 120, 122–123, 125
ADC status and control register (ADSCR) . . . . . . . . . . . . 120, 122
alternate timer registers (ATRH/L) . . . . . . . . . . . . . . . . . . . . . . . 99
COP register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 81
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 68
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 71
data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . 74
data direction register D (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . 77
input capture registers (ICRH/ICRL) . . . . . . . . . . . . . . . . . . . . . . 89
input capture registers (ICRH/L) . . . . . . . . . . . . . . 96–97, 100, 102
output compare registers (OCRH/L) . . . . . . . . . . . . . . . 96–97, 101
output compare registers (OCRH/OCRL) . . . . . . . . . . . . . . . . . . 90
port A data register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
port B data register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
port C data register (PORTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
port D data register (PORTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SIOP control register (SCR) . . . . . . . . . . . . . . . . . . . 107, 112, 115
SIOP data register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . 114–115
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Freescale Semiconductor, Inc...
SIOP status register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . 55–56, 95
timer registers (TRH/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96–98
timer status register (TSR) . . . . . . . . . . . . . . . 55–56, 96, 100–101
ICF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94, 97, 100, 102
ICIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94–95
IEDG bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34–37
input capture interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
input capture registers (ICRH/L) . . . . . . . . . . . . . . 89, 96–97, 100, 102
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 123
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54–55
interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . 57
software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
introduction, MC68HC05P9A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
IRQ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 53
IRQ/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
146
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MOTOROLA
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Index
J
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Freescale Semiconductor, Inc...
L
literature updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
low voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
ADC in stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
COP in stop, halt, and wait modes . . . . . . . . . . . . . . . . . . . . . . . 82
HALT instruction flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SIOP in stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . 116
STOP instruction flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
STOP/WAIT clock logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
timer in stop and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . 102
WAIT instruction flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
M
mask options
COP watchdog enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SIOP data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
mask selectable options
COP watchdog enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . 12
external interrupt pin enable/disable . . . . . . . . . . . . . . . . . . . . . . 12
keyscan pullups/interrupts on port A enable/disable . . . . . . . . . . 12
SIOP data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STOP instruction enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . 12
mechanical specifications
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
parallel I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ROM security feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MSTR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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147
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N
noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15, 17
Freescale Semiconductor, Inc...
O
OCF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94, 97, 101
OCIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94–95
OLVL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, 96
on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
stabilization delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50, 82, 116
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
output compare interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 90
output compare registers (OCRH/L) . . . . . . . . . . . . . . . 90, 96–97, 101
P
PA[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
package dimensions
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
parallel I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PB[7:5] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
PB5/SDO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, 112
PB6/SDI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, 112
PB7/SCK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71, 107–108, 112
PB7SCK pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
PC[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PC3/AN3 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119, 124
PC4/AN2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119, 124
PC5/AN1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119, 124
148
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Index
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PC6/AN0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119, 124
PC7/VRH pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 119
PD5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PD7 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
PD7/TCAP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 89, 96–97
pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 67
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 68
port A data register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
port A I/O pin interrupts/pullups . . . . . . . . . . . . . . . . . . . . . . . . . . 70
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 70
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 71
port B data register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 73
data direction register C (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . 74
high current sink/source capability . . . . . . . . . . . . . . . . . . . . . . . 75
PC0–PC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
port C data register (PORTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 76
data direction register D (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . 77
port D data register (PORTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
parallel I/O port register summary . . . . . . . . . . . . . . . . . . . . . . . . 66
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124, 129
power supply (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36, 39, 50, 56
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149
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R
Freescale Semiconductor, Inc...
RAM
locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
registers
ADC I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
parallel I/O port register summary . . . . . . . . . . . . . . . . . . . . . . . . 66
parallel I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
SIOP I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
timer I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17, 50–52
reset sources
COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49–50
COP watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 80
COP watchdog reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . 80
external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
low-voltage protection reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
power-on reset (POR) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . 57
resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
S
self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
serial input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
SIOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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Freescale Semiconductor, Inc...
SIOP (serial input/output port)
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110–111
SIOP control register (SCR) . . . . . . . . . . . . . . . . . . . . . . 107, 112, 115
SIOP data register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114–115
SIOP status register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
software failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
software interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SPE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, 112, 115
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
See "electrical specifications." . . . . . . . . . . . . . . . . . . . . . . . . . 128
See "mechanical specifications." . . . . . . . . . . . . . . . . . . . . . . . 139
SPIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
stack RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24, 56
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
effect on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
effect on capture/compare timer . . . . . . . . . . . . . . . . . . . . . . . . 102
effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
effect on SIOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
STOP instruction flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
stop recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
STOP/WAIT clock logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
supply voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80, 128
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T
TCMP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18, 89–90, 96, 101
thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55, 94
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89, 99
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91–93
timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . 55–56, 95
timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
timer registers (TRH/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96–98
timer resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
timer status register (TSR) . . . . . . . . . . . . . . . . . . 55–56, 96, 100–101
TOF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56, 94, 97–99
TOIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56, 94–95
V
VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VSS pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
W
wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
effect on ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
effect on capture/compare timer . . . . . . . . . . . . . . . . . . . . . . . . 102
effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
effect on SIOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
STOP/WAIT clock logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
WAIT instruction flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
152
Index
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