MCP79410/MCP79411/MCP79412
I2C™ Real-Time Clock/Calendar with EEPROM, SRAM,
Unique ID and Battery Switchover
Device Selection Table
Description:
Part
Number
EEPROM
(Kbits)
SRAM
(Bytes)
MCP79410
1K
64
Blank
MCP79411
1K
64
EUI-48™
MCP79412
1K
64
EUI-64™
Unique ID
Features:
• Real-Time Clock/Calendar (RTCC), Battery
Backed:
- Hours, Minutes, Seconds, Day of Week, Day,
Month and Year
- Dual alarm with single output
• On-Chip Digital Trimming/Calibration:
- Range -127 to +127 ppm
- Resolution 1 ppm
• Programmable Open-Drain Output Control:
- CLKOUT with 4 selectable frequencies
- Alarm output
• 64 Bytes SRAM, Battery Backed
• 1 Kbits EEPROM (128x8):
- 8 bytes/page
- Block/sector write protection
- Protect none, 1/4, 1/2 or all of array
• Separate 64-Bit Unique ID:
- User or factory programmable
- Protected area
- EUI-48™ or EUI-64™ MAC address
- Custom ID programming
• Automatic VCC Switchover to VBAT Backup
Supply
• Power-Fail Time-Stamp for Battery Switchover
• Low-Power CMOS Technology:
- Dynamic Current: 400 A max read
- Dynamic Current: 3mA max EEPROM write
- Battery Backup Current: <700nA @ 1.8V
• 100 kHz and 400 kHz Compatibility
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Packages include 8-Lead SOIC, TSSOP, 2x3
TDFN, MSOP
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C.
2011 Microchip Technology Inc.
The MCP7941X series of low-power Real-Time Clocks
(RTC) uses digital timing compensation for an accurate
clock/calendar, a programmable output control for
versatility, a power sense circuit that automatically
switches to the backup supply, and nonvolatile memory
for data storage. Using a low-cost 32.768 kHz crystal,
it tracks time using several internal registers. For
communication, the MCP7941X uses the I2C™ bus.
The clock/calendar automatically adjusts for months
with fewer than 31 days, including corrections for
leap years. The clock operates in either the 24-hour
or 12-hour format with an AM/PM indicator and
settable alarm(s) to the second, minute, hour, day of
the week, date or month. Using the programmable
CLKOUT, frequencies of 32.768, 8.192 and 4.096
kHz and 1 Hz can be generated from the external
crystal.
Along with the on-board Serial EEPROM and batterybacked SRAM memory, a 64-bit protected space is
available for a unique ID or MAC address to be
programmed at the factory or by the end user.
The device is fully accessible through the serial
interface while VCC is between 1.8V and 5.5V, but can
operate down to 1.3V for timekeeping and SRAM
retention only.
The RTC series of devices are available in the standard
8-lead SOIC, TSSOP, MSOP and 2x3 TDFN packages.
Package Types
MSOP
X1
1
8
VCC
X2
2
7
MFP
VBAT
3
6
SCL
VSS
4
5
SDA
TDFN
X1 1
X2 2
VBAT 3
VSS 4
SOIC, TSSOP
Preliminary
X1
1
8
VCC
X2
2
7
MFP
VBAT
3
6
SCL
VSS
4
5
SDA
8 VCC
7 MFP
6 SCL
5 SDA
DS22266B-page 1
MCP7941X
FIGURE 1-1:
TYPICAL OPERATING
CIRCUIT
RTCC
Oscillator
X1
Time-Stamp/
Alarms
VCC
SRAM
X2
VBAT
MFP
VBAT Switch
VSS
DS22266B-page 2
EEPROM
I2C™
ID
SCL
SDA
Preliminary
2011 Microchip Technology Inc.
MCP7941X
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
Min.
Typ.
Max.
Units
TA = -40°C to +85°C
Conditions
—
SCL, SDA pins
—
—
—
—
D1
VIH
High-level input voltage
0.7 VCC
—
V
—
D2
VIL
Low-level input voltage
—
0.3 VCC
0.2 VCC
V
VCC = 2.5V to 5.5V
D3
VHYS
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05
VCC
—
V
(Note 1)
D4
VOL
Low-level output voltage
(MFP, SDA)
—
0.40
V
IOL = 3.0 ma @ VCC = 4.5V
IOL = 2.1 ma @ VCC = 2.5V
D5
ILI
Input leakage current
—
±1
A
VIN = VSS or VCC
D6
ILO
Output leakage current
—
±1
A
VOUT = VSS or VCC
D7
CIN,
COUT
Pin capacitance
(SDA, SCL and MFP)
—
10
pF
VCC = 5.0V (Note 1)
TA = 25°C, f = 400 kHz
D8
ICC Read Operating current
ICC Write EEPROM
—
400
A
VCC = 5.5V, SCL = 400 kHz
—
3
mA
VCC = 5.5V
ICC Read Operating current
ICC Write SRAM
—
300
A
VCC = 5.5V, SCL = 400 kHz
—
400
A
VCC = 5.5V, SCL = 400 kHz
D9
5
A
VCC = 5.5V, SCL = SDA = VCC
—
nA
VBAT = 1.8V @ 25°C
1.7
V
1.5V typical at TAMB = 25°C
D10
ICCS
Standby current (Note 2)
—
D11
IBAT
VBAT Standby Current
(Note 2)
—
D12
VTRIP
VBAT Change Over
1.3
D13
VCCFT
VCC Fall Time (Note 1)
300
s
From VTRIP (max) to VTRIP (min)
D14
VCCRT
VCC Rise Time (Note 1)
0
s
From VTRIP (min) to VTRIP (max)
D15
VBAT
VBAT Voltage Range
(Note 1)
V
—
Note 1:
2:
700
1.3
5.5
This parameter is periodically sampled and not 100% tested.
Standby with oscillator running
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 3
MCP7941X
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
TA = -40°C to +85°C
Conditions
1
FCLK
Clock frequency
—
—
100
400
kHz
1.8V VCC < 2.5V
2.5V VCC 5.5V
2
THIGH
Clock high time
4000
600
—
—
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
3
TLOW
Clock low time
4700
1300
—
—
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
4
TR
SDA and SCL rise time
(Note 1)
—
—
1000
300
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
5
TF
SDA and SCL fall time
(Note 1)
—
—
1000
300
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
6
THD:STA Start condition hold time
4000
600
—
—
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
7
TSU:STA
4700
600
—
—
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
Start condition setup time
8
THD:DAT Data input hold time
0
—
ns
9
TSU:DAT
Data input setup time
250
100
—
—
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
10
TSU:STO
Stop condition setup time
4000
600
—
—
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
11
TAA
Output valid from clock
—
—
3500
900
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
12
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
—
—
ns
1.8V VCC < 2.5V
2.5V VCC 5.5V
13
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
(Note 1 and Note 2)
14
TWC
Write cycle time (byte or
page)
—
5
ms
—
15
—
Endurance
1M
—
cycles
25°C, VCC = 5.5V Page mode
(Note 3)
Note 1: Not 100% tested.
2: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
DS22266B-page 4
Preliminary
2011 Microchip Technology Inc.
MCP7941X
FIGURE 1-2:
BUS TIMING DATA
5
SCL
7
SDA
In
D4
2
3
8
9
4
10
6
13
11
12
SDA
Out
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 5
MCP7941X
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
FIGURE 2-1:
DEVICE PINOUTS
SOIC/DFN/MSOP/TSSOP
2.1
X1
1
8
Vcc
X2
2
7
MFP
VBAT
3
6
SCL
Vss
4
5
SDA
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to VCC (typically 10 k for 100 kHz, 2 k for
400 kHz). For normal data transfer SDA is allowed to
change only during SCL low. Changes during SCL high
are reserved for indicating the Start and Stop
conditions.
2.2
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
TABLE 2-1:
PIN DESCRIPTIONS
Pin Name
Vss
SDA
SCL
X1
X2
VBAT
MFP
Vcc
Pin Function
Ground
Bidirectional Serial Data
Serial Clock
Xtal Input, External Oscillator Input
Xtal Output
Battery Backup Input (3V Typ)
Multi Function Pin
+1.8V to +5.5V Power Supply
DS22266B-page 6
Preliminary
2011 Microchip Technology Inc.
MCP7941X
3.0
I2C BUS CHARACTERISTICS
3.1.1.4
3.1
I2C Interface
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The MCP7941X supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the Start and Stop
conditions, while the MCP7941X works as slave. Both
master and slave can operate as transmitter or receiver
but the master device determines which mode is
activated.
3.1.1
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
3.1.1.5
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Bus not Busy (A)
Both data and clock lines remain high.
3.1.1.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.1.3
Stop Data Transfer (C)
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
Note:
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1.1.1
Data Valid (D)
The MCP7941X does not generate any
EEPROM Acknowledge bits if an internal
programming cycle is in progress. The
user may still access the SRAM and RTCC
registers during an EEPROM write.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (MCP7941X) will leave the data line high to
enable the master to generate the Stop condition.
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must end with a Stop condition.
FIGURE 3-1:
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
(D)
Start
Condition
Address or
Acknowledge
Valid
(C)
(A)
SCL
SDA
2011 Microchip Technology Inc.
Data
Allowed
to Change
Preliminary
Stop
Condition
DS22266B-page 7
MCP7941X
FIGURE 3-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
1
SCL
2
3
SDA
4
5
6
7
8
9
1
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
DEVICE ADDRESSING AND OPERATION
selected. The next byte received defines the address of
the data byte (Figure 3-3). The upper address bits are
transferred first, followed by the Least Significant bits
(LSb).
A control byte is the first byte received following the
Start condition from the master device (Figure 3-2).
The control byte consists of a control code; for the
MCP7941X this is set as ‘1010111’ for read and write
operations for the EEPROM.
Following the Start condition, the MCP7941X monitors
the SDA bus, checking the device type identifier being
transmitted. Upon receiving an ‘1010111’ or
‘1101111’ code, the slave device outputs an
Acknowledge signal on the SDA line. Depending on the
state of the R/W bit, the MCP7941X will select a read
or write operation.
The control byte for accessing the SRAM and RTCC
registers are set to ‘1101111’. The RTCC registers and
the SRAM share the same address space.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
FIGURE 3-3:
3
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
3.1.2
2
ADDRESS SEQUENCE BIT ASSIGNMENTS
EEPROM CONTROL BYTE
1
0
1
0
1
1
ADDRESS BYTE
1 R/W
CONTROL
CODE
X
•
•
•
•
•
A
0
•
{“A7” is “Don’t Care” for normal EEPROM
operations, but is used to access unique ID
location and STATUS register.)
X = Don’t Care
SRAM RTCC CONTROL BYTE
1
1
0
1
1
1
1 R/W
ADDRESS BYTE
X
•
•
•
•
•
•
A
0
CONTROL
CODE
X = Don’t Care
DS22266B-page 8
Preliminary
2011 Microchip Technology Inc.
MCP7941X
3.1.3
ACKNOWLEDGE POLLING
Since the device will not acknowledge an EEPROM
command during an EEPROM write cycle, this can be
used to determine when the cycle is complete. This
feature can be used to maximize bus throughput. Once
the Stop condition for a write command has been
issued from the master, the device initiates the
internally timed write cycle. ACK polling can be initiated
immediately. This involves the master sending a Start
condition, followed by the control byte for a write
command (R/W = 0). If the device is still busy with the
write cycle, then no ACK will be returned. If no ACK is
returned, then the Start bit and control byte must be
resent. If the cycle is complete, then the device will
return the ACK, and the master can then proceed with
the next read or write command. See Figure 3-4 for the
flow diagram.
FIGURE 3-4:
ACKNOWLEDGE
POLLING FLOW
Send
EE Write Command
Send Stop
Condition to
Initiate EE Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 9
MCP7941X
4.0
RTCC FUNCTIONALITY
The MCP7941x family is a highly integrated RTCC. Onboard time and date counters are driven from a lowpower oscillator to maintain the time and date. An
integrated VCC switch enables the device to maintain
the time and date and also the contents of the SRAM
during a VCC power failure.
4.1
RTCC MEMORY MAP
The RTCC registers are contained in addresses
0x00h-0x1fh. 64 bytes of user-accessable SRAM are
located in the address range 0x20-0x5f. The SRAM
memory is a separate block from the RTCC control
and Configuration registers. All SRAM locations are
battery-backed-up during a VCC power fail. Unused
locations are not accessible, MCP7941X will noACK
after the address byte if the address is out of range.
The shaded areas are not implemented and read as
‘0’. No error checking is provided when loading time
and date registers.
• Addresses 0x00h-0x06h are the RTCC Time and
Date registers. These are read/write registers.
Care must be taken when writing to these registers with the oscillator running.
• Incorrect data can appear in the Time and Date
registers if a write is attempted during the time
frame where these internal registers are being
incremented. The user can minimize the likelihood of data corruption by ensuring that any
writes to the Time and Date registers occur before
the contents of the second register reach a value
of 0x59H.
• Addresses 0x07h-0x09h are the device Configuration, Calibration and ID Unlock registers.
• Addresses 0x0Ah-0x10h are the Alarm 0 registers. These are used to set up the Alarm 0, the
Interrupt polarity and the Alarm 0 Compare.
• Addresses 0x11h-0x17h are the same as 0x0Bh0x11h but are used for Alarm 1.
• Addresses 0x18h-0x1Fh are used for the timestamp feature.
The Memory Map is shown in Table 4-1.
DS22266B-page 10
Preliminary
2011 Microchip Technology Inc.
MCP7941X
TABLE 4-1:
Address
00h
Bit 7
RTCC MEMORY MAP
Bit 6
ST
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Function
Range
Reset
State
10 Seconds
Seconds
Seconds
00-59
00h
01h
10 Minutes
Minutes
Minutes
00-59
00h
02h
10 Hour
AM/PM
10 Hour
Hours
1-12 + AM/PM
00 - 23
00h
OSCON
VBAT
Day
1-7
01h
Date
01-31
01h
Month
01-12
01h
Year
00-99
12/24
03h
VBATEN
Day
10 Date
04h
LP
05h
06h
07h
Hour
Date
10 Month
Month
10 Year
OUT
SQWE
Year
ALM1
ALM0
EXTOSC RS2
RS1
RS0
01h
Control Reg.
80h
08h
CALIBRATION
Calibration
00h
09h
UNIQUE UNLOCK ID SEQUENCE
Unlock ID
00h
0Ah
10 Seconds
Seconds
Seconds
00-59
00h
0Bh
10 Minutes
Minutes
Minutes
00 - 59
00h
Hours
1-12 + AM/PM
00-23
00h
01h
0Ch
0Dh
ALM0POL
10 Hour
AM/PM
10 Hours
12/24
ALM0C2
ALM0C1
ALM0C0
0Eh
Hour
ALM0IF
10 Date
Day
Date
0Fh
10 Month
10h
Reserved – Do not use
Month
Day
1-7
Date
01-31
01h
Month
01-12
01h
Reserved
01h
11h
10 Seconds
Seconds
Seconds
00-59
00h
12h
10 Minutes
Minutes
Minutes
00-59
00h
Hours
1-12 + AM/PM
00-23
00h
01h
13h
14h
ALM1POL
10 Hour
AM/PM
10 Hours
12/24
ALM1C2
ALM1C1
ALM1C0
15h
Month
Reserved - Do not use
18h
10 Minutes
19h
10 Hour
AM/PM
12/24
1Ah
10 Hours
10 Date
Day
10 Month
10 Minutes
1Dh
12/24
1Eh
1Fh
Day
Date
10 Month
17h
1Ch
ALM1IF
10 Date
16h
1Bh
Hour
10 Hour
AM/PM
10 Hours
10 Date
Day
2011 Microchip Technology Inc.
10 Month
Day
1-7
Date
01-31
01h
Month
01-12
01h
Reserved
01h
Minutes
00h
Hour
00h
Date
00h
Month
00h
Minutes
00h
Hour
00h
Date
00h
Month
00h
Preliminary
DS22266B-page 11
MCP7941X
4.1.1
RTCC REGISTER ADDRESSES
0x00h – Contains the BCD seconds and 10 seconds.
The range is 00 to 59. Bit 7 in this register is used to
start or stop the on-board crystal oscillator. Setting this
bit to a ‘1’ starts the oscillator and clearing this bit to a
‘0’ stops the on-board oscillator.
0x01h – Contains the BCD minutes and 10 minutes.
The range is 00 to 59.
0x02h – Contains the BCD hour in bits 3:0. Bits 5:4
contain either the 10 hour in BCD for 24-hour format or
the AM/PM indicator and the 10-hour bit for 12-hour
format. Bit 6 determines the hour format. Setting this
bit to ‘0’ enables 24-hour format, setting this bit to ‘1’
enables 12-hour format.
0x03h – Contains the BCD day. The range is 1-7.
Additional bits are also used for configuration and
status.
• Bit 3 is the VBATEN bit. If this bit is set, the
internal circuitry is connected to the VBAT pin
when VCC fails. If this bit is ‘0’ then the VBAT pin is
disconnected and the only current drain on the
external battery is the VBAT pin leakage.
• Bit 4 is the VBAT bit. This bit is set by hardware
when the VCC fails and the VBAT is used to power
the Oscillator and the RTCC registers. This bit is
cleared by software. Clearing this bit will also
clear all the time-stamp registers.
• Bit 5 is the OSCON bit. This is set and cleared by
hardware. If this bit is set, the oscillator is running,
if cleared, the oscillator is not running. This bit
does not indicate that the oscillator is running at
the correct frequency. The RTCC will wait 32
oscillator cycles before the bit is set. The RTCC
will wait roughly 32 clock cycles to clear this bit.
0x04h – Contains the BCD date and 10 date. The
range is 01-31.
0x05h – Contains the BCD month. Bit 4 contains the
10 month. Bit 5 is the Leap Year bit, which is set during
a leap year and is read-only.
0x06h – Contains the BCD year and 10 year. The
Range is 00-99.
0x07h – Is the Control register.
• Bit 7 is the OUT bit. This sets the logic level on the
MFP when not using this as a square wave output.
• Bit 6 is the SQWE bit. Setting this bit enables the
divided output from the crystal oscillator.
• Bits 5:4 determine which alarms are active.
- 00 – No Alarms are active
- 01 – Alarm 0 is active
- 10 – Alarm 1 is active
- 11 – Both Alarms are active
DS22266B-page 12
• Bit 3 is the EXTOSC enable bit. Setting this bit will
allow an external 32.768 kHz signal to drive the
RTCC registers eliminating the need for an
external crystal.
• Bit 2:0 sets the internal divider for the 32.768 kHz
oscillator to be driven to the MFP. The duty cycle is
50%. The output is responsive to the Calibration
register. The following frequencies are available:
- 000 – 1 Hz
- 001 – 4.096 kHz
- 010 – 8.192 kHz
- 011 – 32.768 kHz
- 1xx enables the Cal output function. Cal
output appears on MFP if SQWE is set (64
Hz Nominal).
Note:
The RTCC counters will continue to
increment during the calibration.
0x08h is the Calibration register. This is an 8-bit
register that is used to add or subtract clocks from the
RTCC counter every minute. The MSB is the sign bit
and indicates if the count should be added or
subtracted. The remaining 7 bits, with each bit adding
or subtracting 2 clocks, give the user the ability to add
or subtract up to 254 clocks per minute.
0x09h is the unlock sequence address. To unlock write
access to the unique ID area in the EEPROM, a
sequence must be written to this address in separate
commands. The process is fully detailed in
Section 4.2.2 “Unlock Sequence”.
0x0Ah-0x0fh and 0x11-0x16h are the Alarm 0 and
Alarm 1 registers. The bits are the same as the RTCC
bits with the following differences:
Locations 0x10h and 0x17h are reserved and should
not be used to allow for future device compatibility.
0x0Dh/0x14h has additional bits for alarm configuration.
• ALMxPOL: This bit specifies the level that the
MFP will drive when the alarm is triggered.
ALM2POL is a copy of ALM1POL. The default
state of the MFP when used for alarms is the
inverse of ALM1POL.
• ALMxIF: This is the Alarm Interrupt Fag. This bit is
set in hardware if the alarm was triggered. The bit
is cleared in software.
Preliminary
2011 Microchip Technology Inc.
MCP7941X
4.2
• ALMxC2:0: These Configuration bits determine
the alarm match. The logic will trigger the alarm
based on one of the following match conditions:
4.2.1
000
–
Seconds match
001
–
Minutes match
010
–
Hours match (takes into account 12/24
hour)
011
–
Matches the current day, interrupt at
12.00.00 a.m. Example: 12 midnight on
100
– Date
101
– RESERVED
110
– RESERVED
111
– Seconds, Minutes, Hour, Day, Date,
Month
• The 12/24-hour bits 0xCh.6 and 0x13h.6 are copies of the bit in 0x02h.6. The bits are read-only.
0x18h-0x1Bh are used for the timesaver function.
These registers are loaded at the time when VCC fails
and the RTCC operates on the VBAT. The VBAT bit is
also set at this time. These registers are cleared when
the VBAT bit is cleared in software.
0x1Ch-0x1Fh are used for the timesaver function.
These registers are loaded at the time when VCC is
restored and the RTCC switches to VDD. These
registers are cleared when the VBAT bit is cleared in
software.
Note:
It is strongly recommended that the
timesaver function only be used when the
oscillator is running. This will ensure
accurate functionality.
FEATURES
STATUS REGISTER
The STATUS register is in the nonvolatile EEPROM
array. To access the STATUS register, the address of
0xFFh is written to and read from. ACK polling may be
used to determine if the write is complete. The bits in
this register are defined as:
• Bit 3:2 are the EEPROM array block protection
bits. These bits are in the nonvolatile EEPROM
array. This allows protection of the following
areas:
- 00 – None of the array is protected.
- 01 – The upper 1/4 of the array 0x60h-0x7fh
is protected.
- 10 – The upper 1/2 of the array 0x40h-0x7fh
is protected.
- 11 – All of the array 0x00-0x7fh is protected.
• The unused bits are reserved at this time and
read as ‘0’.
• With the current address read operation, the
address is not incremented. Consequently, the
subsequent reads are done from the same
location.
If multiple bytes are loaded to the STATUS register,
only the last byte is written.
4.2.2
UNLOCK SEQUENCE
The unique ID location is user accessible by using the
unlock ID sequence.
The unique ID location is 64-bits (8 bytes) and is
stored in EEPROM locations 0xF0 to 0xF7. This
location can be read at any time, however, a write is
inhibited until unlocked.
To unlock the write access to this location the following
sequence must be completed:
• A single write of 0x55h to address 0x09. Stop
• A single write of 0xAAh to address 0x09. Stop
This will allow the unique EEPROM locations to be
written.
After the byte or page write to these locations, the
write sequence is initiated by the Stop condition. At
this time, the ID locations are locked and no further
writes are possible to this location unless a complete
unlock sequence is repeated.
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 13
MCP7941X
4.2.3
CALIBRATION
The MCP7941X utilizes digital calibration to correct for
inaccuracies of the input clock source (either external
or crystal). Calibration is enabled by setting the value
of the Calibration register at address 08H. Calibration
is achieved by adding or subtracting a number of input
clock cycles per minute in order to achieve ppm level
adjustments in the internal timing function of the
MCP7941X.
RS2
RS1
RS0
Output Signal
0
0
0
0
0
0
1
1
0
1
0
1
32768
8
4
1
With regards to the calibration function, the Calibration
register setting has no impact upon the MFP output
clock signal when bits RS1 and RS0 are set to ‘11’.
The setting of the Calibration register to a non-zero
value (i.e., values other than 00H or 80H) enables the
calibration function which can be observed on the
MFP output pin. The calibration function can be
expressed in terms of the number of input clock cycles
added/subtracted from the internal timing function.
The MSB of the Calibration register is the sign bit, with
a ‘1’ indicating subtraction and a ‘0’ indicating addition.
The remaining seven bits in the register indicate the
number of input clock cycles (multiplied by two) that
are subtracted or added per minute to the internal
timing function.
The internal timing function can be monitored using
the MFP open-drain output pin by setting bit [6]
(SQWE) and bits [2:0] (RS2, RS1, RS0) of the control
register at address 07H. Note that the MFP output
waveform is disabled when the MCP7941X is running
in VBAT mode. With the SQWE bit set to ‘1’, there are
two methods that can be used to observe the internal
timing function of the MCP7941X:
With bits RS1 and RS0 set to ‘00’, the calibration
function can be expressed as:
Toutput
=
(32768 +/- (2 * CALREG)) Tinput
Toutput
=
clock period of MFP output signal
Tinput
=
clock period of input signal
CALREG
=
decimal value of Calibration
register setting and the sign is
determined by the MSB of
Calibration register.
where:
A. RS2 BIT SET TO ‘0’
With the RS2 bit set to ‘0’, the RS1 and RS0 bits
enable the following internal timing signals to be
output on the MFP pin:
RS2
RS1
RS0
Output Signal
0
0
0
0
0
0
1
1
0
1
0
1
1 Hz
4.096 kHz
8.192 kHz
32.768 kHz
Since the calibration is done once per minute (i.e.,
when the internal minute counter is incremented), only
one cycle in sixty of the MFP output waveform is
affected by the calibration setting. Also note that the
duty cycle of the MFP output waveform will not
necessarily be at 50% when the calibration setting is
applied.
With bits RS1 and RS0 set to ‘01’ or ‘10’, the
calibration function can not be expressed in terms of
the input clock period. In the case where the MSB of
the Calibration register is set to ‘0’, the waveform
appearing at the MFP output pin will be “delayed”,
once per minute, by twice the number of input clock
cycles defined in the Calibration register. The MFP
waveform will appear as:
The frequencies listed in the table presume an input
clock source of exactly 32.768 kHz. In terms of the
equivalent number of input clock cycles, the table
becomes:
FIGURE 4-1:
RS1 AND RS0 WITH AND WITHOUT CALIBRATION
Delay
DS22266B-page 14
Preliminary
2011 Microchip Technology Inc.
MCP7941X
In the case where the MSB of the Calibration register
is set to ‘1’, the MFP output waveforms that appear
when bits RS1 and RS0 are set to ‘01’ or ‘10’ are not
as responsive to the setting of the Calibration register.
For example, when outputting the 4.096 kHz
waveform (RS1, RS0 set to ‘01’), the output waveform
is generated using only eight input clock cycles.
Consequently, attempting to subtract more than eight
input clock cycles from this output does not have a
meaningful effect on the resulting waveform. Any
effect on the output will appear as a modification in
both the frequency and duty cycle of the waveform
appearing on the MFP output pin.
B.RS2 BIT SET TO ‘1’
RS2
RS1
RS0
Output Signal
1
x
x
64.0 Hz
The frequency listed in the table presumes an input
clock source of exactly 32.768 kHz. In terms of the
equivalent number of input clock cycles, the table
becomes:
RS2
RS1
RS0
Output Signal
1
x
x
512
MFP
Pin 7 is a multi-function pin and supports the following
functions:
• Use of the OUT bit in the Control register for
single bit I/O
• Alarm Outputs – Available in VBAT mode
• FOUT mode – driven from a FOSC divider – Not
available in VBAT mode
The internal control logic for the MFP is connected to
the switched internal supply bus, this allows operation
in VBAT mode. The Alarm Output is the only mode that
operates in VBAT mode, other modes are suspended.
4.2.5
With the RS2 bit set to ‘1’, the following internal timing
signal is output on the MFP pin:
VBAT
If the VBAT feature is not being used, the VBAT pin
should be connected to GND. A low-value series
resistor is recommended between the external battery
and the VBAT pin.
The VBAT point is defined as 1.5V typical. When VDD
falls below 1.5V the system will continue to operate
the RTCC and SRAM using the VBAT supply. The
following conditions apply:
TABLE 4-2:
Unlike the method previously described, the
calibration setting is continuously applied and affects
every cycle of the output waveform. This results in the
modulation of the frequency of the output waveform
based upon the setting of the Calibration register.
Using this setting, the calibration function can be
expressed as:
=
(2 * (256 +/- (2 * CALREG))) Tinput
Toutput
=
clock period of MFP output signal
Tinput
=
clock period of input signal
CALREG
=
decimal value of the Calibration
register setting, and the sign is
determined by the MSB of the
Calibration register.
Toutput
4.2.4
where:
Supply
Condition
Read/Write
Access
Powered
By
VCC < VTRIP, VCC < VBAT
VCC > VTRIP, VCC < VBAT
VCC > VTRIP, VCC > VBAT
No
Yes
Yes
VBAT
VCC
VCC
4.2.6
CRYSTAL SPECS
The MCP7941X has been designed to operate with a
standard 32 kHz crystal. Devices with a specified load
capacitance of either 12pF or 6pF can be used. The
end user should fully validate the chosen crystal across
all the expected design parameters of the system to
ensure correct operation.
The following crystals have been tested and shown to
work with the MCP7941X:
Since the calibration is done every cycle, the frequency
of the output MFP waveform is constant.
• CM200S 12pF surface mount crystals from
Citizen
• ECS-.327 12pF surface mount crystals from ECS
INC
• CFS206 12pF leaded crystals from Citizen
This is not a definitive list and all crystals should be
tested in the target application across all temperature,
voltage and other significant environmental conditions.
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 15
MCP7941X
4.2.7
POWER-FAIL TIME-STAMP
The MCP7941X family of RTCC devices feature a
power-fail time-stamp feature. This feature will save
the time at which VCC crosses the VTRIP voltage. To
use this feature, a VBAT supply must be present and
the oscillator must also be running.
There are two separate sets of registers that are used
to record this information:
• The first set located at 0x18h through 0x1Bh are
loaded at the time when VCC fails and the RTCC
operates on the VBAT. The VBAT (register 0x03h
bit 4) bit is also set at this time.
• The second set of registers, located at 0x1Ch
through 0x1Fh, are loaded at the time when VCC
is restored and the RTCC switches to VCC.
The power-fail time-stamp registers are cleared when
the VBAT bit is cleared in software.
DS22266B-page 16
Preliminary
2011 Microchip Technology Inc.
MCP7941X
5.0
ON BOARD MEMORY
The MCP7941X has both on-board EEPROM memory
and Battery-Backed SRAM. The SRAM is arranged as
64 x 8 bytes and is retained when the VCC supply is
removed, provided the VBAT supply is present and
enabled. The EEPROM is organized as 128 x 8 bytes.
The EEPROM is nonvolatile memory and does not
require the VBAT supply for retention.
5.1
SRAM
FIGURE 5-1:
SRAM/RTCC BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
S1 1 01111 0
S
T
O
P
DATA
x
P
A
C
K
BUS ACTIVITY
FIGURE 5-2:
ADDRESS
BYTE
A
C
K
A
C
K
SRAM/RTCC MULTIPLE BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
P
A
C
K
A
C
K
The 64 bytes of user SRAM are at location 0x20h and
can be accessed during an RTCC update. Upon POR
the SRAM will be in an undefined state.
Writing to the SRAM and RTCC is accomplished in a
similar way to writing to the EEPROM (as described
later in this document) with the following considerations:
• There is no page. The entire 64 bytes of SRAM or
32 bytes of RTCC register can be written in one
command.
• The SRAM allows an unlimited number of read/
write cycles with no cell wear out.
• The RTCC and SRAM are not accessible when
the device is running on the external VBAT.
• The RTCC and SRAM are separate blocks. The
SRAM array may be accessed during an RTCC
update.
2011 Microchip Technology Inc.
DATA BYTE N
x
S11 0 11110
BUS ACTIVITY
DATA BYTE 0
S
T
O
P
A
C
K
A
C
K
• Read and write access is limited to either the
RTCC register block or the SRAM array. The
Address Pointer will rollover to the start of the
addressed block.
• Data written to the RTCC and SRAM are on a per
byte basis.
Note:
Preliminary
Entering an address past 5F for an SRAM
operation will result in the MCP7941X not
acknowledging the address.
DS22266B-page 17
MCP7941X
5.2
5.2.1
EEPROM
EEPROM BYTE WRITE
Following the Start condition from the master, the
control code and the R/W bit (which is a logic low) are
clocked onto the bus by the master transmitter. This
indicates to the addressed slave receiver that a byte
with a word address will follow after it has generated an
Acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the master is
the word address and will be written into the Address
Pointer of the MCP7941X. After receiving another
Acknowledge signal from the MCP7941X, the master
device transmits the data word to be written into the
addressed memory location. The MCP7941X
acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle, and,
during this time, the MCP7941X does not generate
Acknowledge signals for EEPROM write commands. If
an attempt is made to write to an address and the
protection is set then the device will acknowledge the
command but no write cycle will occur, no data will be
written, and the device will immediately accept a new
command. After a byte write command, the internal
address counter will point to the address location
following the one that was just written.
5.2.2
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being
transmitted.
Physical
page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and end at addresses that are
integer multiples of [page size - 1]. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Note:
Addressing undefined EEPROM locations
will result in the MCP7941X not
acknowledging the address.
EEPROM PAGE WRITE
The write control byte, word address, and the first data
byte are transmitted to the MCP7941X in the same way
as in a byte write. But instead of generating a Stop
condition, the master transmits up to 7 additional bytes,
which are temporarily stored in the on-chip page buffer
and will be written into memory after the master has
transmitted a Stop condition. After receipt of each word,
the three lower Address Pointer bits are internally
incremented by one. If the master should transmit more
than 8 bytes prior to generating the Stop condition, the
address counter will roll over and the data received
previously will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 5-4).
DS22266B-page 18
Preliminary
2011 Microchip Technology Inc.
MCP7941X
FIGURE 5-3:
EE BYTE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
S1 0 10111 0
ADDRESS
BYTE
DATA
x
P
A
C
K
x = don’t care for 1K devices
A
C
K
BUS ACTIVITY
FIGURE 5-4:
S
T
O
P
A
C
K
EE PAGE WRITE
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
ADDRESS
BYTE
DATA BYTE 7
DATA BYTE 0
x
S10 1 01110
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
S
T
O
P
A
C
K
x = don’t care for 1K devices
5.2.3
FIGURE 5-1:
BLOCK PROTECTION
The EEPROM does not support a hardware write
protection pin, however, software block protection is
available to the use and is configured using the
STATUS register.
5.2.4
READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read. The SRAM array can be read in
the same way as the EEPROM using the control byte
for the SRAM ‘1101111’ with a valid address.
5.2.4.1
Current Address Read
The MCP7941X contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n (n is any legal
address), the next current address read operation
would access data from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the MCP7941X issues an Acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a Stop condition and the
MCP7941X discontinues transmission (Figure 5-1).
2011 Microchip Technology Inc.
CURRENT ADDRESS READ
(EEPROM SHOWN)
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S 1 0 1 0 1 1 1 1
CONTROL
BYTE
BUS ACTIVITY
5.2.4.2
S
T
O
P
DATA
BYTE
P
A
C
K
N
O
A
C
K
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
MCP7941X as part of a write operation (R/W bit set to
‘0’). After the word address is sent, the master
generates a Start condition following the Acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again but with the R/W bit set to a one.
The MCP7941X will then issue an Acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer but it does generate a Stop
condition which causes the MCP7941X to discontinue
transmission (Figure 5-2). After a random read
command, the internal address counter will point to the
address location following the one that was just read.
Preliminary
DS22266B-page 19
MCP7941X
5.2.4.3
Sequential Read
master, the master will NOT generate an Acknowledge
but will generate a Stop condition. To provide
sequential reads, the MCP7941X contains an internal
Address Pointer which is incremented by one at the
completion of each operation. This Address Pointer
allows the entire memory contents to be serially read
during one operation. The internal Address Pointer will
automatically roll over to the start of the Block.
Sequential reads are initiated in the same way as a
random read except that after the MCP7941X transmits
the first data byte, the master issues an Acknowledge
as opposed to the Stop condition used in a random
read. This Acknowledge directs the MCP7941X to
transmit the next sequentially addressed 8-bit word
(Figure 5-3). Following the final byte transmitted to the
FIGURE 5-2:
RANDOM READ (EEPROM SHOWN)
BUS ACTIVITY
MASTER
SDA LINE
S
T
A
R
T
CONTROL
BYTE
S1 0 1 0 1 1 1 0
CONTROL
BYTE
S1 0 1 0
A
C
K
BUS ACTIVITY
FIGURE 5-3:
S
T
A
R
T
ADDRESS
BYTE
P
1
A
C
K
N
O
A
C
K
A
C
K
SEQUENTIAL READ (EEPROM SHOWN)
BUS ACTIVITY
MASTER
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
BUS ACTIVITY
S
T
O
P
DATA n + X
P
SDA LINE
5.3
S
T
O
P
DATA
BYTE
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Unique ID
The MCP7941X features an additional 64-bit unique ID
area. This is separate and in addition to the 1K of onboard EEPROM.
The unique ID is located at addresses 0xF0 through
0xF7. Reading the unique ID requires the user to
simply address these bytes.
The unique ID area is protected to prevent unintended
writes to these locations. The unlock sequence is
detailed in 4.2.2 “Unlock Sequence”.
The unique ID can be factory programmed on some
devices to provide a unique IEEE EUI-48 or EUI-64
value. In addition, customer-provided codes can also
be programmed.
DS22266B-page 20
Preliminary
2011 Microchip Technology Inc.
MCP7941X
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead SOIC (3.90 mm)
Example:
XXXXXT
XXYYWW
NNN
79410I
SN e3 0527
13F
Example:
8-Lead TSSOP
XXXX
7941
TYWW
I527
NNN
13F
Example:
8-Lead MSOP
XXXXX
79401I
YWWNNN
52713F
8-Lead 2x3 TDFN
Example:
XXX
YWW
NN
AC4
527
13
1st Line Marking Codes
Part Number
TSSOP
MSOP
MCP79410
7941
79410T
AAP
MCP79411
9411
79411T
AAQ
MCP79412
9412
79412T
AAR
Note:
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
TDFN
T = Temperature grade
NN = Alphanumeric traceability code
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 21
MCP7941X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22266B-page 22
Preliminary
2011 Microchip Technology Inc.
MCP7941X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 23
MCP7941X
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Preliminary
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MCP7941X
Note:
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http://www.microchip.com/packaging
DS22266B-page 26
Preliminary
2011 Microchip Technology Inc.
MCP7941X
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DS22266B-page 27
MCP7941X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22266B-page 28
Preliminary
2011 Microchip Technology Inc.
MCP7941X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 29
MCP7941X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22266B-page 30
Preliminary
2011 Microchip Technology Inc.
MCP7941X
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2011 Microchip Technology Inc.
Preliminary
DS22266B-page 31
MCP7941X
APPENDIX A:
REVISION HISTORY
Revision A (10/2010)
Original release of this document.
APPENDIX B:
DEVICE ERRATA
Devices with silicon revision prior to A4 (date code prior
to 11/10) have an errata where the AM/PM bit (Bit 5 in
register 02h) may be flipped if the oscillator is stopped.
This is coincident with the OSCON bit getting cleared.
Revision B (03/2011)
This can occur due to the following conditions:
Minor typographical edits;
• The oscillator is stopped on the application.
• The oscillator is stopped by clearing the ST bit (Bit
7 in register 00h).
• The external CMOS source is stopped in
EXTOSC mode.
Added Appendix B: Device Errata
The work-around is to determine when the OSCON bit
is cleared and check in software for AM/PM bit corruption.
Devices with silicon revision A4 or later (date code after
11/09) do not have this issue.
DS22266B-page 32
Preliminary
2011 Microchip Technology Inc.
MCP7941X
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 33
MCP7941X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
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RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: MCP7941X
Literature Number: DS22266B
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS22266B-page 34
Preliminary
2011 Microchip Technology Inc.
MCP7941X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering
combination is listed below.
X
PART NO.
Device
Device:
/XX
Examples:
Temperature Package
Range
MCP79410 =
MCP79410T =
MCP79411 =
MCP79411T =
MCP79412 =
MCP79412T =
1.8V - 5.5V I2C™ Serial RTCC
1.8V - 5.5V I2C Serial RTCC
1.8V - 5.5V I2C Serial RTCC, EUI-48TM
1.8V - 5.5V I2C Serial RTCC, EUI-48TM
(Tape and Reel)
1.8V - 5.5V I2C Serial RTCC, EUI-64TM
1.8V - 5.5V I2C Serial RTCC, EUI-64TM
(Tape and Reel)
Temperature
Range:
I
=
-40°C to +85°C
Package:
SN
ST
=
=
8-Lead Plastic Small Outline (3.90 mm body)
8-Lead Plastic Thin Shrink Small Outline
(4.4 mm)
8-Lead Plastic Micro Small Outline
8-Lead Plastic Dual Flat, No Lead
MS
=
MNY(1) =
a)
MCP79410-I/SN: Industrial
ture, SOIC package.
Tempera-
b)
MCP79410T-I/SN: Industrial Temperature, SOIC package, Tape and Reel.
c)
MCP79410T-I/MNY: Industrial Temperature, TDFN package, Tape and Reel.
d)
MCP79411-I/SN: Industrial Temperature,
SOIC package, EUI-48TM.
e)
MCP79411-I/MS: Industrial Temperature
MSOP package, EUI-48TM.
f)
MCP79412-I/SN: Industrial Temperature, SOIC package, EUI-64TM.
g)
MCP79412-I/ST: Industrial Temperature,
TSSOP package, EUI-64TM.
h)
MCP79412T-I/ST: Industrial Temperature,
TSSOP package, Tape and Reel, EUI-64TM.
Note 1: ’Y’ indicates a Nickel Palladium Gold (NiPdAu) finish.
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 35
MCP7941X
NOTES:
DS22266B-page 36
Preliminary
2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-980-8
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2011 Microchip Technology Inc.
Preliminary
DS22266B-page 37
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
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Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
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Tel: 91-11-4160-8631
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02/18/11
DS22266B-page 38
Preliminary
2011 Microchip Technology Inc.