MITSUBISHI <Standard Linear IC> M62352AGP 8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS DESCRIPTION M62352A is a CMOS structured semiconductor integrated ciruict integrating 12 channels of built-in D-A converters with high performance buffer operational amplifierf or each channel output. 3-wire serial interface (DI,CLK,LD) method is used for the taransfer format of digital data to allow connection with microcomputer with minimum wiring Do terminal is provided to allow cascading serial use. Built-in buffer operational amplifiers are designed to operate or full-swing in the whole voltage range from Vcc to GND for each input/output. And their higher stability for capacitive load perfectly fits in to the use for electronic volume (VCA) or the replacement for semi-variable resistor for tuning. Pin configuration(Top View) FEATURES 12 bit serial data input (3 wire serial data transfer method, DI, CLK, LD) Corresponds to TTL input for digital input (VINH ≥ 2V, VINL ≤ 0.8V) R-2R + segment method high performance 12 channel 8 bit D-A converters 12ch buffer operational amplifiers opperating in the whole voltage range from Vcc to GND Buffer operational amplifiers with high oscillation stability for capacitive load VSS 1 AO3 2 AO4 3 AO5 4 AO6 5 AO7 6 AO8 7 AO9 8 AO10 9 VDD 10 20 19 18 17 16 15 14 13 12 11 GND AO2 AO1 DI CLK LD DO AO12 AO11 VCC Outline 20P2E-A APPLICATION Adjustment or control of industrial or home-use electronic equipments such as VTR camera, VTR set, TV, and CRT display. 20 19 18 17 16 15 D0 8bit R-2R + segment D-A converter 14 13 12 11 10 11 D-A L (12) ch3 4 5 6 7 8 9 10 8bit R-2R +segment D-A converter ( 1 / 6) 0107 MITSUBISHI <Standard Linear IC> M62352AGP 8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS EXPLANATION OF TERMINALS Pin No. symbol Function Serial data input terminal.12bit serial data is input to this terminal. 17 DI 14 DO Serial data output terminal.Serial data of 12bit shift register is output from this terminal. 16 CLK Serial clock input terminal.Input signal from DI terminal is input to 12bit shift register upon the rise of shift clock. 15 LD 18 AO1 AO2 19 2 Data is loaded to register when 'H' is input to LD terminal. AO3 AO4 3 4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 5 6 7 8 9 12 13 11 8bit D-A converter output terminal. Built-in buffer amp.is connected to VCC. D-A converted voltage between VDD and VSS is output to each terminal. 20 VCC GND Power supply terminal. 10 VDD Digital and Analog common GND D-A converter High level reference voltage input terminal. 1 VSS D-A converter Low level reference voltage input terminal. BLOCK DIAGRAM FOR EXPLANATION OF TERMINALS VCC GND 11 20 DI 17 CLK 12 BIT SHIFT REGISTER 16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 14 DO D11 15 LD DECODER (8) (12) 1 2 3 4 5 6 7 8 9 10 11 12 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit Latch 8bit D-A converter 8bit D-A converter 8bit D-A converter 8bit D-A converter 8bit D-A converter 8bit D-A converter A1 10 18 VDD AO1 A4 19 AO2 A5 A10 2 9 AO3 AO10 ( 2 / 6) A11 12 AO11 A12 13 AO12 1 VSS 0107 MITSUBISHI <Standard Linear IC> M62352AGP 8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS DIGITAL DATA FORMAT Last LSB First MSB D0 D1 D2 D3 D4 D5 D6 D7 DAC DATA D8 D9 D10 D11 DAC SELECT DATA DAC DATA D0 D1 D2 D3 D4 D5 D6 D7 D-A output 0 0 0 0 0 0 0 0 (VrefU-VrefL)/256 x 1+VrefL[V] (1LSB) 1 0 0 0 0 0 0 0 (VrefU-VrefL)/256 x 2+VrefL[V] (2LSB) 0 1 0 0 0 0 0 0 (VrefU-VrefL)/256 x 3+VrefL[V] (3LSB) 1 1 0 0 0 0 1 0 (VrefU-VrefL)/256 x 4+VrefL[V] (3LSB) : : : : : : : : 0 1 1 1 1 1 1 1 (VrefU-VrefL)/256 x 255+VrefL[V] (255LSB) 1 1 1 1 1 1 1 1 VrefU[V] (256LSB) : VrefU=VDD VrefL=VSS DAC SELECT DATA D8 D9 D10 D11 DAC SELECTION 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don't Care A1select A2select A3select A4select A5select A6select A7select A8select A9select A10select A11select A12select Don't Care Don't Care Don't Care TIMING CHART (model) CLK SI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LD AO1~ AO12 ( 3 / 6) 0107 MITSUBISHI <Standard Linear IC> M62352AGP 8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS ABSOLUTE MAXMUM RATING Symbol Vcc VDD VIN Vout Pd Topr Tstg Parameter Conditions Ratings Unit Supply voltage D-A converter High levelreference voltage - 0.3 ~ 7.0 V - 0.3 ~ 7.0 V Digital input voltage - 0.3 ~ VCC+0.3 V Output voltage - 0.3 ~ VCC+0.3 V Power dissipation Operating temperature 150 - 20 ~ 85 mW °C Storage temperature - 40 ~ 125 °C ELECTRIC CHARACTERISTICS <Digital part> (VCC, VrefU=5V ± 10% , VCC ≥ VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85 ºC unless otherwise specified.) Symbol Parameter Ratings Conditions Vcc Supply voltage Icc Supply current CLK=1MHz Operation IILK Input leak current VIN=0 ~ VCC VIL VIH Digital input Low voltage 4.5 V CC =5V, IAO =0 A Digital output Low voltage Digital output High voltage Unit TYP MAX 5.0 5.5 V 1.5 3.5 mA 10 A 0.8 V V 0.4 V -10 2.0 Digital input High voltage VOL VOH MIN IOL = 2.5mA IOH= - 400 A VCC -0.4 V Note: Changes from M62352GP: Digital input voltage corresponds to TTL spec. <Analog Part> (VCC, VrefU=5V ± 10% , VCC ≥ VrefU, GND, VrefL=0.0V, Ta=-20 ~ + 85 ºC unless otherwise specified.) Symbol Parameter Reference voltage pin current D-A converter High level VDD(V refU ) reference voltage range D-A converter Low level VSS (V refL ) reference voltage range IrefU VAO IAO SDL SL Szero SFULL Co Ro Buffer amplifier output drive range Buffer amplifier output drive range Differential nonlinearity Nonlinearity Zero code error Full scale error Conditions MIN Ratings TYP MAX Unit 1.4 2.5 mA VrefU =5V,VrefL =0V,IAO=0 A Data condition: at Maxmum Current The output does not necessarily be the Values within the reference voltage setting range.The output value is determined by the buffer amplifier output voltage range(VAO). IAO = ± 100 A IAO = ± 500 A Upper side saturation voltage=0.3V Lower side saturation voltage=0.2V VrefU = 4.79V VrefL = 0.95V (15mV/LSB) VCC = 5.5V without load(I AO=+0 A) 3.5 VCC GND VCC -3.5 0.1 VCC-0.1 0.2 VCC-0.2 V 1 mA LSB -1.5 1.0 1.5 -2.0 -2.0 2.0 2.0 LSB -1 -1.0 Output capacitative load 0.1 5 ( 4 / 6) V LSB LSB F ohm 0107 MITSUBISHI <Standard Linear IC> M62352AGP 8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS <AC characteristics> Symbol (VCC, VrefU=5V ± 10% , VCC ≥ VrefU, GND, VrefL=0.0V, Ta=-20 ~ +85 ºC unless otherwise specified.) Ratings Parameter Conditions MIN TYP MAX Unit tCKL Clock "L" puise width 200 ns tCKH Clock "H" pulse width 200 ns tCR tCF Clock rise time Clock fall time tDCH Data setup time 30 ns tCHD Data hold time 60 ns tCHL 200 ns tLDC LD setup time LD hold time tLDH LD "H" hold time 100 100 ns ns tDO Data output delay time tLDD 200 CL≤ 100pF 70 CL ≤ 100pF,VAO:0.5 D-A output settling time 350 4.5V 300 The time until the output becomes the final value of 1/2 LSB ns ns s Measurement circuit DUT input output C L ≤ 100pF TIMING CHART tCR tCKH tCF tCHL CLK tCKL tLDC DI tDCH tLDH tCHD tCHL LD tLDD AO1~ AO12 output t tDO DO DO output ( 5 / 6) 0107 MITSUBISHI <Standard Linear IC> M62352AGP 8BIT 12CH D-A CONVERTER WITH BUFFER AMPLIFIERS TYPICAL APPLICATION 11 VCC VDD(VrefU) AO1 18 AO2 19 AO3 2 AO4 3 DI CLK AO5 4 16 LD AO6 5 15 DO AO7 6 AO8 7 AO9 8 AO10 9 AO11 12 AO12 13 18 17 MCU 10 GND 20 VSS(VrefL) 1 Note: M62352AGP has 3 terminals(VDD, VCC, and VSS) to which constant voltage is to be applied. Ripple voltage or spike noise to these terminals may worsen converting precision or cause erroneous operations. So be sure to use this device by putting cacpacitor between each terminal and GND to get D-A conversion operation stabilized. Output buffer amplifiers have high oscillation stability against capacitive load. This means that jitters by wirings around output terminals or capcitor between output and GND(0.1uF max.) do not cause any problems with DAC operations. Connect capacitor(0.1uF or around) between output and GND for protection from spark discharge when this device is used under such high electric field as that for instance of instruments with cathode ray tube. ( 6 / 6) 0107