Mitsubishi M37733MHB242FP Prom version of m37733mhbxxxfp(microcomputers) Datasheet

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PROM VERSION OF M37733MHBXXXFP
DESCRIPTION
●Single power supply ...................................................... 5 V ± 10%
●Low power dissipation (at 25 MHz frequency)
............................................47.5 mW (Typ.)
●Interrupts ............................................................ 19 types, 7 levels
●Multiple-function 16-bit timer ................................................. 5 + 3
●Serial I/O (UART or clock synchronous) ..................................... 3
●10-bit A-D converter ............................................ 8-channel inputs
●Watchdog timer
●Programmable input/output
(ports P0, P1, P2, P3, P4, P5, P6, P7, P8) ............................... 68
●Clock generating circuit ........................................ 2 circuits built-in
The M37733EHBXXXFP is a single-chip microcomputer using the
7700 Family core. This single-chip microcomputer has a CPU and a
bus interface unit. The CPU is a 16-bit parallel processor that can be
an 8-bit parallel processor, and the bus interface unit enhances the
memory access efficiency to execute instructions fast. This
microcomputer also includes a 32 kHz oscillation circuit, in addition
to the PROM, RAM, multiple-function timers, serial I/O, A-D converter,
and so on.
The M37733EHBXXXFP has the same function as the
M37733MHBXXXFP except that the built-in ROM is PROM. (Refer
to the basic function blocks description.) For program development,
the M37733EHBFS with erasable ROM that is housed in a windowed
ceramic LCC is also provided.
APPLICATION
Control devices for general commercial equipment such as office
automation, office equipment, and so on.
Control devices for general industrial equipment such as
communication equipment, and so on.
Note. Do not use the windowed EPROM version for mass production,
because it is a tool for program development (for evaluation).
FEATURES
●Number of basic instructions .................................................. 103
●Memory size
PROM ............................................. 124 Kbytes
RAM ................................................ 3968 bytes
●Instruction execution time
The fastest instruction at 25 MHz frequency ...................... 160 ns
41
42
43
44
45
47
46
48
49
50
51
53
52
54
55
57
56
59
58
60
62
61
64
32
P24/A20/D4
P25/A21/D5
P26/A22/D6
P27/A23/D7
P30/R/W
P31/BHE
P32/ALE
P33/HLDA
Vss
74
31
E
75
30
76
29
XOUT
XIN
77
28
RESET
78
27
79
26
80
25
CNVSS
BYTE
P40/HOLD
65
40
66
39
67
38
68
37
69
36
70
35
71
34
72
33
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
7
6
5
4
3
1
2
8
M37733EHBXXXFP
73
P70/AN0
P67/TB2IN/φSUB
P66/TB1IN
P65/TB0IN
P64/INT2
P63/INT1
P62/INT0
P61/TA4IN
P60/TA4OUT
P57/TA3IN/KI3
P56/TA3OUT/KI2
P55/TA2IN/KI1
P54/TA2OUT/KI0
P53/TA1IN
P52/TA1OUT
P51/TA0IN
P50/TA0OUT
P47
P46
P45
P44
P43
P42/φ1
P41/RDY
P83/TXD0
P82/RXD0/CLKS0
P81/CLK0
P80/CTS0/RTS0/CLKS1
VCC
AVCC
VREF
AVSS
VSS
P77/AN7/XcIN
P76/AN6/XcOUT
P75/AN5/ADTRG /TxD2
P74/AN4/RxD2
P73/AN3/CLK2
P72/AN2/CTS2
P71/AN1
63
P84/CTS1/RTS1
P85/CLK1
P86/RXD1
P87/TXD1
P00/A0
P01/A1
P02/A2
P03/A3
P04/A4
P05/A5
P06/A6
P07/A7
P10/A8/D8
P11/A9/D9
P12/A10/D10
P13/A11/D11
P14/A12/D12
P15/A13/D13
P16/A14/D14
P17/A15/D15
P20/A16/D0
P21/A17/D1
P22/A18/D2
P23/A19/D3
PIN CONFIGURATION (TOP VIEW)
Outline 80P6N-A
1
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PROM VERSION OF M37733MHBXXXFP
Reference
External data bus width
voltage input
selection input
VREF
BYTE
Data Bus(Even)
Data Bus(Odd)
P0(8)
Instruction Queue Buffer Q0(8)
Instruction Queue Buffer Q1(8)
P1(8)
Instruction Queue Buffer Q2(8)
AVCC
Instruction Register(8)
Data Buffer DBL(8)
Input/Output
port P0
Data Buffer DBH(8)
Address Bus
Input/Output
port P1
IM
REL
Incrementer/Decrementer(24)
(0V)
VSS
Program Counter PC(16)
Program Bank Register PG(8)
Input/Output
port P3
P2(8)
A-D Converter(10)
CNVss
Data Address Register DA(24)
P3(4)
(0V)
AVSS
Program Address Register PA(24)
Input/Output
port P2
Incrementer(24)
2
P4(8)
Input/Output
port P4
Input/Output
port P5
Input/Output
port P6
Timer TB0(16)
Timer TA0(16)
P5(8)
Timer TB1(16)
P6(8)
Timer TB2(16)
Timer TA1(16)
UART0(9)
Watchdog Timer
XCOUT
XCIN
Accumulatcr B(16)
E
Input/Output
port P7
P7(8)
3968 bytes
RAM
Accumulator A(16)
Input/Output
port P8
124 Kbytes
P8(8)
XCOUT
XCIN
Arithmetic Logic
Unit(16)
PROM
Clock Generating Circuit
Enable output
Index Register X(16)
Timer TA4(16)
Stack Pointer S(16)
Timer TA2(16)
RESET
Direct Page Register DPR(16)
Index Register Y(16)
Clock input Clock output
XIN
XOUT
M37733EHBXXXFP BLOCK DIAGRAM
Reset input
Processor Status Register PS(11)
Timer TA3(16)
Input Butter Register IB(16)
UART1(9)
UART2(9)
VCC
Data Bank Register DT(8)
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M37733EHBXXXFP
M37733EHBFS
PROM VERSION OF M37733MHBXXXFP
FUNCTIONS OF M37733EHBXXXFP
Parameter
Number of basic instructions
Instruction execution time
Memory size
Input/Output ports
Multi-function timers
PROM
RAM
P0 – P2, P4 – P8
P3
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2
Serial I/O
A-D converter
Watchdog timer
Interrupts
Clock generating circuit
Supply voltage
Power dissipation
Input/Output characteristic
Input/Output voltage
Output current
Memory expansion
Operating temperature range
Device structure
Package
M37733EHBXXXFP
M37733EHBFS
Functions
103
160 ns (the fastest instruction at external clock 25 MHz frequency)
124 Kbytes
3968 bytes
8-bit ✕ 8
4-bit ✕ 1
16-bit ✕ 5
16-bit ✕ 3
(UART or clock synchronous serial I/O) ✕ 3
10-bit ✕ 1 (8 channels)
12-bit ✕ 1
3 external types, 16 internal types
Each interrupt can be set to the priority level (0 – 7.)
2 circuits built-in (externally connected to a ceramic resonator or a
quartz-crystal oscillator)
5 V ± 10%
47.5 mW (at external clock 25 MHz frequency)
5V
5 mA
Maximum 16 Mbytes
–20 to 85 °C
CMOS high-performance silicon gate process
80-pin plastic molded QFP (80P6N-A)
80-pin ceramic LCC (with a window) (80D0)
3
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PROM VERSION OF M37733MHBXXXFP
PIN DESCRIPTION
Pin
Vcc,
Vss
CNVss
Name
Input/Output
Power source
Apply 5 V ± 10% to Vcc and 0 V to Vss.
CNVss input
Input
RESET
Reset input
Input
XIN
Clock input
Input
XOUT
_____
Clock output
Output
E
Enable output
Output
BYTE
External data
bus width
selection input
Analog power
source input
Reference
voltage input
I/O port P0
Input
_
AVcc,
AVss
VREF
P00 – P07
Input
I/O
P10 – P17 I/O port P1
I/O
P20 – P27 I/O port P2
I/O
P30 – P33 I/O port P3
I/O
P40 – P47 I/O port P4
I/O
P50 – P57 I/O port P5
I/O
P60 – P67 I/O port P6
I/O
P70 – P77 I/O port P7
I/O
P80 – P87 I/O port P8
I/O
4
Functions
This pin controls the processor mode. Connect to Vss for the single-chip mode and the memory
expansion mode, and to Vcc for the microprocessor mode.
When “L” level is applied to this pin, the microcomputer enters the reset state.
These are pins of main-clock generating circuit. Connect a ceramic resonator or a quartzcrystal oscillator between XIN and XOUT. When an external clock is used, the clock source should
be connected to the XIN pin, and the XOUT pin should be left open.
This pin functions as the enable
signal output pin which indicates the access status in the internal
_
bus. When output level of E signal is “L”, data/instruction read or data write is performed.
In the memory expansion mode or the microprocessor mode, this pin determines whether the
external data bus has an 8-bit width or a 16-bit width. The data bus has a 16-bit width when “L”
signal is input and an 8-bit width when “H” signal is input.
Power source input pin for the A-D converter. Externally connect AVcc to Vcc and AVss to Vss.
This is reference voltage input pin for the A-D converter.
In the single-chip mode, port P0 becomes an 8-bit I/O port. An I/O direction register is available so
that each pin can be programmed for input or output. These ports are in the input mode when
reset.
In the memory expansion mode or the microprocessor mode, these pins output address (A0 – A7).
In the single-chip mode, these pins have the same functions as port P0. When the BYTE pin is set
to “L” in the memory expansion mode or the microprocessor mode and external data bus has a
16-bit width, high-order data (D8 – D15) is input/output or an address (A8 – A15) is output. When
the BYTE pin is “H” and an external data bus has an 8-bit width, only address (A8 – A15) is output.
In the single-chip mode, these pins have the same functions as port P0. In the memory expansion
mode or the microprocessor mode, low-order data (D0 – D7) is input/output or an address
(A0 – A7) is output .
In the single-chip mode, these pins have
the same function
as port P0. In the memory expansion
__ ____
_____
mode or the microprocessor mode, R/W, BHE, ALE, and HLDA signals are output.
In the single-chip mode, these pins have the same functions as_____
port P0. In____
the memory expansion
mode or the microprocessor mode, P40, P41, and P42 become HOLD and RDY input pins, and a
clock φ1 output pin, respectively. Functions of the other pins are the same as in the single-chip
mode. However, in the memory expansion mode, P42 can be selected as an I/O port.
In addition to having the same functions as port P0 in the single-chip mode, these pins
also
__
__
function as I/O pins for timers A0 to A3 and input pins for key input interrupt input (KI0 – KI3 ).
In addition to having the same functions as port P0 in the single-chip mode,
____ these
____ pins also
function as I/O pins for timer A4, input pins for external interrupt input (INT0 – INT2) and input pins
for timers B0 to B2. P67 also functions as sub-clock φSUB output pin.
In addition to having the same functions as port P0 in the single-chip mode, these pins function as
input pins for A-D converter. P72 to P75 also function as I/O pins for UART2. Additionally, P76 and
P77 have the function as the output pin (XCOUT) and the input pin (XCIN) of the sub-clock (32 kHz)
oscillation circuit, respectively. When P76 and P77 are used as the XCOUT and XCIN pins, connect
a resonator or an oscillator between the both.
In addition to having the same functions as port P0 in the single-chip mode, these pins also
function as I/O pins for UART 0 and UART 1.
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PROM VERSION OF M37733MHBXXXFP
PIN DESCRIPTION (EPROM MODE)
Pin
VCC, VSS
CNVSS
BYTE
_____
RESET
XIN
XOUT
_
E
AVCC, AVSS
VREF
P00 – P07
P10 – P17
P20 – P27
P30
P31 – P33
P40 – P47
P50 – P57
Name
Power supply
VPP input
VPP input
Reset input
Clock input
Clock output
Enable output
Analog supply input
Reference voltage input
Address input (A0 – A7)
Address input (A8 – A15)
Data I/O (D0 – D7)
Address input (A16)
Input port P3
Input port P4
Control signal input
P60 – P67
Input port P6
P70 – P77
P80 – P87
Input port P7
Input port P8
Input/Output
Input
Input
Input
Input
Output
Output
Input
Input
Input
I/O
Input
Input
Input
Input
Input
Input
Input
Functions
Supply 5V±10% to VCC and 0V to VSS.
Connect to VPP when programming or verifing.
Connect to VPP when programming or verifing.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Keep open.
Connect AVCC to VCC and AVSS to VSS.
Connect to VSS.
Port P0 functions as the lower 8 bits address input (A0 – A7).
Port P1 functions as the higher 8 bits address input (A8 – A15).
Port P2 functions as the 8 bits data input/output (D0 – D7).
P30 functions as the most significant bit address input (A16).
Connect to VSS.
Connect to VSS.
_____ ___
___
P50, P51, and P52 function as PGM, OE, and CE input pins respectively.
Connect P53, P54, P55, and P56 to VCC. Connect P57 to VSS.
Connect to VSS.
Connect to VSS.
Connect to VSS.
5
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PROM VERSION OF M37733MHBXXXFP
BASIC FUNCTION BLOCKS
The M37733EHBXXXFP has the same functions as the
M37733MHBXXXFP except for the following:
(1) The built-in ROM is PROM.
(2) The status of bit 3 of the oscillation circuit control register 1 (address
6F16) at a reset is different.
(3) The usage condition of bit 3 of the oscillation circuit control register
1 is different.
7
6
5
4
3
0
1
2
1
Accordingly, refer to the basic function blocks description in the
M37733MHBXXXFP except for Figure 1 (bit configuration of the
oscillation circuit control register 1) and Figure 3 (microcomputer
internal status during reset).
In the M37733EHBXXXFP, bit 3 of the oscillation circuit control
register 1 must be “1”. (Refer to Figure 1.) The status of this bit at
a reset is “1”.
0
CC2 CC1 CC0
Oscillation circuit control register 1
Main clock division selection bit
0 : Main clock is divided by 2.
1 : Main clock is not divided by 2.
Address
6F16
Note. Write to the oscillation circuit control
register 1 as the flow shown in Figure 2.
Main clock external input selection bit
0 : Main-clock oscillation circuit is operating by itself.
Watchdog timer is used at returning from STP state.
1 : Main-clock is input externally.
Watchdog timer is not used at returning from STP state.
Sub clock external input selection bit
0 : Sub-clock oscillation circuit is operating by itself.
Port P76 functions as XCOUT pin.
Watchdog timer is used at returning from STP state.
1 : Sub-clock is input externally.
Port P76 functions as I/O port.
Watchdog timer is not used at returning from STP state.
1 : Always “1” (“1” at reset)
0 : Always “0” (However, writing data “5516” shown in Figure 2 is possible.)
Clock prescaler reset bit
Fig. 1 Bit configuration of oscillation circuit control register 1 (corresponding to Figure 63 in data sheet “M37733MHBXXXFP”)
Writing data “5516” (LDM instruction)
Next instruction
Writing data “8016” (LDM instruction)
Reset clock prescaler
• How to reset clock prescaler
Writing data “0Y16” (LDM instruction)
CC2 to CC0 selection bits
• How to write in CC2 to CC0 selection bits
Note. “Y” is the sum of bits to be set. For example, when
setting bits 2 and 1 to “1”, “Y” becomes “6”.
Fig. 2 How to write data in oscillation circuit control register 1 (identical with Figure 64 in data sheet “M37733MHBXXXFP”)
6
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PROM VERSION OF M37733MHBXXXFP
Address
Address
(0416)•••
0016
Watchdog timer frequency selection flag
(6116)•••
Port P1 direction register
(0516)•••
0016
Memory allocation control register
0
(6316)••• 0 0 0 0 0 0 0 1
Port P2 direction register
(0816)•••
0016
UART2 transmit/receive mode register
(6416)•••
0 0 0 0 0 0 0
1 0 0 0
Port P0 direction register
0 0 0 0
0
Port P3 direction register
(0916)•••
UART2 transmit/receive control register 0
(6816)•••
Port P4 direction register
(0C16)•••
0016
UART2 transmit/receive control register 1
(6916)••• 0 0 0 0 0 0 1 0
Port P5 direction register
(0D16)•••
0016
Oscillation circuit control register 0
(6C16)••• 0 0 0 0 0 0 0 1
Port P6 direction register
(1016)•••
0016
Port function control register
(6D16)••• 0
Port P7 direction register
(1116)•••
0016
Serial transmit control register
(6E16)•••
Port P8 direction register
(1416)•••
0016
Oscillation circuit control register 1
(6F16)••• 0
0 0 0 0 0 ? ? ?
A-D/UART2 trans./rece. interrupt control register
A-D control register 0
(1E16)•••
A-D control register 1
(1F16)•••
0 0 0
UART 0 transmit/receive mode register
(3016)•••
0016
UART 0 receive interrupt control register
UART 1 transmit/receive mode register
(3816)•••
0016
UART 0 transmit/receive
control register 0
UART 1 transmit/receive
control register 0
UART 0 transmit/receive
control register 1
UART 1 transmit/receive
control register 1
Count start flag
(3416)••• 0 0 0 0 1 0 0 0
0016
0 0
0 1 0 0 0
(7016)•••
0 0 0 0
UART 0 transmission interrupt control register (7116)•••
0 0 0 0
(7216)•••
0 0 0 0
UART 1 transmission interrupt control register (7316)•••
0 0 0 0
UART 1 receive interrupt control register
(7416)•••
0 0 0 0
(3C16)••• 0 0 0 0 1 0 0 0
Timer A0 interrupt control register
(7516)•••
0 0 0 0
(3516)••• 0 0 0 0 0 0 1 0
Timer A1 interrupt control register
(7616)•••
0 0 0 0
(3D16)••• 0 0 0 0 0 0 1 0
Timer A2 interrupt control register
(7716)•••
0 0 0 0
1 1
(4016)•••
0016
Timer A3 interrupt control register
(7816)•••
0 0 0 0
One- shot start flag
(4216)•••
0 0 0 0 0
Timer A4 interrupt control register
(7916)•••
0 0 0 0
Up-down flag
(4416)•••
0016
Timer B0 interrupt control register
(7A16)•••
0 0 0 0
Timer A0 mode register
(5616)•••
0016
Timer B1 interrupt control register
(7B16)•••
0 0 0 0
Timer A1 mode register
(5716)•••
0016
Timer B2 interrupt control register
(7C16)•••
0 0 0 0
Timer A2 mode register
(5816)•••
0016
INT0 interrupt control register
(7D16)•••
0 0 0 0 0 0
Timer A3 mode register
(5916)•••
0016
INT1 interrupt control register
(7E16)•••
0 0 0 0 0 0
Timer A4 mode register
(5A16)•••
0016
INT2/Key input interrupt control register
(7F16)•••
0 0 0 0 0 0
Timer B0 mode register
(5B16)••• 0 0 1 0 0 0 0 0
Timer B1 mode register
(5C16)•••
0 0 1
0 0 0 0
Timer B2 mode register
(5D16)••• 0 0 1
0 0 0 0
Processor mode register 0
(5E16)•••
Processor mode register 1
(5F16)•••
Watchdog timer register
(6016)•••
0016
0
FFF16
Processor status register (PS)
Program bank register (PG)
0 0 0 ? ? 0 0 0 1 ? ?
0016
Program counter (PCH)
Content of FFFF16
Program counter (PCL)
Content of FFFE16
Direct page register (DPR)
Data bank register (DT)
000016
0016
Contents of other registers and RAM are undefined during reset. Initialize them by software.
Fig. 3 Microcomputer internal status during reset
7
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PROM VERSION OF M37733MHBXXXFP
EPROM MODE
The M37733EHBXXXFP features
an EPROM mode in addition to its
_____
normal modes. When the RESET signal level is “L”, the chip
automatically enters the EPROM mode. Table 1 list the
correspondence between pins and Figure 4 shows the pin
connections in the EPROM mode.
The EPROM mode is the 1M mode for the EPROM that is equivalent
to the M5M27C101K.
When in the EPROM mode, ports P0, P1, P2, P30, P50, P51, P52,
CNV SS, and BYTE are used for the EPROM (equivalent to the
Table 1 Pin function in EPROM mode
VCC
VPP
VSS
Address input
Data I/O
___
CE
___
OE
_____
PGM
8
M37733EHBXXXFP
VCC
M5M27C101K
VCC
CNVSS, BYTE
VSS
VPP
VSS
A0 – A16
D0 – D7
Ports P0, P1, P30
Port P2
P52
P51
P50
___
CE
___
OE
_____
PGM
M5M27C101K).
When in this mode, the built-in PROM can be programmed or read
from using these pins in the same way as with the M5M27C101K.
This chip does not have Device Identifier Mode, so that set the
corresponding program algorithm. The program area should specify
address 0100016 – 1FFFF16.
Connect the clock which is either ceramic resonator or external clock
to XIN pin and XOUT pin.
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41
42
45
44
43
46
49
48
47
50
53
52
51
54
55
57
56
58
59
62
61
60
65
40
66
39
67
38
68
37
69
36
70
35
34
71
72
73
M37733EHBXXXFP
33
32
74
31
75
30
76
29
77
28
78
27
79
26
80
25
↔ P24/A20 /D4
↔ P25/A21 /D5
↔ P26/A22 /D6
↔ P27/A23 /D7
↔ P30/R/W
↔ P31/BHE
↔ P32/ALE
↔ P33/HLDA
VSS
→E
→ XOUT
← XIN
← RESET
CNVSS
← BYTE
↔ P40/HOLD
D4
D5
D6
D7
A16
VSS





∗
VPP
PGM
CE
OE
P70/AN0 ↔ 1
P67/TB2IN/φSUB ↔ 2
P66/TB1IN ↔ 3
P65/TB0IN ↔ 4
P64/INT 2 ↔ 5
P63/INT 1 ↔ 6
P62 /INT 0 ↔ 7
P61/TA4IN ↔ 8
P60/TA4OUT ↔ 9
P57/TA3IN /KI3 ↔ 10
P56 /TA3OUT /KI 2 ↔ 11
P55/TA2IN /KI 1 ↔ 12
P54/TA2OUT /KI0 ↔ 13
P53/TA1IN ↔ 14
P52/TA1OUT ↔ 15
P51/TA0IN ↔ 16
P50/TA0OUT ↔ 17
P47 ↔ 18
P46 ↔ 19
P45 ↔ 20
P44 ↔ 21
P43 ↔ 22
P42/ φ1 ↔ 23
P41/RDY ↔ 24
VCC
P83/TXD0 ↔
P82 /RXD 0/CLKS0 ↔
P81/CLK0 ↔
P80 /CTS 0/RTS 0/CLKS1 ↔
VCC
AVCC
VREF →
AVSS
VSS
P77/AN7/XCIN ↔
P76/AN6/XCOUT ↔
P75 /AN5/AD TRG /TXD2 ↔
P74/AN4/RXD2 ↔
P73/AN3/CLK2 ↔
P72/AN2 /CTS 2 ↔
P71/AN1 ↔
63
64
↔ P84/CTS 1/RTS 1
↔ P85 /CLK1
↔ P86/RXD1
↔ P87/TXD1
↔ P00/A0
↔ P01/A1
↔ P02/A2
↔ P03/A3
↔ P04/A4
↔ P05/A5
↔ P06/A6
↔ P07/A7
↔ P10/A8/D8
↔ P11/A9/D9
↔ P12 /A10 /D10
↔ P13/A11 /D11
↔ P14/A12 /D12
↔ P15/A13 /D13
↔ P16/A14 /D14
↔ P17/A15 /D15
↔ P20/A16 /D0
↔ P21/A17 /D1
↔ P22/A18 /D2
↔ P23/A19 /D3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
PROM VERSION OF M37733MHBXXXFP
✽ : Connect to ceramic oscillation circuit.
Outline 80P6N-A
: It is used in the EPROM mode.
Fig. 4 Pin connection in EPROM mode
9
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FUNCTION IN EPROM MODE
1M mode (equivalent to the M5M27C101K)
Reading
___
___
To read the EPROM, set the CE and OE pins to a “L” level. Input the
address of the data (A0 – A16) to be read, and the data will be output
to the
I/O pins
D0 – D7. The data I/O pins will be floating when either
__
__
the CE or OE pins are in the “H” state.
Programming
Programming must be performed
in 8 bits by a byte program.
To
___
___
program to the EPROM, set the CE pin to a “L” level and the OE pin to
a “H” level. The CPU will enter the programming mode when 12.5 V
is applied to the VPP pin. The address to be programmed to is selected
with pins A0 –_____
A16, and the data to be programmed is input to pins D0
– D7. Set the PGM pin to a “L” level to being programming.
PROM VERSION OF M37733MHBXXXFP
Programming operation
To program the M37733EHBXXXFP, first set VCC = 6 V, VPP = 12.5
V, and set the address to 0100016. Apply a 0.2 ms programming
pulse, check that the data can be read, and if it cannot be read OK,
repeat the procedure, applying a 0.2 ms programming pulse and
checking that the data can be read until it can be read OK. Record
the accumulated number of pulse applied (X) before the data can be
read OK, and then write the data again, applying a further once this
number of pulses (0.2 ✕ X ms).
When this series of programming operations is complete, increment
the address, and continue to repeat the procedure above until the
last address has been reached.
Finally, when all addresses have been programmed, read with VCC =
VPP = 5 V (or VCC = VPP = 5.5 V).
Table 2. I/O signal in each mode
Pin
Erasing
To erase data on this chip, use an ultraviolet light source with a 2537
Angstrom wave length. The minimum radiation power necessary for
erasing is 15 J/cm2.
___
___
_____
CE
OE
PGM
VPP
VCC
Data I/O
VIL
VIL
VIL
VIH
VIL
VIH
X
VIH
X
X
5V
5V
5V
5V
Output
Floating
X
5V 5V
VIL 12.5 V 6 V
Floating
Input
Programming
Verify
VIL
VIL
VIH 12.5 V 6 V
Output
Program Disable
VIH
VIH
VIH 12.5 V 6 V
Floating
Mode
Read-out
Output
Disable
Programming
Note 1 : An X indicates either VIL or VIH.
Programming operation (equivalent to the M5M27C101K)
AC ELECTRICAL CHARACTERISTICS (Ta = 25 ± 5 °C, VCC = 6 V ± 0.25 V, VPP = 12.5 ± 0.3 V, unless otherwise noted)
Symbol
Parameter
Test conditions
Min.
2
tAS
Address setup time
tOES
tDS
tAH
tDH
tDFP
tVCS
OE setup time
2
Data setup time
Address hold time
Data hold time
Output enable to output float delay
VCC setup time
VPP setup time
2
tVPS
tPW
tOPW
tCES
tOE
10
___
_____
2
0.19
2
CE setup time
__
Data valid from OE
130
0
2
PGM over program pulse width
Unit
µs
µs
2
0.19
___
Max.
0
PGM pulse width
_____
Limits
Typ.
0.2
0.21
µs
µs
µs
ns
µs
µs
5.25
ms
ms
150
µs
ns
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PROM VERSION OF M37733MHBXXXFP
AC waveforms
PROGRAM
VERIFY
VIH
ADDRESS
VIL
tAH
tAS
VIH/VOH
DATA
DATA OUTPUT VALID
DATA SET
VIL/VOL
tDS
tDH
tDFP
VPP
VPP
VCC
VCC +1
VCC
VCC
tVPS
tVCS
VIH
CE
VIL
tCES
VIH
PGM
tOES
VIL
tOE
tPW
VIH
tOPW
OE
VIL
Test conditions for A.C. characteristics
Input voltage : VIL = 0.45 V, VIH = 2.4 V
Input rise and fall times (10 % – 90 %) : ≤ 20 ns
Reference voltage at timing measurement : Input, Output
“L” = 0.8 V, “H” = 2 V
Programming algorithm flow chart
START
ADDR=FIRST LOCATION
VCC=6.0 V
VPP=12.5 V
X=0
PROGRAM ONE PULSE OF 0.2 ms
X=X+1
YES
X=25?
NO
FAIL
VERIFY
BYTE
FAIL
VERIFY
BYTE
PASS
PROGRAM PULSE OF
0.2X ms DURATION
DEVICE
FAILED
PASS
NO
INCREMENT ADDR
LAST ADDR?
YES
VCC=VPP=*5.0 V
VERIFY
ALL BYTE
FAIL
DEVICE
FAILED
PASS
DEVICE PASSED
*4.5 V ≤ VCC = VPP ≤ 5.5 V
11
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PROM VERSION OF M37733MHBXXXFP
SAFETY INSTRUCTIONS
(1) Sunlight and fluorescent lamp contain light that can erase written
information. When using in read mode, be sure to cover the
transparent glass portion with a seal or other materials (ceramic
package product).
(2) Mitsubishi Electric corp. provides the seal for covering the
transparent glass. Take care that the seal does not touch the read
pins (ceramic package product).
(3) Clean the transparent glass before erasing. Fingers’ fat and paste
disturb the passage of ultraviolet rays and may affect badly the
erasure capability (ceramic package product).
(4) A high voltage is used for programming. Take care that overvoltage is not applied. Take care especially at power on.
(5) The programmable M37733EHBFP that is shipped in blank is also
provided. For the M37733EHBFP, Mitsubishi Electric corp. does
not perform PROM programming test and screening following the
assembly processes. To improve reliability after programming,
performing programming and test according to the flow below
before use is recommended.
Programming with PROM programmer
Screening
(Caution)
(Leave at 150 °C for 40 hours)
Verify test with PROM programmer
Function check in target device
Caution : Never expose to 150 °C exceeding 100 hours.
12
ADDRESSING MODES
The M37733EHBXXXFP has 28 powerful addressing modes. Refer
to the “7700 Family Software Manual” for the details.
MACHINE INSTRUCTION LIST
The M37733EHBXXXFP has 103 machine instructions. Refer to the
“7700 Family Software Manual” for the details.
DATA REQUIRED FOR PROM ORDERING
Please send the following data for writing to PROM.
(1) M37733EHBXXXFP writing to PROM order confirmation form
(2) 80P6N mark specification form
(3) ROM data (EPROM 3 sets)
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PROM VERSION OF M37733MHBXXXFP
ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
AVcc
VI
VI
VO
Pd
Topr
Tstg
Parameter
Conditions
Power source voltage
Analog power_____
source voltage
Input voltage RESET, CNVss, BYTE
Input voltage P00 – P07, P10 – P17, P20 – P27,
P30 – P33, P40 – P47, P50 – P57,
P60 – P67, P70 – P77, P80 – P87,
VREF, XIN
Output voltage P00 – P07, P10 – P17, P20 – P27,
P30 – P33, P40 – P47, P50 – P57,
7, P70 – P77, P80 – P87,
P60 – P6
_
XOUT, E
Power dissipation
Ta = 25 °C
Operating temperature
Storage temperature
Ratings
–0.3 to +7
–0.3 to +7
–0.3 to +12 (Note)
Unit
V
V
V
–0.3 to Vcc + 0.3
V
–0.3 to Vcc + 0.3
V
300
–20 to +85
–40 to +150
mW
°C
°C
Note. When the EPROM is programmed, input voltage of pins CNVss and BYTE is 13 V respectively.
RECOMMENDED OPERATING CONDITIONS (Vcc = 5 V ± 10%, Ta = –20 to +85 °C, unless otherwise noted)
Symbol
Vcc
AVcc
Vss
AVss
VIH
VIH
VIH
VIL
VIL
VIL
IOH(peak)
IOH(avg)
IOL(peak)
IOL(peak)
IOL(avg)
IOL(avg)
f(XIN)
f(XCIN)
Parameter
f(XIN) : Operating
Power source voltage
f(XIN) : Stopped, f(XCIN) = 32.768 kHz
Analog power source voltage
Power source voltage
Analog power source voltage
3, P40 – P47, P50 – P57, P60 – P67,
High-level input voltage P00 – P07, P30 – P3
_______
P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3)
High-level input voltage P10 – P17, P20 – P27 (in single-chip mode)
High-level input voltage P10 – P17, P20 – P27
(in memory expansion mode and microprocessor mode)
3, P40 – P47, P50 – P57, P60 – P67,
Low-level input voltage P00 – P07, P30 – P3_______
P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE, XCIN (Note 3)
Low-level input voltage P10 – P17, P20 – P27 (in single-chip mode)
Low-level input voltage P10 – P17, P20 – P27
(in memory expansion mode and microprocessor mode)
High-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,
P40 – P47, P50 – P57, P60 – P67, P70 – P77,
P80 – P87
High-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,
P40 – P47, P50 – P57, P60 – P67, P70 – P77,
P80 – P87
Low-level peak output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,
P40 – P43, P54 – P57, P60 – P67, P70 – P77,
P80 – P87
Low-level peak output current P44 – P47, P50 – P53
Low-level average output current P00 – P07, P10 – P17, P20 – P27, P30 – P33,
P40 – P43, P54 – P57, P60 – P67, P70 – P77,
P80 – P87
Low-level average output current P44 – P47, P50 – P53
Main-clock oscillation frequency (Note 4)
Sub-clock oscillation frequency
Min.
4.5
2.7
Limits
Typ.
5.0
Max.
5.5
5.5
Vcc
0
0
Unit
V
V
V
V
0.8 Vcc
Vcc
V
0.8 Vcc
Vcc
V
0.5 Vcc
Vcc
V
0
0.2Vcc
V
0
0.2Vcc
V
0
0.16Vcc
V
–10
mA
–5
mA
10
mA
20
mA
5
mA
15
25
50
mA
MHz
kHz
32.768
Notes 1. Average output current is the average value of a 100 ms interval.
2. The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,
the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,
the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and
the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.
3. Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1”.
4. The maximum value of f(XIN) = 12.5 MHz when the main clock division selection bit = “1”.
13
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PROM VERSION OF M37733MHBXXXFP
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted)
Symbol
VOH
VOH
VOH
VOH
VOL
VOL
VOL
VOL
VOL
VT+ – VT–
VT+ – VT–
VT+ – VT–
VT+ – VT–
IIH
IIL
IIL
VRAM
14
Parameter
Test conditions
High-level output voltage P00 – P07, P10 – P17, P20 – P27,
P33, P40 – P47, P50 – P57,
IOH = –10 mA
P60 – P67, P70 – P77, P80 – P87
High-level output voltage P00 – P07, P10 – P17, P20 – P27,
IOH = –400 mA
P33
IOH = –10 mA
High-level output voltage P30 – P32
ICH = –400 µA
_
IOH = –10 mA
High-level output voltage E
IOH = –400 µA
Low-level output voltage P00 – P07, P10 – P17, P20 – P27,
P33, P40 – P43, P54 – P57,
IOL = 10 mA
P60 – P67, P70 – P75, P80 – P87
Low-level output voltage P44 – P47, P50 – P53
IOL = 20 mA
Low-level output voltage P00 – P07, P10 – P17, P20 – P27,
IOL = 2 mA
P33
IOL = 10 mA
Low-level output voltage P30 – P32
IOL = 2 mA
_
IOL = 10 mA
Low-level output voltage E
IOL = 2 mA
______ ____
Hysteresis ___
HOLD, ___
RDY, ____
TA0IN –___
TA4IN
, TB0IN – TB2IN,
___ ___
INT0 – INT2, AD
TRG, __
CTS0, CTS1, CTS2, CLK0,
__
CLK1, CLK2, KI0 – KI3
_____
Hysteresis RESET
Hysteresis XIN
Hysteresis XCIN (When external clock is input)
High-level input current
P00 – P07, P10 – P17, P20 – P27, P30 – P33,
VI = 5 V
– P57, P60 – P67, P70 – P77,
P40 – P47, P50 _____
P80 – P87, XIN, RESET, CNVss, BYTE
Low-level input current
P00 – P07, P10 – P17, P20 – P27, P30 – P33,
VI = 0 V
P61, P65 – P67,
P40 – P47, P50 – P53, P60,_____
P70 – P77, P80 – P87, XIN, RESET, CNVss, BYTE
VI = 0 V,
Low-level input current P54 – P57, P62 – P64
RAM hold voltage
Min.
Limits
Typ.
Unit
3
V
4.7
V
3.1
4.8
3.4
4.8
V
V
2
V
2
V
0.45
V
1.9
0.43
1.6
0.4
V
V
0.4
1
V
0.2
0.1
0.1
0.5
0.4
0.4
V
V
V
without a pull-up transistor
VI = 0 V,
with a pull-up transistor
When clock is stopped.
Max.
–0.25
2
–0.5
5
µA
–5
µA
–5
µA
–1.0
mA
V
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PROM VERSION OF M37733MHBXXXFP
ELECTRICAL CHARACTERISTICS (Vcc = 5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Typ.
Max.
Unit
9.5
19
mA
1.3
2.6
mA
VCC = 5V,
f(XIN) = 25 MHz (square waveform),
f(XCIN) = 32.768 kHz,
when a WIT instruction is executed (Note 2)
10
20
µA
VCC = 5 V,
f(XIN) : Stopped,
f(XCIN) : 32.768 kHz,
in operating (Note 3)
50
100
µA
Test conditions
Min.
VCC = 5 V,
f(XIN) = 25 MHz (square waveform),
(f(f2) = 12.5 MHz),
f(XCIN) = 32.768 kHz,
in operating (Note 1)
VCC = 5 V,
f(XIN) = 25 MHz (square waveform),
(f(f2) = 1.5625 MHz),
f(XCIN) = Stopped,
in operating (Note 1)
Power source
current
ICC
Notes 1.
2.
3.
4.
In single-chip
mode, output pins
are open, and
other pins are VSS.
VCC = 5 V,
f(XIN) : Stopped,
5
10
µA
f(XCIN) : 32.768 kHz,
when a WIT instruction is executed (Note 4)
Ta = 25 °C,
1
µA
when clock is stopped
Ta = 85 °C,
20
µA
when clock is stopped
This applies when the main clock external input selection bit = “1”, the main clock division selection bit = “0”, and the signal output stop
bit = “1”.
This applies when the main clock external input selection bit = “1” and the system clock stop bit at wait state = “1”.
This applies when CPU and the clock timer are operating with the sub clock (32.768 kHz) selected as the system clock.
This applies when the XCOUT drivability selection bit = “0” and the system clock stop bit at wait state = “1”.
A–D CONVERTER CHARACTERISTICS
(VCC = AVCC = 5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted)
Symbol
Parameter
Test conditions
Resolution
VREF = VCC
Absolute accuracy
VREF = VCC
RLADDER
Ladder resistance
VREF = VCC
tCONV
Conversion time
VREF
Reference voltage
Analog input voltage
VIA
Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
Min.
—
—
10
9.44
2
0
Limits
Typ.
Max.
10
±3
25
VCC
VREF
Unit
Bits
LSB
kΩ
µs
V
V
15
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PROM VERSION OF M37733MHBXXXFP
TIMING REQUIREMENTS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted (Note))
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.
External clock input
Symbol
Parameter
Limits
Unit
Max.
tc
External clock input cycle time (Note 1)
ns
tw(H)
External clock input high-level pulse width (Note 2)
ns
tw(L)
External clock input low-level pulse width (Note 2)
ns
tr
External clock rise time
8
ns
External clock fall time
8
ns
tf
Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 80 ns.
2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.
Min.
40
15
15
Single-chip mode
Symbol
tsu(P0D–E)
tsu(P1D–E)
tsu(P2D-E)
tsu(P3D–E)
tsu(P4D–E)
tsu(P5D–E)
tsu(P6D–E)
tsu(P7D–E)
tsu(P8D–E)
th(E–P0D)
th(E–P1D)
th(E–P2D)
th(E–P3D)
th(E–P4D)
th(E–P5D)
th(E–P6D)
th(E–P7D)
th(E–P8D)
Parameter
Port P0 input setup time
Port P1 input setup time
Port P2 input setup time
Port P3 input setup time
Port P4 input setup time
Port P5 input setup time
Port P6 input setup time
Port P7 input setup time
Port P8 input setup time
Port P0 input hold time
Port P1 input hold time
Port P2 input hold time
Port P3 input hold time
Port P4 input hold time
Port P5 input hold time
Port P6 input hold time
Port P7 input hold time
Port P8 input hold time
Limits
Min.
60
60
60
60
60
60
60
60
60
0
0
0
0
0
0
0
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Memory expansion mode and microprocessor mode
Symbol
tsu(D–E)
tsu(RDY–φ1)
tsu(HOLD–φ1)
th(E–D)
th(φ1–RDY)
th(φ1–HOLD)
16
Parameter
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
___
RDY input hold time
____
HOLD input hold time
___
____
Limits
Min.
32
55
55
0
0
0
Max.
Unit
ns
ns
ns
ns
ns
ns
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Timer A input
(Count input in event counter mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
PROM VERSION OF M37733MHBXXXFP
parameter
TAiIN input cycle time
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
80
40
40
Max.
Unit
ns
ns
ns
Timer A input (Gating input in timer mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
parameter
TAiIN input cycle time (Note)
TAiIN input high-level pulse width (Note)
TAiIN input low-level pulse width (Note)
Limits
Min.
320
160
160
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 19.
Timer A input (External trigger input in one-shot pulse mode)
Symbol
t c(TA)
tw(TAH)
tw(TAL)
parameter
TAiIN input cycle time (Note)
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
320
80
80
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 19.
Timer A input (External trigger input in pulse width modulation mode)
Symbol
tw(TAH)
tw(TAL)
parameter
TAiIN input high-level pulse width
TAiIN input low-level pulse width
Limits
Min.
80
80
Max.
Unit
ns
ns
Timer A input (Up-down input in event counter mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP–TIN)
th(TIN–UP)
parameter
TAiOUT input cycle time
TAiOUT input high-level pulse width
TAiOUT input low-level pulse width
TAiOUT input setup time
TAiOUT input hold time
Limits
Min.
2000
1000
1000
400
400
Max.
Unit
ns
ns
ns
ns
ns
Timer A input (Two-phase pulse input in event counter mode)
Symbol
t c(TA)
TAjIN input cycle time
tsu(TAjIN–TAjOUT) TAjIN input setup time
tsu(TAjOUT–TAjIN) TAjOUT input setup time
parameter
Limits
Min.
800
200
200
Max.
Unit
ns
ns
ns
17
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PROM VERSION OF M37733MHBXXXFP
Timer B input (Count input in event counter mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Limits
Parameter
Min.
80
40
40
160
80
80
TBiIN input cycle time (one edge count)
TBiIN input high-level pulse width (one edge count)
TBiIN input low-level pulse width (one edge count)
TBiIN input cycle time (both edges count)
TBiIN input high-level pulse width (both edges count)
TBiIN input low-level pulse width (both edges count)
Max.
Unit
ns
ns
ns
ns
ns
ns
Timer B input (Pulse period measurement mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Limits
Parameter
Min.
320
160
160
TBiIN input cycle time (Note)
TBiIN input high-level pulse width (Note)
TBiIN input low-level pulse width (Note)
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 19.
Timer B input (Pulse width measurement mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Limits
Parameter
Min.
320
160
160
TBiIN input cycle time (Note)
TBiIN input high-level pulse width (Note)
TBiIN input low-level pulse width (Note)
Max.
Unit
ns
ns
ns
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS” on page 19.
A-D trigger input
Symbol
Limits
Parameter
Min.
1000
125
____
tc(AD)
tw(ADL)
ADTRG input cycle time (minimum allowable trigger)
____
ADTRG input low-level pulse width
Max.
Unit
ns
ns
Serial I/O
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C–Q)
th(C–Q)
tsu(D–C)
th(C–D)
Limits
Parameter
Min.
200
100
100
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Max.
80
0
30
90
____
Unit
ns
ns
ns
ns
ns
ns
ns
___
External interrupt INTi input, key input interrupt KIi input
Symbol
Parameter
___
tw(INH)
tw(INL)
tw(KIL)
18
INTi input high-level pulse width
INTi input low-level pulse width
KIi input low-level pulse width
___
__
Limits
Min.
250
250
250
Max.
Unit
ns
ns
ns
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PROM VERSION OF M37733MHBXXXFP
DATA FORMULAS
Timer A input (Gating input in timer mode)
Symbol
Parameter
tc(TA)
TAiIN input cycle time
tw(TAH)
TAiIN input high-level pulse width
tw(TAL)
TAiIN input low-level pulse width
Limits
Min.
8 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
Max.
Unit
ns
ns
ns
Timer A input (External trigger input in one-shot pulse mode)
Symbol
tc(TA)
Parameter
TAiIN input cycle time
Limits
Min.
8 ✕ 109
2 · f(f2)
Max.
Unit
ns
Timer B input (In pulse period measurement mode or pulse width measurement mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time
tw(TBH)
TBiIN input high-level pulse width
tw(TBL)
TBiIN input low-level pulse width
Limits
Min.
8 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
Max.
Unit
ns
ns
ns
Note. f(f2) represents the clock f2 frequency.
For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.
19
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PROM VERSION OF M37733MHBXXXFP
SWITCHING CHARACTERISTICS (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85°C, f(XIN) = 25 MHz (Note), unless otherwise noted)
Single-chip mode
Symbol
Parameter
Test conditions
td(E–P0Q)
Port P0 data output delay time
td(E–P1Q)
Port P1 data output delay time
td(E–P2Q)
Port P2 data output delay time
td(E–P3Q)
Port P3 data output delay time
Fig. 5
td(E–P4Q)
Port P4 data output delay time
td(E–P5Q)
Port P5 data output delay time
td(E–P6Q)
Port P6 data output delay time
td(E–P7Q)
Port P7 data output delay time
Port P8 data output delay time
td(E–P8Q)
Note. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
P0
P1
P2
P3
50 pF
P4
P5
P6
P7
P8
φ1
E
Fig. 5 Measuring circuit for ports P0 – P8 and φ1
20
Limits
Min.
Max.
80
80
80
80
80
80
80
80
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
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PROM VERSION OF M37733MHBXXXFP
Memory expansion mode and microprocessor mode
(VCC = 5 V ± 10%, VSS = 0 V, Ta = 25 °C, f(XIN) = 25 MHz (Note 1), unless otherwise noted)
Symbol
td(An–E)
td(A–E)
Parameter
Address output delay time
Address output delay time
th(E–An)
Address hold time
tw(ALE)
ALE pulse width
tsu(A–ALE)
th(ALE–A)
Address output setup time
Address hold time
td(ALE–E)
ALE output delay time
td(E–DQ)
th(E–DQ)
Data output delay time
Data hold time
tw(EL)
tpxz(E–DZ)
tpzx(E–DZ)
_
E pulse width
BHE output delay time
_
td(R/W–E)
R/ W output delay time
___
th(E–BHE)
th(E–R/W)
td(E–φ1)
td(φ1–HLDA)
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
Fig. 5
Limits
Min.
Max.
No wait
Wait 1
Wait 0
ns
87
ns
12
ns
75
ns
18
ns
22
ns
57
ns
5
ns
45
ns
9
ns
15
ns
4
ns
18
50
ns
ns
ns
ns
130
ns
10
20
ns
ns
12
ns
87
ns
12
ns
87
18
18
0
ns
ns
ns
ns
ns
5
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
BHE
hold time
_
R/ W hold time
φ1 output delay time
____
HLDA output delay time
Unit
12
45
Floating start delay time
Floating release delay time
___
td(BHE–E)
Test
(Note 2)
Wait mode conditions
No wait
Wait 1
Wait 0
No wait
Wait 1
Wait 0
18
50
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 12.5 MHz.
2. No wait : Wait bit = “1”.
Wait 1 : The external memory area is accessed with wait bit = “0” and wait selection bit = “1”.
Wait 0 : The external memory area is accessed with wait bit = “0” and wait selection bit = “0”.
21
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PROM VERSION OF M37733MHBXXXFP
Memory expansion mode and microprocessor mode
Bus timing data formulas (VCC = 5 V ± 10%, VSS = 0 V, Ta = –20 to 85 °C,
Symbol
td(An–E)
Parameter
Address output delay time
f(XIN) = 25 MHz (Max., Note 1), unless otherwise noted)
Wait mode
No wait
Wait 1
Wait 0
td(A–E)
Address output delay time
No wait
Wait 1
Wait 0
th(E–An)
Address hold time
tw(ALE)
ALE pulse width
No wait
Wait 1
Wait 0
tsu(A–ALE)
Address output setup time
No wait
Wait 1
Wait 0
th(ALE–A)
Address hold time
No wait
Wait 1
ALE output delay time
No wait
Wait 1
Wait 0
td(ALE–E)
Wait 0
td(E–DQ)
th(E–DQ)
No wait
tpxz(E–DZ)
Floating start delay time
tpzx(E–DZ)
Floating release delay time
___
td(BHE–E)
BHE output delay time
Wait 1
Wait 0
_
R/W output delay time
No wait
Wait 1
No wait
Wait 1
Wait 0
___
th(E–BHE)
BHE hold time
_
th(E–R/W)
R/W hold time
td(E–φ1)
φ1 output delay time
1 ✕ 109
2 · f(f2)
2 ✕ 109
2 · f(f2)
4 ✕ 109
2 · f(f2)
1 ✕ 109
2 · f(f2)
1 ✕ 109
2 · f(f2)
3 ✕ 109
2 · f(f2)
1 ✕ 109
2 · f(f2)
3 ✕ 109
2 · f(f2)
1 ✕ 109
2 · f(f2)
1 ✕ 109
2 · f(f2)
0
Notes 1. This applies when the main-clock division selection bit = “0”.
2. f(f2) represents the clock f2 frequency.
For the relation to the main clock and sub clock, refer to Table 9 in data sheet “M37733MHBXXXFP”.
22
ns
ns
ns
ns
ns
ns
ns
ns
– 25
ns
ns
– 30
ns
ns
– 22
ns
– 30
ns
– 30
ns
5
Wait 0
td(R/W–E)
ns
4
1 ✕ 109
2 · f(f2)
Unit
ns
45
Data hold time
E pulse width
Max.
9
1 ✕ 109
2 · f(f2)
Data output delay time
_
tw(EL)
Limits
Min.
1 ✕ 109
– 28
2 · f(f2)
3 ✕ 109
– 33
2 · f(f2)
1 ✕ 109
– 28
2 · f(f2)
3 ✕ 109
– 45
2 · f(f2)
9
1 ✕ 10
– 22
2 · f(f2)
9
1 ✕ 10
– 18
2 · f(f2)
9
2 ✕ 10
– 23
2 · f(f2)
9
1 ✕ 10
– 35
2 · f(f2)
9
2 ✕ 10
– 35
2 · f(f2)
ns
– 20
ns
– 28
ns
– 33
ns
– 28
ns
– 33
ns
– 22
ns
– 22
ns
18
ns
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TIMING DIAGRAM
PROM VERSION OF M37733MHBXXXFP
tr
tf
tc
tw(H)
tw(L)
XIN
E
td(E–P0Q)
Port P0 output
tsu(P0D–E)
th(E–P0D)
Port P0 input
td(E–P1Q)
Port P1 output
tsu(P1D–E)
th(E–P1D)
Port P1 input
td(E–P2Q)
Port P2 output
tsu(P2D–E)
th(E–P2D)
Port P2 input
td(E–P3Q)
Port P3 output
tsu(P3D–E)
th(E–P3D)
Port P3 input
td(E–P4Q)
Port P4 output
tsu(P4D–E)
th(E–P4D)
Port P4 input
td(E–P5Q)
Port P5 output
tsu(P5D–E)
th(E–P5D)
Port P5 input
td(E–P6Q)
Port P6 output
tsu(P6D–E)
th(E–P6D)
Port P6 input
td(E–P7Q)
Port P7 output
tsu(P7D–E)
th(E–P7D)
Port P7 input
td(E–P8Q)
Port P8 output
tsu(P8D–E)
th(E–P8D)
Port P8 input
23
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PROM VERSION OF M37733MHBXXXFP
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
In event counter mode TAiOUT input
(Up-down input)
TAiIN input
(when count by falling)
TAiIN input
(when count by rising)
th(TIN–UP)
tsu(UP–TIN)
In event counter mode
(When two-phase pulse input is selected)
tc(TA)
TAjIN input
tsu(TAjIN–TAjOUT)
tsu(TAjIN–TAjOUT)
tsu(TAjOUT–TAjIN)
TAjOUT input
tsu(TAjOUT–TAjIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
24
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PROM VERSION OF M37733MHBXXXFP
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
th(C–D)
RxDi
tw(INL)
INTi input
Kli input
tw(INH)
tw(KNL)
25
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PROM VERSION OF M37733MHBXXXFP
Memory expansion mode and microprocessor mode
(When wait bit = “1”)
φ1
E
RDY input
tsu(RDY–φ1) th(φ1–RDY)
( When wait bit = “0”)
φ1
E
RDY input
tsu(RDY–φ1) th(φ1–RDY)
(When wait bit = “1” or “0” in common)
φ1
tsu(HOLD–φ1)
th(φ1–HOLD)
HOLD input
td(φ1–HLDA)
HLDA output
Test conditions
• VCC = 5 V ± 10%
• Input timing voltage : V IL = 1.0 V, VIH = 4.0 V
• Output timing voltage : V OL = 0.8 V, VOH = 2.0 V
26
td(φ1–HLDA)
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PROM VERSION OF M37733MHBXXXFP
Memory expansion mode and microprocessor mode
(No wait : When wait bit = “1”)
tw(L)
tw(H)
tf
tr
tc
XIN
φ1
td(E-φ1)
td(E-φ1)
tw(EL)
E
td(An-E)
An
th(E-An)
Address
tw(ALE)
Address
Address
td(ALE-E)
ALE
th(ALE-A)
th(E-DQ)
tsu(A-ALE)
Am/Dm
Address
Data
tpxz(E-DZ)
tpzx(E-DZ)
Address
Address
th(E-D)
td(E-DQ)
td(A-E)
tsu(D-E)
DmIN
Data
td(BHE-E)
th(E-BHE)
BHE
td(R/W-E)
th(E-R/W)
R/W
Test conditions
• VCC = 5 V ± 10%
• Output timing voltage : VOL = 0.8 V, VOH = 2.0 V
• Data input DmIN : VIL = 0.8 V, VIH = 2.5 V
27
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PROM VERSION OF M37733MHBXXXFP
Memory expansion mode and microprocessor mode
(Wait 1 : The external memory area is accessed when wait bit = “0” and wait selection bit = “1”.)
tw(L)
tw(H)
tf tr
tc
XIN
φ1
td(E–φ1)
td(E–φ1)
tw(EL)
E
td(An–E)
th(E–An)
Address
An
tw(ALE)
Address
td(ALE–E)
ALE
th(ALE–A)
tsu(A–ALE)
Am/Dm
th(E–DQ)
Address
td(A–E)
Data
tpzx(E–DZ)
tpxz(E–DZ)
Address
Address
td(E–DQ)
th(E–D)
tsu(D–E)
DmIN
Data
td(BHE–E)
th(E–BHE)
td(R/W–E)
th(E–R/W)
BHE
R/W
Test conditions
• Vcc = 5 V ± 10%
• Output timing voltage : V OL = 0.8 V, V OH = 2.0 V
• Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V
28
MITSUBISHI MICROCOMPUTERS
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PROM VERSION OF M37733MHBXXXFP
Memory expansion mode and microprocessor mode
(Wait 0 : The external memory area is accessed when wait bit = “0” and wait selection bit = “0”.)
tw(L)
tw(H)
tf tr
tc
XIN
φ1
td(E–φ1)
td(E–φ1)
tw(EL)
E
td(An–E)
th(E–An)
Address
An
tw(ALE)
td(ALE–E)
tsu(A–ALE)
th(ALE–A)
Address
Address
ALE
th(E–DQ)
Am/Dm
Address
Data
tpzx(E–DZ)
tpxz(E–DZ)
Address
Address
td(E–DQ)
td(A–E)
tsu(D–E)
th(E–D)
Data
DmIN
td(BHE–E)
th(E–BHE)
BHE
td(R/W–E)
th(E–R/W)
R/W
Test conditions
• Vcc = 5 V ± 10%
• Output timing voltage : V OL = 0.8 V, V OH = 2.0 V
• Data input Dm IN : VIL = 0.8 V, VIH = 2.5 V
29
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PACKAGE OUTLINE
30
MITSUBISHI MICROCOMPUTERS
M37733EHBXXXFP
M37733EHBFS
PROM VERSION OF M37733MHBXXXFP
GZZ–SH00–80B<84A0>
ROM number
7700 FAMILY WRITING TO PROM ORDER CONFIRMATION FORM
SINGLE-CHIP 16-BIT MICROCOMPUTER
M37733EHBXXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Section head Supervisor
signature
signature
TEL
(
Company
name
Customer
Date
issued
)
Date:
Issuance
signatures
Note : Please fill in all items marked
Responsible
officer
Supervisor
1. Confirmation
Specify the name of the product being ordered and the type of EPROMs submitted.
Three sets of EPROMs are required for each pattern.
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce writing to PROM based on this
data. We shall assume the responsibility for errors only if the written PROM data on the products we produce differ from this data.
Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM areas
(hexadecimal notation)
EPROM Type :
(1) Set “FF 16” in the shaded area.
27C201
(2) Address 0 16 to 0F16 are the area for storing the data on
model designation.This area must be written with the data
shown below.
Address and data are written in hexadecimal notation.
00000
00010
20000
128K
DATA
3FFFF
Note : Make sure that address 01FFFF16
of the microcomputer’s internal
ROM corresponds to address
3FFFF16 of EPROM.
4D
33
37
37
33
33
45
48
Address
0
1
2
3
4
5
6
7
42
FF
FF
FF
FF
FF
FF
FF
Address
8
9
A
B
C
D
E
F
2. Mark specification
Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate
80P6N Mark Specification Form (for M37733EHBXXXFP) and attach to the Writing to PROM Order Confirmation Form.
3. Comments
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
64
41
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
25
80
1
24
B. Customer’s Parts Number + Mitsubishi IC Catalog Name
64
41
40
65
25
80
1
24
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Notes 1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s parts number can be up to 14 alphanumeric characters for capital letters, hyphens, commas, periods and so on.
4 : If the Mitsubishi logo
is not required, check the box below.
Mitsubishi logo is not required
C. Special Mark Required
64
41
65
40
80
25
1
Notes1 : If special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be
duplicated technically as close as possible.
Mitsubishi product number (6-digit, or 7-digit) and Mask
ROM number (3-digit) are always marked for sorting the
products.
2 : If special character fonts (e,g., customer’s trade mark
logo) must be used in Special Mark, check the box below.
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
24
Special character fonts required
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MITSUBISHI MICROCOMPUTERS
M37733EHBXXXFP
M37733EHBFS
PROM VERSION OF M37733MHBXXXFP
Keep safety first in your circuit designs!
¡ Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
¡ These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
¡ Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
¡ All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
¡ Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
¡ The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
¡ If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
¡ Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1996 MITSUBISHI ELECTRIC CORP.
H-LF449-A KI-9610 Printed in Japan (ROD) 2
New publication, effective Oct. 1996.
32
Specifications
subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
M37733EHBXXXFP, M37733EHBFS Datasheet
Rev.
date
Revision Description
1.00
First Edition
970604
1.01
The following are added:
980526
• PROM ORDER CONFIRMATION FORM
• MARK SPECIFICATION FORM
2.00
The following are revised:
Page
P12
Right
Column
Line 2
980731
Previous Version
Revised Version
The M37733EHBXXXFP has 28 powerful
addressing modes. Refer to the MITSUBISHI
SEMICONDUCTORS DATA BOOK SINGLECHIP 16-BIT MICROCOMPUTERS for the details
of each addressing mode.
The M37733EHBXXXFP has 28 powerful
addressing modes. Refer to the “7700 Family
Software Manual” for the details.
MACHINE INSTRUCTION LIST
The M37733EHBXXXFP has 103 machine
instructions. Refer to the MITSUBISHI
SEMICONDUCTORS DATA BOOK SINGLECHIP 16-BIT MICROCOMPUTERS for details.
(1)
MACHINE INSTRUCTION LIST
The M37733EHBXXXFP has 103 machine
instructions. Refer to the “7700 Family Software
Manual” for the details.