Fairchild FDC658P Single p-channel, logic level, powertrenchtm mosfet Datasheet

February 1999
FDC658P
Single P-Channel, Logic Level, PowerTrenchTM MOSFET
General Description
Features
This P-Channel Logic Level MOSFET is produced
using
Fairchild
Semiconductor's
advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
low gate charge for superior switching performance.
These devices are well suited for notebook computer
applications: load switching and power management,
battery charging circuits, and DC/DC conversion.
SuperSOTTM-6
SOT-23
SuperSOTTM-8
-4 A, -30 V. RDS(ON) = 0.050 Ω @ VGS = -10 V
RDS(ON) = 0.075 Ω @ VGS = -4.5 V.
Low gate charge (8nC typical).
High performance trench technology for extremely low
RDS(ON).
SuperSOTTM-6 package: small footprint (72% smaller than
standard SO-8); low profile (1mm thick).
SOIC-16
SOT-223
SO-8
S
1
6
8
.65
2
5
3
4
D
D
G
D
SuperSOT
TM
-6
pin 1
Absolute Maximum Ratings
Symbol
Parameter
VDSS
D
TA = 25°C unless otherwise note
Ratings
Units
Drain-Source Voltage
-30
V
VGSS
Gate-Source Voltage - Continuous
±20
V
ID
Drain Current - Continuous
-4
A
(Note 1a)
- Pulsed
PD
Maximum Power Dissipation
-20
(Note 1a)
(Note 1b)
TJ,TSTG
Operating and Storage Temperature Range
1.6
W
0.8
-55 to 150
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
30
°C/W
© 1999 Fairchild Semiconductor Corporation
FDC658P Rev.C
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
-30
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
ID = -250 µA, Referenced to 25 C
IDSS
Zero Gate Voltage Drain Current
VDS = -24 V, VGS = 0 V
o
V
mV/oC
-22
TJ = 55 oC
-1
µA
-10
µA
IGSSF
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
100
nA
IGSSR
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
-100
nA
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
∆VGS(th)/∆TJ
Gate Threshold VoltageTemp.Coefficient
ID = -250 µA, Referenced to 25 oC
-1
RDS(ON)
Static Drain-Source On-Resistance
VGS = -10 V, ID = -4.0 A
TJ = 125 C
VGS = -4.5 V, ID = -3.4 A
On-State Drain Current
VGS = -10 V, VDS = -5 V
gFS
Forward Transconductance
VDS = -5V, ID = -4 A
-3
V
mV/oC
4.1
o
ID(on)
-1.7
0.041
0.05
0.058
0.08
0.06
0.075
-20
Ω
A
9
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
VDS = -15 V, VGS = 0 V,
750
pF
Coss
Output Capacitance
f = 1.0 MHz
220
pF
Crss
Reverse Transfer Capacitance
100
pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn - On Delay Time
VDD = -15 V, ID = -1 A,
12
22
ns
tr
Turn - On Rise Time
VGS = -10 V, RGEN = 6 Ω
14
25
ns
tD(off)
Turn - Off Delay Time
24
38
ns
tf
Turn - Off Fall Time
16
27
ns
Qg
Total Gate Charge
VDS = -15 V, ID = -4.0 A,
8
12
nC
Qgs
Gate-Source Charge
VGS = -5 V
Qgd
Gate-Drain Charge
1.8
nC
3
nC
DRAIN-SOURCE DIODE CHARACTERISTICS
IS
Continuous Source Diode Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -1.3 A
(Note 2)
-0.76
-1.3
A
-1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design.
a. 78oC/W when mounted on a 1 in2 pad of 2oz Cu on FR-4 board.
b. 156oC/W when mounted on a minimum pad of 2oz Cu on FR-4 board.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDC658P Rev.C
Typical Electrical Characteristics
16
R DS(on) , NORMALIZED
- ID , DRAIN-SOURCE CURRENT (A)
VGS= -10V
-6.0V
-4.5V
-4.0V
12
-3.5V
8
-3.0V
4
0
0
1
2
3
-VDS , DRAIN-SOURCE VOLTAGE (V)
DRAIN-SOURCE ON-RESISTANCE
2
20
1.8
VGS = -4.0 V
1.6
-4.5V
1.4
-6.0V
1.2
-8.0V
-10.0V
1
0.8
4
-5.0V
0
4
8
12
- I D , DRAIN CURRENT (A)
16
20
Figure 2. On-Resistance Variation with
Figure 1. On-Region Characteristics.
Drain Current and Gate Voltage.
0.16
I D = -4A
V GS = -10V
1.4
1.2
1
0.8
0.6
-50
ID = -2A
R DS(ON) , ON-RESISTANCE (OHM)
R DS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
1.6
0.12
0
25
50
75
100
T J , JUNCTION TEMPERATURE (°C)
125
150
- I D , DRAIN CURRENT (A)
V DS = -5V
TJ = -55°C
-IS , REVERSE DRAIN CURRENT (A)
20
125°C
25°C
12
8
4
1
0.04
TJ = 25°C
2
3
4
5
-VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
2
4
6
8
-V GS , GATE TO SOURCE VOLTAGE (V)
10
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
with Temperature.
0
TJ = 125°C
0
-25
Figure 3. On-Resistance Variation
16
0.08
6
20
10
VGS = 0V
TJ = 125°C
1
25°C
0.1
-55°C
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
-VSD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDC658P Rev.C
Typical Electrical Characteristics (continued)
3000
I D = -4A
8
VDS = -5V
-10V
CAPACITANCE (pF)
-VGS , GATE-SOURCE VOLTAGE (V)
10
-15V
6
4
1000
Ciss
300
Coss
2
0
0
3
6
9
Q g , GATE CHARGE (nC)
12
100
30
0.1
15
0.3
1
3
7
-V DS , DRAIN TO SOURCE VOLTAGE (V)
15
30
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
80
5
10
S
RD
(ON
)L
IMI
100
us
T
1m
s
10m
s
10
0m
s
1s
3
1
0.3
VGS = -10V
SINGLE PULSE
R θJA = 156°C/W
TA = 25°C
0.1
0.03
0.01
0.1
0.2
SINGLE PULSE
RθJA =156°C/W
TA = 25°C
4
POWER (W)
30
3
2
DC
1
0.5
1
2
5
10
20
50
0
0.01
0.1
1
10
100
300
SINGLE PULSE TIME (SEC)
-VDS , DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum Power
Dissipation.
TRANSIENT THERMAL RESISTANCE
1
r(t), NORMALIZED EFFECTIVE
-ID, DRAIN CURRENT (A)
Crss
f = 1 MHz
VGS = 0 V
0.5
D = 0.5
0.2
0.1
0.05
R θJA (t) = r(t) * R θJA
R θJA = 156°C/W
0.2
0.1
P(pk)
0.05
t1
0.02
0.02
0.01
t2
TJ - TA = P * R θJA (t)
0.01
Duty Cycle, D = t 1/ t 2
Single Pulse
0.005
0.00001
0.0001
0.001
0.01
0.1
1
10
100
300
t 1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDC658P Rev.C
SuperSOTTM-6 Tape and Reel Data and Package Dimensions
SSOT-6 Packaging
Configuration: Figure 1.0
Customize Label
Antistatic Cover Tape
Conductive Embossed
Carrier Tape
F63TNR
Label
631
Packaging Option
Packaging type
Standard
(no flow code)
TNR
Qty per Reel/Tube/Bag
3,000
Reel Size
631
631
D87Z
SSOT-6 Unit Orientation
TNR
10,000
7” Dia
13”
184x187x47
343x343x64
Max qty per Box
9,000
20,000
Weight per unit (gm)
0.0158
0.0158
Weight per Reel (kg)
0.1440
0.4700
Box Dimension (mm)
631
Pin 1
SSOT-6 Packaging Information
343mm x 342mm x 64mm
Intermediate box for D87Z Option
F63TNR Label
Note/Comments
F63TNR
Label
F63TNR Label sample
184mm x 184mm x 47mm
Pizza Box for Standard Option
F63TNR
Label
LOT: CBVK741B019
QTY: 3000
FSID: FDC633N
SPEC:
D/C1: D9842
D/C2:
Trailer
SSOT-6 Tape Leader
Configuration: Figure 2.0
QTY1:
QTY2:
SPEC REV:
CPN:
QARV:
(F63TNR)2
Carrier Tape
Cover Tape
 1998 Fairchild Semiconductor Corporation
Trailer Tape
160mm minimum
Components
Leader Tape
390mm minimum
December 1998, Rev. B
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SSOT-6 Embossed Carrier Tape
Configuration: Figure 3.0
P0
D0
T
E1
F
K0
Wc
W
E2
B0
Tc
A0
D1
P1
User Direction of Feed
Dimensions are in millimeter
Pkg type
A0
B0
SSOT-6
(8mm)
3.23
+/-0.10
3.18
+/-0.10
W
8.0
+/-0.3
D0
D1
E1
E2
1.55
+/-0.05
1.00
+/-0.125
1.75
+/-0.10
F
6.25
min
3.50
+/-0.05
P1
P0
4.0
+/-0.1
4.0
+/-0.1
K0
T
1.37
+/-0.10
0.255
+/-0.150
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
Wc
0.06
+/-0.02
0.5mm
maximum
20 deg maximum
Typical
component
cavity
center line
B0
5.2
+/-0.3
Tc
0.5mm
maximum
20 deg maximum component rotation
Typical
component
center line
Sketch A (Side or Front Sectional View)
A0
Component Rotation
Sketch C (Top View)
Component lateral movement
Sketch B (Top View)
SSOT-6 Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A
Max
Dim A
max
See detail AA
Dim N
7” Diameter Option
B Min
Dim C
See detail AA
W3
13” Diameter Option
Dim D
min
W2 max Measured at Hub
DETAIL AA
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 – 0.429
7.9 – 10.9
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
4.00
100
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 – 0.429
7.9 – 10.9
8mm
7” Dia
7.00
177.8
8mm
13” Dia
13.00
330
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
December 1998, Rev. B
SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SuperSOT-6 (FS PKG Code 31, 33)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0158
 1998 Fairchild Semiconductor Corporation
September 1998, Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
TinyLogic™
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
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be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
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Definition of Terms
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Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
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First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
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