IRF IR3541AMTRPBF Digital multi-phase buck controller pmbus address pin or variable gate drive Datasheet

Digital Multi-Phase Buck Controller
FEATURES
DESCRIPTION
 5-phase dual output PWM Controller
 Phases are flexibly assigned between Loops 1 & 2
 Intel® VR12, AMD® 400kHz & 3.4MHz SVI and
Memory modes
 Dual OCP support for I-spike enhanced AMD CPUs
 SMB_Alert Pin for Servers
 PMBus Address pin or Variable Gate Drive
 Overclocking & Gaming Mode with Vmax setting
 Switching frequency from 200kHz to 1.2MHz per
phase
 IR Efficiency Shaping Features including Variable
Gate Drive and Dynamic Phase Control
 Programmable 1-phase or 2-phase for Light Loads
and Active Diode Emulation for Very Light Loads
 IR Adaptive Transient Algorithm (ATA) on both
loops minimizes output bulk capacitors and
system cost
 Auto-Phase Detection with auto-compensation
 Per-Loop Fault Protection: OVP, UVP, OCP,
OTP, CFP
 I2C/SMBus/PMBus system interface for telemetry
of Temperature, Voltage, Current & Power for
both loops
 Non-Volatile Memory (NVM) for custom
configuration
 Compatible with IR ATL and 3.3V Tri-state Drivers
 +3.3V supply voltage; -20ºC to 85ºC ambient
operation
 Pb-Free, RoHS, 6x6 40-pin QFN, MSL2 package
IR3541A
A/B
The IR3541A is a dual-loop, digital multi-phase buck
controller that drive up to 5 phases. The IR3541A is fully
Intel® VR12 and AMD® SVI compliant on both loops and
provides a Vtt tracking function for DDR memory.
NVM storage saves pins and enables a small package size.
The IR3541A includes the IR Efficiency Shaping Technology
to deliver exceptional efficiency at minimum cost across the
entire load range. IR Variable Gate Drive optimizes the
MOSFET gate drive voltage as a function of real-time load
current. IR Dynamic Phase Control adds/drops active phases
based upon load current. The IR3541A can be configured to
enter 1-phase operation and active diode emulation mode
automatically or by command.
IR’s unique Adaptive Transient Algorithm (ATA), based on
proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors.
The I2C/PMBus interface can communicate with up to 16
IR3541A based VR loops. Device configuration and fault
parameters are easily defined using the IR Intuitive Power
Designer (DPDC) GUI and stored in
on-chip NVM.
The IR3541A also includes numerous features like register
diagnostics for fast design cycles and platform
differentiation, truly simplifying VRD design and enabling
fastest time-to-market with its “set-and-forget”
methodology.
PIN DIAGRAM
APPLICATIONS
 Intel ® VR12 & AMD® SVI based systems
 DDR Memory with Vtt tracking
IR3541A
 Overclocked & Gaming platforms
Figure 1: IR3541A Package Top View
1
June 21, 2013 | FINAL | V1.09
Digital Multi-Phase Buck Controller
IR3541A
A/B
ORDERING INFORMATION
IR3541AM         
Package
Packing
Qty
Part Number
QFN
TR=3000
TY=4900
IR3541AMTRPBF
IR3541AMTYPBF
QFN
TR=3000
IR3541AMxxyyTRP
P/PBF – Lead Free
TR – Tape & Reel / TY - Tray
yy – Configuration File ID
xx – Customer ID
IR3541A
Figure 2: IR3541A Package Top View, Enlarged
June 21, 2013 | FINAL | V1.09
Default
1
Customer
Configuration
Notes:
1. xx = Customer ID and yy = Configuration File
(Codes assigned by IR Marketing).
Package Type (QFN)
2
Programming
Digital Multi-Phase Buck Controller
FUNCTIONAL BLOCK DIAGRAM
V18A
RCSP_L2
IR3541A
A/B
VCC
VID_2
RSCM_L2
1.8V
AFE_2
LDO
VSEN_L2
VRTN_L2
ITOT_2
Vout1_Error
Voltage
ADC
RCSP
PWM1
RSCM
Vout2_Error
AFE_1
PWM2
VSEN
VID_1
VRTN
PWM3
PWM Generator
ISEN1
PWM4
IP1
Mode Control
IRTN1
PWM5
ISEN2
Control
and
Monitoring
IP2
IRTN2
Σ
ISEN3
Phase_
Period_1
Phase_
Period_2
VAR_GATE_PM_ADDR
(CHL8325A)
ITOT_1
IP3
IRTN3
ISEN4
Iout
IP4
Vin
IRTN4
ITOT_2
ISEN5
IP5
IRTN5
Σ
Vout
Temp
Current ADC
Fault Bus
System Clock
IP1
IP2
IP3
System Clock
ADC Clocks
IP4
MUX Clocks
IP5
Phase_Period_1
TSEN2
(CHL8325B)
Phase_Period_2
TSEN
VINSEN
Monitor ADC
V3_3
SMB_DIO
SMB_CLK
SV_CLK1/SVC2
SV_DIO1/SVD2
EN
Reference,
Oscillator,
State Control,
Interfaces,
Registers and
NVM
VID_1
VID_2
Iout
Vin
Temp
Fault Bus
SMB_ALERT#
SV_ALERT#1/VFIXEN2
VR_HOT#1/VRHOT_ICRIT#2
VR_READY_L11/PWRGD2
VR_READY_L21/PWROK2
Notes
1
Pin definition in Intel & MPoL modes
2
Pin definition in AMD mode
RRES
Figure 4: IR3541A Functional Block Diagram
3
June 21, 2013 | FINAL | V1.09
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