Ordering number : EN5815B CMOS IC LC72121, 72121M, 72121V PLL Frequency Synthesizers for Electronic Tuning Overview The LC72121 and the LC72121M and the LC72121V are high input sensitivity (20 mVrms at 130 MHz) PLL frequency synthesizers for 3 V systems. These ICs are serial data (CCB) compatible with the LC72131, and feature the improved input sensitivity and lower spurious radiation (provided by a redesigned ground system) required in high-performance AM/FM tuners. Functions • High-speed programmable divider — FMIN: 10 to 160 MHz ... Pulse swallower technique (With built-in divide-by-2 prescaler) — AMIN: 2 to 40 MHz ... Pulse swallower technique 0.5 to 10 MHz ... Direct division technique • IF counter — IFIN: 0.4 to 15 MHz ... For AM and FM IF counting • Reference frequency — One of 12 reference frequencies can be selected (using a 4.5 or 7.2 MHz crystal element) 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, and 100 kHz • Phase comparator — Supports dead zone control. — Built-in unlocked state detection circuit — Built-in deadlock clear circuit • An MOS transistor for an active low-pass filter is built in. • I/O ports — Output-only ports: 4 pins — I/O ports: 2 pins — Supports the output of a clock time base signal. • Operating ranges — Supply voltage: 2.7 to 3.6 V — Operating temperature: – 40 to 85°C • Package — DIP22S, MFP24S, SSOP24 • Comparison with the LC72131/M — Serial data compatible (CCB) — Identical pin functions — Two VSS pins were added. — The DIP version is pin compatible (VSS pins were inserted as the DIP22S NC pins.) — The MFP product provides a modified pin assignment (The MFP20 package was replaced by an MFP24 package, and extra VSS pins were added.) — The SSOP24 is a newly developed package that has the same pin assignment as the MFP24S product. • CCB is a trademark of SANYO ELECTRIC CO., LTD. • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. 10803AS (OT) /D3098HA (OT) /70398RM (OT) No. 5815-1/23 LC72121, 72121M, 72121V Package Dimensions unit: mm unit: mm 3059-DIP22S 3112-MFP24S [LC72121] [LC72121M] 12 13 24 6.35 7.6 1 5.4 0.25 7.62 6.4 22 11 0.48 1.78 1.5 0.15 0.625 1.8max 3.9max 12 12.6 0.1 0.95 1 3.3 0.51min 3.25 21.2 1.7 0.35 SANYO: DIP22S 1.0 0.8 SANYO: MFP24S unit: mm 3175A-SSOP24 1.0 [LC72121V] 24 0.5 7.6 5.6 13 12 1.6max 1 0.15 0.1 8.0 0.22 0.65 0.43 SANYO: SSOP24 Pin Assignments Top view No. 5815-2/23 LC72121, 72121M, 72121V Block Diagram No. 5815-3/23 LC72121, 72121M, 72121V Specifications Absolute Maximum Ratings at Ta = 25°C, VSSd = VSSa = VSSX = 0 V Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Maximum output current Allowable power dissipation Symbol Conditions Ratings Unit VDD max VDD –0.3 to +7.0 VIN1 max CE, DI, CL, AIN –0.3 to +7.0 V VIN2 max XIN, FMIN, AMIN, IFIN –0.3 to VDD +0.3 V V V VIN3 max IO1, IO2 –0.3 to +15 VO1 max DO –0.3 to +7.0 V VO2 max XOUT, PD –0.3 to VDD +0.3 V VO3 max BO1 to BO4, IO1, IO2, AOUT IO1 max DO, AOUT IO2 max BO1 to BO4, IO1, IO2 Pd max –0.3 to +15 V 0 to +6.0 (Ta ≤ 85°C) mA 0 to +10.0 mA DIP22S: 350 mW MFP24S: 200 mW SSOP24: 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Allowable Operating Ranges at Ta = – 40 to +85°C, VSSd = VSSa = VSSX = 0 V Parameter Supply voltage Input high-level voltage Input low-level voltage Output voltage Input frequency Input amplitude Guaranteed crystal oscillator frequency Symbol Conditions Ratings min typ Unit max VDD VDD 2.7 3.6 V VIH1 CE, DI, CL 0.7 VDD 6.5 V VIH2 IO1, IO2 V 0.7 VDD 13 VIL CE, DI, CL, IO1, IO2 0 0.3 VDD V VO1 DO 0 6.5 V VO2 BO1 to BO4, IO1, IO2, AOUT 0 13 V fIN1 XIN: VIN1 1 8 MHz fIN2 FMIN: VIN2 10 160 MHz fIN3 AMIN (SNS = 1): VIN3 2 40 MHz fIN4 AMIN (SNS = 0): VIN4 0.5 10 MHz fIN5 IFIN: VIN5 0.4 15 MHz VIN1 XIN: fIN1 200 800 mVrms mVrms VIN2-1 FMIN: f = 10 to 130 MHz 20 800 VIN2-2 FMIN: f = 130 to 160 MHz 40 800 mVrms VIN3 AMIN (SNS = 1): fIN3 40 800 mVrms VIN4 AMIN (SNS = 0): fIN4 40 800 mVrms VIN5-1 IFIN: fIN5, IFS = 1 40 800 mVrms VIN5-2 IFIN: fIN5, IFS = 0 70 800 mVrms 4 8 Xtal XIN, XOUT: * MHz Note: Recommended value for CI for the crystal oscillator element: CI ≤ 120Ω (4.5MHz), CI ≤ 70Ω (7.2MHz) Electrical Characteristics in the Allowable Operating Ranges Parameter Symbol Conditions Ratings min typ max Unit Rf1 XIN 1 MΩ Rf2 FMIN 500 kΩ Rf3 AMIN 500 kΩ Rf4 IFIN 250 Rpd1 FMIN 100 200 400 kΩ Rpd2 AMIN 100 200 400 kΩ Hysteresis VHIS CE, DI, CL Output high-level voltage VOH1 PD: IO = –1 mA Internal feedback resistance Internal pull-down resistance 0.1 VDD VDD – 1.0 kΩ V V Continued on next page. No. 5815-4/23 LC72121, 72121M, 72121V Continued from preceding page. Parameter Symbol VOL1 VOL2 Output low-level voltage VOL3 Input low-level current typ Unit max PD: IO = 1 mA 1.0 V BO1 to BO4, IO1, IO2: IO = 1 mA 0.2 V BO1 to BO4, IO1, IO2: IO = 8 mA 1.6 V DO: IO = 1 mA 0.2 V V DO: IO = 5 mA 1.0 0.5 V IIH1 CE, DI, CL: VI = 6.5 V 5.0 µA IIH2 IO1, IO2: VI = 13 V 5.0 µA IIH3 XIN: VI = VDD 1.3 8 µA IIH4 FMIN, AMIN: VI = VDD 2.5 15 µA IIH5 IFIN: VI = VDD 5.0 30 µA IIH6 AIN: VI = 6.5 V 200 nA IIL1 CE, DI, CL: VI = 0 V 5.0 µA IIL2 IO1, IO2: VI = 0 V 5.0 µA IIL3 XIN: VI = 0 V 1.3 8 µA IIL4 FMIN, AMIN: VI = 0 V 2.5 15 µA IIL5 IFIN: VI = 0 V 5.0 30 µA IIL6 AIN: VI = 0 V 200 nA BO1 to BO4, IO1, IO2, AOUT: VO = 13 V 5.0 µA IOFF1 Output off leakage current Ratings min AOUT: IO = 1 mA, AIN = 1.3 V VOL4 Input high-level current Conditions IOFF2 DO: VO = 6.5 V 5.0 µA High-level 3-state off leakage current IOFFH PD: VO = VDD 0.01 200 nA Low-level 3-state off leakage current IOFFL PD: VO = 0 V 0.01 200 nA Input capacitance Supply current CIN FMIN IDD1 VDD: Xtal = 7.2 MHz, fIN2 = 130 MHz, VIN2 = 20 mVrms 2.5 IDD2 VDD: PLL block stopped (PLL inhibit mode) Crystal oscillator operating (crystal frequency: 7.2 MHz) 0.3 IDD3 VDD: PLL block stopped, crystal oscillator stopped 6 pF 6 mA mA 10 µA Pin Descriptions Pin name Pin No. LC72121 Type LC72121M LC72121V XIN 1 1 XOUT 22 24 Xtal Function Equivalent circuit • Crystal oscillator element connections (4.5 or 7.2 MHz) • FMIN is selected when DVS in the serial data is set to 1. • Input frequency: 10 to 160 MHz FMIN 16 17 Local oscillator signal input • The signal is passed through an internal divide-by-two prescaler and then input to the swallow counter. • The divisor can be set to a value in the range 272 to 65535. Since the internal divide-by-two prescaler is used, the actual divisor will be twice the set value. • AMIN is selected when DVS in the serial data is set to 0. • When SNS in the serial data is set to 1: • Input frequency: 2 to 40 MHz • The signal is input to the swallow counter directly. AMIN 15 16 Local oscillator signal input • The divisor can be set to a value in the range 272 to 65535. The set value becomes the actual divisor. • When SNS in the serial data is set to 0: • Input frequency: 0.5 to 10 MHz • The signal is input to a 12-bit programmable divider directly. • The divisor can be set to a value in the range 4 to 4095. The set value becomes the actual divisor. Continued on next page. No. 5815-5/23 LC72121, 72121M, 72121V Continued from preceding page. Pin No. Pin name LC72121 LC72121M LC72121V CE 3 3 Chip enable • This pin must be set high to enable serial data input (DI) or serial data output (DO). DI 4 4 Input data • Input for serial data transferred from the controller CL 5 5 Clock • Clock used for data synchronization for serial data input (DI) and serial data output (DO). DO 6 6 Output data • Output for serial data transmitted to the controller. The content of the data transmitted is determined by DOC0 through DOC2. VDD 17 18 Power supply • LC72121 power supply (VDD 2.7 to 3.6 V) • The power on reset circuit operates when power is first applied. —— Type Function Equivalent circuit VSSX 2 2 Ground • Ground for the crystal oscillator circuit —— VSSa 21 22 Ground —— VSSd 14 15 Ground • Ground for the low-pass filter MOS transistor • Ground for the LC72121 digital systems other than those that use VSSa or VSSX. IO1 11 11 IO2 13 14 BO1 7 7 BO2 8 8 BO3 9 9 BO4 10 10 I/O port • Shared function I/O ports • The pin function is determined by IOC1 and IOC2 in the serial data. When the data value 0: Input port When the data value 1: Output port • When specified to function as an input port: The input pin state is reported to the controller through the DO pin. When the input state is low: The data will be 0: When the input state is high: The data will be 1: • When specified to function as an output port: The output state is determined by IO1 and IO2 in the serial data. When the data value is 0: The output state will be the open circuit state. When the data value is 1: The output state will be a low level. • These pins are set to input mode after a power on reset. Output port • Output-only ports • The output state is determined by BO1 through BO4 in the serial data. When the data value is 0: The output state will be the open circuit state. When the data value is 1: The output state will be a low level. • A time base signal (8 Hz) is output from BO1 when TBC in the serial data is set to 1. Charge pump output • PLL charge pump output A high level is output when the frequency of the local oscillator signal divided by N is higher than the reference frequency, and a low level is output when that frequency is lower. This pin goes to the highimpedance state when the frequencies match. PD 18 19 AIN 19 20 AOUT 20 21 Low-pass filter • Connections for the MOS transistor used for the PLL active low-pass amplifier filter. transistor IFIN 12 13 IF counter NC — 12 23 NC pin —— • The input frequency range is 0.4 to 15 MHz • The signal is passed directly to the IF counter. • The result is output, MSB first, through the DO pin. • Four measurement periods are supported: 4, 8, 32, and 64 ms. • No connection —— No. 5815-6/23 LC72121, 72121M, 72121V Procedures for Input and Output of Serial Data This product uses the CCB (Computer Control Bus), which is Sanyo’s audio product serial bus format, for data input and output. This product adopts an 8-bit address CCB format. I/O mode 1 2 3 IN1 (82) IN2 (92) OUT (A2) Address Function B0 B1 B2 B3 A0 A1 A2 A3 0 0 0 1 0 1 0 0 • Control data input (serial data input) mode • 24 bits of data are input. • See the “DI Control Data (serial data input)” section for details on the content of the input data. 0 • Control data input (serial data input) mode • 24 bits of data are input. • See the “DI Control Data (serial data input)” section for details on the content of the input data. 0 • Data output (serial data output) mode • The number of bits output is equal to the number of clock cycles. • See the “DO output Data (serial data output)” section for details on the content of the output data. 1 0 0 1 0 0 1 1 0 0 1 1 0 0 I/O mode determined Normally high Normally low No. 5815-7/23 LC72121, 72121M, 72121V Structure of the DI Control Data (serial data input) • IN1 mode • IN2 mode No. 5815-8/23 LC72121, 72121M, 72121V DI Control Data No. Control block/data Function Related data • Specifies the divisor for the programmable divider. This is a binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS. (* : don’t care) DVS Programmable divider data 1 SNS LSB Set divisor (N) Actual divisor 1 * P0 272 to 65535 Twice the set value 0 1 P0 272 to 65535 The set value 0 0 P4 4 to 4095 The set value * LSB: When P4 is the LSB, P0 to P3 are ignored. P0 to P15 DVS, SNS • These pins select the signal input to the programmable divider (FMIN or AMIN) and switch the input frequency range. (* : don’t care) DVS SNS Input pin Frequency range accepted by the input pin 10 to 160 MHz 1 * FMIN 0 1 AMIN 2 to 40 MHz 0 0 AMIN 0.5 to 10 MHz * See the “Structure of the Programmable Divider” section for details. • Reference frequency selection Reference divider data 2 R0 to R3 XS R3 R2 R1 R0 0 0 0 0 Reference frequency 100 0 0 0 1 50 0 0 1 0 25 0 0 1 1 25 0 1 0 0 12.5 0 1 0 1 6.25 0 1 1 0 3.125 0 1 1 1 1 0 0 0 10 1 0 0 1 9 1 0 1 0 5 1 0 1 1 1 1 1 0 0 3 1 1 0 1 15 1 1 1 0 PLL INHIBIT + Xtal OSC STOP 1 1 1 1 PLL INHIBIT kHz 3.125 * PLL INHIBIT mode In this mode, the programmable divider and the IF counter block are stopped, the FMIN, AMIN, and IFIN pins are pulled down to ground, and the charge pump output goes to the high-impedance state. • Crystal oscillator element selection data XS = 0: 4.5 MHz XS = 1: 7.2 MHz Note that 7.2 MHz is selected after a power on reset. • IF counter measurement start command data CTE = 1: Starts the counter CTE = 0: Resets the counter IF counter control data 3 • Determines the IF counter measurement time. GT1 GT0 Measurement time Wait time CTE 0 0 4 ms 3 to 4 ms GT0, GT1 0 1 8 3 to 4 1 0 32 7 to 8 1 1 64 7 to 8 IFS * See the “Structure of the IF Counter” section for details. Continued on next page. No. 5815-9/23 LC72121, 72121M, 72121V Continued from preceding page. No. Control block/data 4 I/O port setup data IOC1,IOC2 5 Output port data BO1 to BO4 IO1,IO2 Function Related data • Specifies input or output for the shared function I/O pins (IO1 and IO2). Data = 0: Input port Data = 1: Output port • Determines the output state of the BO1 through BO4, IO1, and IO2 output ports. Data = 0: Open Data = 1: Low level • The data is reset to 0, setting the pins to the open state, after a power on reset. IOC1 IOC2 • Determines the DO pin output. 6 DOC2 DOC1 DOC0 0 0 0 DO pin state Open 0 0 1 Low when the PLL is unlocked 0 1 0 end-UC *1 0 1 1 Open 1 0 0 Open 1 0 1 The IO1 pin state *2 1 1 0 The IO2 pin state *2 1 1 1 Open UL0, UL1 The open state is selected after a power on reset. DO pin control data *1. end-UC: IF counter measurement end check DOC0 CTE DOC1 IOC1 DOC2 IOC2 (1)When end-UC is selected and an IF count is started (by switching CTE from 0 to 1), the DO pin automatically goes to the open state. (2)When the IF counter measurement period completes, the DO pin goes to the low level, allowing applications to test for the completion of the count period. (3)The DO pin is set to the open state by performing a serial data input or output operation (when the CE pin is set high). *2. The DO pin will go to the open state if the corresponding IO pin is set up to be an output port. Note: During the data input period (the period that CE is high in IN1 or IN2 mode), the DO pin goes to the open state regardless of the DO pin control data (DOC0 to DOC2). During the data output period (the period that CE is high in OUT mode) the DO pin state reflects the internal DO serial data in synchronization with the CL clock, regardless of the DO pin control data (DOC0 to DOC2). • Selects the width of the phase error (øE) detected for PLL lock state discrimination. The state is taken to be unlocked if a phase error in excess of the detection width occurs. 7 Unlocked state detection data UL0, UL1 UL1 UL0 øE detection width Detection output 0 0 Stopped Open 0 1 0 øE is output directly 1 0 ±0.55 µs øE is extended by 1 to 2 ms 1 1 ±1.11 µs øE is extended by 1 to 2 ms DOC0 DOC1 DOC2 * When the PLL is unlocked, the DO pin goes low and UL in the serial data output is set to 0. • Controls the phase comparator dead zone 8 DZ1 DZ Dead zone mode Phase comparator control data 0 0 DZA 0 1 DZB DZ0, DZ1 1 0 DZC 1 1 DZD Dead zone width: DZA < DZB < DZC < DZD Continued on next page. No. 5815-10/23 LC72121, 72121M, 72121V Continued from preceding page. No. 9 Control block/data Clock time base TBC Function • Setting the TBC bit to 1 causes an 8-Hz clock time base signal with a 40% duty to be output from the BO1 pin. (The BO1 data will be ignored.) Related data BO1 • Forcibly controls the charge pump output. 10 Charge pump control data DLC 11 IF counter control data IFS 12 13 Test data TEST0 to 2 DNC DLC Charge pump output 0 Normal operation 1 Forced to low * If the circuit deadlocks due to the VCO control voltage (Vtune) being 0 and the VCO being stopped, applications can get out of the deadlocked state by setting the charge pump output to low and setting Vtune to VCC. (Deadlock clear circuit) • This data is normally set to 1. Setting this data to 0 sets the circuit to reduced input sensitivity mode, in which the sensitivity is reduced by about 10 to 30 mV rms. * See the “IF Counter Operation” section for details. • Test data TEST0 TEST1 All these bits must be set to 0. TEST2 All these bits are set to 0 after a power on reset. • This bit must be set to 0. Structure of the DO Output Data (serial data output) • OUT mode DO Output Data No. 1 Control block/data I/O port data 12, I1 2 PLL unlocked state data 3 IF counter binary data UL C19 to C0 Function Related data • Data latched from the I/O port IO1 or IO2 pin states. • These bits reflect the pin states regardless of the I/O port mode (input or output). The data is latched at the point the circuit enters data output mode (OUT mode). H:1 I1 ← The IO1 pin state I2 ← The IO2 pin state L:0 IOC1 IOC2 • Indicates the state of the unlocked state detection circuit. UL ← 0: When the PLL is unlocked. UL ← 1: When the PLL is locked or in the detection disabled mode. UL0 UL1 • Indicates the value of the IF counter (20-bit binary counter). C19 ← MSB of the binary counter C0 ← LSB of the binary counter CTE GT0 GT1 No. 5815-11/23 LC72121, 72121M, 72121V Serial Data Input (IN1/IN2) tSU, tHD, tEL, tES, tEH ≥ 0.75 µs tLC < 0.75 µs • CL: Normally high • CL: Normally low Serial Data Output (Out) tSU, tHD, tEL, tES, tEH ≥ 0.75 µs tDC, tDH < 0.35 µs • CL: Normally high • CL: Normally low Note: The data conversion times (tDC and tDH) depend on the value of the pull-up resistor and the printed circuit board capacitance since the DO pin is an n-channel open-drain circuit. No. 5815-12/23 LC72121, 72121M, 72121V Serial Data Timing When CL is Stopped at the Low Level When CL is Stopped at the High Level Parameter Symbol Conditions Ratings min typ max Unit Data setup time tSU DI, CL 0.75 µs Data hold time tHD DI, CL 0.75 µs Clock low level time tCL CL 0.75 µs Clock high level time tCH CL 0.75 µs CE wait time tEL CE, CL 0.75 µs CE setup time tES CE, CL 0.75 µs CE hold time tEH CE, CL 0.75 Data latch change time tLC Data output time µs 0.75 µs tDC DO, CL These values differ depending on the value of the pull-up 0.35 µs tDH DO, CE resistor used and the printed circuit board capacitance. 0.35 µs No. 5815-13/23 LC72121, 72121M, 72121V Structure of the Programmable Divider DVS SNS Input pin Set divisor Actual divisor Input frequency range A 1 * FMIN 272 to 65535 Twice the set value 10 to 160 MHz B 0 1 AMIN 272 to 65535 The set value 2 to 40 MHz C 0 0 AMIN 4 to 4095 The set value 0.5 to 10 MHz *: Don’t care Sample Programmable Divider Divisor Calculations • For FM with a step size of 50 kHz (DVS = 1, SNS = *: FMIN selected) FM RF = 90.0 MHz (IF +10.7 MHz) FM VCO = 100.7 MHz PLL fref = 25 kHz (R0 = 0, R1 = 1, R2 = 0, R3 = 0) 100.7 MHz (FM VCO) ÷ 25 kHz (fref) ÷ 2 (for the FMIN 1/2 prescaler) 2014 → 07DE (hexadecimal) • For SW with a step size of 5 kHz (DVS = 0, SNS = 1: AMIN high-speed operation selected) SW RF = 21.75 MHz (IF +450 kHz) SW VCO = 22.20 MHz PLL fref = 5 kHz (R0 = 0, R1 = 1, R2 = 0, R3 = 1) 22.2 MHz (SW VCO) ÷ 5 kHz (fref) = 4440 → 1158 (hexadecimal) • For MW with a step size of 9 kHz (DVS = 0, SNS = 0: AMIN low-speed operation selected) MW RF = 1008 kHz (IF +450 kHz) WM VCO = 1458 kHz PLL fref =9 kHz (R0 = 1, R1 = 0, R2 = 0, R3 = 1) 1458 (MW VCO) ÷ 9 kHz (fref) = 162 → 0A2 (hexadecimal) No. 5815-14/23 LC72121, 72121M, 72121V Structure of the IF Counter The LC72121 IF counter is a 20-bit binary counter, and takes the IF signal from the IFIN pin as its input. The result of the count can be read out serially, MSB first, from the DO pin. GT1 GT0 0 Measurement time Measurement time (GT) Wait time (tWU) 0 4 ms 3 to 4 ms 0 1 8 3 to 4 ms 1 0 32 7 to 8 ms 1 1 64 7 to 8 ms The IF frequency (Fc) is measured by determining how many pulses were input to the IF counter in the stipulated measurement time, GT. C (C = Fc x GT) Fc =—— GT C: Counted value (the number of pulses) IF Counter Frequency Measurement Examples • When the measurement time (GT) is 32 ms and the counted value (C) is 53980 (hexadecimal) or 342,400 (decimal). IF frequency (FC) = 342400 ÷ 32 ms = 10.7 MHz • When the measurement time (GT) is 8 ms and the counted value (C) is E10 (hexadecimal) or 3600 (decimal). IF frequency (FC) = 3600 ÷ 8 ms = 450 kHz No. 5815-15/23 LC72121, 72121M, 72121V IF Counter Operation Applications must first, before starting an IF count operation reset the IF counter by setting CTE in the serial data to 0. The IF counter operation is started setting CTE in the serial data from 0 to 1. Although the serial data is latched by dropping the CE pin from high to low, the IF signal input to the IFIN pin must be provided within the wait time from the point CE goes low. Next, the readout of the IF counter after measurement is complete must be performed while CTE is still 1, since the counter will be reset if CTE is set to 0. Note: If IF counting is used, applications must determine whether or not the IF IC SD (station detect) signal is present in the microcontroller software, and perform the IF count only if that signal is asserted. This is because auto-search techniques that use IF counting only are subject to incorrect stopping at points where there is no station due to IF buffer leakage. Note that the LC72121 input sensitivity can be controlled with the IFS bit in the serial data. Reduced sensitivity mode (IFS = 0) must be selected when this IC is used in conjunction with an IF IC that does not provide an SD output and auto-search is implemented using only IF counting. IFIN Minimum Sensitivity Standard Input frequency : f [MHz] IFS data 0.4 ≤ f < 0.5 0.5 ≤ f < 8 8 ≤ f ≤ 15 1(Normal mode) 40 mVrms (0.1 to 3 mVrms) 40 mVrms 40 mVrms (1 to 15 mVrms) 0 (Degraded sensitivity mode) 70 mVrms (5 to 10 mVrms) 70 mVrms 70 Vrms (30 to 40 mVrms) Note: Values in parentheses are actual performance values that are provided for reference purposes. No. 5815-16/23 LC72121, 72121M, 72121V Unlocked State Detection Timing • Unlocked state detection timing Unlocked state detection is performed during the reference frequency (fref) period (interval). This means that a period at least as long as the period of the reference frequency is required to recognize the locked/unlocked state. However, applications must wait at least twice the period of the reference frequency immediately after changing the divisor (N) before checking the locked/unlocked state. Figure 1 Unlocked State Detection Timing For example, if fref is 1 kHz (a period of 1 ms) applications must wait at least 2 ms after the divisor N is changed before performing a locked/unlocked check. Figure 2 Circuit Structure No. 5815-17/23 LC72121, 72121M, 72121V Figure 3 Combining with Software • Outputting the unlocked state data in the serial data At the point of data output 1 in figure 3, the unlocked state data will indicate the unlocked state, since the VCO frequency is not stable (locked) yet. In cases such as this, the application should wait at least one whole period and then check again whether or not the frequency has stabilized with the data output 2 operation in the figure. Applications can implement even more reliable recognition of the locked state by performing several more checks of the state and requiring that the locked state be detected sequentially. <Flowchart for Lock Detection> Divisor N changed (data input) Wait at least 2 reference frequency periods. Data output (1) Valid output data is acquired by using an interval of at least one reference frequency period. Data output (2) *: Even more reliable recognition of the locked state can be achieved by performing several checks of the state and requiring that the locked state be detected sequentially. Locked state check * NO YES A10180 • Directly outputting the unlocked state to the DO pin Since the unlocked state (high level when locked, low when unlocked) is output from the DO pin, applications can check for the locked state by waiting at least two reference frequency periods after changing the divisor N. However, in this case also, even more reliable recognition of the locked state can be achieved by performing several checks of the state and requiring that the locked state be detected sequentially. No. 5815-18/23 LC72121, 72121M, 72121V Clock Time Base Usage Notes When using the clock time base output function, the output pin (BO1) pull-up resistor must have a value of over 100 kΩ. The use of a Schmitt input in the microcontroller that accepts this signal is recommended to reduce chattering. This is to prevent degradation of the VCO C/N characteristics when combining with a loop filter that uses the internal transistor provided to form a low-pass filter. Although the ground for the clock time base output pin (VSSd) and the ground for the transistor (VSSa) are isolated internally on the chip, applications must take care to avoid ground loops and minimize current fluctuations in the time base pin to prevent degradation of the low-pass filter characteristics. Pin States after a Power on Reset No. 5815-19/23 LC72121, 72121M, 72121V Sample Application Circuit (Using the DIP22S package) Since this is a high-impedance circuit, it is susceptible to noise. Therefore, lines in the printed circuit board pattern should be made as short as possible and it should be surrounded by the ground pattern. No. 5815-20/23 LC72121, 72121M, 72121V Other Items • Notes on the phase comparator dead zone DZ1 DZ0 Dead zone mode Charge pump Dead zone 0 0 DZA ON/ON – –0s 0 1 DZB ON/ON –0s 1 0 DZC OFF/OFF +0s 1 1 DZD OFF/OFF + +0s When the charge pump is used with one of the ON/ON modes, correction pulses are generated from the charge pump even if the PLL is locked. As a result, it is easy for the loop to become unstable, and special care is required in application design. The following problems can occur if an ON/ON mode is used. — Sidebands may be created by reference frequency leakage. — Sidebands may be created by low-frequency leakage due to the correction pulse envelope. Although the loop is more stable when a dead zone is present (i.e. when an OFF/OFF mode is used), a dead zone makes it more difficult to achieve excellent C/N characteristics. On the other hand, while it is easy to achieve good C/N characteristics when there is no dead zone, achieving good loop stability is difficult. Accordingly, the DZA and DZB settings, in which there is no dead zone, can be effective in situations where a signal-to-noise ratio of 90 to 100 dB or higher is required in FM reception, or where it is desirable to increase the pilot margin in AM stereo reception. However, if such a high signal-to-noise ratio is not required for FM reception, if an adequate pilot margin can be acquired in AM stereo reception, or if AM stereo is not required, then either DZC or DZD, in which there is a dead zone, should be chosen. Dead Zone As shown in figure 1, the phase comparator compares a reference frequency (fr) with fp. As shown in figure 2, the phase comparator's characteristics consist of an output voltage (V) that is proportional to the phase difference ø. However, due to internal circuit delay and other factors, an actual circuit has a region (the dead zone, B) where the circuit cannot actually compare the phases. To implement a receiver with a high S/N ratio, it is desirable that this region be as small as possible. However, it is often desirable to have the dead zone be slightly wider in popularly-priced models. This is because in certain cases, such as when there is a strong RF input, popularly-priced models can suffer from mixer to VCO RF leakage that modulates the VCO. When the dead zone is small, the circuit outputs signals to correct this modulation and this output further modulates the VCO. This further modulation may then generate beats and the RF signal. Figure 1 Figure 2 • Notes on the FMIN, AMIN, and IFIN pins Coupling capacitors should be placed as close to their pin as possible. A capacitance of about 100 pF is desirable for these capacitors. In particular, if the IFIN pin coupling capacitor is not held under 1000 pF, the time to reach the bias level may become excessive and incorrect counts may result due to the relationship with the wait time. • Notes on IF counting → Use the SD signal in conjunction with IF counting When counting the IF frequency, the microcontroller must determine the presence or absence of the IF IC SD (station detect) signal and turn on the IF counter buffer output and execute the IF count only if there is an SD signal. Autosearch techniques that only use the IF counter are subject to incorrect stopping at points where there is no station due to IF buffer leakage. No. 5815-21/23 LC72121, 72121M, 72121V • DO pin usage The DO pin can be used for IF counter count completion checking and as an unlock detection output in addition to its use in data output mode. It is also possible to have the DO pin reflect the state of an input pin to input that state to the microcontroller. • Power supply pins Capacitors must be inserted between the power supply VDD and VSS pins for noise exclusion. These capacitors must be placed as close as possible to the VDD and VSS pins. • VCO setup Applications must be designed so that the VCO (local oscillator) does not stop, even if the control voltage (Vtune) goes to 0 V. If it is possible for the oscillator to stop, the application must use the control data (DLC) to temporarily force Vtune to VCC to prevent deadlock from occurring. (Deadlock clear circuit) • Front end connection example Since this product (and the LC72131 as well) is designed with the relatively high resistance of 200 kΩ for the pulldown (on) resistors built in to the FMIN and AMIN pins, a common AM/FM local oscillator buffer can be used as shown in the following circuit. • PD pin Note that the charge pump output voltage is reduced when this IC, which is a 3-V system, is used to replace the LC72131, which is a 5-V system. This means that since the loop gain is reduced, the loop filter constants, the lock time (SD wait time), and other related parameters must be reevaluated in the end product design. No. 5815-22/23 LC72121, 72121M, 72121V Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 2003. Specifications and information herein are subject to change without notice. PS No. 5815-23/23