APW8813/A DDR2 And DDR3 Power Solution Synchronous Buck Controller With 1.5A LDO Features General Description Buck Controller (VDDQ) • The APW8813/A integrates a synchronous buck PWM High Input Voltages Range from 3V to 28V Input controller to generate VDDQ, a sourcing and sinking LDO linear regulator to generate VTT. It provides a complete Power • Provide 1.8V (DDR2), 1.5V (DDR3) or Adjustable power supply for DDR2 and DDR3 memory system. It offers the lowest total solution cost in system where space Output Voltage from 0.75V to 5.5V - ±1% Accuracy Over-Temperature • Integrated MOSFET Drivers and Bootstrap Diode • Excellent Line and Load Transient Responses • PFM Mode for Increased Light Load Efficiency • Constant-On-Time Controller Scheme is at a premium. The APW8813/A provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the APW8813/A provides very high efficiency over light to heavy loads with loading-modulated switching frequencies. On TQFN4x4- - Switching Frequency Compensation for PWM 24A package, the Forced PWM Mode works nearly at constant frequency for low-noise requirements. Mode - Adjustable Switching Frequency from 100kHz The APW8813/A is equipped with accurate current-limit, output under-voltage, and output over-voltage protections. to 550kHz in PWM Mode with DC Output Current • Integrated MOSFET Drivers and Bootstrap Diode • S3 and S5 Pins Control The Device in S0, S3, or A Power-On-Reset function monitors the voltage on VCC prevents wrong operation during power on. S4/S5 State • Power Good Monitoring • 70% Under-Voltage Protection (UVP) • 125% Over-Voltage Protection (OVP) • Adjustable Current-Limit Protection The LDO is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. The device integrates two power transistors to source or sink current up to 1.5A. It also incorporates current-limit and thermal shutdown protection. The output voltage of LDO tracks the voltage at VTTREF - Using Sense Low-Side MOSFET RDS(ON) pin. An internal resistor divider is used to provide a half voltage of VDDQ for VTTREF and VTT Voltage. The VTT ±1.5A LDO Section (VTT) • Souring or Sinking Current up to 1.5A • Fast Transient Response for Output Voltage • Output Ceramic Capacitors Support at Least output voltage is only requiring 20µF of ceramic output capacitance for stability and fast transient response. The S3 and S5 pins provide the sleep state for VTT (S3 state) and suspend state (S4/S5 state) for device, when S5 and 10µF MLCC • S3 are both pulled low the device provides the soft-off for VTT and VTTREF. VTT and VTTREF Track at Half the VDDQSNS by Internal Divider The APW8813/A is available in 4mmx4mm 24-pin TQFN package, and the APW8813A is available in 3mmx3mm • ±20mV Accuracy for VTT and VTTREF • Independent Over-Current-Limit (OCL) • Thermal Shutdown Protection • QFN-24 4mmx4mm Thin Package (TQFN4x4-24A) Applications for APW8813 and QFN-20 3mmx3mm Thin Package (TQFN3x3-20) for APW8813A • DDR2, and DDR3 Memory Power Supplies • SSTL-2 SSTL-18 and HSTL Termination • 20-pin TQFN package. Lead Free and Green Devices Available (RoHS Compliant) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 1 www.anpec.com.tw APW8813/A Simplified Application Circuit 5V VIN +3V~28V RCS Q1 LOUT VDDQ PWM Q2 S3 VTT VDDQ/2 DDR LDO S5 Pin Configuration APW8813A 17 CS_GND 14 PGND GND 3 13 CS VTTREF 4 12 PVCC VDDQSNS 5 11 VCC VDDQSNS VDDQSET S3 VDDQSET NC 21 PGND 6 TON 10 11 12 S5 9 PHASE LGATE 2 13 PGOOD 8 UGATE 15 VTTSNS 14 VCC 7 BOOT VTTGND 1 15 PVCC FCCM 6 16 7 8 9 10 PGOOD MODE 4 VTTREF 5 17 18 PGND 16 CS 25 PGND 18 TON GND 3 19 S5 VTTSNS 2 20 S3 VTTGND 1 LDOIN 24 23 22 21 20 19 VTT LGATE PHASE UGATE BOOT VTT LDOIN APW8813 TQFN3x3-20 (Top View) TQFN4x4-24A (Top View) = Thermal Pad (connected to GND plane for better heat dissipation) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 2 www.anpec.com.tw APW8813/A Ordering and Marking Information Package Code QB : TQFN4x4-24A QB : TQFN3x3-20 Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APW8813/A Assembly Material Handling Code Temperature Range Package Code APW8813 QB : APW8813A QB : APW8813 XXXXX XXXXX - Date Code APW 8813A XXXXX XXXXX - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Note 1, 2) Symbol Rating Unit VCC Supply Voltage (VCC to GND) -0.3 ~ 7 V VPVCC PVCC Supply Vo ltage (PVCC to GND) -0.3 ~ 7 V VBOOT BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 7 V BOOT Supply Voltage (BOOT to GND) -0 .3 ~ 35 V -5 ~ VBOOT +0.3 -0.3 ~ VBOOT+0.3 V <400ns Pulse Width >400ns Pulse Width -5 ~ PVCC+0.3 -0.3 ~ PVCC+0.3 V <400ns Pulse Width >400ns Pulse Width -5 ~ 35 -0 .3 ~ 28 V -0.3 ~ 0.3 V -0.3 ~ 7 V VCC VBOOT-GND Parameter UGATE Voltage (UGATE to PHASE) <400ns Pulse Width >400ns Pulse Width LGATE Voltage (LGATE to GND) PHASE Voltage (PHASE to GND) PGND, VTTGND and CS_GND to GND Voltage All Other Pins (CS, MODE, S3, S5, VTTSNS, VDDQSNS, LDOIN, FCCM, VDDQSET, PGOOD, VTT, VTTREF GND) TJ Maximum Junction Temperature TSTG Storage Temperature TSDR Maximum Soldering Temperature , 10 Seconds 150 o -65 ~ 150 o 260 o C C C Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2: The device is ESD sensitive. Handling precautions are recommended. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 3 www.anpec.com.tw APW8813/A Thermal Characteristics (Note 3) Symbol Parameter Thermal Resistance - Junction to Ambient θJA Typical Value Unit TQFN4x4-24A TQFN3x3-20 52 68 °C/W TQFN4x4-24A TQFN3x3-20 7 8 °C/W Thermal Resistance - Junction to Case θJC Note 3: θJA and θJC are measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Recommended Operating Conditions (Note 4) Symbol VCC, VPVCC VIN Parameter Range Unit 4.5 ~ 5.5 V 3 ~ 28 V 0.75 ~5.5V/ DDR2 (1.8V)/ DDR3 (1.5V) V 0.375 ~ 2.75 V VCC and PVCC Supply Voltage Converter Input Voltage VVDDQ Converter Output Voltage VVTT LDO Output Voltage IOUT Converter Output Current IVTT LDO Output Current CVCC, CPVCC VCC and PVCC Capacitance CVTT CVTTREF TA TJ 0 ~ 15 A -1.5 ~ +1.5 A 1~ µF VTT Output Capacitance 10~100 µF VTTREF Output Capacitance 0.01~0.1 µF Ambient Temperature -40 ~ 85 o -40 ~ 125 o Junction Temperature C C Note 4: Refer to the typical application circuit. Electrical Characteristics Refer to the typical application circuits. These specifications apply over VVCC=VPVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APW8813/A Test Conditions Unit Min. Typ. Max. SUPPLY CURRENT IPVCCSDN IVCC PVCC Shutdown Current TA =25oC, VS3 = VS5 = 0V, no load - 0.1 1 µA VCC Supply Current TA = 25oC, VS3 = VS5 = 5V, no load, PVCC Plus VCC Current, No Switching - 0.8 3 mA o IVCCSTB VCC Standby Current TA = 25 C, VS3 = 0V, VS5 = 5V, no load, PVCC Plus VCC Current, No Switching - 240 800 µA IVCCSDN VCC Shutdown Current TA =25oC, VS3 = VS5 = 0V, no load - 0.1 1 µA - - 40 µA ILDOIN LDOIN Supply Current o TA = 25 C, VS3 = VS5 = 5V, no load o ILDOINSTB LDOIN Standby Current TA = 25 C, VS3 = 0V, VS5 = 5V, no load - 0.1 10 ILDOINSDN LDOIN Shutdown Current TA = 25oC, VS3 = VS5 = 0V, no load - 0.1 1 4.0 4.2 4.4 V - 100 - mV µA POWER-ON-RESET VCC POR Threshold VCC Rising VCC POR Hysteresis Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 4 www.anpec.com.tw APW8813/A Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VVCC=VPVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APW8813/A Test Conditions Unit Min. Typ. Max. VLDOIN = VVDDQSNS = 1.8V - 0.9 - VLDOIN = VVDDQSNS = 1.5V - 0.75 - VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT, IVTT = 0A -20 - 20 VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - VVTT, IVTT = 1.5A -30 - 30 VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT, IVTT = 0A -20 - 20 VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - VVTT, IVTT = 1.5A -30 - 30 TJ = 25oC 1.8 2 3 TJ = 125oC 1.6 - - TJ = 25 C -2 -2.2 -3 TJ = 125oC -1.6 - - TJ = 25 C 1.6 1.8 2.6 o 1.1 - - TJ = 25 C -1.6 -1.8 -2.6 TJ = 125oC -1.1 - - Upper MOSFET - 350 500 Lower MOSFET - 350 500 VVTT = 1.25V, VS3 = 0V, VS5 = 5V, TA = 25oC -1.0 - 1.0 µA o -1.00 0.01 1.00 µA 15 25 35 mA VLDOIN = VVDDQSNS = 1.8V, VVDDQSNS/2 - 0.9 - VLDOIN = VVDDQSNS = 1.5V, VVDDQSNS/2 - 0.75 - 0mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF VLDOIN = VVTTREF =1.8V -18 - +18 0mA < IVTTREF < 10mA, VVDDQSNS/2 - VVTTREF VLDOIN = VVDDQSNS = 1.5V -20 - +20 VTTREF Source Current VVTTREF = 0V 10 20 40 mA VTTREF Sink Current VVTTREF = 1.5V, VTT=0.75V -10 -20 -40 mA 1.787 1.8 1.813 V VVDDQSET = 5V, No load, TA = -40 C to 85 C 1.782 1.8 1.818 V VVDDQSET = 5V, Load = 0 to 10A, TA = 25oC 1.764 1.8 1.836 V VTT OUTPUT VVTT VVTT VTT Output Voltage VTT Output Tolerance Sourcing Current (VIN = 1.8V) o Sinking Current (VIN = 1.8V) ILIM Current-Limit o Sourcing Current (VIN = 1.5V) TJ = 125 C o Sinking Current (VIN = 1.5V) RDS(ON) IVTTLK IVTTSNSLK VTT Power MOSFETs RDS(ON) VTT Leakage Current VTTSNS Leakage Current VVTT = 1.25V, TA = 25 C V mV A A mΩ o IVTTDIS VTT Discharge Current VVTT = 0.5V, VS3 = VS5 = 0V, TA = 25 C, VVREF = 0V VTTREF OUTPUT VVTTREF VTTREF Output Voltage VTTREF Tolerance IVTTREF V mV VDDQ OUTPUT VVDDQSET = 5V, No load, TA = 25oC VVDDQ 1.8V VDDQ Output Voltage Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 o 5 o www.anpec.com.tw APW8813/A Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VVCC=VPVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APW8813/A Test Conditions Unit Min. Typ. Max. 1.488 1.5 1.512 V 1.485 1.5 1.515 V VDDQ OUTPUT (CONT.) VVDDQSET = 0V, No load, TA = 25oC VVDDQ 1.5V VDDQ Output Voltage o o VVDDQSET = 0V, No load, TA = -40 C to 85 C o VVDDQSET = 0V, Load = 0 to 10A, TA = 25 C 1.47 1.5 1.53 V Adjust Mode, TA = 25oC 0.745 0.75 0.755 V 0.7425 0.75 0.7575 V -0.1 - +0.1 % Adjust Mode, TA = 25 C, Load = 0 to 10A, VVCC = 4.5V to 5.5V -1 - +1 % VVDDQSET = 0V (DDR3) - 240 - VVDDQSET = 5V (DDR2) - 288 - o o Adjust Mode, TA = -40 C to 85 C VVDDQSET VDDQSET Regulation Voltage o Adjust Mode, TA = 25 C, VVCC = 4.5V to 5.5V, VIN = 3V to 28V o RVDDQSNS VDDQSNS Input Impedance kΩ VDDQSET Input Current VVDDQSET = 0.78V -0.1 - +0.1 µA VDDQ Discharge Current VS3 = VS5 = 0V, VVDDQSNS = 0.5V, VMODE = 0V (Non-Tracking) 15 25 - mA LDOIN Discharge Current VS3 = VS5 = 0V, VVDDQSNS = 0.5V, VMODE = 0.5V (Tracking, only for APW8813) 400 550 - mA PWM CONTROLLERS FSW Operating Frequency Adjustable Frequency 100 - 550 kHz TSS Internal Soft-Start Time S5 is High to VVDDQ Regulation 0.9 1.2 1.5 ms TO On Time VIN = 19V, VVDDQ = 1.5V, RTON = 1.2M 235 277 320 ns TOFF(MIN) Minimum off Time - 300 - ns TON(MIN) Minimum on Time 80 110 140 ns Zero-Crossing Threshold -9.5 0.5 10.5 mV TA = 25oC 9 10 11 Temperature Coefficient, On The Basis of 25°C - 4500 - µA ppm/ o C VDDQ PROTECTIONS CS Pin Sink Current OCP Comparator Offset (VPVCC - VCS) - (VPHASE - PGND), VPVCC - VCS = 60mV -15 0 +15 mV VDDQ Current-Limit Setting Range VPVCC-VCS 30 - 200 mV VDDQ OVP Trip Threshold VVDDQ Rising 120 125 130 % - 1.5 - µs 60 70 80 % VDDQ UVP Trip Hysteresis - 3 - % VDDQ UVP Debounce - 10 - µs VDDQ UVP Enable Delay - 2 - ms VDDQ OVP Debounce Delay VFB Rising, DV = 10mV VDDQ UVP Trip Threshold VVDDQ Falling Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 6 www.anpec.com.tw APW8813/A Electrical Characteristics (Cont.) Refer to the typical application circuits. These specifications apply over VVCC=VPVCC=VBOOT=5V, VIN=12V and TA= -40 ~ 85 °C, unless otherwise specified. Typical values are at TA=25°C. Symbol Parameter APW8813/A Test Conditions Unit Min. Typ. Max. 87 90 93 % PGOOD PGOOD in from Lower (PGOOD Goes High) VPGOOD PGOOD Threshold PGOOD Low Hysteresis (PGOOD Goes Low) - 3 - % PGOOD in from Higher (PGOOD Goes Low) 120 125 130 % - 3 - % PGOOD High Hysteresis (PGOOD Goes High) IPGOOD PGOOD Leakage Current VPGOOD = 5V PGOOD Sink Current VPGOOD = 0.5V PGOOD Debounce Time - 0.1 1.0 µA 2.5 7.5 - mA - 63 - µs GATE DRIVERS UGATE Pull-Up Resistance BOOT-UGATE = 0.5V - 5 7 Ω UGATE Sink Resistance UGATE-PHASE = 0.5V - 1 2.5 Ω LGATE Pull-Up Resistance PVCC-LGATE = 0.5V - 5 7 Ω LGATE Sink Resistance LGATE-PGND = 0.5V - 1 2.5 Ω UGATE to LGATE Dead Time UGATE falling to LGATE rising, no load - 40 - ns LGATE to UGATE Dead Time LGATE falling to UGATE rising, no load - 40 - ns Forward Voltage VPVCC - VBOOT, IF = 10mA, TA = 25oC - 0.5 0.8 V Reverse Leakage VBOOT = 30V, VPHASE = 25V, VPVCC = 5V, TA = 25oC - - 0.5 µA BOOTSTRAP DIODE LOGIC THRESHOLD VIH S3, S5 High Threshold Voltage S3, S5 Rising 1.6 - - V VIL S3, S5 Low Threshold Voltage S3, S5 Falling - - 0.3 V S5 to S3 Debounce Time S5 from L to H, VDDQ, VREF are on - 90 - µs S3 to S0 Debounce Time S3 from L to H, VTT is on - 10 - µs VS3 = VS5 = VMODE = 5V, TA = 25 C -1 - 4.7 µA In Automatic PFM/PWM Mode 4.7 - - V - - 0.1 V 4.7 - - - - 0.1 VVDDQ = 1.5V 0.08 0.15 0.4 VVDDQ = 1.8V 3.5 4 4.5 - 160 - o - o IILEAK VFCCMTHR VFCCMTHF VTHMODE Logic Input Leakage Current FCCM High Threshold (Only for APW8813) FCCM Low Threshold (Only for APW8813) MODE Threshold (Only for APW8813) VDDQSET Threshold o In Force PWM Mode No Discharge Non-tracking Discharge V V THERMAL SHUTDOWN TSD Thermal Shutdown Temperature TJ Rising Thermal Shutdown Hysteresis Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 - 7 25 C C www.anpec.com.tw APW8813/A Pin Description PIN APW8813 APW8813A FUNCTION NAME 1 1 VTTGND Power ground output for the VTT LDO. 2 2 VTTSNS Voltage sense input for the V TT LDO. Connect to plus terminal of the VTT LDO output capacitor. 3 3 GND 4 - MODE 5 4 VTTREF Signal ground for the PWM control ler and VTT LDO. Connect to minus terminal of the VTT LDO output capacitor. Discharge mode setting pin. When this pin connects to VCC, it is no discharge state. When this pin connects to VDDQ, it is tracking discharge state. When this pin connects to GND, it is non-tracking discharge state. VTTREF buffered reference ou tput. Selection pin for PWM controller to operate in either forced PWM or automatic PWM/PFM mode. Force PWM mode is enabl e when FCCM pin is pulled below the falling threshold voltage VFCCMTHF, and force PWM is disabled when the FCCM pin is pulled above the rising threshold voltage VFCCMTHR. 6 - FCCM 7 - NC 8 5 VDDQ reference input for VTT and VTTREF. Power supply fo r the VTTREF. Discharge V DDQSNS current sinking terminal for VDDQ non-tracking discharge. Output voltage feedback input for VDDQ output if VDDQSET pin is connected to VCC or GND. 9 6 VDDQSET VDDQ output voltage setting pin. 10 7 S3 S3 signal input. 11 8 S5 S5 signal input. 12 9 TON This Pin is Allowed to Adjust The Switching Frequency. Connect a resistor R TON from TON pin to PHASE VIN terminal. 13 10 PGOOD Power-good output pin. PGOOD i s an open drain output used to Indicate the status of the output voltage. When VDDQ output voltage is within the ta rget range, it is in high state. 14 11 VCC 15 12 PVCC 5V power supply voltage input pin for low-side MOSFET gate driver on TQFN-24 package. 16 13 CS Over-current trip voltage setting input for RDS(ON) current sense scheme if connected to VCC through the voltage setting resistor. 17 - CS_GND 18 14 PGND Power ground of the LGATE low-side MOSFET driver. Connect the pin to the Source of the low-side MOS FET. Also i t is current sense comparator positive input terminal and the ground of power good circuit on SSOP-20 package. 19 15 LGATE Output of the low-side MOSFET driver for PWM. C onnect this pin to Gate of the low-side MOSFET. Swings from PGND to VCC. 20 16 P HASE 21 17 UGATE 22 18 BOOT 23 19 LDOIN 24 20 VTT No Connection. Filtered 5V power supply input for internal control circuitry. Connect R-C network from PVCC to VCC. Current sense comparator posi tive input terminal and the ground for power good circuit. Junction point of the high-side MOSFET Source, output filter inductor and the low-side MOSFET Drain. Connect this pin to the Source of the high-side MOSFET. PHASE serves as the lower supply rail for the UGATE high-side gate driver. Output of the high-side MOSFE T driver for PWM. Connect this pin to Gate of the high-side MOSFET. Supply Input for the UGATE Gate Driver and an internal level-shift circuit. Connect to an external capacitor and diode to create a boosted voltage suitable to drive a logic-level N-channel MOSFET. Supply voltage input for the VTT LDO. Power output for the VTT LDO. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 8 www.anpec.com.tw APW8813/A Typical Operating Characteristics VDDQ Voltage Regulation vs. Junction Temperature VDDQ Voltage Regulation vs. Junction Temperature 1.55 1.85 VDDQ Output Voltage (V) VDDQSET = GND, VDDQ = 1.5V VDDQ Output Voltage (V) 1.53 1.51 1.49 1.83 1.81 1.79 1.77 1.47 1.45 -40 -20 0 20 40 60 1.75 -40 -20 80 100 120 Junction Temperature, TJ (oC) Supply Current vs. Junction 1.0 Shutdown Current, IPVCC Plus IVCC (uA) Supply Current, IPVCC Plus IVCC (mA) 2.5 2 1.5 1 0.8 0.6 0.4 0.2 0.5 0 -40 -20 0 -40 -20 0 20 40 60 80 100 120 Junction Temperature, TJ (oC) CS Pin Sink Current vs. Junction Temperature 330 Switching Frequency,FSW (KHz) 14 CS Sink Current (uA) 0 20 40 60 80 100 120 Junction Temperature, TJ (oC) Shutdown Current vs. Junction Temperature Temperature 3.0 16 VDDQSET = VCC, VDDQ = 1.8V 12 10 8 6 4 2 0 -40 -20 0 20 40 60 o Junction Temperature, TJ ( C) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 9 Frequency vs. Junction Temperature 320 310 300 290 280 270 -40 -20 80 100 120 0 20 40 60 80 100 120 Junction Temperature, TJ (oC) 0 20 40 60 80 100 120 Junction Temperature, TJ (oC) www.anpec.com.tw APW8813/A Typical Operating Characteristics Load Regulation, VVDDQ=1.5V 1.53 1.51 1.49 PFM Mode Force PWM Mode (Only for APW8813) 1.47 1.45 0 1.55 2 4 6 VDDQ Current (A) 8 VDDQ Voltage, VVDDQ(V) 1.49 PFM Mode Force PWM Mode (Only for APW8813) 15 20 Input Voltage (V) VTT Load Regulation PFM Mode Force PWM Mode (Only for APW8813) 1.77 0 2 4 6 VDDQ Current (A) 8 10 FSW=300kHz 1.83 1.81 1.79 PFM Mode Force PWM Mode (Only for APW8813) 1.77 1.75 25 10 1.79 1.85 1.51 5 1.81 Line Regulation, VVDDQ=1.8V 1.53 1.45 1.83 1.75 10 Line Regulation, VVDDQ=1.5V FSW=300kHz 1.47 FSW=300kHz 1.85 VDDQ Voltage, VVDDQ(V) VDDQ Voltage, VVDDQ(V) 1.55 VDDQ Voltage, VVDDQ(V) Load Regulation, VVDDQ=1.8V FSW=300kHz 5 10 15 20 25 Input Voltage (V) VTT Voltage, VVTT(V) 0.76 0.755 0.75 0.745 0.74 -1.5 -1 -0.5 0.5 0 VTT Current, IVTT (A) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 1 1.5 10 www.anpec.com.tw APW8813/A Typical Operating Characteristics Output Current vs. Switching Output Current vs. Switching Frequency Frequency 500 DDRII, VIN=12V, VDDQ=1.8V, S5=5V, S3=GND Switching Frequency (kHz) Switching Frequency (kHz) DDRII, VIN=8V, VDDQ=1.8V, S5=5V, S3=GND 400 300 200 100 0 0.001 600 0.01 0.1 1 400 300 200 100 0 0.001 10 1 Output Current vs. Switching Frequency Output Current vs. Switching 10 Frequency 500 DDRIII, VIN=8V, VDDQ=1.5V, S5=5V, S3=GND Switching Frequency (kHz) Switching Frequency (kHz) 0.1 Output Current (A) DDRII, VIN=20V, VDDQ=1.8V, S5=5V, S3=GND 500 400 300 200 100 0 0.001 0.01 0.1 1 400 300 200 100 0 0.001 10 Output Current (A) 0.01 0.1 1 10 Output Current (A) Output Current vs. Switching Frequency Output Current vs. Switching Frequency 700 500 DDRIII, VIN=20V, VDDQ=1.5V, S5=5V, S3=GND Switching Frequency (kHz) DDRIII, VIN=12V, VDDQ=1.5V, S5=5V, S3=GND Switching Frequency (kHz) 0.01 Output Current (A) 400 300 200 100 600 500 400 300 200 100 0 0.001 0.01 0.1 1 0 0.001 10 Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 0.01 0.1 1 10 Output Current (A) Output Current (A) 11 www.anpec.com.tw APW8813/A Typical Operating Characteristics Output Current vs. Switching Frequency Output Current vs. Switching Frequency 500 600 RTON=1M, VIN=19V, VDDQ=1.5V, S5=5V, S3=GND Switching Frequency (kHz) Switching Frequency (kHz) RTON=1.2M, VIN=19V, VDDQ=1.5V, S5=5V, S3=GND 400 In Force PWM 300 200 100 500 In Force PWM 400 300 200 100 In Auto PFM/ PWM 0 In Auto PFM/ PWM 0 0.001 0.01 0.1 1 10 0.001 Output Current (A) 0.01 0.1 1 10 Output Current (A) Output Current vs. Switching Frequency 600 Switching Frequency (kHz) RTON=750k, VIN=19V, VDDQ=1.5V, S5=5V, S3=GND 500 In Force PWM 400 300 200 100 In Auto PFM/ PWM 0 0.001 0.01 0.1 1 10 Output Current (A) Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 12 www.anpec.com.tw APW8813/A Operating Waveforms Non-Zero VDDQ S5 Enable S5 Enable, No Load 1 1 2 2 3 3 4 4 CH1: VS5 (5V/div) CH2: VVDDQ (1V/div) CH3: VUGATE (20V/div) CH4: VPOK (5V/div) Time: 500µs/div CH1: VS5 (5V/div) CH2: VVDDQ (1V/div) CH3: VVTTREF (500mV/div) CH4: VPOK (5V/div) Time: 500µs/div S5 Shutdown- Tracking Discharge ( Only for APW8813) S5 Shutdown- Non-Tracking Discharge 1 1 2 2 3 3 4 4 CH1: VS5 (5V/div) CH2: VVDDQ (1V/div) CH3: VVTTREF (500mV/div) CH4: VVTT (500mV/div) Time: 200µs/div Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 CH1: VS5 (5V/div) CH2: VVDDQ (1V/div) CH3: VVTTREF (500mV/div) CH4: VVTT (500mV/div) Time: 5ms/div 13 www.anpec.com.tw APW8813/A Operating Waveforms Load Transient, IVDDQ = 0A->10A->0A PFM Mode S3 Enable-Shutdown 1 1 2 2 3 3 4 4 CH1: VS3 (5V/div) CH2: VVDDQ (1V/div) CH3: VVTTREF (500mV/div) CH4: VVTT (500mV/div) Time: 10ms/div CH1: VVDDQ (200mV/div) CH2: VUGATE (20V/div) CH3: VLGATE (5V/div) CH4: IL (10A/div) Time: 20µs/div Load Transient, IVDDQ = 0A->10A->0A Force PWM Mode (Only for APW8813) 1 2 3 4 CH1: VVDDQ (200mV/div) CH2: VUGATE (20V/div) CH3: VLGATE (5V/div) CH4: IL (10A/div) Time: 20µs/div Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 14 www.anpec.com.tw APW8813/A Block Diagram APW8813 0.5 x VDDQ VDDQSNS VTTREF LDOIN Thermal Shutdown S3 S3,S5 Control Logic Current-Limit VTT S5 0.5 x VDDQ +5/10% VTTSNS VTTGND 0.5 x VDDQ -5/10% 0.15V 0.15V Discharge Mode Select DDR3 Adjust ADJUST MODE 4V DDR2 4V VCC SoftStart VREF Adjust VCC POR 1.25V Current-Limit VDDQSET CS 0.75V 10µA 125% x 0.75 OV Error Comparator BOOT UGATE UV PWM Signal Controller 70% x 0.75 TON PHASE TON Generator PHASE PVCC ZC LGATE 0.75 x 125% / 122% PGOOD PGND GND Delay CS_GND 0.75 x 90% / 87% Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 15 Force PWM or Automatic PFM/PWM Mode Selection FCCM www.anpec.com.tw APW8813/A Block Diagram (Cont.) APW8813A 0.5 x VDDQ VDDQSNS VTTREF LDOIN Thermal Shutdown S3 S3,S5 Control Logic Current Limit VTT S5 0.5 x VDDQ +5/10% VTTSNS 0.5 x VDDQ 5/10% VTTGND 0.15V DDR3 Adjust Non-Tracking Discharge ADJUST DDR2 4V VCC Soft Start POR VREF Adjust VCC 1.25V Current Limit VDDQSET CS 0.75V 10uA 125% x 0.75 OV Error Comparat or BOOT UGATE UV PWM Signal Controller 70% x 0.75 TON PHASE TON Generator PHASE PVCC ZC LGATE 0.75 x 125%/122% PGOOD PGND GND Delay 0.75 x 90%/87% Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 16 www.anpec.com.tw APW8813/A Typical Application Circuit APW8813 CBOOT VIN 7V~25V CIN 10µF x 2 0.1µF Q1 LOUT 1µH PHASE VDDQ VTT VDDQ/2 VDDQ 10A COUT 150µF x 2 LGATE PHASE VTTGND UGATE BOOT CVTT 10µF x 2 LDOIN VTT Q2 PGND CSGND VTTSNS RCS GND 5.1K, 1% PVCC VCC VCC RVCC VCC RPGOOD 2.2 100K CVCC 1µF TON S5 PGOOD S3 FCCM NC CVTTREF 0.033µF VDQQSET VTTREF VDDQSNS MODE VTTREF VDDQ/2 PVCC CS APW8813 TQFN4x4-24A CPVCC 4.7µF 100K RTON 100K RTOP 75K, 1% VDDQ VIN or PHASE 1.2M RGND 75K, 1% VDDQ=Adjustable, External LDOIN, Non-tracking Discharge Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 17 www.anpec.com.tw APW8813/A Typical Application Circuit APW8813A CBOOT VIN 7V~25V CIN 0.1uF Q1 LOUT 1uH PHASE VDDQ 10uF x 2 VTT VDDQ/2 VDDQ 10A COUT LGATE VTTGND PGND VTTSNS RCS APW8813A GND 5.1K, 1% PVCC VTTREF VCC RVCC VCC VDDQSNS CPVCC PGOOD TON S5 2.2 S3 VDQQSET CVTTREF 0.033uF PVCC CS TQFN-20 VTTREF VDDQ/2 150uF x 2 PHASE UGATE BOOT CVTT 10uF x 2 LDOIN VTT Q2 CVCC 4.7uF 1uF RPGOOD PGOOD RTON VDDQ RTOP 75K, 1% 100k VIN or PHASE RGND 75K, 1% 1.2M VDDQ=Adjustable, External LDOIN Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 18 www.anpec.com.tw APW8813/A Function Description The APW8813/A integrates a synchronous buck PWM controller to generate VDDQ, a sourcing and sinking LDO a switching frequency control circuit in the on-time generator block. The switching frequency control circuit senses the switching frequency of the high-side switch linear regulator to generate VTT. It provides a complete power supply for DDR2 and DDR3 memory system in and keeps regulating it at a constant frequency in PWM mode. The design improves the frequency variation and both TQFN packages. The preset output voltage is selectable from 1.8V or 1.5V. User defined output voltage is be more outstanding than a conventional constant-ontime controller which has large switching frequency varia- also possible and can be adjustable from 0.75V to 5.5V. Input voltage range of the PWM converter is 3V to 28V. tion over input voltage, output current and temperature. Both in PFM and PWM, the on-time generator, which The converter runs an adaptive on-time PWM operation at high-load condition and automatically reduces fre- senses input voltage on PHASE pin, provides very fast on-time response to input line transients. quency to keep excellent efficiency down to several mA. The VTT LDO can source and sink up to 1.5A peak cur- Another one-shot sets a minimum off-time (typical: 300ns). The on-time one-shot is triggered if the error com- rent with only 10µF ceramic output capacitor. VTTREF tracks VDDQ/2 within 1% of VDDQ. VTT output tracks parator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time one- VTTREF within 20 mV at no load condition while 40 mV at full load. The LDO input can be separated from VDDQ shot has timed out. and optionally connected to a lower voltage by using LDOIN pin. This helps reducing power dissipation in Power-On-Reset sourcing phase. The APW8813/A is fully compatible to JEDEC DDR2/DDR3 specifications at S3/S5 sleep state A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The (see Table 1). Only for APW8813, when both VTT and VDDQ are disabled, the part has two options of output POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set high. When the rising VCC voltage reaches the rising discharge function. The tracking discharge mode discharges VDDQ and VTT outputs through the internal LDO POR voltage threshold (4.2V typical), the POR signal goes high and the chip initiates soft-start operations. When transistors and then VTT output tracks half of VDDQ voltage during discharge. The non-tracking discharge mode this voltage drops lower than 4.1V (typical), the POR disables the chip. discharges outputs using internal discharge MOSFETs that are connected to VDDQSNS and VTT. The current Soft-Start capability of these discharge MOSFETs are limited and discharge occurs more slowly than the tracking The APW8813/A integrates digital soft-start circuits to ramp discharge. Selecting non-discharge mode can disable these discharge functions. up the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. The slew Constant-On-Time PWM Controller with Input Feed-For- rate of output voltage is internally controlled to limit the inrush current through the output capacitors during soft- ward The constant-on-time control architecture is a pseudo- start process. The figure 1 shows VDDQ soft-start sequence. When the S5 pin is pulled above the rising S5 fixed frequency with input voltage feed-forward. This architecture relies on the output filter capacitor’s effective threshold voltage, the device initiates a soft-start process to ramp up the output voltage. The soft-start interval is series resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. 1.2ms (typical) and independent of the UGATE switching frequency. In PFM operation, the high-side switch on-time controlled by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 19 www.anpec.com.tw APW8813/A Function Description (Cont.) Soft-Start (Cont.) converter’s output voltage is greater than 90% of its target value, the internal open-drain device will be pulled low. After 63µs debounce time, the PGOOD goes high. 2ms The PGOOD goes low if VVDDQ output is 13% below or 25% above its nominal regulation point. VCC and VPVCC 1.2ms Under-Voltage Protection (UVP) VOUT If VDDQSET is connected to VCC or GND, an internal resistor divider inside VDDQSNS pin makes the feedback voltage. If an external resistor divider is connected S5 to VDDQSET pin, the feedback voltage is VDDQSET voltage itself. In the process of operation, if a short-circuit occurs, the output voltage will drop quickly. When load current is bigger than current-limit threshold value, the output voltage will fall out of the required regulation range. The under- VPGOOD voltage continually monitors the setting output voltage after 2ms of PWM operations to ensure start-up. If a load Figure 1. Soft-Start Sequence During soft-start stage before the PGOOD pin is ready, step is strong enough to pull the output voltage lower than the under-voltage threshold (70% of normal output the under-voltage protection is prohibited. The over-voltage and current-limit protection functions are enabled. If voltage), after 10 µs debounce time, APW8813/A shuts down the output gradually and latches off both high and the output capacitor has residue voltage before start-up, both low-side and high-side MOSFETs are in off-state low side MOSFETs. until the internal digital soft-start voltage equals to the VVDDQSET or internal feedback voltage. This will ensure the Over-Voltage Protection output voltage starts from its existing voltage level. The VTT LDO part monitors the output current, both sourc- The feedback voltage should increase over 125% of the reference voltage due to the high-side MOSFET failure or for other reasons, and the over-voltage protection com- ing and sinking current, and limits the maximum output current to prevent damages during current overload or parator designed with a 1.5µs noise filter will force the low-side MOSFET gate driver to be high. This action ac- short circuit (shorted from VTT to GND or LDOIN) conditions. tively pulls down the output voltage and eventually attempts to blow the battery fuse. The VTT LDO provides a soft-start function, using the constant current to charge the output capacitor that gives When the OVP occurs, the PGOOD pin will pull down and latch-off the converter. This OVP scheme only clamps the a rapid and linear output voltage rise. If the load current is above the current-limit start-up, the VTT cannot start voltage overshoot, and does not invert the output voltage when otherwise activated with a continuously high output successfully. APW8813/A has an independent counter for each output, from low-side MOSFET driver. It’s a common problem for OVP schemes with a latch. Once an over-voltage fault but the PGOOD signal indicates only the status of VDDQ and does not indicate VTT power good externally. condition is set, toggling VCC power-on-reset signal can only reset it. Power-Good Output (PGOOD) PGOOD is an open-drain output and the PGOOD comparator continuously monitors the output voltage. PGOOD is actively held low in shutdown, and standby. When PWM Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 20 www.anpec.com.tw APW8813/A Function Description (Cont.) PWM Converter Current-Limit rent sensing algorithm (Figure 2). CS pin should be connected to VCC through the trip voltage-setting resistor, RCS. CS terminal sinks 10µA current, ICS, and the currentlimit threshold is set to the voltage across the RCS. The voltage between PGND and PHASE pin monitors the inductor current so that PHASE pin should be connected to the drain terminal of the low side MOSFET. PGND is used as the positive current sensing node so that PGND IVALLEY Time Figure 2. Current-Limit Algorithm VTT Sink/Source Regulator side MOSFET. If the magnitude of the current-sense signal is above the The output voltage at VTT pin tracks the reference voltage applied at VTTREF pin. Two internal N-channel MOSFETs controlled by separate high bandwidth error amplifiers current-limit threshold, the PWM is not allowed to initiate a new cycle. The actual peak current is greater than the regulate the output voltage by sourcing current from LDOIN pin or sinking current to GND pin. To prevent two pass current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit char- transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error acteristic and maximum load capability are the function of the sense resistance, inductor value, and input voltage. amplifiers. The VTT with fast response feedback loop keeps tracking to the VTTREF within ±40mV at all condi- The equation for the current-limit threshold is as below: = ILIMIT 0 should be connected to the proper current sensing device, i.e. the sense resistor or the source terminal of the low ILIMIT = IPEAK INDUCTOR CURRENT The current-limit circuit employs an unique “valley” cur- VCS I + RIPPLE RDS(ON) 2 tions including fast load transient. RCS × 10µA (VIN − VVDDQ ) VVDDQ x + RDS(ON) 2 × L × FSW VIN S3, S5 Control In the DDR2/DDR3 memory applications, it is important Where to keep VDDQ always higher than VTT/VTTREF including both start-up and shutdown. ILIMIT is the desired current-limit threshold RCS is the value of the current sense resistor con- The S3 and S5 signals control the VDDQ, VTT, VTTREF states and these pins should be connected to SLP_S3 nected to CS and VCC pins VCS is the voltage across the RCS resistor and SLP_S5 signals respectively. The table1 shows the truth table of the S3 and S5 pins. When both S3 and S5 IRIPPLE is inductor peak to peak current FSW is the PWM switching frequency are above the logic threshold voltage, the VDDQ, VTT and VTTREF are turned on at S0 state. When S3 is low and In a current-limit condition, the current to the load exceeds the current to the output capacitor, thus the output voltage S5 is high, the VDDQ and VTTREF are kept on while the VTT voltage is disabled and left high impedance in S3 tends to fall down. If the output voltage becomes less than power good level, the VCS is cut into half and the state. When both S3 and S5 are low, the VDDQ, VTT and VTTREF are turned off and discharged to the ground ac- output voltage tends to be even lower. Eventually, it crosses the under-voltage protection threshold and cording to the discharge mode selected by MODE pin during S4/S5 state, only for APW8813. On APW8813A, the shutdown. default discharge mode is non-tracking discharge. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 21 www.anpec.com.tw APW8813/A Function Description (Cont.) S3, S5 Control (Cont.) regulates the output again through initiation of a new soft- Table1: The Truth Table of S3 and S5 Pins. start cycle after the junction temperature cools by 25oC, resulting in a pulsed output during continuous thermal STATE S3 S5 VDDQ VTTREF VTT S0 H H 1 1 1 S3 L H 1 1 0 (high-Z) S4/5 L L overload conditions. The thermal shutdown is designed with a 25oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. 0 0 0 (discharge) (discharge) (discharge) VDDQ and VTT Discharge Control For normal operation, device power dissipation should be externally limited so that junction temperatures will APW8813/A discharges VDDQ, VTTREF and VTT outputs not exceed +125oC. during S3 and S5 are both low. The APW8813A default discharge mode is non-tacking discharge and there are Programming the On-Time Control and PWM Switching Frequency two different discharge modes for APW8813. Connecting MODE pin as shown in Table 2 can set the discharge The APW8813/A does not use a clock signal to produce PWM. The device uses the constant-on-time control ar- mode. Table 2. Discharge Selection. (Only for APW8813) MODE DISCHARGE MODE VCC No Discharge VDDQ Tracking Discharge GND Non-Tracing Discharge chitecture to produce pseudo-fixed frequency with input voltage feed-forward. The on-time pulse width is proportional to output voltage VVDDQ and inverses proportional to input voltage VIN. In PWM, the on-time calculation is written as below : ( ) When in tracking-discharge mode, the device discharges 1 VVDDQ + 75mV − 50ns TON = 11.5 ×10−12 × RTON 4 VIN outputs through the internal VTT regulator transistors and VTT output tracks half of VDDQ voltage during this Where: discharge. Note that VDDQ discharge current flows via LDOIN to VTTGND thus LDOIN must be connected to RTON is the resistor connected from TON pin to VIN or PHASE pin. Furthermore, the approximate PWM switch- VDDQ output in this mode. The internal LDO can handle up to 1.5A and discharge quickly. After VDDQ is discharged ing frequency is written as : down to 0.2V, the internal LDO is turned off and the operation mode is changed to the non-tracking discharge TON = mode. When in non-tracking-discharge mode, the device dis- D ⇒ FSW = FSW VVDDQ VIN TON Where: charges outputs using internal MOSFETs that are connected to VDDQSNS and VTT. The current capability of FSW is the PWM switching frequency. APW8813/A doesn’t have VIN pin to calculate on-time these MOSFETs is limited to discharge slowly. Note that VDDQ discharge current flows from VDDQSNS pulse width. Therefore, monitoring VPHASE voltage as input voltage to calculate on-time when the high-side to PGND in this mode. In case of no discharge mode, APW8813/A does not discharge output charge at all. MOSFET is turned on. And then, use the relationship between ontime and duty cycle to obtain the switching Thermal Shutdown frequency. A thermal shutdown circuit limits the junction temperature of APW8813/A. When the junction temperature exceeds +160oC, PWM converter, VTTLDO and VTTREF are shut off, allowing the device to cool down. The regulator Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 22 www.anpec.com.tw APW8813/A Application Information power dissipation of the converter. The maximum Output Voltage Selection Connect VDDQSET to GND to set the DDR3 fixed 1.5V or ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be connect VDDQSET to VCC to set the DDR2 fixed 1.8V output voltage. The output voltage, VOUT = VVDDQ, of PWM approximately 30% of the maximum output current. Once the inductance value has been chosen, selecting can be also adjusted from 0.75V to 5.5V with a resistordriver at VDDQSET between VDDQSNS and GND. Using an inductor is capable of carrying the required peak current without going into saturation. In some types of 1% or better resistors for the resistive divider is recommended. The VDDQSET pin is the inverter input of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will the error amplifier, and the reference voltage is 0.75V. Take the example, the output voltage of PWM1 is deter- be result in a larger output ripple voltage. mined by: Output Capacitor Selection RTOP VOUTI = 0.75 × 1 + R GND Ou tp ut vol ta ge r ip pl e and t he t rans ie nt vol ta g e de viat ion are fac tor s th at h ave to be take n in to Where RTOP is the resistor connected from V OUTI to consideration when selecting an output capacitor. Higher capacitor value and lower ESR reduce the V VDDQSET and R GND is the resistor connected from VDDQSET to GND. output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switching regulator applications. In addition to high frequency noise related MOSFET turn-on and turn- Output Inductor Selection The duty cycle of a buck converter is the function of the off, the output voltage ripple includes the capacitance voltage drop and ESR voltage drop caused by the AC peak- input voltage and output voltage. Once an output voltage is fixed, it can be written as: to-peak current. These two voltages can be represented by: V D = OUT VIN ∆VESR The inductor value determines the inductor ripple current These two components constitute a large portion of the total output voltage ripple. In some applications, multiple and affects the load transient reponse. Higher inductor value reduces the inductor’s ripple current and induces capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support lower output ripple voltage. The ripple current and ripple voltage can be approxminated by: IRIPPLE another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR VIN - VOUT VOUT = × FSW × L VIN and suppress the voltage ripple to a tolerable level. A small decoupling capacitor in parallel for bypassing Where FSW is the switching frequency of the regulator. Although increase the inductor value and frequency the noise is also recommended, and the voltage rating of the output capacitors must also be considered. reduce the ripple current and voltage, there is a tradeoff between the inductor’s ripple current and the regulator To support a load transient that is faster than the switching frequency, more capacitors have to be used to reduce the voltage excursion during load step change. load transient response time. A smaller inductor will give the regulator a faster load Another aspect of the capacitor selection is that the total AC current going through the capacitors has to be transient response at the expense of higher ripple current. Increasing the switching frequency (FSW ) also less than the rated RMS current specified on the ca- reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 IRIPPLE 8COUTFSW = IRIPPLE × RESR ∆VCOUT = pacitors to prevent the capacitor from over-heating. 23 www.anpec.com.tw APW8813/A Application Information (Cont.) Input Capacitor Selection losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and low- The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select side MOSFETs, the losses are approximately given by the following equations : the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS 2 Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW 2 current rating requirement is approximately IOUT/2, where IOUT is the load current. During power up, the input capaci- Plow-side = IOUT (1+ TC)(RDS(ON))(1-D) tors have to handle large amount of surge current. In lowduty notebook appliactions, ceramic capacitors are Where I is the load current OUT TC is the temperature dependency of RDS(ON) remmended. The capacitors must be connected between the drain of high-side MOSFET and the source of low- FSW is the switching frequency tSW is the switching interval side MOSFET with very low-impeadance PCB layout. D is the duty cycle Note that both MOSFETs have conduction losses while MOSFET Selection The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs the high-side MOSFET includes an additional transition loss. The switching internal, t SW , is the function should be used. The design has to trade off the gate charge with the RDS(ON) of the MOSFET: of the reverse transfer capacitance CRSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) • For the low-side MOSFET, before it is turned on, the and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET.. body diode has been conducted. The low-side MOSFET driver will not charge the miller capacitor of this Layout Consideration MOSFET. In any high switching frequency converter, a correct layout • In the turning off process of the low-side MOSFET, is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the the load current will shift to the body diode first. The high dv/dt of the phase node voltage will charge the miller capacitor through the low-side MOSFET driver resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit sinking current path. This results in much less switching loss of the low-side MOSFETs. The duty elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the cycle is often very small in high battery voltage applications, and the low-side MOSFET will con- MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling duct most of the switching cycle; therefore, the RDS(ON) of the low-side MOSFET, the less the power loss. The by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike gate charge for this MOSFET is usually a secondary consideration. The high-side MOSFET does not have during the switching interval. In general, using short and wide printed circuit traces should minimize interconnect- this zero voltage switching condition, and because it conducts for less time compared to the low-side ing impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separating and MOSFET, the switching loss tends to be dominant. Priority should be given to the MOSFETs with less finally combined to use the ground plane construction or single point grounding. The best tie-point between the gate charge, so that both the gate driver loss and switching loss will be minimized. The selection of the N-channel power MOSFETs are determined by the RDS(ON), reversing transfer capacitance signal ground and the power ground is at the negative side of the output capacitor on each channel, where there is less noise. Noisy traces beneath the IC are not recommended. Below is a checklist for your layout: (CRSS) and maximum output current requirement. The Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 24 www.anpec.com.tw APW8813/A Application Information (Cont.) Layout Consideration (Cont.) • The PGND trace should be a separate trace, and inde • Keep the switching nodes (UGATE, LGATE, BOOT, and pendently go to the source of the low-side MOSFETs for current limit accuracy. PHASE) away from sensitive small signal nodes (VDDQSET, VTTREF, CS, and MODE) since these nodes are fast mov ing signals. Therefore, keep traces TQFN4x4-24A to these nodes as short as possible and there should be no other weak signal traces in parallel with theses 4mm ThermalVia diameter 0.3mm X 4 traces on any layer. • The signals going through theses traces have both discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE) should be short 0.5mm * 0.25mm 2.25 mm high dv/dt and high di/dt, with high peak charging and and wide. • Place the source of the high-side MOSFET and the drain 4mm 0.5mm of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. 2.25 mm 0.46mm 0.4mm • Decoupling capacitor, the resistor dividers, boot capacitors, and current limit stetting resistor should be close their pins. (For example, place the decoupling * Just Recommend ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placednear the drain). TQFN3x3-20 • The input capacitor should be near the drain of the up 3mm per MOSFET; the high quality ceramic decoupling capacitor can be put close to the VCC and GND pins; the VTTREF decoupling capasitor should be close to the VTTREF pin and GND; the VDDQ and VTT output ca- 0.5mm * pacitors should be located right across their output pin as clase as possible to the part to minimize parasitics. 0.2mm 1.66 mm The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. • The drain of the MOSFETs (V and PHASE nodes) IN 3mm 0.4mm should be a large plane for heat sinking. And PHASE pin traces are also the return path for UGATE. Connect 1.66 mm 0.17 mm 0.5mm this pin to the converter’s upper MOSFET source. • The APW8813/A used ripple mode control. Build the resistor divider close to the VDDQSET pin so that the high imped ance trace is shorter when the output volt- * Just Recommend age is in ad justable mode. And the VDDQSET pin traces can’t be closed to the switching signal traces Figure 3. Recommened Minimum Footprint (UGATE, LGATE, BOOT, and PHASE). Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 25 www.anpec.com.tw APW8813/A Package Information TQFN4x4-24A A E b D Pin 1 A1 A3 NX D2 aaa c L K E2 Pin 1 Corner e S Y M B O L TQFN4x4-24A MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.032 A1 0.00 0.05 0.000 A3 0.20 REF 0.002 0.008 REF b 0.18 0.30 0.007 0.012 D 3.90 4.10 0.154 0.161 D2 2.00 2.50 0.079 0.098 0.161 0.098 E 3.90 4.10 0.154 E2 2.00 2.50 0.079 0.45 0.014 e L K 0.50 BSC 0.35 0.020 BSC 0.20 aaa Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 0.018 0.008 0.08 0.003 26 www.anpec.com.tw APW8813/A Package Information TQFN3x3-20 D E b A Pin 1 A1 A3 D2 NX aaa C L K E2 Pin 1 Corner e S Y M B O L TQFN3x3-20 MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.25 0.006 0.010 A3 0.20 REF 0.008 REF b 0.15 D 2.90 3.10 0.114 0.122 D2 1.50 1.80 0.059 0.071 E 2.90 3.10 0.114 0.122 E2 1.50 1.80 0.059 0.071 0.50 0.012 e 0.40 BSC L 0.30 K 0.20 0.016 BSC 0.008 0.08 aaa 0.020 0.003 Note : 1. Followed from JEDEC MO-220 WEEE Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 27 www.anpec.com.tw APW8813/A Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN4x4-24A Application TQFN3x3-20 A H T1 C d D W E1 F 330.0±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.25±0.20 4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 -0.00 A H T1 C d D W E1 F 330±2.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 3.30±0.20 3.30±0.20 1.30±0.20 4.0±0.10 8.0±0.10 Devices Per Unit Package Type TQFN4x4-24A TQFN3x3-20 (mm) Unit Tape & Reel Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 Quantity 3000 3000 28 www.anpec.com.tw APW8813/A Taping Direction Information TQFN4x4-24A USER DIRECTION OF FEED TQFN3x3-20 USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 29 www.anpec.com.tw APW8813/A Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 30 www.anpec.com.tw APW8813/A Classification Reflow Profiles Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245°C 1000 Hrs, Bias @ Tj=125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.6 - Sep., 2012 31 www.anpec.com.tw