Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design CSD17308Q3 SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 CSD17308Q3 30-V N-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • • 1 Product Summary Optimized for 5-V Gate Drive Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free VSON 3.3 mm × 3.3 mm Plastic Package TA = 25°C 30 V Qg Gate charge total (4.5 V) 3.9 nC Qgd Gate charge gate to drain RDS(on) VGS(th) 0.8 Drain-to-source on resistance nC VGS = 3 V 12.5 mΩ VGS = 4.5 V 9.4 mΩ VGS = 8 V 8.2 mΩ Threshold voltage 1.3 V Ordering Information(1) DEVICE Notebook Point of Load Point-of-Load Synchronous Buck in Networking, Telecom, and Computing Systems CSD17308Q3 This 30-V, 8.2-mΩ, 3.3 mm × 3.3 mm VSON NexFET™ power MOSFET is designed to minimize losses in power conversion applications and optimized for 5-V gate drive applications. Top View 7 6 VALUE UNIT 30 V VGS Gate-to-source voltage +10 / –8 V D D 5 D 2500 Drain-to-source voltage D D SHIP Tape and Reel VDS PD S PACKAGE SON 3.3 mm × 3.3 mm Plastic Package Absolute Maximum Ratings IDM S MEDIA 13-Inch Reel TA = 25°C unless otherwise stated ID 8 S QTY (1) For all available packages, see the orderable addendum at the end of the data sheet. 3 Description G UNIT Drain-to-source voltage 2 Applications • • VALUE VDS Continuous Drain Current (Package Limited) 50 Continuous drain current, TC = 25°C 44 Continuous drain current(1) 14 Pulsed drain current, TA = 25°C(2) 167 Power dissipation(1) 2.7 Power Dissipation, TC = 25°C 28 TJ, Tstg Operating Junction and Storage Temperature Range EAS Avalanche energy, single pulse ID = 36 A, L = 0.1 mH, RG = 25 Ω A A W –55 to 150 °C 65 mJ P0095-01 (1) Typical RθJA = 46°C/W when mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick FR4 PCB. (2) Max RθJC = 4.5°C/W, pulse duration ≤100 μs, duty cycle ≤1%. RDS(on) vs VGS Gate Charge 8 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 30 25 20 15 10 5 ID = 10 A 7 VDS = 15 V 6 5 4 3 2 1 0 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) 9 10 D007 0 1 2 3 4 5 Qg - Gate Charge (nC) 6 7 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD17308Q3 SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 6.2 6.3 6.4 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q3 Package Dimensions .......................................... 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Opening ............................... 9 Q3 Tape and Reel Information................................ 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2010) to Revision B Page • Added part number to title ..................................................................................................................................................... 1 • Added Package Limited Continuous Drain Current ............................................................................................................... 1 • Added line for Power Dissipation, TC = 25°C in Absolute Maximum Ratings table ............................................................... 1 • Updated pulsed current conditions ........................................................................................................................................ 1 • Updated Figure 1 to show RθJC curves................................................................................................................................... 4 • Added 4.5 V curve in Figure 8 ............................................................................................................................................... 6 • Udated Figure 10 ................................................................................................................................................................... 6 • Added the Device and Documentation Support section ........................................................................................................ 7 • Updated the Mechanical, Packaging, and Orderable Information section ............................................................................. 8 Changes from Original (February 2010) to Revision A • 2 Page Deleted the Package Marking Information section............................................................................................................... 10 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 CSD17308Q3 www.ti.com 5 SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 30 0.9 Drain-to-source on resistance gfs Transconductance μA 100 nA 1.3 1.8 V 12.5 16.5 mΩ VGS = 4.5 V, ID = 10 A 9.4 11.8 mΩ VGS = 8 V, ID = 10 A 8.2 10.3 mΩ VDS = 15 V, ID = 10 A 37 VGS = 3 V, ID = 10 A RDS(on) V 1 S DYNAMIC CHARACTERISTICS CISS Input capacitance 540 700 pF COSS Output capacitance CRSS Reverse transfer capacitance 280 365 pF 27 35 Rg pF Series gate resistance 0.9 1.8 Ω Qg Gate charge total (4.5 V) 3.9 5.1 nC Qgd Gate charge gate to drain 0.8 nC Qgs Gate charge gate to source 1.3 nC Qg(th) Gate charge at Vth 0.7 nC QOSS Output charge 7.4 nC td(on) Turn on delay time 4.5 ns tr Rise time 5.7 ns td(off) Turn off delay time 9.9 ns tf Fall time 2.3 ns VGS = 0 V, VDS = 15 V, ƒ = 1 MHz VDS = 15 V, ID = 10 A VDS = 13 V, VGS = 0 V VDS = 15 V, VGS = 4.5 V, ID = 10 A, RG = 2 Ω DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time IDS = 10 A, VGS = 0 V 0.85 VDD = 13 V, IF = 10 A, di/dt = 300 A/μs 1 V 9.3 nC 14.3 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) MAX UNIT RθJC Junction-to-case thermal resistance (1) THERMAL METRIC 4.5 °C/W RθJA Junction-to-ambient thermal resistance (1) (2) 58 °C/W (1) (2) MIN TYP RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 3 CSD17308Q3 SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 GATE www.ti.com GATE Source Source Max RθJA = 58°C/W when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Max RθJA = 165°C/W when mounted on a minimum pad area of 2 oz. (0.071 mm thick) Cu. DRAIN DRAIN M0161-02 M0161-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 CSD17308Q3 www.ti.com SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 30 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 50 40 30 20 10 VGS = 3.5 V VGS = 4.5 V VGS = 8.0 V 0 TC = 125° C TC = 25° C TC = -55° C 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 VDS - Drain-to-Source Voltage (V) 1 1 1.2 1.4 D002 1.6 1.8 2 2.2 2.4 2.6 VGS - Gate-to-Source Voltage (V) 2.8 3 D003 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 7 6 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 8 5 4 3 2 1000 100 1 10 0 0 1 2 3 4 5 Qg - Gate Charge (nC) ID = 10 A 6 0 7 5 D004 Figure 4. Gate Charge D005 Figure 5. Capacitance 30 RDS(on) - On-State Resistance (m:) VGS(th) - Threshold Voltage (V) 30 VDS = 15 V 1.7 1.5 1.3 1.1 0.9 0.7 -75 10 15 20 25 VDS - Drain-to-Source Voltage (V) 25 20 15 10 5 0 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 175 0 1 D006 ID = 250 µA 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) 9 10 D007 ID = 10 A Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 5 CSD17308Q3 SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 1.6 VGS = 4.5 V VGS = 8.0 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 1.8 1.4 1.2 1 0.8 0.6 0.4 -75 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) ID = 10 A 125 150 0 175 Figure 8. Normalized On-State Resistance vs Temperature 1 D009 Figure 9. Typical Diode Forward Voltage 100 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) VGS = 8 V 1000 100 10 1 100 ms 10 ms 0.11 0.1 0.2 D008 1 ms 100 µs 10 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25q C TC = 125q C 10 1 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D011 Single Pulse, Max RθJC = 4.5°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (°C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 CSD17308Q3 www.ti.com SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 6 Device and Documentation Support 6.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.2 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 7 CSD17308Q3 SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q3 Package Dimensions DIM MILLIMETERS NOM MAX MIN NOM MAX A 0.950 1.000 1.100 0.037 0.039 0.043 A1 0.000 0.000 0.050 0.000 0.000 0.002 b 0.280 0.340 0.400 0.011 0.013 0.016 b1 0.310 NOM 0.012 NOM c 0.150 0.200 0.250 0.006 0.008 0.010 D 3.200 3.300 3.400 0.126 0.130 0.134 D2 1.650 1.750 1.800 0.065 0.069 0.071 d 0.150 0.200 0.250 0.006 0.008 0.010 d1 0.300 0.350 0.400 0.012 0.014 0.016 E 3.200 3.300 3.400 0.126 0.130 0.134 E2 2.350 2.450 2.550 0.093 0.096 0.100 0.550 0.014 e H 0.650 TYP 0.35 K 8 INCHES MIN 0.450 0.026 TYP 0.650 TYP 0.018 0.022 0.026 TYP L 0.35 0.450 0.550 0.014 0.018 0.022 L1 0 — 0 0 — 0 θ 0 — 0 0 — 0 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 CSD17308Q3 www.ti.com SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 7.2 Recommended PCB Pattern For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Opening All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 9 CSD17308Q3 SLPS262B – FEBRUARY 2010 – REVISED OCTOBER 2015 www.ti.com 1.75 ±0.10 7.4 Q3 Tape and Reel Information 2.00 ±0.05 4.00 ±0.10 (See Note 1) 8.00 ±0.10 +0.10 –0.00 3.60 1.30 3.60 5.50 ±0.05 12.00 +0.30 –0.10 Ø 1.50 M0144-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified). 5. Thickness: 0.30 ±0.05 mm 6. MSL1 260°C (IR and Convection) PbF-Reflow Compatible 10 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: CSD17308Q3 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD17308Q3 ACTIVE VSON-CLIP DQG 8 2500 Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM -55 to 150 CSD17308 CSD17308Q3T ACTIVE VSON-CLIP DQG 8 250 Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM -55 to 150 CSD17308 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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