SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
D 15-V Digital or ±7.5-V Peak-to-Peak
D
D
D
D
D
D
D
D
D Matched Control-Input to Signal-Output
Switching
125-Ω Typical On-State Resistance for 15-V
Operation
Switch On-State Resistance Matched to
Within 5 Ω Over 15-V Signal-Input Range
On-State Resistance Flat Over Full
Peak-to-Peak Signal Range
High On/Off Output-Voltage Ratio: 80 dB
Typical at fis = 10 kHz, RL = 1 kΩ
High Degree of Linearity: <0.5% Distortion
Typical at fis = 1 kHz, Vis = 5 V p-p,
VDD − VSS ≥ 10 V, RL = 10 kΩ
Extremely Low Off-State Switch Leakage,
Resulting in Very Low Offset Current and
High Effective Off-State Resistance: 10 pA
Typical at VDD − VSS = 10 V, TA = 25°C
Extremely High Control Input Impedance
(Control Circuit Isolated From Signal
Circuit): 1012 Ω Typical
Low Crosstalk Between Switches: −50 dB
Typical at fis = 8 MHz, RL = 1 kΩ
D
D
D
D
D
Capacitance: Reduces Output Signal
Transients
Frequency Response, Switch On = 40 MHz
Typical
100% Tested for Quiescent Current at 20 V
5-V, 10-V, and 15-V Parametric Ratings
Meets All Requirements of JEDEC Tentative
Standard No. 13-B, Standard Specifications
for Description of “B” Series CMOS
Devices
Applications:
− Analog Signal Switching/Multiplexing:
Signal Gating, Modulator, Squelch
Control, Demodulator, Chopper,
Commutating Switch
− Digital Signal Switching/Multiplexing
− Transmission-Gate Logic Implementation
− Analog-to-Digital and Digital-to-Analog
Conversion
− Digital Control of Frequency, Impedance,
Phase, and Analog-Signal Gain
E, F, M, NS, OR PW PACKAGE
(TOP VIEW)
SIG A IN/OUT
SIG A OUT/IN
SIG B OUT/IN
SIG B IN/OUT
CONTROL B
CONTROL C
VSS
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD
CONTROL A
CONTROL D
SIG D IN/OUT
SIG D OUT/IN
SIG C OUT/IN
SIG C IN/OUT
description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals.
It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the
on-state resistance is relatively constant over the full signal-input range.
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices
in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the
n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch
is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and,
thus, keeps the on-state resistance low over the full operating-signal range.
The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply
voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold
applications, the CD4016B is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
POST OFFICE BOX 655303
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1
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
description/ordering information (continued)
ORDERING INFORMATION
−55°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TOP-SIDE
MARKING
CDIP − F
Tube of 25
CD4066BF3A
CD4066BF3A
PDIP − E
Tube of 25
CD4066BE
CD4066BE
Tube of 50
CD4066BM
Reel of 2500
CD4066BM96
Reel of 250
CD4066BMT
Reel of 2000
CD4066BNSR
Tube of 90
CD4066BPW
Reel of 2000
CD4066BPWR
SOIC − M
SOP − NS
TSSOP − PW
CD4066BM
CD4066B
CM066B
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Switch
Control
In
Vis
p
n
p
n
Control
VC†
Out
Vos
n
VSS
VDD
VSS
† All control inputs are protected by the CMOS protection network.
NOTES: A. All p substrates are connected to VDD.
B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS
C. Signal-level range: VSS ≤ Vis ≤ VDD
92CS-29113
Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
DC supply-voltage range, VDD (voltages referenced to VSS terminal) . . . . . . . . . . . . . . . . . . . . −0.5 V to 20 V
Input voltage range, Vis (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V
DC input current, IIN (any one input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Package thermal impedance, θJA (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 265°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN
VDD
TA
Supply voltage
Operating free-air temperature
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
3
18
V
−55
125
°C
3
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
electrical characteristics
LIMITS AT INDICATED TEMPERATURES
PARAMETER
IDD
TEST CONDITIONS
Quiescent device
current
VIN
(V)
VDD
(V)
UNIT
25°C
−55°C
−40°C
85°C
125°C
TYP
MAX
0, 5
5
0.25
0.25
7.5
7.5
0.01
0.25
0, 10
10
0.5
0.5
15
15
0.01
0.5
0, 15
15
1
1
30
30
0.01
1
0, 20
20
5
5
150
150
0.02
5
5
800
850
1200
1300
470
1050
10
310
330
500
550
180
400
15
200
210
300
320
125
240
µA
A
Signal Inputs (Vis) and Outputs (Vos)
ron
On-state resistance
(max)
VC = VDD,
RL = 10 kΩ returned
ǒV DD * V SSǓ
to
,
2
Vis = VSS to VDD
∆ron
THD
Iis
4
15
10
10
15
5
On-state resistance
difference between
any two switches
RL = 10 kΩ, VC = VDD
Total harmonic
distortion
VC = VDD = 5 V, VSS = −5 V,
Vis(p-p) = 5 V (sine wave centered on 0 V),
RL = 10 kΩ, fis = 1-kHz sine wave
0.4
%
−3-dB cutoff
frequency
(switch on)
VC = VDD = 5 V, VSS = −5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ
40
MHz
−50-dB feedthrough
frequency (switch off)
VC = VSS = −5 V, Vis(p-p) = 5 V
(sine wave centered on 0 V), RL = 1 kΩ
1
MHz
Input/output leakage
current (switch off)
(max)
VC = 0 V, Vis = 18 V, Vos = 0 V;
and
VC = 0 V, Vis = 0 V, Vos = 18 V
VC(A) = VDD = 5 V,
VC(B) = VSS = −5 V,
Vis(A) = 5 Vp-p, 50-Ω source,
RL = 1 kΩ
−50-dB crosstalk
frequency
tpd
5
Ω
Propagation delay
(signal input to
signal output)
Cis
Input capacitance
Cos
Cios
RL = 200 kΩ, VC = VDD,
VSS = GND, CL = 50 pF,
Vis = 10 V
(square wave centered on 5 V),
tr, tf = 20 ns
18
±0.1
±0.1
±1
±1
±10−5
Ω
±0.1
8
µA
MHz
5
20
40
10
10
20
15
7
15
ns
8
pF
Output capacitance
VDD = 5 V, VC = VSS = −5 V
VDD = 5 V, VC = VSS = −5 V
8
pF
Feedthrough
VDD = 5 V, VC = VSS = −5 V
0.5
pF
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
electrical characteristics (continued)
LIMITS AT INDICATED TEMPERATURES
CHARACTERISTIC
TEST CONDITIONS
UNIT
25°C
VDD
(V)
−55°C
−40°C
85°C
125°C
TYP
MAX
Control (VC)
VILC
Control input,
low voltage (max)
|Iis| < 10 µA,
Vis = VSS, VOS = VDD, and
Vis = VDD, VOS = VSS
5
1
1
1
1
1
10
2
2
2
2
2
15
2
2
2
2
2
5
VIHC
IIN
Control input,
high voltage
3.5 (MIN)
10
7 (MIN)
15
11 (MIN)
V
Input current (max)
Vis ≤ VDD, VDD − VSS = 18 V,
VCC ≤ VDD − VSS
18
Crosstalk (control input
to signal output)
VC = 10 V (square wave),
tr, tf = 20 ns, RL = 10 kΩ
10
50
5
35
70
Turn-on and turn-off
propagation delay
VIN = VDD, tr, tf = 20 ns,
CL = 50 pF, RL = 1 kΩ
10
20
40
15
15
30
5
6
10
9
15
9.5
Maximum control input
repetition rate
CI
See Figure 6
Vis = VDD, VSS = GND,
RL = 1 kΩ to GND, CL = 50 pF,
VC = 10 V (square wave
centered on 5 V), tr, tf = 20 ns,
Vos = 1/2 Vos at 1 kHz
V
±0.1
±0.1
±1
±1
±10−5
Input capacitance
5
±0.1
µA
mV
ns
MHz
7.5
pF
switching characteristics
SWITCH
OUTPUT, Vos
(V)
SWITCH INPUT
VDD
(V)
Vis
(V)
Iis (mA)
−55°C
−40°C
25°C
85°C
125°C
5
0
0.64
0.61
0.51
0.42
0.36
5
5
−0.64
−0.61
−0.51
−0.42
−0.36
10
0
1.6
1.5
1.3
1.1
0.9
10
10
−1.6
−1.5
−1.3
−1.1
−0.9
15
0
4.2
4
3.4
2.8
2.4
15
15
−4.2
−4
−3.4
−2.8
−2.4
POST OFFICE BOX 655303
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MIN
MAX
0.4
4.6
0.5
9.5
1.5
13.5
5
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
600
Supply Voltage (VDD − VSS) = 5 V
500
TA = 125°C
400
300
+25°C
200
−55°C
100
0
−4
−3
−2
−1
0
1
2
3
4
r − Channel On-State Resistance − Ω
on
r − Channel On-State Resistance − Ω
on
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
300
Supply Voltage (VDD − VSS) = 10 V
250
TA = 125°C
200
+25°C
150
−55°C
100
50
0
−10
−7.5
−5
−2.5
0
2.5
5
7.5
Vis − Input Signal Voltage − V
Vis − Input Signal Voltage − V
92CS-27327RI
92CS-27326RI
Figure 2
Figure 3
Supply Voltage (VDD − VSS) = 15 V
300
250
200
TA = 125°C
150
+25°C
100
−55°C
50
0
−7.5
−5
−2.5
0
2.5
5
7.5
10
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
r − Channel On-State Resistance − Ω
on
r − Channel On-State Resistance − Ω
on
TYPICAL ON-STATE RESISTANCE
vs
INPUT SIGNAL VOLTAGE (ALL TYPES)
−10
TA = 125°C
600
Supply Voltage (VDD − VSS) = 5 V
500
400
300
200
10 V
−15 V
100
0
−10
−7.5
−5
−2.5
0
2.5
5
7.5
10
Vis − Input Signal Voltage − V
Vis − Input Signal Voltage − V
92CS-27329RI
92CS-27330RI
Figure 5
Figure 4
6
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
Iis
Vis
CD4066B
1 of 4 Switches
ron =
Vos
|Vis − Vos|
|Iis|
92CS-30966
Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification
Keithley
160 Digital
Multimeter
VDD
TG
On
10 kΩ
1-kΩ
Range
Y
X-Y
Plotter
VSS
H. P.
Moseley
7030A
X
92CS-22716
Figure 7. Channel On-State Resistance Measurement Circuit
POWER DISSIPATION PER PACKAGE
vs
SWITCHING FREQUENCY
TYPICAL ON CHARACTERISTICS
FOR 1 OF 4 CHANNELS
3
VO − Output Voltage − V
2
1
0
VC = VDD
−1
Vis
CD4066B
1 of 4
Switches
Vos
RL
VSS
−2
−3
−3
VDD
All unused terminals are
connected to VSS
−2
−1
0
1
2
3
PD − Power Dissipation Per Package − µ W
104
4
6
4
TA = 25°C
2
103
Supply Voltage
(VDD) = 15 V
6
4
2
10 V
102
5V
6
4
14
5
2
6
101
12
6
4
13
CD4066B
7
2
10
10
VDD
2
VI − Input Voltage − V
4
6
102
2
4
VSS
6
103
f − Switching Frequency − kHz
92CS-30919
Figure 9
Figure 8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
92C-30920
7
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
Cios
VDD = 5 V
VC = −5 V
CD4066B
1 of 4
Switches
VC = VSS
Vis = VDD
Cis
VSS = −5 V
Cos
Figure 10. Typical On Characteristics
for One of Four Channels
Vos
I
92CS-30922
All unused terminals are connected to VSS.
Figure 11. Off-Switch Input or Output Leakage
VDD
VC = VDD
Vis
CD4066B
1 of 4
Switches
VSS
92CS-30921
Measured on Boonton capacitance bridge, model 75a (1 MHz);
test-fixture capacitance nulled out.
VDD
CD4066B
1 of 4
Switches
VSS
+10 V
Vos
50 pF
VC
tr = tf = 20 ns
200 kΩ
VDD
VDD
V
Vis
CD4066B os
1 of 4
Switches
10 kΩ
1 kΩ
VSS
tr = tf = 20 ns
92CS-30924
92CS-30923
All unused terminals are connected to VSS.
All unused terminals are connected to VSS.
Figure 12. Propagation Delay Time Signal Input
(Vis) to Signal Output (Vos)
8
POST OFFICE BOX 655303
Figure 13. Crosstalk-Control Input
to Signal Output
• DALLAS, TEXAS 75265
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
VDD
VDD
VC = VDD
tr = tf = 20 ns
CD4066B
1 of 4
Switches
VDD
VSS
Vos
50 pF
1 kΩ
NOTES: A. All unused terminals are connected to VSS.
B. Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).
92CS-30925
Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output
tr
VC
10%
tf
10 V
90%
50%
0V
Repetition
Rate
tr = tf = 20 ns
Vos
V OS +
V OS at 1 kHz
2
VDD = 10 V
VC
Vis = 10 V
CD4066B
1 of 4
Switches
V OS +
50 pF
V OS at 1 kHz
2
1 kΩ
VSS
All unused terminals are connected to VSS.
92CS-30925
Figure 15. Maximum Allowable Control-Input Repetition Rate
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9
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
VDD
Inputs
VDD
I
VSS
92CS-27555
VSS
Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.
Figure 16. Input Leakage-Current Test Circuit
10
10
Clock
Reset
14
2
P E J1
7
9
12
J2
J3
J4
J5
Clock
CD4018B
15
1
3
External
Reset
13
14
P E J1
15
1/4 CD4066B
1
4
3
7
9
12
J2
J3
J4
J5
CD4018B
Q1 Q2
1
Q1 Q2
5
2
5
2
4
13
1
3
7
2
2
1/3 CD4049B
5
6
4
8
9
8
6
5
2
1
1/3 CD4049B
5
CD4001B
3
12
6
4
9
CD4001B
10
10
11
4
3
10
9
6
12
5
12
13
6
5
Signal
Outputs
11
11
13
Signal
Inputs
11
12
Channel 1
Channel 2
4
Channel 3
CD4066B
5
9
11
10
3
4
4
Channel 4
1/4 CD4066B
3
8
9
10 kΩ
Maximum
Allowable
Signal Level
LPF
Channel 2
10 kΩ
CD4066B
11
Package Count
2 - CD4001B
1 - CD4049B
3 - CD4066B
2 - CD4018B
Channel 1
1
3
8
LPF
10 k Ω
1/6 CD4049B
2
1
2
12
LPF
Channel 3
10 kΩ
VDD
Clock
30% (VDD − VSS)
VSS
10
LPF Channel 4
10 kΩ
Chan 1 Chan 2 Chan 3 Chan 4
92CM-30928
Figure 17. Four-Channel PAM Multiplex System Diagram
10
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SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
TYPICAL CHARACTERISTICS
5V
0
−5 V
Analog Inputs (±5 V)
VDD = 5 V
VDD = 5 V
CD4066B
5V
SWA
0
IN
SWB
CD4054B
SWC
SWD
Digital
Control
Inputs
VSS = 0 V
VEE = −5 V
Analog Outputs (±5 V)
VSS = −5 V
92CS-30927
Figure 18. Bidirectional Signal Transmission Via Digital Control Logic
POST OFFICE BOX 655303
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11
SCHS051D − NOVEMBER 1998 − REVISED SEPTEMBER 2003
APPLICATION INFORMATION
In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability
should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids
any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B.
In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid
drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional
switch must not exceed 0.8 V (calculated from ron values shown).
No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD4066BE
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD4066BE
CD4066BEE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD4066BE
CD4066BF
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD4066BF
CD4066BF3A
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD4066BF3A
CD4066BF3AS2283
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
CD4066BF3AS2534
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
CD4066BM
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BM96
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BM96E4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BM96G4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BME4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BMG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BMT
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BMTE4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BMTG4
ACTIVE
SOIC
D
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066BM
CD4066BNSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066B
CD4066BNSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066B
CD4066BNSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CD4066B
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD4066BPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM066B
CD4066BPWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM066B
CD4066BPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM066B
CD4066BPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM066B
CD4066BPWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM066B
CD4066BPWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
CM066B
JM38510/05852BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
05852BCA
M38510/05852BCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
JM38510/
05852BCA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL :
• Catalog: CD4066B
• Automotive: CD4066B-Q1, CD4066B-Q1
• Military: CD4066B-MIL
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD4066BM96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD4066BM96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD4066BM96G4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD4066BM96G4
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD4066BMT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD4066BNSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
CD4066BPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Dec-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD4066BM96
SOIC
D
14
2500
367.0
367.0
38.0
CD4066BM96
SOIC
D
14
2500
333.2
345.9
28.6
CD4066BM96G4
SOIC
D
14
2500
367.0
367.0
38.0
CD4066BM96G4
SOIC
D
14
2500
333.2
345.9
28.6
CD4066BMT
SOIC
D
14
250
367.0
367.0
38.0
CD4066BNSR
SO
NS
14
2000
367.0
367.0
38.0
CD4066BPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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