Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ THIS DOCUMENT IS FOR MAINTENANCE PURPOSES ONLY AND IS NOT RECOMMENDED FOR NEW DESIGNS NJ8820 DS3277-1.2 NJ8820 FREQUENCY SYNTHESISER (PROM INTERFACE) The NJ8820 is a synthesiser circuit fabricated on the GPS CMOS process and is capable of achieving high sideband attenuation and low noise performance. It contains a reference oscillator, 11-bit programmable reference divider, digital and sample-and-hold comparators, 10-bit programmable ‘M’ counter, 7-bit programmable ‘A’ counter and the necessary control and latch circuitry for accepting and latching the input data. Data is presented as eight 4-bit words read from an external memory, with the necessary timing signals generated internally. It is intended to be used in conjunction with a two-modulus prescaler such as the SP8710 series to produce a universal binary coded synthesiser. The NJ8820 is available in Plastic DIL (DP) and Miniature Plastic DIL (MP) packages, both with operating temperature range of 230°C to 170°C. The NJ8820MA is available only in Ceramic DIL package with operating temperature range of 240°C to 185°C. PDA 1 20 CH PDB 2 19 RB LD 3 18 MC FIN 4 17 DS2 VSS 5 16 DS1 VDD 6 15 DS0 OSC IN 7 14 PE OSC OUT 8 13 ME D0 9 12 D3 D1 10 11 D2 FEATURES ■ ■ ■ ■ NJ8820 DP20, MP20, DG20 Fig.1 Pin connections - top view Low Power Consumption Direct Interface to ROM or PROM ABSOLUTE MAXIMUM RATINGS High Performance Sample and Hold Phase Detector 20·5V to 7V Supply voltage, VDD2VSS Input voltage 7V Open drain outputs, pins 3 and 13 VSS20·3V to VDD10·3V All other pins Storage temperature 265°C to 1150°C (DG package, NJ8820MA) 255°C to 1125°C Storage temperature (DP and MP packages, NJ8820) >10MHz Input Frequency ORDERING INFORMATION NJ8820 BA DP Plastic DIL Package NJ8820 BA MP Miniature Plastic DIL Package NJ8820 MA DG Ceramic DIL Package MEMORY ENABLE (ME) DATA SELECT OUTPUTS DS0 DS1 DS2 15 13 PROGRAM ENABLE (PE) OSC IN OSC OUT 14 7 PULSE DETECT 16 RB 17 19 FIN REFERENCE COUNTER (11BITS) 42 fr 8 VDD 9 10 11 12 4 SAMPLE/HOLD PHASE DETECTOR 1 FREQUENCY/ PHASE DETECTOR 2 3 LATCH 4 LATCH 5 LATCH 1 LATCH 2 LATCH 3 ‘A’ COUNTER (7 BITS) ‘M’ COUNTER (10 BITS) PDA PDB LOCK DETECT (LD) VSS fv 6 CONTROL LOGIC VSS 20 TO INTERNAL LATCHES SEQUENCE COUNTER LATCH 6 LATCH 7 LATCH 8 D0 DATA D1 INPUTS D2 D3 CH 5 Fig.2 Block diagram 18 MODULUS CONTROL OUTPUT (MC) NJ8820 ELECTRICAL CHARACTERISTICS AT VDD = 5V Test conditions unless otherwise stated: VDD–VSS=5V ±0·5V. Temperature range NJ8820 BA: –30°C to +70°C; NJ8820 MA: –40°C to +85°C DC Characteristics Value Min. Supply current OUTPUT LEVELS Memory Enable Output (ME) Low level Open drain pull-up voltage Data Select Outputs (DS0-DS2) High level Low level Modulus Control Output (MC) High level Low level Lock Detect Output (LD) Low level Open drain pull-up voltage PDB Output High level Low level 3-state leakage current INPUT LEVELS Data Inputs (D0-D3) High level Low level Program Enable Input (PE) Trigger level Units Conditions Typ. Max. 3·5 0·7 5·5 1·5 mA mA 0·4 7 V V ISINK = 4mA 0·4 V V ISOURCE = 1mA ISINK = 2mA 0·4 V V ISOURCE = 1mA ISINK = 1mA 0·4 7 V V ISINK = 4mA 0·4 60·1 V V µA ISOURCE = 5mA ISINK = 5mA 0·75 V V TTL compatible See note 1 V VBIAS = self-bias point of PE (nominally VDD/2) 4·6 4·6 4·6 4·25 VBIAS 6100mV fosc, fFIN = 10MHz fosc, fFIN = 1·0MHz Characteristic 0 to 5V square wave AC Characteristics Value Characteristic Min. FIN and OSC IN input level Max. operating frequency, fFIN and fosc Propagation delay, clock to MC PE pulse length, tW Data set-up time, tDS Data hold time, tDH Digital phase detector propagation delay Gain programming resistor, RB Hold capacitor, CH Output resistance, PDA Digital phase detector gain Power supply rise time Typ. Units Max. 200 10·6 30 50 5 1 10 500 5 1 5 0·4 100 Conditions mVRMS 10MHz AC-coupled sinewave MHz Input squarewave VDD to VSS, See note 5. See note 2. ns Pulse to VSS or VDD. µs µs ns ns kΩ See note 3. nF kΩ V/Rad 10% to 90%, see note 4. µs NOTES 1. Data inputs have internal pull-up resistors to enable them to be driven from TTL outputs. 2. All counters have outputs directly synchronous with their respective clock rising edges. 3. The finite output resistance of the internal voltage follower and ‘on’ resistance of the sample switch driving this pin will add a finite time constant to the loop. An external 1nF hold capacitor will give a maximum time constant of 5µs, typically. 4. To ensure correct operation of power-on programming. 5. Operation at up to 15MHz is possible with a full logic swing but is not guaranteed. 2 NJ8820 PIN DESCRIPTIONS Pin no. Name Description 1 PDA Analog output from the sample and hold phase comparator for use as a ‘fine’ error signal. Output at (VDD2VSS)/2 when the system is in lock. Voltage increases as fv phase lead increases; voltage decreases as fr phase lead increases. Output is linear over only a narrow phase window, determined by gain (programmed by RB). 2 PDB Three-state output from the phase/frequency detector for use as a ‘coarse’ error signal. fv. fr or fv leading: positive pulses with respect to the bias point VBIAS fv , fr or fr leading: negative pulses with respect to the bias point VBIAS fv = fr and phase error within PDA window: high impedance. 3 LD An open-drain lock detect output at low level when phase error is within PDA window (in lock); high impedance at all other times. 4 FIN The input to the main counters, normally driven from a prescaler, which may be AC-coupled or, when a full logic swing is available, may be DC-coupled. 5 VSS Negative supply (ground). 6 VDD Positive supply. OSC IN/ These pins form an on-chip reference oscillator when a series resonant crystal is connected across OSC OUT them. Capacitors of appropriate value are also required between each end of the crystal and ground to provide the necessary additional phase shift. An external reference signal may, alternatively, be applied to OSC IN. This may be a low-level signal, AC-coupled, or if a full logic swing is available it may be DC-coupled. The program range of the reference counter is 3 to 2047, with the division ratio being twice the programmed number. 7, 8 9,10, 11, 12 D0-D3 Information on these inputs is transferred to the internal data latches during the appropriate data read time slot. D3 is MSB, D0 is LSB. 13 ME An open drain output for use in controlling the power supply to an external ROM or PROM. ME is low during the data read period and high impedance at other times. 14 PE A positive or negative pulse or edge AC-coupled into this pin initiates the single-shot data read procedure. Grounding this pin repeats the data read procedure in a cyclic manner. 15, 16, 17 DS0-DS2 Internally generated three-state data select outputs, which may be used to address external memory. 18 MC Modulus control output for controlling an external dual-modulus prescaler. MC will be low at the beginning of a count cycle and will remain low until the ‘A’ counter completes its cycle. MC then goes high and remains high until the ‘M’ counter completes its cycle, at which point both ‘A’ and ‘M’ counters are reset. This gives a total division ratio of MP1A, where P and P11 represent the dual-modulus prescaler values. The program range of the ‘A’ counter is 0-127 and therefore can control prescalers with a division ratio up to and including 4128/129. The programming range of the ‘M’ counter is 8-1023 and, for correct operation, M>A. Where every possible channel is required, the minimum total division ratio should be P 22P. 19 RB An external sample and hold phase comparator gain programming resistor should be connected between this pin and VSS. 20 CH An external hold capacitor should be connected between this pin and VSS. 2·0 8 VDD = 5V FIN = LOW FREQUENCY 0V TO 5V SQUARE WAVE 7 1·5 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) VDD = 5V OSC IN, FIN = 0V TO 5V SQUARE WAVE OSC IN 1·0 FIN 0·5 6 5 10MHz 4 1MHz 3 2 TOTAL SUPPLY CURRENT IS THE SUM OF THAT DUE TO FIN AND OSC IN 1 2 3 4 5 6 7 INPUT FREQUENCY (MHz) 8 9 Fig. 3 Typical supply current v. input frequency 1 10 0·2 0·4 0·6 0·8 1·0 1·2 INPUT LEVEL (V RMS) 1·4 1·6 Fig. 4 Typical supply current v. input level, OSC IN 3 NJ8820 PROGRAMMING Program information can be obtained from an external ROM or PROM under the control of the NJ8820. Twenty-eight data bits are required per channel arranged as eight 4-bit words leaving four redundant bits, two of which are available on the data bus driving the data transfer time slot and may be used for external control purposes. A suitable PROM would be the 74S287, giving up to 32 channel capability as shown in Fig. 5. Note that the choice of PNP transistor and supply bypass capacitor on the ROM should be such that the ROM will power up in time: for example, at 10MHz oscillator frequency, the ROM must be powered up in less than 25µs. Reading this data is normally done in single shot mode, with the data read cycle started by either a positive or negative pulse on the program enable (PE) pin. The data read cycle is generated from a program clock at 1/64 of the reference oscillator frequency. A memory enable signal (ME) is supplied to allow power-down of the ROM when it is not in use. Data select outputs (DS0-DS2) remain in a high impedance state when the program cycle is completed to allow the address bus to be used for other functions if desired. The data map, data read cycle and timing diagram are shown in Figs. 6 to 8. Data is latched internally during the portions of the program cycle shown shaded in Fig. 7 and all data is transferred to the counters and latched during the data transfer time slot. Alternatively, the PE pin may be grounded, causing the data read cycle to repeat cyclically to allow continuous up-dating of the program information. In this mode, external memory will be enabled continuously (ME low) and the data read cycle will repeat every sixteen cycles of the internal program clock, i.e. every 1024/fosc seconds. This programming method is not recommended because the higher power consumption and the possibilities of noise into the loop from the digital data lines. Power-on Programming On power-up, the data read cycle is automatically initiated, making it unnecessary to provide a PE pulse. The circuit detects the power supply rising above a threshold point (nominally 1·5V) and, after an internally generated delay to allow the supply to rise fully, the circuit is programmed in the normal way. This delay is generated by counting reference oscillator pulses and is therefore dependent on the crystal used. The delay consists of 53248 reference oscillator cycles, giving a delay of about 5ms at 10MHz. To ensure correct operation of this function, the power supply rise time should be less than 5ms (at 10MHz), rising smoothly through the threshold point. 15V A4-A7 (CHANNEL SWITCH) 100k 1·5k 16 1 0·1µ 1 20 2 15 2 19 3 14 3 18 4 13 4 17 12 5 6 11 6 15 7 10 7 14 8 9 8 13 9 12 10 11 5 74S287 10µ D0 D1 NJ8820 16 C2B 22p DS2 DS1 DS0 C2A 22p PE C1 47p ME D3 C1 > C2A 1 C2B 1... D2 Fig. 5 Programming via PROM WORD DS2 DS1 DS0 D3 D2 D1 D0 1 2 3 4 5 6 7 8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 M1 M5 M9 A3 R3 R7 - M0 M4 M8 A2 A6 R2 R6 R10 M3 M7 A1 A5 R1 R5 R9 M2 M6 A0 A4 R0 R4 R8 Fig. 6 Data map 4 NJ8820 PROGRAM CLOCK PE ME DATA TRANSFER ON 2VE CYCLE OF PROGRAM CLOCK DS0 DS1 DS2 DATA TRANSFER 4 PROGRAM CLOCK CYCLES FROM SETTLING WORD WORD WORD WORD WORD WORD WORD WORD 1 2 3 4 5 6 7 8 Fig.7 Data selection PE DS0 tW (PE INTERNAL) D0 - D3 tDS tDH (DATA - INTERNAL MODE) Fig.8 Timing diagram PHASE COMPARATORS The digital phase/frequency detector drives a three-state output, PDB, which provides a ‘coarse’ error signal to enable fast switching between channels. The PDB output is active until the phase error is within the sample and hold phase detector, PDA, window, when PDB becomes high impedance. Phase-lock is indicated at this point by a low level on LD. The sample and hold phase detector provides a ‘fine’ error signal to give further phase adjustment and to hold the loop in lock. An internally generated ramp, controlled by the digital output from both the reference and main divider chains, is sampled at the reference frequency to give the ‘fine’ error signal, PDA. When in phase lock, this output would be typically at (VDD2VSS)/2 and any offset from this would be proportional to phase error. The relationship between this offset and the phase error is the phase comparator gain, which is programmable with an external resistor, RB. An internal 50pF capacitor is used in the sample and hold comparator. CRYSTAL OSCILLATOR When using the internal oscillator, the stability may be enhanced at high frequencies by the inclusion of a resistor between pin 8 (OSC OUT) and the other components. A value of 2·2kΩ is advised. PROGRAMMING/POWER UP Data and signal input pins should not have input applied to them prior to the application of VDD, as otherwise latch-up may occur. 5 NJ8820 HEADQUARTERS OPERATIONS GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017 1500 Green Hills Road, Scotts Valley, California 95067-0017, United States of America. Tel: (408) 438 2900 Fax: (408) 438 5576 CUSTOMER SERVICE CENTRES • FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax : (1) 64 46 06 07 • GERMANY Munich Tel: (089) 3609 06-0 Fax : (089) 3609 06-55 • ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993 • JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 • NORTH AMERICA Scotts Valley, USA Tel (408) 438 2900 Fax: (408) 438 7023. • SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872 • SWEDEN Stockholm, Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 • TAIWAN, ROC Taipei Tel: 886 2 5461260. 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