LINER LTC6991HS6PBF Timerblox: resettable, low frequency oscillator Datasheet

LTC6991
TimerBlox: Resettable, Low
Frequency Oscillator
Features
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Description
Period Range: 1ms to 9.5 Hours
Configured with 1 to 3 Resistors
<1.5% Maximum Frequency Error
Output Reset Function
2.25V to 5.5V Single Supply Operation
55µA to 80µA Supply Current
(2ms to 9.5hr Clock Period)
500µs Start-Up Time
CMOS Output Driver Sources/Sinks 20mA
–40°C to 125°C Operating Temperature Range
Available in Low Profile (1mm) SOT-23 (ThinSOT™)
and 2mm × 3mm DFN Packages
Applications
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“Heartbeat” Timers
Watchdog Timers
Intervalometers
Periodic “Wake-Up” Call
High Vibration, High Acceleration Environments
Portable and Battery-Powered Equipment
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT and TimerBlox are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners.
The LTC®6991 is a silicon oscillator with a programmable
period range of 1.024ms to 9.54 hours (29.1µHz to 977Hz),
specifically intended for long duration timing events. The
LTC6991 is part of the TimerBlox™ family of versatile
silicon timing devices.
A single resistor, RSET , programs the LTC6991’s internal
master oscillator frequency. The output clock period
is determined by this master oscillator and an internal
frequency divider, NDIV , programmable to eight settings
from 1 to 221.
tOUT =
NDIV • RSET
• 1.024ms, NDIV = 18
, , 64,..., 221
50kΩ
In normal operation, the LTC6991 oscillates with a 50%
duty cycle. A reset function is provided to truncate the
pulse (reducing the duty cycle). The reset pin can also be
used to prevent the output from oscillating.
The RST and OUT pins can be configured for active-low
or active-high operation using a polarity function.
POL BIT
0
0
1
1
RST PIN
0
1
0
1
OUTPUT STATE
Oscillating
0 (reset)
1 (reset)
Oscillating
The LTC6991 is available in the 6-lead SOT-23 (ThinSOT)
package or a 6-lead 2mm × 3mm DFN.
Typical Application
Clock Period Range over Eight Divider Settings
10Hr
Low Frequency Pulse Generator
RST
LTC6991
GND
RSET
715k
OUT
2.25V TO 5.5V
V
+
R1
1M
SET
DIV
R2
392k
tPULSE ≈ RPW • CPW ≈ 1µs
0.1µF
6991 TA01a
CLOCK PERIOD (LOG SCALE)
OUT
RPW
2.26k
CPW
470pF
1Hr
1µs PULSE WIDTH
60 SECONDS
10Min
1Min
10Sec
1Sec
100ms
10ms
1ms
0
1.25
0.625
1.875
DIV PIN VOLTAGE, VDIV (V)
2.5
6991 TA01b
6991f
LTC6991
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V+) to GND.........................................6V
Maximum Voltage
on Any Pin................. (GND – 0.3V) ≤ VPIN ≤ (V+ + 0.3V)
Operating Temperature Range (Note 2)
LTC6991C.............................................–40°C to 85°C
LTC6991I..............................................–40°C to 85°C
LTC6991H........................................... –40°C to 125°C
Specified Temperature Range (Note 3)
LTC6991C................................................. 0°C to 70°C
LTC6991I..............................................–40°C to 85°C
LTC6991H........................................... –40°C to 125°C
Junction Temperature............................................ 150°C
Storage Temperature Range................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
S6 Package............................................................ 300°C
Pin Configuration
TOP VIEW
V+ 1
DIV 2
TOP VIEW
6 OUT
7
5 GND
4 RST
SET 3
RST 1
6 OUT
GND 2
5 V+
SET 3
4 DIV
DCB PACKAGE
6-LEAD (2mm s 3mm) PLASTIC DFN
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 64°C/W, θJC = 10.6°C/W
EXPOSED PAD (PIN 7) CONNECTED TO GND,
PCB CONNECTION OPTIONAL
TJMAX = 150°C, θJA = 192°C/W, θJC = 51°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6991CDCB#PBF
LTC6991CDCB#TRPBF
LDWZ
6-Lead (2mm × 3mm) Plastic DFN
0°C to 70°C
LTC6991IDCB#PBF
LTC6991IDCB#TRPBF
LDWZ
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6991HDCB#PBF
LTC6991HDCB#TRPBF
LDWZ
6-Lead (2mm × 3mm) Plastic DFN
–40°C to 125°C
LTC6991CS6#PBF
LTC6991CS6#TRPBF
LTDWY
6-Lead Plastic TSOT-23
0°C to 70°C
LTC6991IS6#PBF
LTC6991IS6#TRPBF
LTDWY
6-Lead Plastic TSOT-23
–40°C to 85°C
LTC6991HS6#PBF
LTC6991HS6#TRPBF
LTDWY
6-Lead Plastic TSOT-23
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6991f
LTC6991
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = 5k, CLOAD = 5pF unless otherwise noted.
SYMBOL
PARAMETER
tOUT
Output Clock Period
fOUT
Output Frequency
∆fOUT
Frequency Accuracy (Note 4)
∆fOUT/∆T
Frequency Drift Over Temperature
CONDITIONS
MIN
TYP
34,360
29.1µ
977
Hz
±1.5
±2.2
%
%
±0.8
l
Frequency Drift Over Supply
Period Jitter (Note 10)
NDIV = 1
NDIV = 8
BW
Frequency Modulation Bandwidth
tS
Frequency Change Settling Time (Note 9)
UNITS
1.024m
29.1µHz ≤ fOUT ≤ 977Hz
V+ = 4.5V to 5.5V
V+ = 2.25V to 4.5V
MAX
l
±0.005
l
l
0.23
0.06
Seconds
%/°C
0.55
0.16
15
7
%/V
%/V
ppmRMS
ppmRMS
0.4 • fOUT
Hz
1
Cycle
Analog Inputs
VSET
Voltage at SET Pin
l
∆VSET/∆T
VSET Drift Over Temperature
l
RSET
Frequency-Setting Resistor
l
0.97
1.00
1.03
±75
V
µV/°C
50
800
kΩ
0
V+
V
l
±1.5
%
DIV Pin Input Current
l
±10
nA
Operating Supply Voltage Range
l
Power-On Reset Voltage
l
VDIV
DIV Pin Voltage
∆VDIV/∆V+
DIV Pin Valid Code Range (Note 5)
l
Deviation from Ideal
VDIV/V+ = (DIVCODE + 0.5)/16
Power Supply
V+
IS
Supply Current
2.25
5.5
V
1.95
V
RL = ∞, RSET = 50k
V+ = 5.5V
V+ = 2.25V
l
l
135
105
170
135
µA
µA
RL = ∞, RSET = 100k
V+ = 5.5V
V+ = 2.25V
l
l
100
80
130
105
µA
µA
RL = ∞, RSET = 800k
V+ = 5.5V
V+ = 2.25V
l
l
65
55
100
85
µA
µA
6991f
LTC6991
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, RST = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
SYMBOL
Digital I/O
VIH
VIL
IOUT(MAX)
VOH
PARAMETER
RST Pin Input Capacitance
RST Pin Input Current
High Level RST Pin Input Voltage
Low Level RST Pin Input Voltage
Output Output Current
High Level Output Voltage (Note 7)
CONDITIONS
(Note 6)
(Note 6)
V+ = 2.7V to 5.5V
V+ = 5.5V
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
tRST
Reset Propagation Delay
tWIDTH
tr
Minimum Input Pulse Width
Output Rise Time (Note 8)
tf
Output Fall Time (Note 8)
MAX
2.5
V+ = 2.25V
Low Level Output Voltage (Note 7)
TYP
RST = 0V to V+
V+ = 3.3V
VOL
MIN
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
V+ = 3.3V
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6991C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6991C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6991C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6991I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6991H is guaranteed
to meet specified performance from –40°C to 125°C.
Note 4: Frequency accuracy is defined as the deviation from the fOUT
equation, assuming RSET is used to program the frequency.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
±10
l
0.7 • V+
0.3 • V+
l
IOUT = –1mA
IOUT = –16mA
IOUT = –1mA
IOUT = –10mA
IOUT = –1mA
IOUT = –8mA
IOUT = 1mA
IOUT = 16mA
IOUT = 1mA
IOUT = 10mA
IOUT = 1mA
IOUT = 8mA
l
l
l
l
l
l
l
l
l
l
l
l
5.45
4.84
3.24
2.75
2.17
1.58
±20
5.48
5.15
3.27
2.99
2.21
1.88
0.02
0.26
0.03
0.22
0.03
0.26
16
24
40
5
1.1
1.7
2.7
1.0
1.6
2.4
0.04
0.54
0.05
0.46
0.07
0.54
UNITS
pF
nA
V
V
mA
V
V
V
V
V
V
V
V
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 6: The RST pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V+. Typical values can
be estimated at any supply voltage using VRST(RISING) ≈ 0.55 • V+ + 185mV
and VRST(FALLING) ≈ 0.48 • V+ – 155mV.
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within ±1% of the final frequency after a 0.5× or 2× change in ISET .
Note 10: Jitter is the ratio of the deviation of the period to the mean of the
period. This specification is based on characterization and is not 100%
tested.
6991f
LTC6991
Typical
Performance Characteristics
+
V = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Frequency Error vs Temperature
Frequency Error vs Temperature
3
GUARANTEED MAX OVER TEMPERATURE
RSET = 50k
3 PARTS
1
0
–1
2
RSET = 200k
3 PARTS
1
ERROR (%)
ERROR (%)
1
0
GUARANTEED MIN OVER TEMPERATURE
–3
–50 –25
50
25
75
0
TEMPERATURE (°C)
100
GUARANTEED MIN OVER TEMPERATURE
–2
–3
–50 –25
125
50
25
75
0
TEMPERATURE (°C)
100
6991 G01
Frequency Error vs RSET
GUARANTEED MAX OVER TEMPERATURE
200
–1
NUMBER OF UNITS
0.2
DRIFT (%)
ERROR (%)
250
0.3
3 PARTS
0.1
0
–0.1
–0.2
REFERENCED TO V+ = 4.5V
RSET = 50k
RSET = 200k
RSET = 800k
–0.3
GUARANTEED MIN OVER TEMPERATURE
–0.4
0
200
400
RSET (kΩ)
600
–0.5
800
2
0.8
0.6
0.6
0.4
0.4
0.2
0.2
–0.6
–0.6
–1.0
0
5
10
ISET (µA)
15
20
6992 G07
100
1.020
0.988
0.996
1.004
VSET (V)
VSET vs Temperature
3 PARTS
1.010
1.005
1.000
0.995
0.990
–0.8
–1.0
1.02
1.012
1.015
0
–0.4
REFERENCED TO ISET = 10µA
150
6991 G06
VSET Drift vs Supply
–0.2
–0.4
–0.8
2 LOTS
DFN AND SOT-23
1274 UNITS
0
0.98
VSET (V)
0.8
DRIFT (mV)
VSET (mV)
1.0
125
Typical VSET Distribution
6991 G05
VSET Drift vs ISET
0
100
50
6
4
3
5
SUPPLY VOLTAGE (V)
6991 G04
–0.2
50
25
75
0
TEMPERATURE (°C)
6991 G03
0.4
1
1.0
–3
–50 –25
125
Frequency Drift vs Supply Voltage
0
GUARANTEED MIN OVER TEMPERATURE
–2
0.5
–2
0
6991 G02
3
2
RSET = 800k
3 PARTS
–1
–1
–2
–3
GUARANTEED MAX OVER TEMPERATURE
GUARANTEED MAX OVER TEMPERATURE
2
ERROR (%)
2
Frequency Error vs Temperature
3
3
0.985
REFERENCED TO V+ = 4V
2
3
4
SUPPLY (V)
6
5
6991 G08
0.980
–50
–25
75
0
25
50
TEMPERATURE (°C)
100
125
6991 G09
6991f
LTC6991
Typical
Performance Characteristics
+
V = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Supply Current vs Supply Voltage
250
150
125
100
RSET = 100k
RSET = 200k
75
RSET = 800k
50
25
2
3
4
5
SUPPLY VOLTAGE (V)
125
POWER SUPPLY CURRENT (µA)
RSET = 50k
POWER SUPPLY CURRENT (µA)
POWER SUPPLY CURRENT (µA)
150
0
5V, RSET = 100k
100
2.5V, RSET = 100k
75
5V, RSET = 800k
50
2.5V, RSET = 800k
25
0
–50 –25
6
50
25
75
0
TEMPERATURE (°C)
100
6991 G10
1000
75
V+ = 2.5V
50
25
200
400
RSET (kΩ)
600
3.3V
RST RISING
100
50
0
0.2
0.6
0.4
VRST/V+ (V/V)
3.5
SET PIN SHORTED TO GND
3.0
POSITIVE-GOING
400
0
1.0
RST Threshold Voltage
vs Supply Voltage
600
800
0.8
6991 G12
200
0
3.3V
RST FALLING
0
RST PIN VOLTAGE (V)
100
V+ = 3.3V
5V
RST RISING
150
125
800
V+ = 5V
ISET (µA)
POWER SUPPLY CURRENT (µA)
125
5V
RST FALLING
200
Typical ISET Current Limit vs V+
150
RSET = 800k
6991 G11
Supply Current vs RSET
0
Supply Current
vs RST Pin Voltage
Supply Current vs Temperature
2.5
2.0
NEGATIVE-GOING
1.5
1.0
0.5
2
3
4
5
SUPPLY VOLTAGE (V)
0
6
2
3
4
5
SUPPLY VOLTAGE (V)
6991 G15
6
6991 G14
6991 G13
Reset Propagation Delay (tRST)
vs Supply Voltage
50
3.0
CLOAD = 5pF
35
30
25
20
15
10
2.0
tRISE
1.5
tFALL
1.0
0.5
5
0
CLOAD = 5pF
2.5
40
RISE/FALL TIME (ns)
PROPAGATION DELAY (ns)
45
Rise and Fall Time
vs Supply Voltage
2
4
3
5
SUPPLY VOLTAGE (V)
6
0
2
3
4
5
SUPPLY VOLTAGE (V)
6
6991 G17
6991 G16
6991f
LTC6991
Typical
Performance Characteristics
+
V = 3.3V, RSET = 200k, TA = 25°C unless otherwise noted.
Output Resistance
vs Supply Current
Typical Start-Up with POL = 1
50
OUTPUT RESISTANCE (Ω)
45
40
35
V+
1V/DIV
OUTPUT SOURCING CURRENT
30
1µs (tMASTER) WIDE
INITIAL PULSE
25
500µs
20
OUT
1V/DIV
OUTPUT SINKING CURRENT
15
10
5
0
2
3
4
5
SUPPLY VOLTAGE (V)
6
6991 G22
Pin Functions
V+ = 2.5V
DIVCODE = 15
RSET = 50k
250µs/DIV
6991 G19
(DCB/S6)
V+ (Pin 1/Pin 5): Supply Voltage (2.25V to 5.5V). This supply should be kept free from noise and ripple. It should be
bypassed directly to the GND pin with a 0.1µF capacitor.
50ppm/°C or better temperature coefficient. For lower accuracy applications an inexpensive 1% thick film resistor
may be used.
DIV (Pin 2/Pin 4): Programmable Divider and Polarity
Input. A V+ referenced A/D converter monitors the DIV
pin voltage (VDIV) to determine a 4-bit result (DIVCODE).
VDIV may be generated by a resistor divider between V+
and GND. Use 1% resistors to ensure an accurate result.
The DIV pin and resistors should be shielded from the
OUT pin or any other traces that have fast edges. Limit
the capacitance on the DIV pin to less than 100pF so that
VDIV settles quickly. The MSB of DIVCODE (POL) determines the polarity of the RST and OUT pins. If POL = 0,
RST is active-high, and forces OUT low. If POL = 1, RST
is active-low and forces OUT high.
Limit the capacitance on the SET pin to less than 10pF
to minimize jitter and ensure stability. Capacitance less
than 100pF maintains the stability of the feedback circuit
regulating the VSET voltage.
SET (Pin 3/Pin 3): Frequency-Setting Input. The voltage
on the SET pin (VSET) is regulated to 1V above GND. The
amount of current sourced from the SET pin (ISET) programs the master oscillator frequency. The ISET current
range is 1.25µA to 20µA. The output oscillation will stop
if ISET drops below approximately 500nA. A resistor connected between SET and GND is the most accurate way to
set the frequency. For best performance, use a precision
metal or thin film resistor of 0.5% or better tolerance and
V+
RST
OUT
LTC6991
GND
SET
RSET
V+
V+
C1
0.1µF
R1
DIV
6991 PF
R2
RST (Pin 4/Pin 1): Output Reset. The behavior of the RST
pin is dependent on the polarity bit (POL). The POL bit is
configured via the DIVCODE setting. When POL = 0, setting
RST high forces OUT low and setting RST low allows the
output to oscillate. When POL = 1, RST is active low. In
that case, setting RST low forces OUT high and setting
RST high allows the output to oscillate.
6991f
LTC6991
Pin Functions
(DCB/S6)
GND (Pin 5/Pin 2): Ground. Tie to a low inductance ground
plane for best performance.
30Ω. When driving an LED or other low impedance load a
series output resistor should be used to limit source/sink
current to 20mA.
OUT (Pin 6/Pin 6): Oscillator Output. The OUT pin swings
from GND to V+ with an output resistance of approximately
Block Diagram (S6 package pin numbers shown)
5
V+
R1
4
DIV
4-BIT A/D
CONVERTER
POL BIT
DIGITAL
FILTER
R2
OUTPUT
POLARITY
V+
MASTER OSCILLATOR
1µs
V
= SET
tMASTER =
50kΩ ISET
MCLK
FIXED
DIVIDER
÷ 1024
PROGRAMMABLE
DIVIDER
÷1, 8, 64, 512
4096, 215, 218, 221
HALT OSCILLATOR
IF ISET < 500nA
POR
D
OUT
6
tOUT
Q
R
INPUT
POLARITY
ISET
+
–
VSET = 1V
+
–
SET
3
1V
RST
GND
2
1
6991 BD
ISET
RSET
6991f
LTC6991
Operation
The LTC6991 is built around a master oscillator with a
1MHz maximum frequency. The oscillator is controlled
by the SET pin current (ISET) and voltage (VSET), with a
1MHz • 50k conversion factor that is accurate to ±0.8%
under typical conditions.
fMASTER =
1
tMASTER
I
= 1MHz • 50kΩ • SET
VSET
A feedback loop maintains VSET at 1V ±30mV, leaving ISET
as the primary means of controlling the output frequency.
The simplest way to generate ISET is to connect a resistor
(RSET) between SET and GND, such that ISET = VSET/RSET .
The master oscillator equation reduces to:
fMASTER =
1
tMASTER
=
DIVCODE
The DIV pin connects to an internal, V+ referenced 4-bit A/D
converter that determines the DIVCODE value. DIVCODE
programs two settings on the LTC6991:
1. DIVCODE determines the output frequency divider setting, NDIV .
2. DIVCODE determines the polarity of the RST and OUT
pins, via the POL bit.
VDIV may be generated by a resistor divider between V+
and GND as shown in Figure 1.
2.25V TO 5.5V
V+
1MHz • 50kΩ
RSET
LTC6991
DIV
R2
From this equation, it is clear that VSET drift will not affect
the output frequency when using a single program resistor
(RSET). Error sources are limited to RSET tolerance and the
inherent frequency accuracy ∆fOUT of the LTC6991.
RSET may range from 50k to 800k (equivalent to ISET
between 1.25µA and 20µA).
Before reaching the OUT pin, the oscillator frequency
passes through a fixed ÷1024 divider. The LTC6991 also
includes a programmable frequency divider which can
further divide the frequency by 1, 8, 64, 512, 4096, 215,
218 or 221. The divider ratio NDIV is set by a resistor divider
attached to the DIV pin.
fOUT =
tOUT =
1MHz • 50kΩ ISET
•
, or
1024 • NDIV VSET
1
fOUT
=
NDIV VSET
•
• 1.024ms
50kΩ ISET
with RSET in place of VSET/ISET the equation reduces to:
N •R
tOUT = DIV SET • 1.024ms
50kΩ
R1
GND
6991 F01
Figure 1. Simple Technique for Setting DIVCODE
Table 1 offers recommended 1% resistor values that accurately produce the correct voltage division as well as the
corresponding NDIV and POL values for the recommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resistor tolerances and temperature effects)
2. The driving impedance (R1||R2) does not exceed
500kΩ.
If the voltage is generated by other means (i.e., the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
V
+
=
DIVCODE + 0.5
± 1.5%
16
For example, if the supply is 3.3V and the desired DIVCODE
is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing that
NDIV is symmetric around the DIVCODE midpoint.
6991f
LTC6991
Operation
Table 1. DIVCODE Programming
DIVCODE
POL
NDIV
RECOMMENDED tOUT
R1 (kΩ)
R2 (kΩ)
VDIV/V+
0
0
1
1.024ms to 16.384ms
Open
Short
≤0.03125 ±0.015
1
0
8
8.192ms to 131ms
976
102
0.09375 ±0.015
2
0
64
65.5ms to 1.05sec
976
182
0.15625 ±0.015
3
0
512
524ms to 8.39sec
1000
280
0.21875 ±0.015
4
0
4,096
4.19sec to 67.1sec
1000
392
0.28125 ±0.015
5
0
32,768
33.6sec to 537sec
1000
523
0.34375 ±0.015
6
0
262,144
268sec to 4,295sec
1000
681
0.40625 ±0.015
7
0
2,097,152
2,147sec to 34,360sec
1000
887
0.46875 ±0.015
8
1
2,097,152
2,147sec to 34,360sec
887
1000
0.53125 ±0.015
9
1
262,144
268sec to 4,295sec
681
1000
0.59375 ±0.015
10
1
32,768
33.6sec to 537sec
523
1000
0.65625 ±0.015
11
1
4,096
4.19sec to 67.1sec
392
1000
0.71875 ±0.015
12
1
512
524ms to 8.39sec
280
1000
0.78125 ±0.015
13
1
64
65.5ms to 1.05sec
182
976
0.84375 ±0.015
14
1
8
8.192ms to 131ms
102
976
0.90625 ±0.015
15
1
1
1.024ms to 16.384ms
Short
Open
≥0.96875 ±0.015
POL BIT = 0
POL BIT = 1
10000
7
6
1000
9
10
5
100
tOUT (SECONDS)
8
11
4
10
12
3
1
13
2
0.1
1
0.01
0.001
14
0
0V
15
0.5•V+
INCREASING VDIV
V+
6991 F02
Figure 2. Frequency Range and POL Bit vs DIVCODE
6991f
10
LTC6991
Operation
RST Pin and Polarity (POL) Bit
The RST pin controls the state of the LTC6991’s output
as seen on the OUT pin. The active/inactive voltage levels
depend on the POL bit setting.
Table 2. Output States
POL BIT
RST PIN
OUTPUT STATE
0
0
Oscillating
0
1
0 (reset)
1
0
1 (reset)
1
1
Oscillating
Each period of the LTC6991’s internal oscillator clocks the
output state latch (see Block Diagram). The reset pin (RST)
can reset or hold off the output latch. The active state of
the reset pin is determined by the polarity function (POL).
Similarly, the output latch is followed by a buffer that can
invert the output. The output polarity is also controlled
by the POL bit.
If POL = 0, the reset pin is active high and the output latch
is not inverted. Therefore, pulling the RST pin high will
reset the output latch and force the OUT pin low. Pulling
RST low will allow the output to oscillate, with the next
rising edge dependent on the internal oscillator.
If POL = 1, the reset pin is active low and the output latch
is inverted. Therefore, pulling the RST pin low will reset
the output latch and force the OUT pin high. Pulling RST
high will allow the output to oscillate, with the next falling
edge dependent on the internal oscillator.
Note that the master oscillator frequency and phase are
not affected by the RST pin; The LTC6991 continues to
oscillate, internally, even when RST is active. While the
reset function can block an output pulse, its exact placement in time can only be changed by power cycling the
LTC6991.
tWIDTH
RST
INTERNAL
OSCILLATOR
tRST
OUT
6991 F03
tOUT
Figure 3. RST Timing Diagram (POL = 0)
RST
tRST
OUT
tOUT
INTERNAL
OSCILLATOR
6991 F04
Figure 4. RST Timing Diagram (POL = 1)
6991f
11
LTC6991
Operation
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. The LTC6991 will respond
to DIVCODE changes in less than one cycle.
start-up time may increase if the supply or DIV pin voltages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
track V+. Less than 100pF will not affect performance.
Start-Up Behavior
tDIVCODE < 500 • tMASTER < tOUT
The output may have an inaccurate pulse width during the
frequency transition. But the transition will be glitch-free
and no high or low pulse can be shorter than the master clock period. A digital filter is used to guarantee the
DIVCODE has settled to a new value before making changes
to the output.
When first powered up, the output is held low. If the polarity is set for non-inversion (POL = 0) and the output is
enabled (RST = 0) at the end of the start-up time, OUT will
begin oscillating. If the output is being reset (RST = 1) at
the end of the start-up time, the first pulse will be skipped.
Subsequent pulses will also be skipped until RST = 0.
Start-Up Time
In inverted operation (POL = 1), the start-up sequence is
similar. However, the LTC6991 does not know the correct
DIVCODE setting when first powered up, so the output
defaults low. At the end of tSTART , the value of DIVCODE is
recognized and OUT goes high (inactive) because POL = 1.
If RST = 1 (inactive) then OUT will quickly fall after a single
tMASTER cycle. If RST = 0 at the end of the start-up time,
the output is held in reset and remains high.
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART . The OUT pin
is held low during this time. The typical value for tSTART
ranges from 0.5ms to 8ms depending on the master oscillator frequency (independent of NDIV):
tSTART(TYP) = 500 • tMASTER
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. The
Figures 7 to 10 detail the four possible start-up sequences.
V+
1V/DIV
DIV
200mV/DIV
OUT
1V/DIV
OUT
1V/DIV
V+ = 3.3V
RSET = 200k
10ms/DIV
6991 F05
Figure 5. DIVCODE Change from 1 to 0
500µs
V+ = 2.5V
DIVCODE = 0
RSET = 50k
250µs/DIV
6991 F06
Figure 6. Typical Start-Up
6991f
12
LTC6991
Operation
RST
OUT
tSTART
tOUT
6991 F07
Figure 7. Start-Up Timing Diagram (RST = 0, POL = 0)
RST
OUT
tSTART
OUTPUT DISABLED FOR
INTEGER MULTIPLE OF tOUT
6991 F08
Figure 8. Start-Up Timing Diagram (RST = 1, POL = 0)
RST
6991 F09
OUT
tSTART
tMASTER
OUTPUT DISABLED FOR
INTEGER MULTIPLE OF tOUT
Figure 9. Start-Up Timing Diagram (RST = 0, POL = 1)
RST
6991 F10
OUT
tSTART
tOUT
tMASTER
Figure 10. Start-Up Timing Diagram (RST = 1, POL = 1)
6991f
13
LTC6991
Applications Information
Basic Operation
The simplest and most accurate method to program the
LTC6991 is to use a single resistor, RSET , between the SET
and GND pins. The design procedure is a 3-step process.
First select the POL bit setting and NDIV value, then calculate
the value for the RSET resistor.
Step 1: Select the POL Bit Setting
For noninverted (active-high) functionality, choose
POL = 0.
Step 2: Select the NDIV Frequency Divider Value
Step 1: Select the POL Bit Setting
The LTC6991 can operate in normal (active-high) or inverted
(active-low) modes, depending on the setting of the POL
bit. The best choice depends on the the application.
Step 2: Select the NDIV Frequency Divider Value
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
NDIV value. For a given output clock period, NDIV should
be selected to be within the following range.
tOUT
t
≤ NDIV ≤ OUT
16.384ms
1.024ms
Example: Design a 1Hz oscillator with minimum power
consumption and active-high reset input.
(1)
To minimize supply current, choose the lowest NDIV value
(generally recommended). Alternatively, use Table 1
as a guide to select the best NDIV value for the given
application.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Choose an NDIV value that meets the requirements of
Equation (1), using tOUT = 1000ms:
61.04 ≤ NDIV ≤ 976.6
Potential settings for NDIV include 64 and 512. NDIV = 64
is the best choice, as it minimizes supply current by using a large RSET resistor. POL = 0 and NDIV = 64 requires
DIVCODE = 2. Using Table 1, choose R1 = 976k and
R2 = 182k values to program DIVCODE = 2.
Step 3: Select RSET
Calculate the correct value for RSET using Equation (2).
RSET =
50k
1000ms
•
= 763k
1.024ms
64
Since 763k is not available as a standard 1% resistor,
substitute 768k if a –0.7% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 576k + 187k to attain a more precise resistance.
The completed design is shown in Figure 11.
Step 3: Calculate and Select RSET
The final step is to calculate the correct value for RSET
using the following equation.
RSET =
t
50k
• OUT
1.024ms NDIV
RST
OUT
LTC6991
GND
(2)
Select the standard resistor value closest to the calculated
value.
RST
2.25V TO 5.5V
V+
R1
976k
SET
RSET
763k
DIV
DIVCODE = 2
R2
182k
6991 F11
Figure 11. 1Hz Oscillator
6991f
14
LTC6991
Applications Information
LTC6991 as “Wake-Up Timer”
input to filter start-up glitches from the system as it is
powered on.
The output latch reset function provided by the RST pin
allows the LTC6991 to enable a larger system at regular
intervals. The on-time can be controlled by the system.
This allows the system to shut itself down immediately after
performing its tasks, reducing power consumption.
If the LTC6991 is enabling a switching regulator that can
operate on supplies greater than 5.5V, it will be necessary
to limit the supply voltage provided to the LTC6991. If
the LTC6991 output is not heavily loaded, and if a large
RSET resistor is used, the supply current will not be much
larger than 100µA, so a simple regulator circuit can be
constructed using a Zener diode.
Figure 12 shows an example using “black boxes” for a
switching regulator and the system being duty-cycled.
In some cases, an RC filter may be necessary at the RST
3V TO 20V
tOUT
3570 SECONDS
RSUPPLY
4.99k
1N4733A
5.1V
V+
R1
1M
0.1µF
OUT
VREG
SWITCHING
REGULATOR
SHDN
LTC6991
DIV
R2 R
SET
681k 665k
VOUT
VIN
V+
GND
SET
RST
SYSTEM
RFILT
100k
DONE
CFILT
0.1µF
6991 F12
THE SYSTEM CAN EXTEND tON AS LONG AS NEEDED (UP TO 50% OF tOUT)
tON
tON
tON
VREG
DONE/RST
LTC6991 OUT
tOUT
tOUT
tOUT
Figure 12. Powering Up a System Once an Hour
6991f
15
LTC6991
Applications Information
Self-Resetting Circuits
OUT
RPW
2.26k
The RST pin has hysteresis to accommodate slow-changing
input voltages. Furthermore, the trip points are proportional
to the supply voltage (see Note 6 and the RST Threshold
Voltage vs Supply Voltage curve in Typical Performance
Characteristics). This allows an RC time constant at the
RST input to generate a delay that is nearly independent
of the supply voltage.
RST
CPW
470pF
OUT
LTC6991
2.25V TO 5.5V
V+
GND
R1
1M
RSET
715k
0.1µF
DIV
SET
R2
392k
A simple application of this technique allows the LTC6991
output to reset itself, producing a well-controlled pulse
once each cycle. Figures 13a and 13b show circuits that
produce approximately 1µs pulses once a minute. The
only difference is in the POL bit setting, which controls
whether the pulse is positive or negative.
VRST(RISING)
V+
tPULSE ≈ –2.26kΩ • 470pF • In(1 – 0.61)
tPULSE ≈ 1µs
tPULSE = –RPW • CPW • In 1–
1µs PULSE WIDTH
60 SECONDS
6991 F13a
Voltage Controlled Frequency
Figure 13a. Self-Resetting Circuit (DIVCODE = 4)
With one additional resistor, the LTC6991 output frequency
can be manipulated by an external voltage. As shown in
Figure 14, voltage VCTRL sources/sinks a current through
RVCO to vary the ISET current, which in turn modulates the
output frequency as described in Equation (3).
OUT
RPW
2.26k
RST
CPW
470pF
GND
 R

V
1MHz • 50kΩ
fOUT =
•  1+ VCO – CTRL  (3)
1024 • NDIV • R VCO  RSET VSET 
RSET
715k
16
V
R1
392k
0.1µF
DIV
SET
VRST(FALLING)
V+
tPULSE ≈ –2.26kΩ • 470pF • In(0.43)
tPULSE ≈ 0.9µs
tPULSE = –RPW • CPW • In
0.9µs PULSE WIDTH
60 SECONDS
6991 F13b
Figure 13b. Self-Resetting Circuit (DIVCODE = 11)
RST
OUT
V+
LTC6991
GND
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25µA to 20µA range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
2.25V TO 5.5V
+
R2
1M
Digital Frequency Control
The control voltage can be generated by a DAC (digitalto-analog converter), resulting in a digitally-controlled
frequency. Many DACs allow for the use of an external
reference. If such a DAC is used to provide the VCTRL
voltage, the VSET dependency can be eliminated by buffering VSET and using it as the DAC’s reference voltage, as
shown in Figure 15. The DAC’s output voltage now tracks
any VSET variation and eliminates it as an error source.
The SET pin cannot be tied directly to the reference input
of the DAC because the current drawn by the DAC’s REF
input would affect the frequency.
OUT
LTC6991
VCTRL
RVCO
SET
RSET
V+
C1
0.1µF
R1
DIV
R2
6991 F14
Figure 14. Voltage-Controlled Oscillator
6991f
LTC6991
Applications Information
RST
OUT
V+
LTC6991
0.1µF
V+
V+
GND
+
SET
1/2
LTC6078
C1
0.1µF
R1
DIV
R2
–
V+
6991 F15
0.1µF
DIN
µP
CLK
VCC
LTC1659
R
D
1MHz • 50kΩ
• 1 + VCO – IN
RSET 4096
1024 • NDIV • RVCO
DIN = 0 TO 4095
fOUT =
REF
VOUT
RVCO
CS/LD
GND
RSET
Figure 15. Digitally-Controlled Oscillator
The oscillator can still function with reduced accuracy
for ISET < 1.25µA. At approximately 500nA, the oscillator
output will be frozen in its current state. The output could
halt in a high or low state. This avoids introducing short
pulses when frequency modulating a very low frequency
output.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Frequency Modulation and Settling Time
The LTC6991 will respond to changes in ISET up to a –3dB
bandwidth of 0.4 • fOUT .
Following a 2× or 0.5× step change in ISET , the output
frequency takes less than one cycle to settle to within 1%
of the final value.
Power Supply Current
ignores CLOAD (valid for CLOAD < 1nF) and assumes the
output has 50% duty cycle.
V+
V+
IS(TYP) ≈ V • fMASTER • 7.8pF +
+
420kΩ 2 • RLOAD
+
+ 1.8 • ISET + 50µA
Supply Bypassing and PCB Layout Guidelines
The LTC6991 is a 2.2% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 18 shows example PCB layouts for both the TSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6991. These layouts are
a guide and need not be followed exactly.
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under
any condition using the following equation. This equation
6991f
17
LTC6991
Applications Information
RST
OUT
LTC6991
GND
SET
V+
V+
C1
0.1µF
R1
DIV
RSET
R2
V+
R1
R2
V+
C1
C1
V+
OUT
RST
OUT
DIV
GND
GND
V+
SET
RST
SET
DIV
R1
RSET
RSET
R2
6991 F18
DFN PACKAGE
TSOT-23 PACKAGE
Figure 18. Supply Bypassing and PCB Layout
1. Connect the bypass capacitor, C1, directly to the V+ and
GND pins using a low inductance path. The connection
from C1 to the V+ pin is easily done directly on the top
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1µF ceramic capacitor.
2. Place all passive components on the top side of the
board. This minimizes trace inductance.
3. Place RSET as close as possible to the SET pin and
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
4. Connect RSET directly to the GND pin. Using a long path
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
5. Use a ground trace to shield the SET pin. This provides
another layer of protection from radiated signals.
6. Place R1 and R2 close to the DIV pin. A direct, short
connection to the DIV pin minimizes the external signal
coupling.
6991f
18
LTC6991
Typical Applications
5 Second On/Off Timed Relay Driver
12V
0.1µF
L
D1
1N4148
RESET
RUN
RELAY ENABLE
RST
OUT
LTC6991
R4
15k
R1
1M
SET
Q1
2N2219A
1
COTO 1022 RELAY
9001-12-01
5V
V+
GND
C
NO
C2
0.1µF
DIV
R2
392k
R3
118k
6991 TA02
1.5ms Radio Control Servo Reference Pulse Generator
5V
R7
10k
RESET = OPEN
RUN = GND
20ms
FRAME RATE
GENERATOR
RST
20ms PERIOD
OUT
LTC6991
GND
TRIG
5V
V+
SET
DIV
R5
102k
GND
C1
0.01µF
1.5ms PULSE
OUT
LTC6993-1
R4
976k
R6
121k
1.5ms
REFERENCE
PULSE
5V
V+
R1
1M
R3
146k
SET
C2
0.1µF
DIV
R2
280k
6991 TA03
6991f
19
LTC6991
Typical Applications
Cycling (10 Seconds On/Off) Symmetrical Power Supplies
M2
Si4435DY
15VIN
RST
R2
1k
M3
Si9410
R11
5k
OUT
LTC6991
V+
GND
5V
C1
0.1µF
R8
1M
SET
M4
Si4435DY
DIV
R9
392k
R10
237k
15VOUT
R6
20k
R1
100k
R3
50k
–15VIN
M1
Si9410
–15VOUT
F6991 TA04
Isolated AC Load Flasher
5V
OPEN = OFF
GND = ON
R3
10k
0.1µF
5
1
RST
V+
OUT
LTC6991
3
RSET
237k
SET
GND
DIV
R4
215Ω
6
4
2
R1
1M
R2
392k
1
U2
MOC3041M
6
R5
5.94k
2
5V
ZERO
CROSSING
U3
NTE5642
4
10 SECONDS ON/OFF
40W LAMP
R6
10k
HOT
117V AC
R7
100Ω
C2
0.022µF
6991 TA05
NEUTRAL
AC
ISOLATION BARRIER = 7500V
6991f
20
LTC6991
Typical Applications
Interval (Wiper) Timer
5V
5s
15s
30s
2s
V+
1m
2m
4m OFF
RST
66.5k
280k
182k
18.2k
OUT
TRIG
LTC6991
5s
15s
30s
2s
GND
V+
V+
0.1µF
1m
2m
4m OFF
SET
OUT
OUTPUT
2s
LTC6993-1
DIV
V+
V+
GND
0.1µF
1M
DIV
SET
383k
1M
2s
tINTERVAL
2 SECONDS TO
4 MINUTES
681k
6991 TA06
182k
280k
113k
133k
5s
15s
30s
1m
2m
4m
2s
OFF
6991f
21
LTC6991
Package Description
DCB Package
6-Lead Plastic DFN (2mm × 3mm)
(Reference LTC DWG # 05-08-1715 Rev A)
0.70 p0.05
3.55 p0.05
1.65 p0.05
(2 SIDES)
2.15 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
1.35 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
R = 0.05
TYP
2.00 p0.10
(2 SIDES)
3.00 p0.10
(2 SIDES)
0.40 p 0.10
4
6
1.65 p 0.10
(2 SIDES)
PIN 1 NOTCH
R0.20 OR 0.25
s 45o CHAMFER
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
3
0.200 REF
0.75 p0.05
1
(DCB6) DFN 0405
0.25 p 0.05
0.50 BSC
1.35 p0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
6991f
22
LTC6991
Package Description
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
0.62
MAX
2.90 BSC
(NOTE 4)
0.95
REF
1.22 REF
3.85 MAX 2.62 REF
1.4 MIN
2.80 BSC
1.50 – 1.75
(NOTE 4)
PIN ONE ID
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
0.30 – 0.45
6 PLCS (NOTE 3)
0.95 BSC
0.80 – 0.90
0.20 BSC
0.01 – 0.10
1.00 MAX
DATUM ‘A’
0.30 – 0.50 REF
0.09 – 0.20
(NOTE 3)
1.90 BSC
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
S6 TSOT-23 0302 REV B
6991f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC6991
Typical Application
Intervalometer for Time-Lapse Photography
ACTIVATES SHUTTER AT
8SEC TO 8.5MIN INTERVALS
RPW
100k
RST
CPW
33µF
GND
RS3
95.3k
8SEC TO
64SEC
RS1
1M
OUT
SHUTTER
LTC6991
V+
R1A
332k
SET
DIV
R1B
1M
1µF
“SLOW RANGE”
1.1MIN TO 8.5 MIN
RS2
2M
R2
130k
6991 TA07
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
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LTC6906/LTC6907
10kHz to 1MHz or 40kHz ThinSOT Silicon Oscillators
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LTC6930
Fixed Frequency Oscillator, 32.768kHz to 8.192MHz
0.09% Accuracy, 110µs Start-Up Time, 105µA at 32kHz
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TimerBlox: Voltage-Controlled Silicon Oscillator
Fixed-Frequency or Voltage-Controlled Operation
LTC6992
TimerBlox: Voltage-Controlled Pulse Width Modulator (PWM)
Simple PWM with Wide Frequency Range
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Resistor Programmable Pulse Width of 1µs to 34sec
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6991f
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT 0910 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2010