GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O 18Mb Pipelined and Flow Through Synchronous NBT SRAM 119, 165, & 209 BGA Commercial Temp Industrial Temp Features De sig n . Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. fo rN ed en d Re co m m The GS8162Z18(B/D)/36(B/D)/72(C) may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock. ar eN ot Functional Description ew • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs • 2.5 V or 3.3 V +10%/–10% core power supply • 2.5 V or 3.3 V I/O supply • User-configurable Pipeline and Flow Through mode • ZQ mode pin for user-selectable high/low output drive • IEEE 1149.1 JTAG-compatible Boundary Scan • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 8M devices • Byte write operation (9-bit Bytes) • 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down • JEDEC-standard 119-, 165-, or 209-Bump BGA package The GS8162Z18(B/D)/36(B/D)/72(C) is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. sp ec if ica ti o n The GS8162Z18(B/D)/36(B/D)/72(C) is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 119-bump (x18 & x36), 165-bump (x18 & x36), or 209-bump (x72) BGA package. is Parameter Synopsis tKQ tCycle 2.5 4.0 2.7 4.4 3.0 5.0 3.4 6.0 3.8 6.7 4.0 7.5 ns ns 3.3 V Curr (x18) Curr (x36) Curr (x72) 280 330 n/a 255 300 n/a 230 270 350 200 230 300 185 215 270 165 190 245 mA mA mA 2.5 V Curr (x18) Curr (x36) Curr (x72) 275 320 n/a 250 295 n/a 230 265 335 195 225 290 180 210 260 165 185 235 mA mA mA Flow Through 2-1-1-1 tKQ tCycle 5.5 5.5 6.0 6.0 6.5 6.5 7.0 7.0 7.5 7.5 8.5 8.5 ns ns 3.3 V Curr (x18) Curr (x36) Curr (x72) 175 200 n/a 165 190 n/a 160 180 225 150 170 115 145 165 210 135 150 185 mA mA mA 2.5 V Curr (x18) Curr (x36) Curr (x72) 175 200 n/a 165 190 n/a 160 180 225 150 170 115 145 165 210 135 150 185 mA mA mA Th e x1 8a nd x3 6 pa rt s in th Pipeline 3-1-1-1 Rev: 2.21 11/2004 -250 -225 -200 -166 -150 -133 Unit 1/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) GS8162Z72 Pad Out—209-Bump BGA—Top View (Package C) 2 3 4 5 6 7 8 9 10 11 A DQG DQG A E2 A ADV A E3 A DQB DQB B DQG DQG BC BG NC W A BB BF C DQG DQG BH BD NC E1 NC BE BA D DQG DQG VSS NC NC G NC NC VSS E DQPG DQPC VDDQ VDDQ VDD VDD VDD VDDQ F DQC DQC VSS VSS VSS ZQ VSS G DQC DQC VDDQ VDDQ VDD MCH VDD H DQC DQC VSS VSS VSS MCL VSS J DQC DQC VDDQ VDDQ VDD MCH K NC NC CK NC VSS L DQH DQH VDDQ VDDQ M DQH DQH VSS N DQH DQH P DQH R DQB DQB DQB DQB VDDQ DQPF DQPB VSS VSS DQF DQF VDDQ ed VDDQ DQF DQF VSS VSS DQF DQF VDD VDDQ VDDQ DQF DQF MCL VSS NC NC NC NC VDD FT VDD VDDQ VDDQ DQA DQA VSS VSS MCL VSS VSS VSS DQA DQA VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQA DQA DQH VSS VSS VSS ZZ VSS VSS VSS DQA DQA DQPD DQPH VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQPA DQPE T DQD DQD VSS NC NC LBO PE NC VSS DQE DQE U DQD DQD NC A NC A NC A NC DQE DQE V DQD DQD A A A A1 A A A DQE DQE W DQD DQD TDI A A0 A TDO TCK DQE DQE th rt s in TMS fo rN en d m Re co m ar eN ot n ica ti o 11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch Th e x1 8a nd x3 6 pa Rev 10 ew DQB is DQB sp ec if De sig n . 1 Rev: 2.21 11/2004 2/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) GS8162Z72 BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD DQE DQF DQG DQH I/O Data Input and Output pins BA, BB, BC,BD, BE, BF, BG,BH I Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low NC — No Connect CK I Clock Input Signal; active high W I Write Enable. Writes all enabled bytes; active low E1, E3 I Chip Enable; active low E2 I Chip Enable; active high G I ZZ I FT I LBO I MCH I De sig n Sleep Mode control; active high ica ti o n Flow Through or Pipeline mode; active low TMS I TDI I sp ec if I is ZQ th I in ADV Linear Burst Order mode; active low Must Connect High Must Connect Low Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) Burst Address Counter Advance Enable; active high FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select rt s I Scan Test Data In pa PE Scan Test Data Out x3 6 O I Scan Test Clock VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply Th e x1 8a nd TCK ew fo rN ed en d m Re co m ar eN ot Output Enable; active low MCL TDO . Symbol Rev: 2.21 11/2004 3/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 CKE ADV A A A B NC A E2 NC BA CK W G A A C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC D NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ E NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ F NC DQB VDDQ VDD VSS VSS VSS VDD G NC DQB VDDQ VDD VSS VSS VSS H FT MCH NC VDD VSS VSS Re co m J DQB NC VDDQ VDD VSS K DQB NC VDDQ VDD VSS L DQB NC VDDQ VDD VSS M DQB NC VDDQ VDD N DQB DNU VDDQ VSS P NC NC A R LBO NC A C NC DQA D NC DQA E VDDQ NC DQA F VDD VDDQ NC DQA G VSS VDD NC ZQ ZZ H VSS VSS VDD VDDQ DQA NC J VSS VSS VDD VDDQ DQA NC K VSS VSS VDD VDDQ DQA NC L VSS VSS VSS VDD VDDQ DQA NC M NC NC NC VSS VDDQ NC NC N A TDI A1 TDO A A A NC P A TMS A0 TCK A A A A R n fo rN ed en d m ew DQA ar eN ot B sp ec if is th in rt s NC 11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch Th e x1 8a nd x3 6 pa A De sig n . 1 ica ti o 165 Bump BGA—x18 Commom I/O—Top View (Package D) Rev: 2.21 11/2004 4/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 CKE ADV A A NC B NC A E2 BD BA CK W G A A C DQC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ F DQC DQC VDDQ VDD VSS VSS VSS VDD G DQC DQC VDDQ VDD VSS VSS VSS H FT MCH NC VDD VSS VSS Re co m J DQD DQD VDDQ VDD VSS K DQD DQD VDDQ VDD VSS L DQD DQD VDDQ VDD VSS M DQD DQD VDDQ VDD N DQD DNU VDDQ VSS P NC NC A R LBO NC A C DQB DQB D DQB DQB E VDDQ DQB DQB F VDD VDDQ DQB DQB G VSS VDD NC ZQ ZZ H VSS VSS VDD VDDQ DQA DQA J VSS VSS VDD VDDQ DQA DQA K VSS VSS VDD VDDQ DQA DQA L VSS VSS VSS VDD VDDQ DQA DQA M NC NC NC VSS VDDQ NC DQA N A TDI A1 TDO A A A NC P A TMS A0 TCK A A A A R n fo rN ed en d m ew DQB ar eN ot B sp ec if is th in rt s NC 11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch Th e x1 8a nd x3 6 pa A De sig n . 1 ica ti o 165 Bump BGA—x36 Common I/O—Top View (Package D) Rev: 2.21 11/2004 5/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B NC E2 A ADV A E3 NC C NC A A VDD A A D DQC DQPC VSS ZQ VSS DQPB fo rN E DQC DQC VSS E1 VSS F VDDQ DQC VSS G G DQC DQC BC A17 H DQC DQC VSS J VDDQ VDD NC K DQD L DQD M VDDQ ew De sig n . 1 en d GS8162Z36 Pad Out—119-Bump BGA—Top View (Package B) NC ed DQB DQB VSS DQB VDDQ BB DQB DQB W VSS DQB DQB VDD NC VDD VDDQ ica ti o n ar eN ot Re co m m DQB VSS CK VSS DQA DQA DQD BD NC BA DQA DQA DQD VSS CKE VSS DQA VDDQ DQD DQD VSS A1 VSS DQA DQA DQD DQPD VSS A0 VSS DQPA DQA R NC A LBO VDD FT A PE T NC NC A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ th is sp ec if DQD Th e x1 8a nd x3 6 pa P rt s in N Rev: 2.21 11/2004 6/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B NC E2 A ADV A E3 NC C NC A A VDD A A NC D DQB NC VSS ZQ VSS DQPA E NC DQB VSS E1 VSS F VDDQ NC VSS G G NC DQB BB A17 H DQB NC VSS J VDDQ VDD NC K NC L DQB M VDDQ ew fo rN ed NC DQA VSS DQA VDDQ NC NC DQA W VSS DQA NC VDD NC VDD VDDQ Re co m m NC ica ti o n ar eN ot De sig n . 1 en d GS8162Z18 Pad Out—119-Bump BGA—Top View (Package B) VSS CK VSS NC DQA NC NC NC BA DQA NC DQB VSS CKE VSS NC VDDQ DQB NC VSS A1 VSS DQA NC NC DQPB VSS A0 VSS NC DQA NC A LBO VDD FT A PE T NC A A NC A A ZZ U VDDQ TMS TDI TCK TDO NC VDDQ th is sp ec if DQB rt s pa P in N Th e x1 8a nd x3 6 R Rev: 2.21 11/2004 7/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) GS8162Z18/36 119-Bump and 165-Bump BGA Pin Description Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs An I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BA , BB , BC , BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low NC — No Connect CK I Clock Input Signal; active high CKE I Clock Enable; active low PE I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) W I Write Enable; active low E1 I Chip Enable; active low E3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active high ZZ I Sleep mode control; active high FT I LBO I ZQ I TMS I TDI I TDO O TCK I VDD I VSS I De sig n ew fo rN ed en d m Re co m ar eN ot ica ti o n Flow Through or Pipeline mode; active low Linear Burst Order mode; active low sp ec if FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In th is Scan Test Data Out in Scan Test Clock rt s Core power supply pa I/O and Core Ground Output driver power supply x3 6 I BPR1999.05.18 Th e x1 8a nd VDDQ . Symbol Rev: 2.21 11/2004 8/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Functional Details De sig n . Clocking Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation. BD Read H X X X X Write Byte “a” L L H H H Write Byte “b” L H L H H Write Byte “c” L H H L H Write Byte “d” L H H H L Write all Bytes L L L L L Write Abort/NOP L H H H H ed BC en d BB m BA Re co m W ar eN ot Function fo rN ew Pipeline Mode Read and Write Operations All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2, and E3). Deassertion of any one of the Enable inputs will deactivate the device. sp ec if ica ti o n Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins. pa rt s in th is Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (BA, BB, BC, and BD) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock. x1 8a nd x3 6 Flow Through Mode Read and Write Operations Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode. Th e Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock. Rev: 2.21 11/2004 9/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Synchronous Truth Table External L-H L L H X L H L L Read Cycle, Continue Burst B Next L-H L H X X X X X L NOP/Read, Begin Burst R External L-H L L H X L H L H Dummy Read, Continue Burst B Next L-H L H X X X X X Write Cycle, Begin Burst W External L-H L L L L L H Write Cycle, Continue Burst B Next L-H L H X L X X Write Abort, Continue Burst B Next L-H L H X H X Deselect Cycle, Power Down D None L-H L L X X Deselect Cycle, Power Down D None L-H L L X Deselect Cycle, Power Down D None L-H L L Deselect Cycle D None L-H L L Deselect Cycle, Continue D None L-H L None X X Current L-H H L Q L Q 1,10 L High-Z 2 L High-Z 1,2,10 L X L D 3 X X L D 1,3,10 X X X L High-Z 1,2,3,10 H X X X L High-Z X X X H X L High-Z X X X L X X L High-Z L H L H L X L High-Z H X X X X X X L High-Z X X X X X X X H High-Z X X X X X X X L - Re co m m en d ed fo rN H ar eN ot n Clock Edge Ignore, Stall ica ti o Sleep Mode Notes . R De sig n Read Cycle, Begin Burst DQ ew Type Address CK CKE ADV W Bx E1 E2 E3 G ZZ Operation 1 1 4 Th e x1 8a nd x3 6 pa rt s in th is sp ec if Notes: 1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Deselect cycle is executed first. 2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W pin is sampled low but no Byte Write pins are active so no write operation is performed. 3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during write cycles. 4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus will remain in High Z. 5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write signals are Low 6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge. 7. Wait states can be inserted by setting CKE high. 8. This device contains circuitry that ensures all outputs are in High Z during power-up. 9. A 2-bit burst counter is incorporated. 10. The address counter is incriminated for all Burst continue cycles. Rev: 2.21 11/2004 10/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Pipelined and Flow Through Read Write Control State Diagram D Deselect De sig n . B W D D W New Read New Write ed R en d R R W B Re co m m B W R ar eN ot Burst Read B fo rN ew R Burst Write B D Key sp ec if Input Command Code ica ti o n D W ƒ Transition Current State (n) Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change. 2. W, R, B, and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 n+3 rt s in n th is Next State (n+1) x3 6 pa Clock (CK) x1 8a nd Command ƒ Current State ƒ ƒ ƒ Next State Th e Current State and Next State Definition for Pipelined and Flow through Read/Write Control State Diagram Rev: 2.21 11/2004 11/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) R B Intermediate R High Z (Data In) Data Out (Q Valid) W D ed R en d W fo rN Intermediate Intermediate D Intermediate De sig n B W ew Intermediate . Pipeline Mode Data I/O State Diagram High Z m B ar eN ot Re co m D Intermediate Key Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change. ica ti o n Input Command Code ƒ Transition Current State (n) Transition is sp ec if Intermediate State (N+1) n+1 n+3 x3 6 rt s pa Clock (CK) n+2 in th n Next State (n+2) 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. x1 8a nd Command ƒ ƒ ƒ Current State Intermediate State Next State ƒ Th e Current State and Next State Definition for Pipeline Mode Data I/O State Diagram Rev: 2.21 11/2004 12/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Flow Through Mode Data I/O State Diagram R B . R High Z (Data In) De sig n B W Data Out (Q Valid) W D W fo rN ew D ed R en d High Z B Key n Input Command Code ar eN ot Re co m m D ica ti o ƒ Transition Current State (n) n+1 n+2 n+3 th is sp ec if 1. The Hold command (CKE Low) is not shown because it prevents any state change. 2. W, R, B, and D represent input command codes as indicated in the Truth Tables. Next State (n+1) n Notes pa rt s in Clock (CK) x1 8a nd x3 6 Command ƒ Current State ƒ ƒ ƒ Next State Th e Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram Rev: 2.21 11/2004 13/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) De sig n . Burst Cycles Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode. fo rN ew Burst Order The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is Low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details. Mode Pin Functions Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ n ica ti o sp ec if FLXDrive Output Impedance Control State Function L Linear Burst ar eN ot Mode Name Re co m m en d ed FLXDrive™ The ZQ pin allows selection between NBT RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. ZQ H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB L High Drive (Low Impedance) H or NC Low Drive (High Impedance) Th e x1 8a nd x3 6 pa rt s in th is Note: There is a are pull-up devicesonthe ZQ and FT pins and a pull-down device on the ZZ pin, so thosethis input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Rev: 2.21 11/2004 14/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence 01 10 11 1st address 00 01 2nd address 01 10 11 00 2nd address 01 00 3rd address 10 11 00 01 3rd address 10 11 4th address 11 00 01 10 4th address 11 10 10 11 11 10 00 01 00 De sig n 00 01 fo rN 1st address . A[1:0] A[1:0] A[1:0] A[1:0] ew A[1:0] A[1:0] A[1:0] A[1:0] Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Re co m m en d ed Note: The burst counter wraps to initial state on the 5th clock. Sleep Mode ar eN ot During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. sp ec if ica ti o n Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. th is Sleep Mode Timing Diagram in tKC pa rt s CK tKL tZZR tZZS tZZH x1 8a nd x3 6 ZZ tKH Th e Designing for Compatibility The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Bump 5R. Not all vendors offer this option, however most mark Bump 5R as VDD or VDDQ on pipelined parts and VSS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets. Rev: 2.21 11/2004 15/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Absolute Maximum Ratings (All voltages reference to VSS) Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature TBIAS Temperature Under Bias ed fo rN ew De sig n . Symbol V –55 to 125 o –55 to 125 o en d C m C ar eN ot Re co m Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V VDD2 2.3 2.5 2.7 V VDDQ3 3.0 3.3 3.6 V VDDQ2 2.3 2.5 2.7 V Notes ica ti o n Parameter sp ec if 2.5 V Supply Voltage 3.3 V VDDQ I/O Supply Voltage is 2.5 V VDDQ I/O Supply Voltage Th e x1 8a nd x3 6 pa rt s in th Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 2.21 11/2004 16/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) VDDQ3 Range Logic Levels Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 VDDQ I/O Input High Voltage VIHQ 2.0 — VDDQ + 0.3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.8 V 1 V 1,3 V 1,3 fo rN ew De sig n . Parameter Re co m m en d ed Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage –0.3 — 0.3*VDD V 1,3 n ar eN ot Parameter ica ti o VDDQ2 Range Logic Levels VILQ in th is sp ec if Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. rt s Recommended Operating Temperatures Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 x1 8a nd x3 6 pa Parameter Th e Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 2.21 11/2004 17/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 50% tKC 50% 50% VDD De sig n VSS . VDD + 2.0 V 50% tKC ew VSS – 2.0 V fo rN VIL Capacitance Input Capacitance CIN VIN = 0 V Input/Output Capacitance CI/O VOUT = 0 V Typ. Max. Unit 4 5 pF 6 7 pF en d Test conditions m Symbol Re co m Parameter ed (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) AC Test Conditions Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 sp ec if ica ti o n Parameter ar eN ot Note: These parameters are sample tested. VDDQ/2 Output reference level Fig. 1 is Output load Th e x1 8a nd x3 6 pa rt s in th Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Rev: 2.21 11/2004 Output Load 1 DQ 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance 18/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH FT, ZQ Input Current IIN2 VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL Output Leakage Current IOL Output Disable, VOUT = 0 to VDD Output High Voltage VOH2 Output High Voltage Output Low Voltage . Parameter De sig n DC Electrical Characteristics 1 uA 100 uA –100 uA –1 uA 1 uA 1 uA –1 uA 1 uA IOH = –8 mA, VDDQ = 2.375 V 1.7 V — VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V — VOL IOL = 8 mA — 0.4 V Th e x1 8a nd x3 6 pa rt s in th is sp ec if ica ti o n ar eN ot Re co m m en d ed fo rN ew –1 uA –1 uA Rev: 2.21 11/2004 19/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology Rev: 2.21 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 20/38 Device Deselected; All other inputs ≥ VIH or ≤ VIL ZZ ≥ VDD – 0.2 V Device Selected; All other inputs ≥VIH or ≤ VIL Output open x3 6 Device Selected; All other inputs ≥VIH or ≤ VIL Output open x1 8a nd Test Conditions Pipeline Flow Through — — (x18) (x36) (x72) DD IDD 60 85 IDD Pipeline 20 ISB Pipeline 20 165 10 IDD IDDQ Flow Through ISB 260 15 IDD IDDQ Pipeline Flow Through 180 20 IDD IDDQ Flow Through IDDQ DD DDQ DD DDQ 290 30 Flow Through 270 20 190 20 300 40 n/a n/a –40 to 85°C 300 45 290 45 140 10 185 15 155 15 205 25 185 30 250 50 0 to 70°C 150 10 195 15 165 15 215 25 195 30 260 50 –40 to 85°C 65 90 30 30 10 60 80 20 20 10 n/a 65 85 30 30 10 n/a 50 75 20 20 10 55 80 30 30 10 50 64 20 20 10 55 70 150 50 60 135 170 10 150 15 190 20 180 30 225 35 135 10 170 15 150 15 190 25 180 30 225 45 0 to 70°C 20 125 10 155 10 140 10 170 15 165 20 205 30 125 10 155 10 140 10 170 20 165 20 205 40 50 55 30 30 135 10 165 10 150 10 180 15 175 20 215 30 135 10 165 10 150 10 180 20 175 20 215 40 –40 to 85°C -133 0 to 70°C De30 20 65sig 50 n. 55 45 30 145 10 180 10 160 15 200 20 190 30 235 35 145 10 180 15 160 15 200 25 190 30 235 45 –40 to 85°C -150 fo10 10 r 30 N 20 ew 30 20 195 10 165 15 215 20 195 30 160 10 225 15 175 15 250 30 205 30 300 60 –40 to 85°C 150 10 215 15 165 15 240 30 195 30 290 60 0 to 70°C -166 205 185 ar n/a n/a 195 30 30 30 eN 300 265 240 250 205 ot275 30 30 30 25 25 20 Re 190 170 180 c165 155 om 175 20 20 20 15 15 15 270 235 245 215 m 225 e 185 15 15 15 15 15 n 10 de 175 155 165 150 160 140d 165 10 245 20 180 20 275 35 n/a n/a –40 to 85°C -200 260 40 155 10 235 20 170 20 265 35 n/a n/a 0 to 70°C -225 250 40 spI 165 175 10 10 I e c if I icn/aa n/a I ti o n I n/a n/a 260 20 180 20 290 40 n/a n/a 0 to 70°C IDD IDDQ is IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDD IDDQ Symbol Pipeline Flow Through Pipeline Flow Through p(x36) ar Flow ts Through in Pipeline th (x18) (x72) Pipeline Mode -250 Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. Deselect Current Standby Current 2.5 V Operating Current 3.3 V Operating Current Th e Parameter Operating Currents mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Unit GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) AC Electrical Characteristics -225 -200 -166 -150 -133 Unit Max Min Max Min Max Min Max Min Max Min Max tKC 4.0 — 4.4 — 5.0 — 6.0 — 6.7 — 7.5 — ns Clock to Output Valid tKQ — 2.5 — 2.7 — 3.0 — 3.4 — 3.8 — 4.0 ns Clock to Output Invalid tKQX 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — ns 1 1.5 — 1.5 — ns 1.5 — 1.5 — ns — 0.5 — 0.5 — ns — 7.5 — 8.5 — ns 7.0 — 7.5 — 8.5 ns tLZ 1.5 — 1.5 — 1.5 — 1.5 — Setup time tS 1.2 — 1.3 — 1.4 — 1.5 — Hold time tH 0.2 — 0.3 — 0.4 — 0.5 Clock Cycle Time tKC 5.5 — 6.0 — 6.5 — 7.0 Clock to Output Valid tKQ — 5.5 — 6.0 — 6.5 — Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — 3.0 — ns Setup time tS 1.5 — 1.5 — Hold time tH 0.5 — 0.5 — Clock HIGH Time tKH 1.3 — 1.3 — Clock LOW Time tKL 1.5 — 1.5 Clock to Output in High-Z tHZ1 1.5 2.5 G to Output Valid tOE — 2.5 G to output in Low-Z tOLZ1 0 G to output in High-Z tOHZ1 — ZZ setup time tZZS2 5 ZZ hold time tZZH2 1 fo rN ed en d m ew Clock to Output in Low-Z Re co m De sig n Min . Clock Cycle Time -250 — 1.5 — 1.5 — 1.5 — ns 0.5 — 0.5 — 0.5 — 0.5 — ns 1.3 — 1.3 — 1.5 — 1.7 — ns — 1.5 — 1.5 — 1.7 — 2 — ns 1.5 2.7 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 ns — 2.7 — 3.2 — 3.5 — 3.8 — 4.0 ns — 0 — 0 — 0 — 0 — 0 — ns 2.5 — 2.7 — 3.0 — 3.0 — 3.0 — 3.0 ns — 5 — 5 — 5 — 5 — 5 — ns — 1 — 1 — 1 — 1 — 1 — ns n ar eN ot 1.5 ica ti o Flow Through Symbol sp ec if Pipeline Parameter Th e x1 8a nd x3 6 pa rt s in th is ZZ recovery tZZR 20 — 20 — 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 2.21 11/2004 21/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Pipeline Mode Timing (NBT) Write A Read B Suspend Read C tKH Write D writeno-op Read E Deselect tKC tKL De sig n . CK tH tS A A B C D E ew tH tS fo rN CKE tH tS ed E* en d tH tS m ADV Re co m tH tS W tH Bn tH tS DQ Q(B) tS tLZ tKQ Q(C) D(D) tHZ tKQX Q(E) Th e x1 8a nd x3 6 pa rt s in th is sp ec if ica ti o n D(A) ar eN ot tH tS Rev: 2.21 11/2004 22/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Flow Through Mode Timing (NBT) Write A Write B Write B+1 Read C Cont Read D Write E Read F Write G tKL tKC . tKH De sig n CK tH tS ew CKE tH fo rN tS E tH ed tS en d ADV tH m tS Re co m W tH tS ar eN ot Bn tH tS A0–An A B C D(B+1) sp ec if D(B) ica ti o tS G tKQX tHZ Q(C) Q(D) tLZ D(E) tKQX Q(F) D(G) tOLZ tOE tOHZ th is G F tKQ tKQ tLZ D(A) DQ E n tH D Th e x1 8a nd x3 6 pa rt s in *Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1 Rev: 2.21 11/2004 23/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) JTAG Port Operation De sig n . Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. fo rN ew Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. Test Data Out ar eN ot TDO Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. n Test Data In ica ti o TDI Re co m m en d ed Pin sp ec if Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. th is JTAG Port Registers pa rt s in Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. x1 8a nd x3 6 Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Th e Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible. Rev: 2.21 11/2004 24/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) De sig n . Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. · · · · · 0 ar eN ot 2 1 0 0 Bypass Register · 1 · 108 · Re co m Boundary Scan Register · · m · en d ed fo rN ew JTAG TAP Block Diagram n Instruction Register ica ti o TDI TDO ID Code Register is sp ec if 31 30 29 in th TMS · · · 2 1 0 Control Signals Test Access Port (TAP) Controller rt s TCK · Th e x1 8a nd x3 6 pa Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 2.21 11/2004 25/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) GSI Technology JEDEC Vendor ID Code . I/O Configuration Not Used De sig n Die Revision Code Presence Register ID Register Contents 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 x36 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 X 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 fo rN ed en d m Tap Controller Instruction Set ew Bit # ar eN ot Re co m Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. Th e x1 8a nd x3 6 pa rt s in th is sp ec if ica ti o n When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 2.21 11/2004 26/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) JTAG Tap Controller State Diagram 0 1 Run Test Idle Select DR 1 0 0 1 1 Capture DR Capture IR 0 1 Shift IR 0 1 1 Exit2 DR Update DR 0 m 1 Exit2 IR 1 0 0 Update IR 1 0 ica ti o n 1 0 Pause IR 0 ar eN ot 1 0 Re co m 1 en d 0 0 Exit1 IR ed Exit1 DR Pause DR fo rN 1 ew 0 Shift DR 1 Select IR . 0 Test Logic Reset De sig n 1 sp ec if Instruction Descriptions th is BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Th e x1 8a nd x3 6 pa rt s in SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is still determined by its input pins. Rev: 2.21 11/2004 27/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output drivers on the falling edge of TCK when the controller is in the Update-IR state. ew De sig n . Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. ed fo rN IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. Re co m m en d SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Instruction Code EXTEST 000 Places the Boundary Scan Register between TDI and TDO. IDCODE 001 Preloads ID Register and places it between TDI and TDO. SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 in ar eN ot JTAG TAP Instruction Set Summary Description Notes GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 n 1 pa rt s th is sp ec if ica ti o 1, 2 1 Th e x1 8a nd x3 6 BYPASS 111 Places Bypass Register between TDI and TDO. Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 2.21 11/2004 28/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) JTAG Port Recommended Operating Conditions and DC Characteristics Symbol Min. Max. 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1 3.3 V Test Port Input Low Voltage VILJ3 –0.3 0.8 V 1 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V 1 TMS, TCK and TDI Input Leakage Current IINHJ –300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ –1 100 uA 3 TDO Output Leakage Current IOLJ –1 1 uA 4 Test Port Output High Voltage VOHJ 1.7 — V 5, 6 Test Port Output Low Voltage VOLJ — 0.4 V 5, 7 Test Port Output CMOS High VOHJC VDDQ – 100 mV — V 5, 8 Test Port Output CMOS Low VOLJC — 100 mV V 5, 9 De sig n ew fo rN ed en d m Re co m Unit Notes . Parameter sp ec if ica ti o n ar eN ot Notes: 1. Input Under/overshoot voltage must be –2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ ≤ VIN ≤ VDDn 3. 0 V ≤ VIN ≤ VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = –4 mA 7. IOLJ = + 4 mA 8. IOHJC = –100 uA 9. IOHJC = +100 uA is JTAG Port AC Test Conditions th Parameter in Input high level pa Input slew rate rt s Input low level Conditions VDD – 0.2 V DQ 0.2 V 50Ω 1 V/ns Input reference level VDDQ/2 Output reference level VDDQ/2 x3 6 JTAG Port AC Test Load 30pF* VDDQ/2 * Distributed Test Jig Capacitance Th e x1 8a nd Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. Rev: 2.21 11/2004 29/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) JTAG Port Timing Diagram tTKC tTKH tTKL . TCK De sig n tTH tTS TDI tTH ew tTS fo rN TMS tTKQ TDO ed tTH en d tTS JTAG Port AC Electrical Characteristics ar eN ot Re co m m Parallel SRAM input Symbol Min Max TCK Cycle Time tTKC 50 — ns TCK Low to TDO Valid tTKQ — 20 ns TCK High Pulse Width tTKH 20 — ns TCK Low Pulse Width tTKL 20 — ns TDI & TMS Set Up Time tTS 10 — ns TDI & TMS Hold Time tTH 10 — ns Unit rt s in th is sp ec if ica ti o n Parameter Th e x1 8a nd x3 6 pa Boundary Scan (BSDL Files) For information regarding the Boundary Scan Chain, or to obtain BSDL files for this part, please contact our Applications Engineering Department at: [email protected]. Rev: 2.21 11/2004 30/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 209 BGA Package Drawing (Package C) 14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Array A De sig n Side View D aaa . C A1 fo rN ew D1 E E1 Bottom View ar eN ot Re co m m en d ed e ∅b Min Typ Max A — — 1.70 A1 0.40 0.50 ∅b 0.50 0.60 c 0.31 0.36 D 21.9 22.0 Symbol Min Typ Max Units mm D1 — 18.0 (BSC) — mm 0.60 mm E 13.9 14.0 14.1 mm 0.70 mm E1 — 10.0 (BSC) — mm 0.38 mm e — 1.00 (BSC) — mm 22.1 mm aaa — 0.15 — mm is th in Th e x1 8a nd x3 6 pa rt s Rev 1.0 Units sp ec if Symbol ica ti o n e Rev: 2.21 11/2004 31/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Package Dimensions—165-Bump FPBGA (Package D; Variation 1) BOTTOM Ø0.10M C Ø0.25M C A B Ø0.40~0.50 1 2 3 4 5 6 7 8 9 10 11 10 9 8 7 6 5 4 3 2 A B C D E F G H J K L M N P R ed 1.0 1.0 10. ica ti o 13±0.0 0.20(4 Th e x1 8a nd x3 6 pa rt s in th is SEATING 0.25~0.4 1.20 C B sp ec if 0.15 C 0.45±0.05 0.25 C n A ar eN ot Re co m m en d 1.0 14. 15±0.0 1.0 fo rN ew A B C D E F G H J K L M N P R (0.26 A1 . TOP De sig n A1 Rev: 2.21 11/2004 32/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Package Dimensions—119-Bump FPBGA (Package B, Variation 2) TOP VIEW 2 3 4 5 6 7 . 1 BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U ed ar eN ot Re co m m en d 20.32 22±0.10 1.27 fo rN ew A B C D E F G H J K L M N P R T U De sig n A1 ica ti o sp ec if 0.15 C n 1.27 A 0.20(4x) 14±0.10 is SEATING PLANE 7.62 0.50~0.70 1.86.±0.13 C x1 8a nd x3 6 pa rt s in th 0.56±0.05 0.70±0.05 0.15 C B Th e BPR 1999.05.18 Rev: 2.21 11/2004 33/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Type Package Speed2 (MHz/ns) TA3 1M x 18 GS8162Z18B-250 NBT Pipeline/Flow Through 119 BGA (var. 2) 250/5.5 C 1M x 18 GS8162Z18B-225 NBT Pipeline/Flow Through 119 BGA (var. 2) 225/6 C 1M x 18 GS8162Z18B-200 NBT Pipeline/Flow Through 119 BGA (var. 2) 200/6.5 1M x 18 GS8162Z18B-166 NBT Pipeline/Flow Through 119 BGA (var. 2) 166/7 1M x 18 GS8162Z18B-150 NBT Pipeline/Flow Through 119 BGA (var. 2) 150/7.5 1M x 18 GS8162Z18B-133 NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 C 512K x 36 GS8162Z36B-250 NBT Pipeline/Flow Through 119 BGA (var. 2) 250/5.5 C 512K x 36 GS8162Z36B-225 NBT Pipeline/Flow Through 119 BGA (var. 2) 225/6 C 512K x 36 GS8162Z36B-200 NBT Pipeline/Flow Through 119 BGA (var. 2) 200/6.5 C 512K x 36 GS8162Z36B-166 NBT Pipeline/Flow Through 119 BGA (var. 2) 166/7 C 512K x 36 GS8162Z36B-150 NBT Pipeline/Flow Through 119 BGA (var. 2) 150/7.5 C 512K x 36 GS8162Z36B-133 NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 C 1M x 18 GS8162Z18D-250 NBT Pipeline/Flow Through 165 BGA (var. 1) 250/5.5 C 1M x 18 GS8162Z18D-225 NBT Pipeline/Flow Through 165 BGA (var. 1) 225/6 C 1M x 18 GS8162Z18D-200 NBT Pipeline/Flow Through 165 BGA (var. 1) 200/6.5 C 1M x 18 GS8162Z18D-166 NBT Pipeline/Flow Through 165 BGA (var. 1) 166/7 C 1M x 18 GS8162Z18D-150 NBT Pipeline/Flow Through 165 BGA (var. 1) 150/7.5 C 1M x 18 GS8162Z18D-133 NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 C 512K x 36 GS8162Z36D-250 NBT Pipeline/Flow Through 165 BGA (var. 1) 250/5.5 C 512K x 36 GS8162Z36D-225 NBT Pipeline/Flow Through 165 BGA (var. 1) 225/6 C 512K x 36 GS8162Z36D-200 NBT Pipeline/Flow Through 165 BGA (var. 1) 200/6.5 C 512K x 36 GS8162Z36D-166 NBT Pipeline/Flow Through 165 BGA (var. 1) 166/7 C 512K x 36 GS8162Z36D-150 NBT Pipeline/Flow Through 165 BGA (var. 1) 150/7.5 C 512K x 36 GS8162Z36D-133 NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 C 256K x 72 GS8162Z72C-200 NBT Pipeline/Flow Through 209 BGA 200/6.5 C 256K x 72 GS8162Z72C-166 209 BGA 166/7 C 256K x 72 GS8162Z72C-150 NBT Pipeline/Flow Through 209 BGA 150/7.5 C 256K x 72 GS8162Z72C-133 NBT Pipeline/Flow Through 209 BGA 133/8.5 C 1M x 18 GS8162Z18B-250I NBT Pipeline/Flow Through 119 BGA (var. 2) 250/5.5 I 1M x 18 GS8162Z18B-225I NBT Pipeline/Flow Through 119 BGA (var. 2) 225/6 I NBT Pipeline/Flow Through 119 BGA (var. 2) 200/6.5 I GS8162Z18B-200I ew ed en d m Re co m ar eN ot n ica ti o sp ec if is th in rt s pa x3 6 x1 8a nd 1M x 18 NBT Pipeline/Flow Through Status . Part Number1 De sig n Org fo rN Ordering Information—GSI NBT Synchronous SRAM C C C Th e Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36B-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 2.21 11/2004 34/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) Type Package Speed2 (MHz/ns) TA3 1M x 18 GS8162Z18B-166I NBT Pipeline/Flow Through 119 BGA (var. 2) 166/7 I 1M x 18 GS8162Z18B-150I NBT Pipeline/Flow Through 119 BGA (var. 2) 150/7.5 I 1M x 18 GS8162Z18B-133I NBT Pipeline/Flow Through 119 BGA (var. 2) 133/8.5 I 512K x 36 GS8162Z36B-250I NBT Pipeline/Flow Through 119 BGA (var. 2) 250/5.5 512K x 36 GS8162Z36B-225I NBT Pipeline/Flow Through 119 BGA (var. 2) 225/6 512K x 36 GS8162Z36B-200I NBT Pipeline/Flow Through 119 BGA (var. 2) 200/6.5 512K x 36 GS8162Z36B-166I NBT Pipeline/Flow Through 119 BGA (var. 2) 166/7 512K x 36 GS8162Z36B-150I NBT Pipeline/Flow Through 119 BGA (var. 2) 512K x 36 GS8162Z36B-133I NBT Pipeline/Flow Through 119 BGA (var. 2) 1M x 18 GS8162Z18D-250I NBT Pipeline/Flow Through 165 BGA (var. 1) 1M x 18 GS8162Z18D-225I NBT Pipeline/Flow Through 165 BGA (var. 1) 1M x 18 GS8162Z18D-200I NBT Pipeline/Flow Through 1M x 18 GS8162Z18D-166I 1M x 18 I I I I 133/8.5 I 250/5.5 I 225/6 I 165 BGA (var. 1) 200/6.5 I NBT Pipeline/Flow Through 165 BGA (var. 1) 166/7 I GS8162Z18D-150I NBT Pipeline/Flow Through 165 BGA (var. 1) 150/7.5 I 1M x 18 GS8162Z18D-133I NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 I 512K x 36 GS8162Z36D-250I NBT Pipeline/Flow Through 165 BGA (var. 1) 250/5.5 I 512K x 36 GS8162Z36D-225I NBT Pipeline/Flow Through 165 BGA (var. 1) 225/6 I 512K x 36 GS8162Z36D-200I NBT Pipeline/Flow Through 165 BGA (var. 1) 200/6.5 I 512K x 36 GS8162Z36D-166I NBT Pipeline/Flow Through 165 BGA (var. 1) 166/7 I 512K x 36 GS8162Z36D-150I NBT Pipeline/Flow Through 165 BGA (var. 1) 150/7.5 I 512K x 36 GS8162Z36D-133I NBT Pipeline/Flow Through 165 BGA (var. 1) 133/8.5 I 256K x 72 GS8162Z72C-200I NBT Pipeline/Flow Through 209 BGA 200/6.5 I 256K x 72 GS8162Z72C-166I NBT Pipeline/Flow Through 209 BGA 166/7 I 256K x 72 GS8162Z72C-150I NBT Pipeline/Flow Through 209 BGA 150/7.5 I 256K x 72 GS8162Z72C-133I NBT Pipeline/Flow Through 209 BGA 133/8.5 I sp ec if ica ti o n ar eN ot Re co m m en d ed fo rN ew I 150/7.5 th is Status . Part Number1 De sig n Org Th e x1 8a nd x3 6 pa rt s in Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8162Z36B-200IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 2.21 11/2004 35/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 18Mb Sync SRAM Datasheet Revision History Content GS8162Z18/36/72B2.00 12/ 1999BGS8162Z18/36/ 72B2.01 1/2000C Format • Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master File Rev B • Added x72 Pinout. De sig n . GS8162Z18/36/72B 1.00 9/ 1999A;GS8162Z18/36/ 72B2.0012/1999B • Added new GSI Logo GS8162Z18/36/72B2.01 1/ 2000C;GS8162Z18/36/ 72B2.02 1/2000D • Added 209 Pin BGA Package diagram ed Content ew New Types of Changes Page;Revisions;Reason Format or Content fo rN DS/DateRev. Code: Old; • Pin 6N changed to MCH. Content 8162Z18_r2_04; 8162Z18_r2_05 Content • Updated BGA pin description tables to meet JEDEC standards 8162Z18_r2_05; 8162Z18_42_06 Content • Changed the value of ZZ recovery in the AC Electrical Characteristics table on page 22 from 20 ns to 100 ns ica ti o is th 8162Z18_r2_06; 8162Z18_r2_07 n GS8162Z18/36/72B2.03 2/ 2000E; 8162Z18_r2_04 sp ec if GS8162Z18/36/72B2.02 1/ 2000DGS8162Z18/36/ 72B2.03 2/2000E ar eN ot Re co m m en d • Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O supply; Completeness • Absolute Maximum Ratings; Changed VDDQ - Value: From: .05 to VDD : to : -.05 to 3.6; Completeness. • Recommended Operating Conditions;Changed: I/O Supply Voltage- Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to 3.6; Same page - took out Note 1;Completeness • Electrical Characteristics - Added second Output High Voltage line to table; completeness. • Note: There was not a Rev 2.02 for the 8160Z or the 8161Z. rt s in Content/Format • Added 225 MHz speed bin • Updated numbers in page 1 table, AC Characteristics table, and Operating Currents table • Updated format to comply with Technical Publications standards Content • Changed VSSQ references to VSS • Changed K4 and K8 in 209-bump BGA to NC 8162Z18_r2_08; 8162Z18_r2_09 Content • Updated numbers for Clock to Output Valid (PL) and Clock to Output Valid (FT) for 166 MHz and 133 MHz on AC Electrical Characteristics table 8162Z18_r2_09; 8162Z18_r2_10 Content • Updated Features list on page 1 • Completely reworked table on page 1 • Updated Mode Pin Functions table on page 14 Th e x1 8a nd x3 6 pa 8162Z18_r2_07; 8162Z18_r2_08 Rev: 2.21 11/2004 36/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New Types of Changes Page;Revisions;Reason Format or Content Content • Updated DQ on page 24 • Updated DQ on page 26 (Q(A3)) • Updated ID Register Contents table • Updated Operating Currents table • Updated power numbers in table on page 1 • Updated Recommended Operating Conditions table (added VDDQ references) 8162Z18_r2_12; 8162Z18_r2_13 Content • Updated table on page 1 • Added 119-Bump BGA Pin Description table • Created recommended operating conditions tables on pages 19 and 20 • Updated AC Electrical Characteristics table • Updated Ordering Information for 225 MHz part (changed from 7ns to 6.5 ns) • Updated BSR table (2 and 3 changed to X (value undefined)) • Added 250 MHz speed bin • Deleted 180 MHz speed bin 8162Z18_r2_13; 8162Z18_r2_14 Content 8162Z18_r2_14; 8162Z18_r2_15 Content sp ec if ica ti o n ar eN ot Re co m m en d ed 8162Z18_r2_11; 8162Z18_r2_11 fo rN ew 8162Z18_r2_10; 8162Z18_r2_11 De sig n . Content • Added 3.3 V references to entire document • Updated Operating Conditions table • Updated JTAG section • Updated Operating Currents table and added note • Updated Boundary Scan Chain table • Updated table on page 1; added power numbers Content • Removed parity I/O bit designation from 165 BGA pinout • Updated both 209 BGA and 119 BGA pin description tables • Removed pin locations from pin description tables • Removed Preliminary banner • Removed BSR table rt s in th is Content x3 6 x1 8a nd Th e 8162Z18_r2_16; 8162Z18_r2_17 Rev: 2.21 11/2004 • Updated pin description tables to match pinouts • Updated Flow Through power numbers in table on page 1 and Operating Currents table • Updated Pipeline and Flow Through numbers in AC Characteristics table • Added 165-bump BGA package, pinout, and pinout description • Removed ByteSafe pins and references • Updated AC Test Conditions table and removed Output Load 2 diagram pa 8162Z18_r2_15; 8162Z18_r2_16 • Added parity bit references to x18 pad out and pin description table • Updated x36 pinout (DQA pins listed twice) 37/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS8162Z18(B/D)/GS8162Z36(B/D)/GS8162Z72(C) 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New Types of Changes Page;Revisions;Reason Format or Content Content 8162Z18_r2_18; 8162Z18_r2_19 Content • Corrected 209 BGA pin description table (removed BW reference and replaced with ADV reference) 8162Z18_r2_19; 8162Z18_r2_20 Content 8162Z18_r2_20; 8162Z18_r2_21 Content fo rN ew De sig n . 8162Z18_r2_17; 8162Z18_r2_18 • Removed 250 MHz and 225 MHz specs from x72 • Updated AC Characteristics table (tHZ, tOE, tOHZ equal to tKQ (PL) for 250 MHz and 225 MHz) • Added new timing diagrams • Added specific address locations to 165 BGA ed • Corrected incorrect DQ designations for x36 “B” Th e x1 8a nd x3 6 pa rt s in th is sp ec if ica ti o n ar eN ot Re co m m en d • Updated format • Updated timing diagrams • Updated truth table Rev: 2.21 11/2004 38/38 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology