SEMICONDUCTOR TECHNICAL DATA The MC10H/100H680 is a dual supply 4–bit differential ECL bus to TTL bus transceiver. It is designed to allow the system designer to no longer be limited in bus speed associated with standard TTL busses. Using a differential ECL Bus will increase the frequency of operation and increase noise immunity. Both the TTL and the ECL ports are capable of driving a bus. The ECL outputs have the ability to drive 25 Ω, allowing both ends of the bus line to be terminated in the characteristic impedance of 50 Ω. The TTL outputs are specified to source 15 mA and sink 48 mA, allowing the ability to drive highly capacitive loads. The ECL output levels are VOH approximately equal to –1.0 V and VOL cutoff equal to –2.0 V (VTT). When the ECL ports are disabled both EIOx and EIOxB go to the VOL cutoff level. The ECL input receivers have special circuitry which detects this disabled condition, prevents oscillation, and forces the TTL output to the low state. The noise margin in this disabled state is greater than 600 mV. Multiple ECL VCCO pins are utilized to minimize switching noise. The TTL ports have standard levels. The TTL input receivers have PNP input devices to significantly reduce loading. Multiple TTL power and ground pins are utilized to minimize switching noise. The control pins (EDIR and ECEB) of the 10H version is compatible with MECL 10H ECL logic levels. The control pins of the 100H version are compatible with 100K levels. • Differential ECL Bus (25 Ω) I/O Ports • High Drive TTL Bus I/O Ports • Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise • Dual Supply • Direction and Chip Enable Control Pins TIO2 GT3 VT2 GT4 TIO3 TCEB ECEB Pinout: 28–Lead PLCC (Top View) 25 24 23 22 21 20 19 VCCO4 VT1 28 16 EIO3 GT1 1 15 VCCE TIO0 2 14 EIO2B TDIR 3 13 VCCO3 EDIR 4 12 EIO2 5 6 7 8 9 10 11 EIO1B 17 V CCO2 27 EI01 GT2 V EE EIO3B EIO0B 18 VCCO1 26 EIO0 T101 FN SUFFIX PLASTIC PACKAGE CASE 776–02 PIN DESCRIPTIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol GT1 TIO0 TDIR EDIR EIO0 VCCO1 EIO0B VEE EIO1 VCCO2 EIO1B EIO2 VCCO3 EIO2B VCCE EIO3 VCCO4 EIO3B ECEB TCEB TIO3 GT4 VT2 GT3 TIO2 TIO1 GT2 VT1 9/96 Motorola, Inc. 1996 2–144 REV 6 Function TTL Ground 1 TTL I/O Bit 0 TTL Direction Control ECL Direction Control ECL I/O Bit 0 ECL VCC 1 (0V) – Outputs ECL I/O Bit 0 Bar ECL Supply (–5.2/–4.5V) ECL I/O Bit 1 ECL VCC 2 (0V) – Outputs ECL I/O Bit 1 Bar ECL I/O Bit 2 ECL VCC 3 (0V) – Outputs ECL I/O Bit 2 Bar ECL VCC (0V) ECL I/O Bit 3 ECL VCC 4 (0V) – Outputs ECL I/O Bit 3 Bar ECL Chip Enable Bar Control TTL Chip Enable Bar Control TTL I/O Bit 3 TTL Ground 4 TTL Supply 2 (5V) TTL Ground 3 TTL I/O Bit 2 TTL I/O Bit 1 TTL Ground 2 TTL Supply 1 (5V) MC10H680 MC100H680 TRUTH TABLE H — HIGH L — LOW LC — ECL Low Cutoff (VTT = –2.0 V) X — Don’t Care Z — High Impedance TDIR — Direction Control TTL Levels EDIR — Direction Control ECL Levels TCEB — Chip Enable Bar Control TTL Levels ECEB — Chip Enable Bar Control ECL Levels TIN — TTL Input TOUT — TTL Output EIN — ECL Input EINB — ECL Input Bar EOUT — ECL Output EOUTB — ECL Output Bar ECEB TCEB EDIR TDIR EIN EINB EOUT EOUTB TIN TOUT H X X X X X LC LC X Z ECL and TTL Outputs Disabled X H X X X X LC LC X Z ECL and TTL Outputs Disabled L L H X H LC NA H ECL to TTL Direction L L H X LC H NA L ECL to TTL Direction L L H X LC LC NA L ECL to TTL Direction (L–L Cond.) L L X H H LC NA H ECL to TTL Direction L L X H LC H NA L ECL to TTL Direction L L X H LC LC NA L ECL to TTL Direction (L–L Cond.) L L L L NA NA H LC H TTL to ECL Direction L L L L NA NA LC H L TTL to ECL Direction COMMENTS ABSOLUTE RATINGS (Do not exceed): Power Supply Voltage VEE (ECL) – 8.0 to 0 Vdc Power Supply Voltage VCCT (TTL) – 0.5 to +7.0 Vdc VI (ECL) VI (TTL) 0.0 to VEE – 0.5 to +7.0 Vdc Disabled 3–State Output Vout (TTL) 0.0 to VCCT Vdc Output Source Current Continuous Iout (ECL) 100 mAdc Output Source Current Surge Iout (ECL) 200 mAdc Storage Temperature Tstg – 65 to 150 °C Operating Temperature Tamb 0.0 to +75 °C Input Voltage MECL Data DL122 — Rev 6 2–145 MOTOROLA MC10H680 MC100H680 ECL DC CHARACTERISTICS: VCCT = + 5.0 V ±10%, VEE = – 5.2 ± 5% (10H Version); VEE = – 4.2 V to – 5.5 V (100H Version) TA = 0°C Test Symbol Parameter IEE Supply Current/ECL IINH Input HIGH Current IINL Input LOW Current VOH VOL Output HIGH Voltage Output LOW Voltage Min TA = 25°C Max Min –110 Min –110 225 145 0.5 –1100 – 2.1 Max TA = 75°C 0.5 – 840 – 2.03 –1100 – 2.1 Max Unit –110 mA 145 µA µA 0.3 – 810 – 2.03 –1100 – 2.1 Condition – 735 – 2.03 mV V 25 Ω to – 2.1 V CONTROL INPUTS ONLY 10H ECL DC CHARACTERISTICS: VCCT = + 5.0 ±10%, VEE = – 5.2 ± 5% TA = 0°C Test Symbol VIH VIL Parameter Input HIGH Voltage Input LOW Voltage TA = 25°C TA = 75°C Min Max Min Max Min Max Unit –1170 –1950 – 840 –1480 –1130 –1950 – 810 –1480 –1070 –1950 – 735 –1450 mV Condition CONTROL INPUTS ONLY 100H ECL DC CHARACTERISTICS: VCCT = + 5.0 ±10%, VEE = – 4.2 V to – 5.5 V TA = 0°C Test Symbol VIH VIL Parameter Input HIGH Voltage Input LOW Voltage TA = 25°C TA = 75°C Min Max Min Max Min Max Unit –1165 –1810 – 880 –1475 –1165 –1810 – 880 –1475 –1165 –1810 – 880 –1475 mV Condition TTL DC CHARACTERISTICS: VCCT = + 5.0 V ±10%, VEE = – 5.2 ± 5% (10H Version); VEE = – 4.2 V to – 5.5 V (100H Version) TA = 0°C Test Symbol Parameter Min TA = 25°C Max Min 2.0 Max VIH VIL Standard Input Standard Input 2.0 VIK Input Clamp VOH Output HIGH Voltage Output HIGH Voltage VOL Output LOW Voltage 0.55 0.55 IIH* TTL (Input HIGH) TTL (Input HIGH) 20 100 IIL* TTL (Input LOW) ICCL TA = 75°C Min Max 2.0 0.8 0.8 –1.2 –1.2 –1.2 IIN = –18 mA IOH = – 3.0 mA IOH = –15 mA 0.55 V IOL = 48 mA 20 100 20 100 µA Vin = 2.7 V Vin = 7.0 V – 0.6 – 0.6 – 0.6 mA Vin = 0.5 V Supply Current 75 75 75 mA ICCH Supply Current 70 70 70 mA ICCZ Supply Current 70 70 70 mA IOS Output Short Circuit Current – 225 mA – 225 –100 2.5 2.0 Vdc V –100 2.5 2.0 Condition Vdc 0.8 2.5 2.0 Unit – 225 –100 VOUT = 0 V * NOTE: TTL Control Inputs only TTL I/O DC CHARACTERISTICS ONLY TA = 0°C Test Symbol IIH/IOZH IIL/IOZL Parameter Output Disable Current MOTOROLA Min TA = 25°C Max 70 200 2–146 Min Max 70 200 TA = 75°C Min Max Unit 70 200 µA Condition VOUT = 2.7 V VOUT = 0.5 V MECL Data DL122 — Rev 6 MC10H680 MC100H680 ECL TO TTL DIRECTION / AC TEST TA = 0°C Test Symbol TA = 25°C TA = 75°C Parameter Waveforms Min Max Min Max Min Max Unit Condition tPLH tPHL Propagation Delay to Output 2, 4 2.7 4.8 2.7 4.8 2.7 4.8 ns CL = 50 pF tPZH tPZL ECEB to Output Enable Time 2, 5, 6 3.5 3.5 6.5 6.0 3.5 3.5 6.5 6.0 3.7 3.7 6.7 6.4 ns CL = 50 pF tPHZ tPLZ ECEB to Output Disable Time 2, 5, 6 3.5 3.5 8.6 6.5 3.5 3.5 8.6 6.5 3.7 3.7 8.8 7.3 ns CL = 50 pF tPZH tPZL TCEB to Output Enable Time 2, 5, 6 5.7 5.4 7.7 6.9 5.7 5.4 7.7 6.9 5.9 5.9 7.9 7.4 ns CL = 50 pF tPHZ tPLZ TCEB to Output Disable Time 2, 5, 6 4.0 4.0 8.5 5.8 4.1 4.2 8.4 6.0 4.2 4.7 8.3 6.5 ns CL = 50 pF tr/tf 1.0 to 2.0 Vdc 3 0.4 1.5 0.4 1.5 0.4 1.5 ns CL = 50 pF TTL TO ECL DIRECTION / AC TEST TA = 0°C Test Symbol TA = 25°C TA = 75°C Parameter Waveforms Min Max Min Max Min Max Unit Condition tPLH tPHL Propagation Delay to Output 1, 4 1.8 4.6 1.8 4.6 2.0 4.9 ns 25 Ω to – 2.0 V tPLH tPHL ECEB to Output 1, 4 2.9 5.1 3.0 5.2 3.4 5.7 ns 25 Ω to – 2.0 V tPLH tPHL TCEB to Output 1, 4 3.4 6.3 3.5 6.6 3.8 7.4 ns 25 Ω to – 2.0 V tr/tf Output Rise/Fall Time 20% – 80% 1, 3 1.0 3.4 1.0 3.4 1.0 3.4 ns 25 Ω to – 2.0 V MECL Data DL122 — Rev 6 2–147 MOTOROLA MC10H680 MC100H680 BLOCK DIAGRAM CONTROL INPUTS EOE TDIR EDIR VCCE TOE VEE TCE ECE GND1 VCCO1 TTL I/O EIO0 ECL I/O TIO0 EIO0 VCCT1 GND2 VCCO2 EIO1 TIO1 EIO1 GND3 VCCO3 EIO2 TIO2 EIO2 VCCT2 GND4 VCCO4 EIO3 TIO3 EIO3 MOTOROLA 2–148 MECL Data DL122 — Rev 6 MC10H680 MC100H680 SWITCHING CIRCUIT AND WAVEFORMS VEE ECL VCC & VCCO TTL USE 0.1 µF CAPACITORS FOR DECOUPLING. 50 Ω COAX PULSE GENERATOR +7 V IN DEVICE UNDER TEST 50 Ω OUT ALL OTHERS 50 Ω COAX 50 Ω COAX tPZL, tPLZ O,C DEVICE UNDER TEST 50 pF USE OSCILLOSCOPE INTERNAL 50 Ω LOAD FOR TERMINATION. CH A OPEN R1 500 Ω R2 500 Ω CH B OSCILLOSCOPE Figure 1. Switching Circuit ECL ECL/TTL Figure 2. ECL/TTL 50%/1.5 V VIN 80%/2.0 V TPLH 20%/1.0 V VOUT TPHL TPD++ TPD–– 50%/1.5 V TRISE TFALL VOUT Figure 3. WAVEFORMS: Rise and Fall Times TTL Figure 4. Propagation Delay — Single Ended TTL VE VE 1.5 V 1.5 V 1.5 V VE 1.5 V VE TPZL VOUT TPZH TPLZ 1.5 V VOUT VOL TPHZ > VOH ≈ 3.5 V 1.5 V 0.3 V 0.3 V Figure 5. 3–State Output Low Enable and Disable Times MECL Data DL122 — Rev 6 Figure 6. 3–State Output High Enable and Disable Times 2–149 MOTOROLA MC10H680 MC100H680 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B T L–M M N S T L–M S S Y BRK –N– 0.007 (0.180) U M N S D Z –M– –L– W 28 D X G1 0.010 (0.250) T L–M S N S S V 1 VIEW D–D A 0.007 (0.180) R 0.007 (0.180) M T L–M S N S C M T L–M S N 0.007 (0.180) H Z M T L–M N S S S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) –T– T L–M S N S M T L–M S N S VIEW S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA 0.007 (0.180) 2–150 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10_ 0.410 0.430 0.040 ––– MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10_ 10.42 10.92 1.02 ––– MECL Data DL122 — Rev 6 MC10H680 MC100H680 Motorola reserves the right to make changes without further notice to any products herein. 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