Burr-Brown OPA2830 Dual, low-power, single-supply, wideband operational amplifier Datasheet

 OPA2830
SBOS309C – AUGUST 2004 – REVISED MARCH 2006
Dual, Low-Power, Single-Supply, Wideband
OPERATIONAL AMPLIFIER
FEATURES
•
•
•
•
•
•
•
•
DESCRIPTION
HIGH BANDWIDTH:
230MHz (G = +1), 100MHz (G = +2)
LOW SUPPLY CURRENT: 7.8mA (VS = +5V)
FLEXIBLE SUPPLY RANGE:
±1.5V to ±5.5V Dual Supply
+3V to +11V Single Supply
INPUT RANGE INCLUDES GROUND ON
SINGLE SUPPLY
4.82VPP OUTPUT SWING ON +5V SUPPLY
HIGH SLEW RATE: 500V/µs
LOW INPUT VOLTAGE NOISE: 9.2nV/√Hz
AVAILABLE IN AN MSOP-8 PACKAGE
The OPA2830 is a dual, low-power, single-supply,
wideband, voltage-feedback amplifier designed to
operate on a single +3V or +5V supply. Operation on
±5V or +10V supplies is also supported. The input
range extends below ground and to within 1.8V of
the
positive
supply.
Using
complementary
common-emitter outputs provides an output swing to
within 25mV of ground and +VS while driving 150Ω.
High output drive current (75mA) and low differential
gain and phase errors also make it ideal for
single-supply consumer video products.
Low distortion operation is ensured by the high gain
bandwidth product (100MHz) and slew rate
(500V/µs), making the OPA2830 an ideal input buffer
stage to 3V and 5V CMOS Analog-to-Digital
Converters (ADCs). Unlike earlier low-power,
single-supply amplifiers, distortion performance
improves as the signal swing is decreased. A low
9.2nV/√Hz input voltage noise supports wide
dynamic range operation.
APPLICATIONS
•
•
•
•
•
•
•
SINGLE-SUPPLY ADC INPUT BUFFERS
SINGLE-SUPPLY VIDEO LINE DRIVERS
CCD IMAGING CHANNELS
LOW-POWER ULTRASOUND
PLL INTEGRATORS
PORTABLE CONSUMER ELECTRONICS
LOW-POWER ACTIVE FILTERS
The OPA2830 is available in an industry-standard
SO-8 package. The OPA2830 is also available in a
small MSOP-8 package. For fixed-gain and line
driver applications, consider the OPA2832.
150pF
RELATED PRODUCTS
+5V
0.1µF
238Ω
506Ω
1/2
OPA2830
+5V
238Ω
100pF
750Ω
5kΩ
VI
2.5V
BUF602
0.1µF
1500Ω
5kΩ
238Ω
SINGLES
DUALS
TRIPLES
QUADS
Rail-to-Rail
OPA830
—
—
OPA4830
Rail-to-Rail Fixed-Gain
OPA832
OPA2832
OPA3832
—
General-Purpose
(1800V/µs slew rate)
OPA690
OPA2690
OPA3690
—
Low-Noise,
High DC Precision
OPA820
OPA2822
—
OPA4820
VO
750Ω
238Ω
0.1µF
DESCRIPTION
100pF
1/2
OPA2830
506Ω
150pF
Single-Supply, Differential, 2nd-Order, 5MHz, Low-Pass Sallen-Key Filter
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2006, Texas Instruments Incorporated
OPA2830
www.ti.com
SBOS309C – AUGUST 2004 – REVISED MARCH 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA2830
SO-8 Surface-Mount
D
OPA2830
(1)
MSOP-8
DGK
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
–40°C to +85°C
OPA2830
–40°C to +85°C
A59
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA2830ID
Rails, 100
OPA2830IDR
Tape and Reel, 2500
OPA2830IDGKT
Tape and Reel, 250
OPA2830IDGKR
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Power Supply
11VDC
Internal Power Dissipation
See Thermal Characteristics
Differential Input Voltage
±2.5V
Input Voltage Range
–0.5V to +VS + 0.3V
Storage Temperature Range: D, DGK
–40°C to +125°C
Lead Temperature (soldering, 10s)
+300°C
Junction Temperature (TJ)
+150°C
ESD Rating:
Human Body Model (HBM)
2000V
Charge Device Model (CDM)
1000V
Machine Model (MM)
(1)
200V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
PIN CONFIGURATIONS
Top View
2
SO, MSOP
Output 1
1
8
+VS
−Input
1
2
7
Output 2
+Input 1
3
6
−Input 2
−VS
4
5
+Input 2
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OPA2830
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 70).
OPA2830ID, IDGK
MIN/MAX OVER
TEMPERATURE
TYP
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
MIN/
MAX
TEST
LEVEL (3)
105
66
64
61
MHz
typ
C
MHz
min
G = +5, VO ≤ 0.2VPP
22
16
14
B
13
MHz
min
G = +10, VO ≤ 0.2VPP
10
8
B
7
6
MHz
min
Gain Bandwidth Product
G ≥ +10
100
80
B
77
75
MHz
min
Peaking at a Gain of +1
VO ≤ 0.2VPP
4
B
dB
typ
C
Slew Rate
G = +2, 2V Step
560
275
265
255
Rise Time
0.5V Step
3.4
5.9
5.95
6.0
V/µs
min
B
ns
max
Fall Time
0.5V Step
3.6
6.0
6.05
B
6.1
ns
max
G = +2, 1V Step
43
64
B
66
67
ns
max
B
RL = 150Ω
–62
RL ≥ 500Ω
–66
–55
–53
–52
dBc
min
B
–58
–57
–56
dBc
min
RL = 150Ω
B
–59
–50
–49
–48
dBc
min
B
RL ≥ 500Ω
–77
–65
–62
–55
dBc
min
B
Input Voltage Noise
f > 1MHz
9.5
10.6
11.1
11.6
nV/√Hz
max
B
Input Current Noise
f > 1MHz
3.7
4.8
5.3
5.8
pA/√Hz
max
B
0.07
%
typ
C
0.17
°
typ
C
PARAMETER
CONDITIONS
+25°C
G = +1, VO ≤ 0.2VPP
290
G = +2, VO ≤ 0.2VPP
UNITS
AC PERFORMANCE (see Figure 70)
Small-Signal Bandwidth
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
VO = 2VPP, f = 5MHz
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE (4)
RL = 150Ω
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
74
66
65
64
dB
min
A
±1.5
±7.5
±8.7
±9.3
mV
max
A
±27
±27
µV/°C
max
B
+12
+13
µA
max
A
±44
±46
nA/°C
max
B
±1.3
±1.5
µA
max
A
±5
±6
nA/°C
max
B
—
VCM = 2.0V
+5
+10
Input Bias Current Drift
Input Offset Current
VCM = 2.0V
Input Offset Current Drift
±0.2
±1.1
—
INPUT
Negative Input Voltage
–5.5
–5.4
–5.3
–5.2
V
max
A
Positive Input Voltage
3.2
3.1
3.0
2.9
V
min
A
80
76
74
71
dB
min
A
Common-Mode Rejection Ratio (CMRR)
Input-Referred
Input Impedance
Differential Mode
10 | | 2.1
kΩ | | pF
typ
C
Common-Mode
400 | | 1.2
kΩ | | pF
typ
C
OUTPUT
Output Voltage Swing
G = +2, RL = 1kΩ to GND
±4.88
±4.86
±4.85
±4.84
V
min
A
G = +2, RL = 150Ω to GND
±4.64
±4.60
±4.58
±4.56
V
min
A
±82
±63
±58
±53
mA
min
A
Current Output, Sinking and Sourcing
Short-Circuit Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
Output Shorted to Ground
150
mA
typ
C
G = +2, f ≤ 100kHz
0.06
Ω
typ
C
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +18°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of pin.
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OPA2830
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 70).
OPA2830ID, IDGK
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
CONDITIONS
+25°C
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
±5.5
±5.5
±5.5
MIN/
MAX
TEST
LEVEL (3)
V
typ
C
V
max
A
UNITS
POWER SUPPLY
Minimum Operating Voltage
±1.4
Maximum Operating Voltage
Maximum Quiescent Current
VS = ±5V, Both Channels
8.5
9.5
10.7
11.9
mA
max
A
Minimum Quiescent Current
VS = ±5V, Both Channels
8.5
8.0
7.2
6.6
mA
min
A
Input-Referred
66
61
60
59
dB
min
A
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio (–PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDGK
Thermal Resistance, θJA
4
D
SO-8
125
°C/W
typ
C
DGK
MSOP-8
150
°C/W
typ
C
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OPA2830
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS: VS = +5V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 72).
OPA2830ID, IDGK
TYP
MIN/MAX OVER TEMPERATURE
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
MIN/
MAX
TEST
LEVEL (3)
100
70
68
66
MHz
typ
C
MHz
min
G = +5, VO ≤ 0.2VPP
21
15
14
B
13
MHz
min
G = +10, VO ≤ 0.2VPP
10
7
B
6
5
MHz
min
Gain-Bandwidth Product
G ≥ +10
100
75
B
65
59
MHz
min
Peaking at a Gain of +1
VO ≤ 0.2VPP
4
B
dB
typ
C
Slew Rate
G = +2, 2V Step
500
270
260
250
Rise Time
0.5V Step
3.4
5.8
5.9
6.0
V/µs
min
B
ns
max
Fall Time
0.5V Step
3.4
5.8
5.9
B
6.0
ns
max
G = +2, 1V Step
44
65
B
67
68
ns
max
B
RL = 150Ω
–58
RL ≥ 500Ω
–62
–52
–51
–50
dBc
min
B
–56
–55
–54
dBc
min
RL = 150Ω
B
–58
–50
–49
–48
dBc
min
B
RL ≥ 500Ω
–84
–65
–62
–60
dBc
min
B
Input Voltage Noise
f > 1MHz
9.2
10.3
10.8
11.3
nV/√Hz
max
B
Input Current Noise
f > 1MHz
3.5
4.6
5.1
5.6
pA/√Hz
max
B
0.075
%
typ
C
0.087
°
typ
C
PARAMETER
CONDITIONS
+25°C
G = +1, VO ≤ 0.2VPP
230
G = +2, VO ≤ 0.2VPP
UNITS
AC PERFORMANCE (see Figure 72)
Small-Signal Bandwidth
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
VO = 2VPP, f = 5MHz
NTSC Differential Gain
NTSC Differential Phase
DC PERFORMANCE (4)
RL = 150Ω
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
72
66
65
64
dB
min
A
±0.5
±5.5
±6.5
±7.0
mV
max
A
±22
±22
µV/°C
max
B
+12
+13
µA
max
A
±44
±46
nA/°C
max
B
±1.1
±1.3
µA
max
A
±5
±6
nA/°C
max
B
—
VCM = 2.5V
+5
+10
Input Bias Current Drift
Input Offset Current
VCM = 2.5V
Input Offset Current Drift
±0.2
±0.9
—
INPUT
Least Positive Input Voltage
–0.5
–0.4
–0.3
–0.2
V
max
A
Most Positive Input Voltage
3.2
3.1
3.0
2.9
V
min
A
80
76
74
71
dB
min
A
10 | | 2.1
kΩ | | pF
typ
C
400 | | 1.2
kΩ | | pF
typ
C
Common-Mode Rejection Ratio
(CMRR)
Input-Referred
Input Impedance, Differential Mode
Common-Mode
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
G = +5, RL = 1kΩ to 2.5V
0.09
0.11
0.12
0.13
V
max
A
G = +5, RL = 150Ω to 2.5V
0.21
0.24
0.25
0.26
V
max
A
G = +5, RL = 1kΩ to 2.5V
4.91
4.89
4.88
4.87
V
min
A
G = +5, RL = 150Ω to 2.5V
4.78
4.75
4.73
4.72
V
min
A
±75
±58
±53
±50
mA
min
A
mA
typ
C
Current Output, Sinking and Sourcing
Short-Circuit Output Current
(1)
(2)
(3)
(4)
Output Shorted to Either Supply
140
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +6°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of pin.
Submit Documentation Feedback
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OPA2830
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 72).
OPA2830ID, IDGK
TYP
PARAMETER
Closed-Loop Output Impedance
6
CONDITIONS
+25°C
G = +2, f ≤ 100kHz
0.06
MIN/MAX OVER TEMPERATURE
+25°C (1)
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0°C to
+70°C (2)
–40°C to
+85°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
Ω
typ
C
OPA2830
www.ti.com
SBOS309C – AUGUST 2004 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS: VS = +5V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to VS/2, unless otherwise noted (see Figure 72).
OPA2830ID, IDGK
TYP
PARAMETER
CONDITIONS
+25°C
MIN/MAX OVER TEMPERATURE
+25°C (1)
0°C to
+70°C (2)
–40°C to
+85°C (2)
+11
+11
+11
MIN/
MAX
TEST
LEVEL (3)
V
min
B
V
max
A
UNITS
POWER SUPPLY
Minimum Operating Voltage
+2.8
Maximum Operating Voltage
Maximum Quiescent Current
VS = +5V, Both Channels
7.8
8.3
9.7
11.1
mA
max
A
Minimum Quiescent Current
VS = +5V, Both Channels
7.8
7.4
6.8
6.2
mA
min
A
Input-Referred
66
61
60
59
dB
min
A
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDGK
Thermal Resistance, θJA
D
SO-8
125
°C/W
typ
C
DGK
MSOP-8
150
°C/W
typ
C
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OPA2830
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS: VS = +3V
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 71).
OPA2830ID, IDGK
TYP
MIN/MAX OVER
TEMPERATURE
CONDITIONS
+25°C
+25°C (1)
0°C to
+70°C (2)
UNITS
MIN/
MAX
TEST
LEVEL (3)
G = +2, VO ≤ 0.2VPP
90
70
66
MHz
min
B
G = +5, VO ≤ 0.2VPP
20
15
14
MHz
min
B
G = +10, VO ≤ 0.2VPP
9
7.5
6.5
MHz
min
B
Gain-Bandwidth Product
G ≥ +10
90
75
65
MHz
min
B
Slew Rate
1V Step
220
135
105
V/µs
min
B
Rise Time
0.5V Step
3.4
5.6
5.7
ns
max
B
Fall Time
0.5V Step
3.4
5.6
5.7
ns
max
B
1V Step
46
73
88
ns
max
B
RL = 150Ω
–60
–56
–54
dBc
min
B
RL ≥ 500Ω
–64
–59
–57
dBc
min
B
RL = 150Ω
–68
–59
–58
dBc
min
B
RL ≥ 500Ω
–72
–65
–64
dBc
min
B
Input Voltage Noise
f > 1MHz
9.2
10.3
10.8
nV/√Hz
max
B
Input Current Noise
f > 1MHz
3.5
4.6
5.1
pA/√Hz
max
B
PARAMETER
AC PERFORMANCE (see Figure 71)
Small-Signal Bandwidth
Settling Time to 0.1%
Harmonic Distortion
2nd-Harmonic
3rd-Harmonic
VO = 1VPP, f = 5MHz
DC PERFORMANCE (4)
Open-Loop Voltage Gain
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
72
66
65
dB
min
A
±1.5
±7.5
±8.7
mV
max
A
±27
µV/°C
max
B
—
VCM = 1.0V
+5
+10
+12
µA
max
A
±44
nA/°C
max
B
VCM = 1.0V
±0.2
±1.1
±1.3
µA
max
A
±5
nA/°C
max
B
Input Bias Current Drift
Input Offset Current
Input Offset Current Drift
—
INPUT
Least Positive Input Voltage
–0.45
–0.4
–0.27
V
max
A
Most Positive Input Voltage
1.2
1.1
1.0
V
min
A
80
74
72
dB
min
A
Common-Mode Rejection Ratio (CMRR)
Input-Referred
Input Impedance
Differential Mode
10 | | 2.1
kΩ | | pF
typ
C
Common-Mode
400 | | 1.2
kΩ | | pF
typ
C
OUTPUT
Least Positive Output Voltage
Most Positive Output Voltage
G = +5, RL = 1kΩ to 1.5V
0.08
0.11
0.125
V
max
A
G = +5, RL = 150Ω to 1.5V
0.17
0.39
0.40
V
max
A
G = +5, RL = 1kΩ to 1.5V
2.91
2.88
2.85
V
min
A
G = +5, RL = 150Ω to 1.5V
2.82
2.74
2.70
V
min
A
±30
±20
±18
mA
min
A
Current Output, Sinking and Sourcing
Short-Circuit Output Current
Closed-Loop Output Impedance
(1)
(2)
(3)
(4)
8
Output Shorted to Either Supply
45
mA
typ
C
See Figure 71, f < 100kHz
0.06
Ω
typ
C
Junction temperature = ambient for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +20°C at high temperature limit for over
temperature specifications.
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Current is considered positive out of node.
Submit Documentation Feedback
OPA2830
www.ti.com
SBOS309C – AUGUST 2004 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS: VS = +3V (continued)
Boldface limits are tested at +25°C.
At TA = +25°C, G = +2V/V, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 71).
OPA2830ID, IDGK
TYP
PARAMETER
CONDITIONS
+25°C
MIN/MAX OVER
TEMPERATURE
+25°C (1)
0°C to
+70°C (2)
+11
+11
MIN/
MAX
TEST
LEVEL (3)
V
min
B
V
max
A
UNITS
POWER SUPPLY
Minimum Operating Voltage
+2.8
Maximum Operating Voltage
Maximum Quiescent Current
VS = +3V, Both Channels
7.4
8.1
8.7
mA
max
A
Minimum Quiescent Current
VS = +3V, Both Channels
7.4
6.6
6.2
mA
min
A
Input-Referred
64
60
58
dB
min
A
–40 to +85
°C
typ
C
Power-Supply Rejection Ratio (PSRR)
THERMAL CHARACTERISTICS
Specification: ID, IDGK
Thermal Resistance, θJA
D
SO-8
125
°C/W
typ
C
DGK
MSOP-8
150
°C/W
typ
C
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 72).
NONINVERTING SMALL-SIGNAL FREQUENCY
RESPONSE
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
3
6
G = +1
RF = 0Ω
Normalized Gain (dB)
0
G = +2
−3
G = +5
−6
−9
G = +10
VO = 0.2VPP
RL = 150Ω
See Figure 72
−15
−18
Gain (dB)
1
−6
G = −5
−9
G = −10
−12
−15
VO = 0.2VPP
RL = 150Ω
−18
10
100
1
600
10
Figure 1.
Figure 2.
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
3
6
0
3
−3
VO = 1VPP
−3
VO = 4VPP
−6
VO = 2VPP
VO = 1VPP
−6
VO = 0.5VPP
−9
100
G = −1V/V
RL = 150Ω
−15
VO = 0.5VPP
10
VO = 4VPP
−12
VO = 2VPP
G = +2V/V
RL = 150Ω
See Figure 72
−12
−18
10
400
Frequency (MHz)
Figure 3.
Figure 4.
NONINVERTING PULSE RESPONSE
0
1.0
Small−Signal ± 100mV
Left Scale
0.5
0
−0.1
−0.5
−0.2
−1.0
−0.3
−1.5
−0.4
−2.0
Small−Signal Output Voltage (V)
0.2
1.5
Large−Signal Output Voltage (V)
Small−Signal Output Voltage (V)
Large−Signal ± 1V
Right Scale
2.0
G = −1V/V
0.3
1.5
0.2
1.0
0.1
0
0.5
Small−Signal ± 100mV
Left Scale
−0.1
−0.2
−0.3
Large−Signal ± 1V
Right Scale
Figure 6.
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−1.0
−1.5
−2.0
Time (10ns/div)
Figure 5.
0
−0.5
−0.4
Time (10ns/div)
10
400
INVERTING PULSE RESPONSE
0.4
2.0
G = +2V/V
See Figure 72
100
Frequency (MHz)
0.4
0.1
400
Frequency (MHz)
0
0.3
100
Frequency (MHz)
9
−9
G = −1
−3
Large−Signal Output Voltage (V)
−12
G = −2
0
Gain (dB)
Normalized Gain (dB)
3
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 72).
HARMONIC DISTORTION vs LOAD RESISTANCE
5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
−40
−50
−45
Harmonic Distortion (dBc)
−60
2nd−Harmonic
−65
−70
−75
G = +2V/V
VO = 2VPP
f = 5MHz
See Figure 72
−80
3rd−Harmonic
−50
−55
−60
2nd−Harmonic
−65
−70
−75
−80
3rd−Harmonic
−85
−85
100
−90
2.0
1k
2.5
3.5
4.0
4.5
Supply Voltage (±VS)
Figure 7.
Figure 8.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
5.0
5.5
6.0
HARMONIC DISTORTION vs FREQUENCY
−50
G = +2V/V
RL = 500Ω
f = 5MHz
See Figure 72
−65
−55
2nd−Harmonic
Harmonic Distortion (dBc)
−60
Harmonic Distortion (dBc)
3.0
Resistance (Ω)
−55
−70
−75
−80
3rd−Harmonic
−85
−90
−60
G = +2V/V
VO = 2VPP
See Figure 72
−65
3rd−Harmonic
RL = 150Ω
2nd−Harmonic
RL = 500Ω
−70
−75
2nd−Harmonic
RL = 150Ω
−80
−85
−90
3rd−Harmonic
RL = 500Ω
−95
−100
−95
−105
0.1
1
10
0.1
PI
Figure 9.
Figure 10.
1 /2
50Ω
PO
O P A 28 30
−50
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
20MHz
500Ω
Output Current (mA)
750Ω
−55
−60
750Ω
10MHz
−65
−70
−75
5MHz
−80
83
13
82
12
81
11
Output Current (sourcing)
80
79
10
Output Current (sinking)
9
78
8
−85
−90
−26
10
Frequency (MHz)
−40
−45
1
Output Voltage Swing (VPP)
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
3rd−Order Spurious Level (dBc)
G = +2V/V
VO = 2VPP
R L = 500Ω
See Figure 72
Input Limited for VCM = 0V
Supply Current (mA)
Harmonic Distortion (dBc)
−55
Quiescent Current (total, both amplifiers)
−20
−14
−8
−2
6
77
−50
7
−25
Single−Tone Load Power (2dBm/div)
Figure 11.
0
25
50
75
100
125
Ambient Temperature ( C)
Figure 12.
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, and RL = 150Ω to GND, unless otherwise noted (see Figure 72).
RECOMMENDED RS vs CAPACITIVE LOAD
120
CL = 10pF
7
5
100
90
CL = 1000pF
4
80
3
2
1
VI
50Ω
0
1/2
O PA2830
VO
750Ω
60
40
1kΩ(1)
750Ω
−2
70
50
RS
CL
−1
0dB Peaking Targeted
110
CL = 100pF
6
RS (Ω)
Normalized Gain to Capacitive Load (dB)
FREQUENCY RESPONSE vs CAPACITIVE LOAD
8
30
NOTE: (1) 1kΩ is optional.
20
−3
10
1
10
100
1
200
10
Figure 13.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
6
5
5
4
4
3
3
G = +5V/V
VS = ±5V
−2
−3
−4
−4
−5
−5
100
1k
Output
Current Lim it
RL = 500Ω
RL = 50Ω
RL = 100Ω
0
−1
−3
10
1W In ternal
Power Lim it
2
1
−2
−6
12
VO (V)
Output Voltage (V)
OUTPUT SWING vs LOAD RESISTANCE
0
−1
1k
Figure 14.
6
2
1
100
Capacitive Load (pF)
Frequency (MHz)
Outpu t
Current Limit
1W Internal
One Channel Only
P ower Limit
−6
−160
−120
−80
−40
0
40
Resistance (Ω )
IO (mA)
Figure 15.
Figure 16.
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80
120
160
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = ±5V, Differential Configuration
At TA = +25°C, RF = 604Ω (as shown in Figure 17), and RL = 500Ω, unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
3
+5V
GD = 1
0
RG
VI
Normalized Gain (dB)
1/2
OPA2830
20Ω
604Ω
RG
RL
500Ω
604Ω
VO
GD = 2
−3
−6
GD = 5
−9
GD = 10
−12
1/2
OPA2830
20Ω
−5V
−15
VO = 200mVPP
RL = 500Ω
1
GD = 604Ω
RG
10
100
200
Frequency (MHz)
Figure 17.
Figure 18.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
−45
9
−50
Harmonic Distortion (dBc)
6
VO = 5VPP
Gain (dB)
3
0
VO = 2VPP
−3
VO = 1VPP
−6
GD = 2
RL = 500Ω
−9
10
100
3rd−Harmonic
−60
−65
−70
−75
GD = 2
VO = 4VPP
f = 5MHz
−80
−85
−90
2nd−Harmonic
−95
VO = 200mVPP
1
−55
−100
100
200
150
Figure 19.
DIFFERENTIAL DISTORTION vs FREQUENCY
300
350
400
450
500
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
−55
GD = 2
VO = 4VPP
RL = 500Ω
3rd−Harmonic
−70
GD = 2
RL = 500Ω
f = 5MHz
−60
Harmonic Distrtion (dBc)
Harmonic Distortion (dBc)
−60
250
Figure 20.
−40
−50
200
Resistance (Ω)
Frequency (MHz)
−80
−90
−100
−65
−70
3rd−Harmonic
−75
−80
−85
2nd−Harmonic
−90
−95
−100
2nd−Harmonic
−110
−105
0.1
1
10
100
1
10
Output Voltage Swing (VPP)
Frequency (MHz)
Figure 21.
Figure 22.
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = +5V
At TA = +25°C, G = +2V/V, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 70).
NONINVERTING SMALL-SIGNAL FREQUENCY
RESPONSE
6
Normalized Gain (dB)
0
G = +2
−3
G = +5
−6
−9
G = +10
−12
VO = 0.2VPP
RL = 150Ω
See Figure 70
−15
−18
1
G = −2
0
G = −1
−3
−6
G = −5
−9
G = −10
−12
VO = 0.2VPP
RL = 150Ω
See Figure 84
−15
−18
10
100
500
1
10
Figure 23.
Figure 24.
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
9
3
6
0
3
−3
0
VO = 0.5VPP
−3
VO = 1VPP
VO = 1VPP
VO = 0.5VPP
−6
−9
G = −1V/V
RL = 150Ω
See Figure 84
−15
−18
10
100
400
10
Frequency (MHz)
Figure 25.
Figure 26.
NONINVERTING PULSE RESPONSE
2.7
4.0
3.5
2.6
3.0
Small−Signal 2.4V to 2.6V
Left Scale
2.4
2.5
2.0
2.3
1.5
G = +2V/V
See Figure 70
1.0
2.1
0.5
Small−Signal Output Voltage (V)
Large−Signal 1.5V to 3.5V
Right Scale
300
INVERTING PULSE RESPONSE
2.9
4.5
Large−Signal Output Voltage (V)
Small−Signal Output Voltage (V)
2.9
4.5
G = −1V/V
2.8
4.0
2.7
3.5
2.6
3.0
2.5
Small−Signal 2.4V to 2.6V
Left Scale
2.4
2.2
1.5
Large−Signal 1.5V to 3.5V
Right Scale
2.1
Figure 28.
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1.0
0.5
Time (10ns/div)
Figure 27.
2.5
2.0
2.3
Time (10ns/div)
14
100
Frequency (MHz)
Large−Signal Output Voltage (V)
−12
2.2
VO = 2VPP
−12
VO = 2VPP
G = +2V/V
RL = 150Ω
See Figure 70
−9
2.5
300
Frequency (MHz)
−6
2.8
100
Frequency (MHz)
Gain (dB)
Normalized Gain (dB)
3
G = +1
RF = 0Ω
3
Gain (dB)
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 70).
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs FREQUENCY
−45
−50
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
2nd−Harmonic
−60
−65
−70
3rd−Harmonic
−75
G = +2V/V
VO = 2VPP
f = 5MHz
See Figure 70
−80
−85
−55
−60
−65
−70
2nd−Harmonic
RL = 150Ω
−75
−80
3rd−Harmonic
RL = 500Ω
−90
3rd−Harmonic
RL = 150Ω
−100
1k
0.1
1
Load Resistance (Ω )
Frequency (MHz)
Figure 29.
Figure 30.
HARMONIC DISTORTION vs OUTPUT VOLTAGE
10
HARMONIC DISTORTION vs NONINVERTING GAIN
−45
−55
G = +2V/V
RL = 500Ω
f = 5MHz
See Figure 70
−55
−60
−60
Input Limited
Harmonic Distortion (dBc)
−50
2nd−Harmonic
−65
−70
−75
−80
−85
−90
2nd−Harmonic
−65
−70
−75
3rd−Harmonic
−80
RL = 500Ω
VO = 2VPP
f = 5MHz
See Figure 70
−85
3rd−Harmonic
−95
−90
−100
0.1
1
1
10
10
Gain (V/V)
Output Voltage Swing (VPP )
Figure 31.
Figure 32.
HARMONIC DISTORTION vs INVERTING GAIN
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
−55
−45
3rd−Order Spurious Level (dBc)
Harmonic Distortion (dBc)
2nd−Harmonic
RL = 500Ω
−85
−95
−90
100
Harmonic Distortion (dBc)
G = +2V/V
VO = 2VPP
See Figure 70
−50
−55
−60
2nd−Harmonic
−65
−70
−75
3rd−Harmonic
−80
RL = 500Ω
VO = 2VPP
f = 5MHz
−85
1
10
−50
PI
−55
1 /2
50Ω
PO
O P A28 30
500Ω
20MHz
750Ω
−60
−65
750Ω
10MHz
−70
−75
−80
5MHz
−85
−90
−95
−26 −24 −22 −20 −18 −16 −14 −12 −10 −8
Gain ( V/V )
Single−Tone Load Power (dBm)
Figure 33.
Figure 34.
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−6
−4
−2
15
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 70).
INPUT VOLTAGE AND CURRENT NOISE DENSITY
CLOSED-LOOP OUTPUT IMPEDANCE vs FREQUENCY
100
Output Impedance (Ω )
Voltage Noise (nV/√Hz)
Current Noise (pA/√Hz)
100
Voltage Noise
(9.2nV/√Hz)
10
Current Noise
(3.5pA/√Hz)
10
1
0.1
0.01
1
10
100
1k
10k
100k
1M
1k
10M
10k
100k
Figure 35.
RECOMMENDED RS vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
110
100
RS (Ω)
90
80
70
60
50
40
30
20
10
10
100
8
CL = 10pF
7
6
CL = 100pF
5
CL = 1000pF
4
3
2
1
VI
50Ω
0
1/2
OPA2830
RS
VO
CL
−1
−2
750Ω
NOTE: (1) 1kΩis optional.
−3
1k
1
10
VOLTAGE RANGES vs TEMPERATURE
180
5.0
70
160
4.5
120
40
100
80
∠ (AOL)
60
10
40
0
20
−10
0
−20
100
−20
1k
10k
100k
1M
10M
100M
1G
Voltage Range (V)
140
20 log (AOL)
3.5
3.0
2.5
Most Positive Input Voltage
2.0
RL = 150Ω
1.5
1.0
Least Positive Output Voltage
0.5
0
−0.5
−1.0
−50
Frequency (Hz)
Least Positive Input Voltage
0
50
Ambient Temperature (10C/div)
Figure 39.
16
Most Positive Output Voltage
4.0
Open−Loop Phase (dB)
Open−Loop Gain (dB)
OPEN-LOOP GAIN AND PHASE
20
300
Figure 38.
80
30
100
Frequency (MHz)
Figure 37.
50
1kΩ(1)
750Ω
Capacitive Load (pF)
60
100M
FREQUENCY RESPONSE vs CAPACITIVE LOAD
< 0.5dB Peaking Targeted
1
10M
Figure 36.
130
120
1M
Frequency (Hz)
Frequency (Hz)
Figure 40.
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = +5V (continued)
At TA = +25°C, G = +2V/V, RF = 750Ω, RL = 150Ω to VS/2, and input VCM = 2.5V, unless otherwise noted (see Figure 70).
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
6
2
4
1
2
10 × Input Offset Current (IOS)
0
0
−1
−2
Input Offset Voltage (VOS)
−2
−4
−3
−6
−4
−50
−25
−8
0
25
50
75
100
125
10.5
95
Output Current (mA)
3
Input Bias and Offset Current (µA)
Input Bias Current (IB)
Input Offset Voltage (mV)
100
8
90
9.5
85
9.0
Output Current, Sinking
80
8.5
75
8.0
Output Current, Sourcing
70
7.5
65
7.0
60
−50
−25
6.5
0
25
50
75
100
125
Ambient Temperature ( C)
Ambient Temperature ( C)
Figure 41.
Figure 42.
CMRR AND PSRR vs FREQUENCY
OUTPUT SWING vs LOAD RESISTANCE
90
5.5
80
5.0
4.5
70
CMRR
Output Voltage (V)
Common−Mode Rejection Ratio (dB)
Power−Supply Rejection Ratio (dB)
10.0
Quiescent Current
Supply Current (mA)
TYPICAL DC DRIFT OVER TEMPERATURE
4
60
50
40
30
PSRR
4.0
3.5
3.0
G = +5V/V
2.5
2.0
1.5
1.0
20
0.5
10
0
−0.5
0
1k
10k
100k
1M
10M
100M
10
100
Frequency (Hz)
Load Resistance (Ω )
Figure 43.
Figure 44.
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1k
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SBOS309C – AUGUST 2004 – REVISED MARCH 2006
TYPICAL CHARACTERISTICS: VS = +5V, Differential Configuration
At TA = +25°C, RF = 604Ω, and RL = 500Ω differential (as shown in Figure 45), unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
3
+5V
GD = 1
0
1.2kΩ
2.5V
0.1µF
1/2
OPA2830
RG
604Ω
RL
VI
RG
GD = 604Ω
RG
Normalized Gain (dB)
1.2kΩ
VO
604Ω
GD = 2
−3
−6
GD = 5
−9
GD = 10
−12
−15
1/2
OPA2830
VO = 200mVPP
RL = 500Ω
1
2.5V
10
100
200
Frequency (MHz)
Figure 45.
Figure 46.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
−40
9
−45
Harmonic Distortion (dBc)
6
VO = 3VPP
Gain (dB)
3
VO = 2VPP
0
−3
VO = 1VPP
−6
GD = 2
RL = 500Ω
−9
1
VO = 0.2VPP
10
−50
3rd−Harmonic
−55
−60
−65
GD = 2
VO = 4VPP
f = 5MHz
−70
−75
−80
−85
100
2nd−Harmonic
−90
100
200
150
Figure 47.
3rd−Harmonic
−60
−70
2nd−Harmonic
−80
−90
−100
400
450
500
−65
3rd−Harmonic
−70
−75
−80
−85
2nd−Harmonic
−90
−95
−110
−100
1
10
100
1
10
Output Voltage Swing (VPP)
Frequency (MHz)
Figure 49.
18
350
GD = 2
RL = 500Ω
f = 5MHz
−60
Harmonic Distrtion (dBc)
Harmonic Distrtion (dBc)
−50
300
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
−55
GD = 2
VO = 4VPP
RL = 500Ω
−40
250
Figure 48.
DIFFERENTIAL DISTORTION vs FREQUENCY
−30
200
Resistance (Ω )
Frequency (MHz)
Figure 50.
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TYPICAL CHARACTERISTICS: VS = +3V
At TA = +25°C, G = +2V/V, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 71).
NONINVERTING SMALL-SIGNAL FREQUENCY
RESPONSE
INVERTING SMALL-SIGNAL FREQUENCY RESPONSE
6
3
G = +1
RF = 0
0
0
−3
Normalized Gain (dB)
G = +2
−6
G = +5
−9
−12
RL = 150Ω
VO = 0.2VPP
See Figure 71
−15
−18
1
G = +10
G = −2
−6
G = −5
−9
−12
−15
100
400
1
10
Figure 51.
Figure 52.
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL FREQUENCY RESPONSE
9
3
6
0
VO = 1VPP
−3
Gain (dB)
VO = 1VPP
−3
VO = 1.5VPP
−6
−12
VO = 0.5VPP
−6
VO = 1.5VPP
−9
−12
G = +2V/V
RL = 150Ω
See Figure 71
−9
−15
G = −1V/V
RL = 150Ω
−18
10
100
10
300
Frequency (MHz)
Figure 53.
Figure 54.
NONINVERTING PULSE RESPONSE
1.50
Small−Signal
0.95V to 1.05V
Left Scale
1.00
0.95
1.25
1.00
0.75
0.90
0.50
G = +2V/V
See Figure 71
0.25
0.80
0
Small−Signal Output Voltage (V)
1.10
1.75
Large−Signal Output Voltage (V)
Large−Signal 0.5V to 1.5V
Right Scale
300
INVERTING PULSE RESPONSE
1.20
2.00
1.05
100
Frequency (MHz)
1.20
Small−Signal Output Voltage (V)
300
Frequency (MHz)
0
0.85
100
Frequency (MHz)
VO = 0.5VPP
1.15
G = −10
RL = 150Ω
VO = 0.2VPP
−18
10
3
Gain (dB)
G = −1
−3
1.15
2.00
G = −1V/V
RL = 150Ω
1.75
1.10
1.50
1.05
1.00
1.25
Small−Signal 0.95V to 1.05V
Left Scale
0.95
0.75
0.90
0.85
1.00
0.50
Large−Signal 0.5V to 1.5V
Right Scale
0.80
0.25
Large−Signal Output Voltage (V)
Normalized Gain (dB)
3
0
Time (10ns/div)
Time (10ns/div)
Figure 55.
Figure 56.
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TYPICAL CHARACTERISTICS: VS = +3V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 71).
HARMONIC DISTORTION vs LOAD RESISTANCE
HARMONIC DISTORTION vs OUTPUT VOLTAGE
−30
−50
Harmonic Distortion (dBc)
2nd−Harmonic
−60
Harmonic Distortion (dBc)
G = +2V/V
VO = 1VPP
f = 5MHz
See Figure 71
−55
−65
−70
−75
3rd−Harmonic
−80
−85
G = +2V/V
RL = 500Ω
f = 5MHz
See Figure 71
−40
−50
−60
2nd−Harmonic
−70
3rd−Harmonic
−80
−90
−90
100
1k
0.1
1
Resistance (Ω)
Figure 57.
Figure 58.
HARMONIC DISTORTION vs FREQUENCY
TWO-TONE, 3RD-ORDER INTERMODULATION SPURIOUS
Harmonic Distortion (dBc)
−65
2nd−Harmonic
RL = 500Ω
−70
2nd−Harmonic
RL = 150Ω
−75
−80
3rd−Harmonic
RL = 150Ω
−85
−90
3rd−Harmonic
RL = 500Ω
−95
3rd−Order Spurious Level (dBc)
−40
G = +2V/V
VO = 1VPP
See Figure 71
−60
−100
0.1
1
−45
1/2
50Ω
−50
PO
O P A 2830
500Ω
−55
750Ω
20MHz
−60
750Ω
−65
−70
−75
10MHz
−80
−85
5MHz
−90
Frequency (MHz)
Single−Tone Load Power (dBm)
Figure 59.
Figure 60.
< 0.5dB Peaking Targeted
170
150
130
110
90
70
50
30
10
10
100
−8
FREQUENCY RESPONSE vs CAPACITIVE LOAD
1k
Normalized Gain to Capacitive Load (dB)
RECOMMENDED RS vs CAPACITIVE LOAD
1
PI
−95
−28 −26 −24 −22 −20 −18 −16 −14 −12 −10
10
190
RS (Ω)
10
Output Voltage Swing (VPP )
−55
8
CL = 10pF
7
CL = 100pF
6
5
CL = 1000pF
4
3
2
1
RS
VI
50Ω
0
VO
O PA2830
CL
1kΩ(1)
750Ω
−1
−2
750Ω
NOTE: (1) 1kΩ is optional.
−3
1
Capacitive Load (pF)
10
Frequency (MHz)
Figure 61.
20
Input Limited
Figure 62.
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TYPICAL CHARACTERISTICS: VS = +3V (continued)
At TA = +25°C, G = +2V/V, and RL = 150Ω to VS/3, unless otherwise noted (see Figure 71).
OUTPUT SWING vs LOAD RESISTANCE
3.5
Output Voltage (V)
3.0
2.5
2.0
G = +5V/V
1.5
1.0
0.5
0
−0.5
10
100
1k
Load Resistance (Ω )
Figure 63.
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TYPICAL CHARACTERISTICS: VS = +3V, Differential Configuration
At TA = +25°C, RF = 604Ω, and RL = 500Ω differential (as shown in Figure 64), unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL FREQUENCY RESPONSE
3
+3V
0
1V
1kΩ
0.1µF
RG
Normalized Gain (dB)
2kΩ
1/2
OPA2830
604Ω
RL
VO
VI
RG
604Ω
GD = 1
−3
GD = 5
−9
GD = 10
−12
−15
1/2
OPA2830
GD = 2
−6
VO = 200mVPP
RL = 500Ω
1
1V
10
GD = 604Ω
RG
100
200
Frequency (MHz)
Figure 64.
Figure 65.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
−40
9
−45
Gain (dB)
3
Harmonic Distortion (dBc)
6
VO = 2VPP
0
VO = 1VPP
−3
VO = 200mVPP
−6
−55
−60
−65
1
10
100
−70
−75
−80
2nd−Harmonic
−90
100
200
3rd−Harmonic
GD = 2
VO = 4VPP
f = 5MHz
−85
GD = 2
−9
−50
150
200
250
Figure 66.
−55
−65
3rd−Harmonic
−75
−85
−95
2nd−Harmonic
−105
−115
22
450
500
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
GD = 2
VO = 2VPP
RL = 500Ω
0.1
400
−75
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
−45
350
Figure 67.
DIFFERENTIAL DISTORTION vs FREQUENCY
−35
300
Resistance (Ω )
Frequency (MHz)
1
10
100
−80
GD = 2
RL = 500Ω
f = 5MHz
3rd−Harmonic
−85
2nd−Harmonic
−90
−95
−100
0.50
0.75
1.00
1.25
1.50
Frequency (MHz)
Output Voltage Swing (VPP)
Figure 68.
Figure 69.
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APPLICATIONS INFORMATION
WIDEBAND VOLTAGE-FEEDBACK
OPERATION
The OPA2830 is a unity-gain stable, very high-speed
voltage-feedback op amp designed for single-supply
operation (+3V to +10V). The input stage supports
input voltages below ground and to within 1.7V of the
positive supply. The complementary common-emitter
output stage provides an output swing to within
25mV of ground and the positive supply. The
OPA2830 is compensated to provide stable
operation with a wide range of resistive loads.
Figure 70 shows the AC-coupled, gain of +2
configuration used for the +5V Specifications and
Typical Characteristic Curves. For test purposes, the
input impedance is set to 50Ω with a resistor to
ground. Voltage swings reported in the Electrical
Characteristics are taken directly at the input and
output pins. For the circuit of Figure 70, the total
effective load on the output at high frequencies is
150Ω || 1500Ω. The 1.5kΩ resistors at the
noninverting input provide the common-mode bias
voltage. Their parallel combination equals the DC
resistance at the inverting input (RF), reducing the
DC output offset due to input bias current.
VS = +5V
6.8µF
+
1.5kΩ
0.1µF
VIN
53.6Ω
0.1µF
2.5V
1.5kΩ
1/2
OPA2830
VOUT
RL
150Ω
RG
750Ω
+VS/2
RF
750Ω
+VS
2
Figure 70. AC-Coupled, G = +2, +5V
Single-Supply Specification and Test Circuit
Figure 71 shows the AC-coupled, gain of +2
configuration used for the +3V Specifications and
Typical Characteristic Curves. Voltage swings
reported in the Electrical Characteristics are taken
directly at the input and output pins. For the circuit of
Figure 71, the total effective load on the output at
high frequencies is 150Ω || 1500Ω. The 1.13kΩ and
2.26kΩ resistors at the noninverting input provide the
common-mode
bias
voltage.
Their
parallel
combination equals the DC resistance at the
inverting input (RF), reducing the DC output offset
due to input bias current.
VS = +3V
6.8µF
+
2.26kΩ
0.1µF
0.1µF
+1V
VIN
53.6Ω
1.13kΩ
1/2
OPA2830
VOUT
RL
150Ω
RG
750Ω
+VS/3
RF
750Ω
+VS
3
Figure 71. AC-Coupled, G = +2, +3V
Single-Supply Specification and Test Circuit
Figure 72 shows the DC-coupled, gain of +2, dual
power-supply circuit configuration used as the basis
of the ±5V Electrical Characteristics and Typical
Characteristics. For test purposes, the input
impedance is set to 50Ω with a resistor to ground
and the output impedance is set to 150Ω with a
series output resistor. Voltage swings reported in the
specifications are taken directly at the input and
output pins. For the circuit of Figure 72, the total
effective load will be 150Ω || 1.5kΩ. Two optional
components are included in Figure 72. An additional
resistor (348Ω) is included in series with the
noninverting input. Combined with the 25Ω DC
source resistance looking back towards the signal
generator, this gives an input bias current cancelling
resistance that matches the 375Ω source resistance
seen at the inverting input (see the DC Accuracy and
Offset Control section). In addition to the usual
power-supply decoupling capacitors to ground, a
0.01µF capacitor is included between the two
power-supply pins. In practical PC board layouts, this
optional capacitor will typically improve the
2nd-harmonic distortion performance by 3dB to 6dB.
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+5V
0.1µF
6.8µF
+
50Ω Source
348Ω
VIN
VO
1/2
OPA2830
50Ω
0.01µF
150Ω
where:
• NG = 1 + R4/R3
• VOUT = (G)VIN + (NG – G)VS
RF
750Ω
RG
750Ω
+
voltage range. Given the desired signal gain (G), and
the amount VOUT needs to be shifted up (∆VOUT)
when VIN is at the center of its range, the following
equations give the resistor values that produce the
desired performance. Assume that R4 is between
200Ω and 1.5kΩ.
• NG = G + VOUT/VS
• R1 = R4/G
• R2 = R4/(NG – G)
• R3 = R4/(NG – 1)
6.8µF
0.1µF
Make sure that VIN and VOUT stay within the specified
input and output voltage ranges.
−5V
+VS
R2
Figure 72. DC-Coupled, G = +2, Bipolar Supply
Specification and Test Circuit
R1
VIN
1/2
OPA2830
SINGLE-SUPPLY ADC INTERFACE
The ADC interface of Figure 73 shows a
DC-coupled, single-supply ADC driver circuit. Many
systems are now requiring +3V to +5V supply
capability of both the ADC and its driver. The
OPA2830 provides excellent performance in this
demanding application. Its large input and output
voltage ranges and low distortion support converters
such as the ADS5203 shown in the figure on page 1.
The input level-shifting circuitry was designed so that
VIN can be between 0V and 0.5V, while delivering an
output voltage of 1V to 2V for the ADS5203.
+3V
2.26kΩ
+3V
374Ω
VIN
1/2
OPA2830
100Ω
22pF
562Ω
1/2
ADS5203
10−Bit
30MSPS
R3
VOUT
R4
Figure 74. DC Level-Shifting
The circuit of Figure 73 is a good example of this
type of application. It was designed to take VIN
between 0V and 0.5V and produce VOUT between 1V
and 2V when using a +3V supply. This means G =
2.00, and ∆VOUT = 1.50V – G × 0.25V = 1.00V.
Plugging these values into the above equations (with
R4 = 750Ω) gives: NG = 2.33, R1 = 375Ω, R2 =
2.25kΩ, and R3 = 563Ω. The resistors were changed
to the nearest standard values for the circuit of
Figure 73.
750Ω
AC-COUPLED OUTPUT VIDEO LINE DRIVER
Figure 73. DC-Coupled, +3V ADC Driver
DC LEVEL-SHIFTING
Figure 74 shows the general form of Figure 73 as a
DC-coupled noninverting amplifier that level-shifts
the input up to accommodate the desired output
24
Low-power and low-cost video line drivers often
buffer digital-to-analog converter (DAC) outputs with
a gain of 2 into a doubly-terminated line. Those
interfaces typically require a DC blocking capacitor.
For a simple solution, that interface often has used a
very large value blocking capacitor (220µF) to limit
tilt, or SAG, across the frames. One approach to
creating a very low high-pass pole location using
much lower capacitor values is shown in Figure 76.
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The input is shifted slightly positive in Figure 76
using the voltage divider from the positive supply.
This gives about a 200mV input DC offset that will
show up at the output pin as a 400mV DC offset
when the DAC output is at zero current during the
sync tip portion of the video signal. This acts to hold
the output in its linear operating region. This will pass
on any power-supply noise to the output with a gain
of approximately –20dB, so good supply decoupling
is recommended on the power-supply pin. Figure 75
shows the frequency response for the circuit of
Figure 76. This plot shows the 8Hz low-frequency
high-pass pole and a high-end cutoff at
approximately 100MHz.
3
0
Normalized Gain (dB)
This circuit gives a voltage gain of 2 at the output pin
with a high-pass pole at 8Hz. Given the 150Ω load, a
simple blocking capacitor approach would require a
133µF value. The two much lower valued capacitors
give this same low-pass pole using this simple SAG
correction circuit of Figure 76.
−3
−6
−9
−12
−15
−18
−21
1
10
102
103
104
105
106
107
108
109
Frequency (Hz)
Figure 75. Video Line Driver Response to
Matched Load
+5V
1.87kΩ
Video DAC
78.7Ω
47µF
1/2
OPA2830
75Ω
VO
75Ω Load
22µF
845Ω
325Ω
528Ω
650Ω
Figure 76. Video Line Driver with SAG Correction
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NONINVERTING AMPLIFIER WITH REDUCED
PEAKING
Figure 77 shows a noninverting amplifier that
reduces peaking at low gains. The resistor RC
compensates the OPA2830 to have higher Noise
Gain (NG), which reduces the AC response peaking
(typically
4dB
at
G = +1 without RC) without changing the DC gain.
VIN needs to be a low impedance source, such as an
op amp.
+5V
RT
VIN
RC
1/2
OPA2830
RG
VOUT
RF
Figure 77. Compensated Noninverting Amplifier
The Noise Gain can be calculated as follows:
R
G1 1 F
RG
R
G2 1 R T GF
1
RC
NG G 1 G 2
RT = RF = 20.0Ω and RC = 40.2Ω (do not use RG).
This gives a noise gain of 2, so the response will be
similar to the Characteristics Plots with G = +2 giving
less peaking.
SINGLE-SUPPLY ACTIVE FILTER
The OPA2830 operating on a single +3V or +5V
supply lends itself well to high-frequency active filter
designs. The key additional requirement is to
establish the DC operating point of the signal near
the supply midpoint for highest dynamic range.
Figure 78 shows an example design of a 1MHz
low-pass Butterworth filter using the Sallen-Key
topology.
Both the input signal and the gain setting resistor are
AC-coupled using 0.1µF blocking capacitors (actually
giving bandpass response with the low-frequency
pole set to 32kHz for the component values shown).
This allows the midpoint bias formed by the two
1.87kΩ resistors to appear at both the input and
output pins. The midband signal gain is set to +4
(12dB) in this case. The capacitor to ground on the
noninverting input is intentionally designed at a
higher value to dominate input parasitic terms. At a
gain of +4, the OPA2830 on a single supply will
show 30MHz small- and large-signal bandwidth. The
filter resistor values have been slightly adjusted to
account for this limited bandwidth in the amplifier
stage. Tests of this circuit show a precise 1MHz,
–3dB point with a maximally-flat passband (above
the 32kHz AC-coupling corner), and a maximum stop
band attenuation of 36dB at the amplifier's –3dB
bandwidth of 30MHz.
A unity-gain buffer can be designed by selecting
+5V
100pF
1.87kΩ
0.1µF
137Ω
432Ω
VI
1.87kΩ
150pF
1/2
OPA2830
4V I
1MHz, 2nd−Order
Butterworth Filter
1.5kΩ
500Ω
0.1µF
Figure 78. Single-Supply, High-Frequency Active Filter
26
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The dual OPA2830 offers an easy means to
implement low-power differential active filters. On a
single supply, one way to implement a 2nd-order,
low-pass filter is shown in Figure 79. This circuit
provides a net differential gain of 1 with a precise
5MHz Butterworth response. The signal is
AC-coupled (giving a high-pass pole at low
frequencies) with the DC operating point for the
circuit set by the unity-gain buffer—the BUF602. This
buffer gives a very low output impedance to high
frequencies to maintain accurate filter characteristics.
If the source is a DC-coupled signal already biased
into the operating range of the OPA2830 input CMR,
these capacitors and the midpoint bias may be
removed. To get the desired 5MHz cutoff, the input
resistors to the filter is actually 119Ω. This is
implemented in Figure 79 as the parallel combination
of the two 238Ω resistors on each half of the
differential input as part of the DC biasing network. If
the BUF602 is removed, these resistors should be
collapsed back to a single 119Ω input resistor.
150pF
238Ω
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
−11
+5V
0.1µF
unity-gain filter characteristic from input to output.
The filter design shown here has also adjusted the
resistor values slightly from an ideal analysis to
account for the 100MHz bandwidth in the amplifier
stages. The filter capacitors at the noninverting
inputs are shown as two separate capacitors to
ground. While it is certainly correct to collapse these
two capacitors into a single capacitor across the two
inputs (which would be 50pF for this circuit) to get
the same differential filtering characteristic, tests
have shown two separate capacitors to a low
impedance point act to attenuate the common-mode
feedback present in this circuit giving more stable
operation in actual implementation. Figure 80 shows
the frequency response for the filter of Figure 79.
Differential Gain (dB)
DIFFERENTIAL LOW-PASS ACTIVE FILTERS
−12
506Ω
102
1/2
OPA2830
103
104
105
106
Frequency (Hz)
+5V
238Ω
100pF
750Ω
Figure 80. 5MHz, 2nd-Order, Butterworth
Low-Pass Filter
5kΩ
VI
2.5V
0.1µF
BUF602
1500Ω
5kΩ
238Ω
0.1µF
238Ω
VO
750Ω
100pF
1/2
OPA2830
506Ω
150pF
Figure 79. Single-Supply, 2nd-Order, Low-Pass
Sallen-Key Filter
HIGH-PASS FILTERS
Another approach to mid-supply biasing is shown in
Figure 81. This method uses a bypassed divider
network in place of the buffer used in Figure 79. The
impedance is set by the parallel combination of the
resistors forming the divider network, but as
frequency increases it looks more and more like a
short due to the capacitor. Generally, the capacitor
value needs to be two to three orders of magnitude
greater than the filter capacitors shown for the circuit
to work properly.
Implementing the DC bias in this way also attenuates
the differential signal by half. This is recovered by
setting the amplifier gain at 2V/V to get a net
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compliance voltage other than ground for operation,
the appropriate voltage level may be applied to the
noninverting input of the OPA2830. The DC gain for
this circuit is equal to RF. At high frequencies, the
DAC output capacitance (CD in Figure 83) will
produce a zero in the noise gain for the OPA2830
that may cause peaking in the closed-loop frequency
response. CF is added across RF to compensate for
this noise gain peaking. To achieve a flat
transimpedance frequency response, the pole in
each feedback network should be set to:
+VS
+5V
374Ω
2.2nF
2.2nF
1/2
OPA2830
750Ω
2kΩ
1µF
VS/2
VI
VO
1
2R FCF
GBP
4R
C
F
D
2kΩ
which will give
approximately:
750Ω
2.2nF
1/2
OPA2830
2.2nF
f 3dB GBP
2R
C
F
a
cutoff
frequency
f–3dB
D
374Ω
+5V
Figure 81. 138kHz, 2nd-Order, High-Pass Filter
2.5kΩ
Results showing the frequency response for the
circuit of Figure 81 is shown in Figure 82.
2.5kΩ
1/2
OPA2830
High−Speed
DAC
3
RF1
0
Gain (dB)
IO
VO = IO R F
CD1
CF1
−3
RF2
−6
−IO
−9
CD2
CF2
+5V
−12
0.01
0.1
1
10
2.5kΩ
Frequency (MHz)
2.5kΩ
Figure 82. Frequency Response for the Filter of
Figure 81
−VO = −IO R F
GBP →Gain Bandwidth
Product (Hz) for the OPA2830
Figure 83. High-Speed DAC—Differential
Transimpedance Amplifier
HIGH-PERFORMANCE DAC
TRANSIMPEDANCE AMPLIFIER
High-frequency video Digital-to-Analog Converters
(DACs) can sometimes benefit from a low distortion
output amplifier to retain their SFDR performance
into real-world loads. Figure 83 shows a differential
output drive implementation. The diagram shows the
signal output current(s) connected into the virtual
ground summing junction(s) of the OPA2830, which
is set up as a transimpedance stage or I-V converter.
If the DAC requires that its outputs terminate to a
28
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DESIGN-IN TOOLS
Demonstration Fixtures
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA2830 in its two package options. Both
of these are offered free of charge as unpopulated
PCBs, delivered with a user's guide. The summary
information for these fixtures is shown in Table 1.
Table 1. Demonstration Fixtures by Package
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA2830ID
SO-8
DEM-OPA-SO-2A
SBOU003
OPA2830IDGK
MSOP-8
DEM-OPA-MSOP-2A
SBOU004
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA2830 product folder.
Macromodel and Applications Support
Computer simulation of circuit performance using
SPICE is often a quick way to analyze the
performance of the OPA2830 and its circuit designs.
This is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can play a major role on circuit performance. A
SPICE model for the OPA2830 is available through
the TI web page (www.ti.com). The applications
department is also available for design assistance.
These models predict typical small signal AC,
transient steps, DC performance, and noise under a
wide variety of operating conditions. The models
include the noise terms found in the electrical
specifications of the data sheet. These models do
not attempt to distinguish between the package types
in their small-signal AC performance.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA2830 is a unity-gain stable,
voltage-feedback op amp, a wide range of resistor
values may be used for the feedback and gain
setting resistors. The primary limits on these values
are set by dynamic range (noise and distortion) and
parasitic capacitance considerations. For a
noninverting unity-gain follower application, the
feedback connection should be made with a direct
short.
Below 200Ω, the feedback network will present
additional output loading which can degrade the
harmonic distortion performance of the OPA2830.
Above 1kΩ, the typical parasitic capacitance
(approximately 0.2pF) across the feedback resistor
may cause unintentional band limiting in the amplifier
response.
A good rule of thumb is to target the parallel
combination of RF and RG (see Figure 72) to be less
than about 400Ω. The combined impedance RF || RG
interacts with the inverting input capacitance, placing
an additional pole in the feedback network, and thus
a zero in the forward response. Assuming a 2pF total
parasitic on the inverting node, holding RF || RG <
400Ω will keep this pole above 200MHz. By itself,
this constraint implies that the feedback resistor RF
can increase to several kΩ at high gains. This is
acceptable as long as the pole formed by RF and any
parasitic capacitance appearing in parallel is kept out
of the frequency range of interest.
In the inverting configuration, an additional design
consideration must be noted. RG becomes the input
resistor and therefore the load impedance to the
driving source. If impedance matching is desired, RG
may be set equal to the required termination value.
However, at low inverting gains, the resultant
feedback resistor value can present a significant load
to the amplifier output. For example, an inverting
gain of 2 with a 50Ω input matching resistor (= RG)
would require a 100Ω feedback resistor, which would
contribute to output loading in parallel with the
external load. In such a case, it would be preferable
to increase both the RF and RG values, and then
achieve the input matching impedance with a third
resistor to ground (see Figure 84). The total input
impedance becomes the parallel combination of RG
and the additional shunt resistor.
BANDWIDTH vs GAIN:
NONINVERTING OPERATION
Voltage-feedback op amps exhibit decreasing
closed-loop bandwidth as the signal gain is
increased. In theory, this relationship is described by
the Gain Bandwidth Product (GBP) shown in the
specifications. Ideally, dividing GBP by the
noninverting signal gain (also called the Noise Gain,
or NG) will predict the closed-loop bandwidth. In
practice, this only holds true when the phase margin
approaches 90°, as it does in high-gain
configurations. At low gains (increased feedback
factors), most amplifiers will exhibit a more complex
response with lower phase margin. The OPA2830 is
compensated to give a slightly peaked response in a
noninverting gain of 2 (see Figure 72). This results in
a typical gain of +2 bandwidth of 105MHz, far
exceeding that predicted by dividing the 105MHz
GBP by 2. Increasing the gain will cause the phase
margin to approach 90° and the bandwidth to more
closely approach the predicted value of (GBP/NG).
At a gain of +10, the 10MHz bandwidth shown in the
Electrical Characteristics agrees with that predicted
using the simple formula and the typical GBP of
105MHz.
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Frequency response in a gain of +2 may be modified
to achieve exceptional flatness simply by increasing
the noise gain to 3. One way to do this, without
affecting the +2 signal gain, is to add an 2.55kΩ
resistor across the two inputs, as shown in
Figure 77. A similar technique may be used to
reduce peaking in unity-gain (voltage follower)
applications. For example, by using a 750Ω feedback
resistor along with a 750Ω resistor across the two op
amp inputs, the voltage follower response will be
similar to the gain of +2 response of Figure 71.
Further reducing the value of the resistor across the
op amp inputs will further dampen the frequency
response due to increased noise gain. The OPA2830
exhibits minimal bandwidth reduction going to
single-supply (+5V) operation as compared with ±5V.
This minimal reduction is because the internal bias
control circuitry retains nearly constant quiescent
current as the total supply voltage between the
supply pins is changed.
INVERTING AMPLIFIER OPERATION
All of the familiar op amp application circuits are
available with the OPA2830 to the designer. See
Figure 84 for a typical inverting configuration where
the I/O impedances and signal gain from Figure 70
are retained in an inverting circuit configuration.
Inverting operation is one of the more common
requirements and offers several performance
benefits. It also allows the input to be biased at VS/2
without any headroom issues. The output voltage
can be independently moved to be within the output
voltage range with coupling capacitors, or bias
adjustment resistors.
+5V
+
0.1µF
6.8µF
2RT
1.5kΩ
0.1µF
50Ω Source
0.1µF
2RT
1.5kΩ
RG
374Ω
1/2
OPA2830
150Ω
+VS
2
RF
750Ω
RM
57.6Ω
Figure 84. AC-Coupled, G = –2 Example Circuit
is that the gain resistor (RG) becomes part of the
signal channel input impedance. If input impedance
matching is desired (which is beneficial whenever the
signal is coupled through a cable, twisted pair, long
PC board trace, or other transmission line
conductor), RG may be set equal to the required
termination value and RF adjusted to give the desired
gain. This is the simplest approach and results in
optimum bandwidth and noise performance.
However, at low inverting gains, the resulting
feedback resistor value can present a significant load
to the amplifier output. For an inverting gain of 2,
setting RG to 50Ω for input matching eliminates the
need for RM but requires a 100Ω feedback resistor.
This configuration has the interesting advantage of
the noise gain becoming equal to 2 for a 50Ω source
impedance—the same as the noninverting circuits
considered above. The amplifier output will now see
the 100Ω feedback resistor in parallel with the
external load. In general, the feedback resistor
should be limited to the 200Ω to 1.5kΩ range. In this
case, it is preferable to increase both the RF and RG
values, as shown in Figure 84, and then achieve the
input matching impedance with a third resistor (RM)
to ground. The total input impedance becomes the
parallel combination of RG and RM.
The second major consideration, touched on in the
previous paragraph, is that the signal source
impedance becomes part of the noise gain equation
and hence influences the bandwidth. For the
example in Figure 84, the RM value combines in
parallel with the external 50Ω source impedance (at
high frequencies), yielding an effective driving
impedance of 50Ω || 57.6Ω = 26.8Ω. This impedance
is added in series with RG for calculating the noise
gain. The resulting noise gain is 2.87 for Figure 84,
as opposed to only 2 if RM could be eliminated as
discussed above. The bandwidth will therefore be
lower for the gain of –2 circuit of Figure 84 (NG =
+2.87) than for the gain of +2 circuit of Figure 70.
The third important consideration in inverting
amplifier design is setting the bias current
cancellation resistors on the noninverting input (a
parallel combination of RT = 750Ω). If this resistor is
set equal to the total DC resistance looking out of the
inverting node, the output DC error, due to the input
bias currents, will be reduced to (Input Offset
Current) times RF. With the DC blocking capacitor in
series with RG, the DC source impedance looking out
of the inverting mode is simply RF = 750Ω for
Figure 84. To reduce the additional high-frequency
noise introduced by this resistor and power-supply
feed-through, RT is bypassed with a capacitor.
In the inverting configuration, three key design
considerations must be noted. The first consideration
30
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OUTPUT CURRENT AND VOLTAGES
DISTORTION PERFORMANCE
The OPA2830 provides outstanding output voltage
capability. For the +5V supply, under no-load
conditions at +25°C, the output voltage typically
swings closer than 90mV to either supply rail.
The OPA2830 provides good distortion performance
into a 150Ω load. Relative to alternative solutions, it
provides exceptional performance into lighter loads
and/or operating on a single +3V supply. Generally,
until the fundamental signal reaches very high
frequency or power levels, the 2nd-harmonic will
dominate
the
distortion
with
a
negligible
3rd-harmonic component. Focusing then on the
2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total
load includes the feedback network; in the
noninverting configuration (see Figure 72) this is sum
of RF + RG, while in the inverting configuration, only
RF needs to be included in parallel with the actual
load. Running differentially
suppresses
the
2nd-harmonic, as shown in the differential typical
characteristic curves.
The minimum specified output voltage and current
specifications over temperature are set by
worst-case simulations at the cold temperature
extreme. Only at cold startup will the output current
and voltage decrease to the numbers shown in the
ensured tables. As the output transistors deliver
power, their junction temperatures will increase,
decreasing their VBEs (increasing the available
output voltage swing) and increasing their current
gains (increasing the available output current). In
steady-state operation, the available output voltage
and current will always be greater than that shown in
the over-temperature specifications, since the output
stage junction temperatures will be higher than the
minimum specified operating ambient.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an
ADC—including additional external capacitance
which may be recommended to improve ADC
linearity. A high-speed, high open-loop gain amplifier
like the OPA2830 can be very susceptible to
decreased stability and closed-loop response
peaking when a capacitive load is placed directly on
the output pin. When the primary considerations are
frequency response flatness, pulse response fidelity,
and/or distortion, the simplest and most effective
solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
The Typical Characteristic curves show the
recommended RS versus capacitive load and the
resulting frequency response at the load. Parasitic
capacitive loads greater than 2pF can begin to
degrade the performance of the OPA2830. Long PC
board traces, unmatched cables, and connections to
multiple devices can easily exceed this value. Always
consider this effect carefully, and add the
recommended series resistor as close as possible to
the output pin (see the Board Layout Guidelines
section).
The criterion for setting this RS resistor is a maximum
bandwidth, flat frequency response at the load. For a
gain of +2, the frequency response at the output pin
is already slightly peaked without the capacitive load,
requiring relatively high values of RS to flatten the
response at the load. Increasing the noise gain will
also reduce the peaking (see Figure 77).
NOISE PERFORMANCE
High slew rate, unity-gain stable, voltage-feedback
op amps usually achieve their slew rate at the
expense of a higher input noise voltage. The
9.2nV/√Hz input voltage noise for the OPA2830
however, is much lower than comparable amplifiers.
The input-referred voltage noise and the two
input-referred current noise terms (2.8pA/√Hz)
combine to give low output noise under a wide
variety of operating conditions. Figure 85 shows the
op amp noise analysis model with all the noise terms
included. In this model, all noise terms are taken to
be noise voltage or current density terms in either
nV/√Hz or pA/√Hz.
ENI
1/2
OPA2830
RS
EO
IBN
ERS
RF
√ 4kTRS
4kT
RG
RG
IBI
√ 4kTRF
4kT = 1.6E − 20J
at 290 K
Figure 85. Noise Analysis Model
The total output spot noise voltage can be computed
as the square root of the sum of all squared output
noise voltage contributors. Equation 1 shows the
general form for the output noise voltage using the
terms shown in Figure 85:
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EO 2
2
2
E NI I BNRS 4kTRS NG 2 I BIR F 4kTRFNG
(1)
Dividing this expression by the noise gain
(NG = (1 + RF/RG)) will give the equivalent
input-referred spot noise voltage at the noninverting
input, as shown in Equation 2:
EN 2
2
ENI IBNR S 4kTRS IBIRF
NG
2
4kTRF
NG
(2)
Evaluating these two equations for the circuit and
component values shown in Figure 70 will give a
total output spot noise voltage of 19.3nV/√Hz and a
total equivalent input spot noise voltage of
9.65nV/√Hz. This is including the noise added by the
resistors. This total input-referred spot noise voltage
is not much higher than the 9.2nV/√Hz specification
for the op amp voltage noise alone.
DC ACCURACY AND OFFSET CONTROL
The balanced input stage of a wideband
voltage-feedback op amp allows good output DC
accuracy in a wide variety of applications. The
power-supply current trim for the OPA2830 gives
even tighter control than comparable products.
Although the high-speed input stage does require
relatively high input bias current (typically 5µA out of
each input terminal), the close matching between
them may be used to reduce the output DC error
caused by this current. This is done by matching the
DC source resistances appearing at the two inputs.
Evaluating the configuration of Figure 72 (which has
matched DC input resistances), using worst-case
+25°C input offset voltage and current specifications,
gives a worst-case output offset voltage equal to:
• (NG = noninverting signal gain at DC)
• ±(NG × VOS(MAX)) + (RF × IOS(MAX))
• = ±(2 × 7.5mV) × (375Ω × 1.1µA)
• = ±15.41mV
A fine-scale output offset null, or DC operating point
adjustment, is often required. Numerous techniques
are available for introducing DC offset control into an
op amp circuit. Most of these techniques are based
on adding a DC current through the feedback
resistor. In selecting an offset trim method, one key
consideration is the impact on the desired signal
path frequency response. If the signal path is
intended to be noninverting, the offset control is best
applied as an inverting summing signal to avoid
interaction with the signal source. If the signal path is
intended to be inverting, applying the offset control to
the noninverting input may be considered. Bring the
DC offsetting current into the inverting input node
through resistor values that are much larger than the
signal path resistors. This will insure that the
adjustment circuit has minimal effect on the loop gain
and hence the frequency response.
THERMAL ANALYSIS
Maximum desired junction temperature will set the
maximum allowed internal power dissipation, as
described below. In no case should the maximum
junction temperature be allowed to exceed 150°C.
Operating junction temperature (TJ) is given by
TA + PD × θJA. The total internal power dissipation
(PD) is the sum of quiescent power (PDQ) and
additional power dissipated in the output stage (PDL)
to deliver load power. Quiescent power is simply the
specified no-load supply current times the total
supply voltage across the part. PDL will depend on
the required output signal and load; though, for
resistive loads connected to mid-supply (VS/2), PDL is
at a maximum when the output is fixed at a voltage
equal to VS/4 or 3VS/4. Under this condition, PDL =
VS2/(16 × RL), where RL includes feedback network
loading.
Note that it is the power in the output stage, and not
into the load, that determines internal power
dissipation.
As a worst-case example, compute the maximum TJ
using an OPA2830 (MSOP-8 package) in the circuit
of Figure 72 operating at the maximum specified
ambient temperature of +85°C and driving a 150Ω
load at +2.5VDC on both outputs.
P D 10V 11.9mA 2
52
16 150 1500
142mW
Maximum T J 85 oC 0.142W 150 oCW 106 oC
Although this is still well below the specified
maximum junction temperature, system reliability
considerations may require lower ensured junction
temperatures. The highest possible internal
dissipation will occur if the load requires current to be
forced into the output at high output voltages or
sourced from the output at low output voltages. This
puts a high current through a large internal voltage
drop in the output transistors.
BOARD LAYOUT GUIDELINES
Achieving
optimum
performance
with
a
high-frequency amplifier like the OPA2830 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a) Minimize parasitic capacitance to any AC
ground for all of the signal I/O pins. Parasitic
32
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capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it can
react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
b) Minimize the distance ( < 0.25") from the
power-supply pins to high-frequency 0.1µF
decoupling capacitors. At the device pins, the ground
and power-plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power
and ground traces to minimize inductance between
the pins and the decoupling capacitors. Each
power-supply connection should always be
decoupled with one of these capacitors. An optional
supply decoupling capacitor (0.1µF) across the two
power supplies (for bipolar operation) will improve
2nd-harmonic distortion performance. Larger (2.2µF
to 6.8µF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PC board.
c) Careful selection and placement of external
components will preserve the high-frequency
performance. Resistors should be a very low
reactance type. Surface-mount resistors work best
and allow a tighter overall layout. Metal film or
carbon composition axially-leaded resistors can also
provide good high-frequency performance. Again,
keep their leads and PC board traces as short as
possible. Never use wire-wound type resistors in a
high-frequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series
output resistor, if any, as close as possible to the
output pin. Other network components, such as
noninverting input termination resistors, should also
be placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side
of the board between the output and inverting input
pins. Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor
values can create significant time constants that can
degrade performance. Good axial metal film or
surface-mount resistors have approximately 0.2pF in
shunt with the resistor. For resistor values > 1.5kΩ,
this parasitic capacitance can add a pole and/or zero
below 500MHz that can effect circuit operation. Keep
resistor values as low as possible consistent with
load driving considerations. The 750Ω feedback
used in the Typical Characteristics is a good starting
point for design.
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the typical characteristic curve
Recommended RS vs Capacitive Load. Low parasitic
capacitive loads (< 5pF) may not need an RS since
the OPA2830 is nominally compensated to operate
with a 2pF parasitic load. Higher parasitic capacitive
loads without an RS are allowed as the signal gain
increases (increasing the unloaded phase margin). If
a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary onboard, and
in fact, a higher impedance environment will improve
distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance
defined (based on board material and trace
dimensions), a matching series resistor into the trace
from the output of the OPA2830 is used as well as a
terminating shunt resistor at the input of the
destination device. Remember also that the
terminating impedance will be the parallel
combination of the shunt resistor and the input
impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a
doubly-terminated transmission line is unacceptable,
a long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in this
case and set the series resistor value as shown in
the typical characteristic curve Recommended RS vs
Capacitive Load. This will not preserve signal
integrity as well as a doubly-terminated line. If the
input impedance of the destination device is low,
there will be some signal attenuation due to the
voltage divider formed by the series output into the
terminating impedance.
e) Socketing a high-speed part is not
recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA2830 onto the board.
d) Connections to other wideband devices on the
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INPUT AND ESD PROTECTION
The OPA2830 is built using a very high-speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins are protected with internal ESD
protection diodes to the power supplies, as shown in
Figure 86.
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (that is, in systems with ±15V supply parts
driving into the OPA2830), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible, since high
values degrade both noise performance and
frequency response.
+VCC
External
Pin
Internal
Circuitry
−VCC
Figure 86. Internal ESD Protection
34
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from B Revision (February 2006) to C Revision ............................................................................................ Page
•
Changed Differential Input Voltage to ±2.5V from ±1.2V...................................................................................................... 2
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PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
OPA2830ID
ACTIVE
SOIC
D
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2830IDG4
ACTIVE
SOIC
D
8
100
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2830IDGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2830IDGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2830IDGKT
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2830IDGKTG4
ACTIVE
MSOP
DGK
8
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2830IDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
OPA2830IDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA2830IDGKR
MSOP
DGK
8
OPA2830IDGKT
MSOP
DGK
OPA2830IDR
SOIC
D
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2830IDGKR
MSOP
DGK
8
2500
346.0
346.0
29.0
OPA2830IDGKT
MSOP
DGK
8
250
184.0
184.0
50.0
OPA2830IDR
SOIC
D
8
2500
346.0
346.0
29.0
Pack Materials-Page 2
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