DATASHEET EL5126 FN7337 Rev 2.00 August 24, 2006 8-Channel TFT-LCD Reference Voltage Generator The EL5126 is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the serial interface. Features A number of the EL5126 can be stacked for applications requiring more than 8 outputs. The reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. • Low supply current of 10mA The EL5126 has 8 outputs and is available in a 32 Ld QFN package. It is specified for operation over the full -40°C to +85°C temperature range. • 8-channel reference outputs • Accuracy of ±0.1% • Supply voltage of 4.5V to 16.5V • Digital supply 3.3V to 5V • Rail-to-rail capability • I2C control interface Applications • TFT-LCD drive circuits • Reference voltage generators Pinout Ordering Information EL5126CL-T7 5126CL 32 Ld QFN 7” MDP0046 EL5126CLZ-T7 (Note) 5126CLZ 32 Ld QFN (Pb-free) 7” MDP0046 EL5126CL-T13 5126CL 32 Ld QFN 13” MDP0046 EL5126CLZ-T13 (Note) 5126CLZ 32 Ld QFN (Pb-free) 13” MDP0046 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN7337 Rev 2.00 August 24, 2006 26 NC MDP0046 VS 1 25 OUTA VSD 2 24 OUTB VS 3 23 OUTC REFH 4 22 OUTD THERMAL PAD REFL 5 21 DGND AGND 6 20 OUTE CAP 7 19 OUTF NC 8 18 OUTG VS 9 17 OUTH NC 16 - 27 FILTER 32 Ld QFN (Pb-free) NC 15 5126CLZ 28 STD/REG EL5126CLZ (Note) NC 14 MDP0046 29 SCL - DGND 13 32 Ld QFN 30 SDA 5126CL NC 12 EL5126CL 31 OSC PKG. NO. DGND 11 TAPE AND REEL 32 OSC_SEL PART MARKING PACKAGE A0 10 PART NUMBER EL5126 (32 LD 5X6 QFN) TOP VIEW Page 1 of 12 EL5126 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VS and GND. . . . . . . . . . . . . . . . . . . .+18V Supply Voltage between VSD and GND . . . . . . . . . . . . . . . . . . .+7V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications VS = 18V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5k and CL = 200pF to 0V, TA = +25°C Unless Otherwise Specified. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT 7.6 9 mA 1.9 3.2 mA 50 150 mV SUPPLY IS Supply Current ISD Digital Supply Current No load ANALOG VOL Output Swing Low Sinking 5mA VOH Output Swing High Sourcing 5mA ISC Short Circuit Current PSRR Power Supply Rejection Ratio tD 14.85 14.95 V RL = 10 150 240 mA VS+ is moved from 14V to 16V 45 60 dB Program to Out Delay 4 ms VAC Accuracy 20 mV VDROOP Droop Voltage RINH Input Resistance @ VREFH, VREFL REG Load Regulation FCLOCK = 25kHz 1 2 32 IOUT = 5mA step 0.5 mV/ms k 1.5 mV/mA DIGITAL VIH Logic 1 Input Voltage VIL Logic 0 Input Voltage FCLK Clock Frequency RSDIN SDIN Input Resistance 1 G tS Setup Time 40 ns tH Hold Time 40 ns tR Rise Time 20 ns tF Fall Time 20 ns FN7337 Rev 2.00 August 24, 2006 VSD20% V 20%* VSD V 400 kHz Page 2 of 12 EL5126 Pin Descriptions PIN NUMBER PIN NAME PIN TYPE PIN DESCRIPTION 1, 3, 9 VS Power Positive power supply for analog circuits 2 VSD Power Positive power supply for digital circuits 4 REFH Analog Input High reference voltage 5 REFL Analog Input Low reference voltage 6, 21, 11, 13 GND Power Ground 7 CAP Analog Decoupling capacitor for internal reference generator 8, 12, 14, 15, 16, 26 NC 10 A0 Logic Input 17 OUTH Analog Output Channel H programmable output voltage 18 OUTG Analog Output Channel G programmable output voltage 19 OUTF Analog Output Channel F programmable output voltage 20 OUTE Analog Output Channel E programmable output voltage 22 OUTD Analog Output Channel D programmable output voltage 23 OUTC Analog Output Channel C programmable output voltage 24 OUTB Analog Output Channel B programmable output voltage 25 OUTA Analog Output Channel A programmable output voltage 27 FILTER Logic Input Activates internal I2C data filter, high = enable, low = disable 28 STD/REG Logic Input Selects mode, high = standard, low = register mode 29 SCL Logic Input I2C clock 30 SDA Logic Input I2C data input 31 OSC IP/OP 32 OSC_SEL Logic Input Development I2C address input, bit 0 Oscillator pin for synchronizing multiple chips Selects internal/external OSC source, high = external, low = internal 0.3 7.8 0.2 7.6 0 -0.1 VS=15V VSD=5V VREFH=13V VREFL=2V -0.2 -0.3 10 210 410 610 810 7.2 7.0 6.8 6.6 1010 INPUT CODE FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE FN7337 Rev 2.00 August 24, 2006 ALL CHANNEL OUTPUT = 0V 7.4 0.1 IS (mA) DIFFERENTIAL NONLINEARITY (LSB) Typical Performance Curves 6.4 4 6 8 10 12 VS (V) 14 16 18 FIGURE 2. SUPPLY VOLTAGE vs SUPPLY CURRENT Page 3 of 12 EL5126 Typical Performance Curves (Continued) VS=VREFH=15V M=400ns/DIV 1.2 ISD (mA) VS=VREFH=15V 1.0 VREFL=0V 0mA 0.8 5mA/DIV 5mA CL=4.7nF RS=20 0.6 0.4 5V 0 200mV/DIV CL=1nF RS=20 0.2 3 3.2 3.4 3.5 3.8 4 4.2 4.4 4.5 4.8 VSD (V) CL=180pF 5 FIGURE 3. DIGITAL SUPPLY VOLTAGE vs DIGITAL SUPPLY CURRENT FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING) VS=VREFH=15V M=400ns/DIV 5mA SCLK 5V 0mA 0V CL=1nF RS=20 SDA 5V 0V 10V CL=4.7nF RS=20 CL=180pF 5V 0V OUTPUT M=400µs/DIV FIGURE 5. TRANSIENT LOAD REGULATION (SINKING) FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V) SCLK 5V SDA 0V SCLK SDA 5V 0V OUTPUT 200mV OUTPUT M=400µs/DIV FIGURE 7. LARGE SIGNAL RESPONSE (FALLING FROM 8V TO 0V) FN7337 Rev 2.00 August 24, 2006 0V M=400µs/DIV FIGURE 8. SMALL SIGNAL RESPONSE (RISING FROM 0V TO 200mV) Page 4 of 12 EL5126 Typical Performance Curves (Continued) 3 2 2 P3 C/W 5° =3 A OUTPUT 2.857W J SDA 2.5 LP POWER DISSIPATION (W) SCLK JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - LPP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 1.5 1 0.5 0 M=400µs/DIV 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 9. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 0V) FIGURE 10. POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 0.7 758mW 0.6 2 W P3 C/ LP 32° =1 J 0.5 A POWER DISSIPATION (W) 0.8 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 11. POWER DISSIPATION vs AMBIENT TEMPERATURE General Description The EL5126 provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the EL5126, the V/T curve can be changed to optimize its characteristics according to the required application of the display product. Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5126. As all of the output buffers are identical, it is also possible to use the EL5126 for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy. FN7337 Rev 2.00 August 24, 2006 Digital Interface The EL5126 uses a simple two-wire I2C digital interface to program the outputs. The bus line SCLK is the clock signal line and bus SDA is the data information signal line. The EL5126 can support the clock rate up to 400kHz. External pull up resistor is required for each bus line. The typical value for these two pull up resistor is about 1k. START AND STOP CONDITION The Start condition is a high to low transition on the SDA line while SCLK is high. The Stop condition is a low to high transition on the SDA line while SCLK is high. The start and stop conditions are always generated by the master. The bus is considered to be busy after the start condition and to be free again a certain time after the stop condition. The two bus lines must be high when the buses are not in use. The I2C Timing Diagram 2 shows the format. Page 5 of 12 EL5126 bit data for each channel output and there are total of 16 data bytes for 8 channels. Data in data byte 1 and 2 is for channel A. Data in data byte 15 and 16 is for channel H. D9 to D0 are the 10-bit data for each channel. The unused bits in the data byte are "don't care" and can be set to either one or zero. See Table 1 for program sample for one channel setting: DATA VALIDITY The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the clock signal on the SCLK line is low. BYTE FORMAT AND ACKNOWLEDGE Every byte put on the SDA line must be eight bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit first (MSB). TABLE 1. DATA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 The master puts a resistive high level on the SDA line during the acknowledge clock pulse. The peripheral that acknowledges has to pull down the SDA line during the acknowledge clock pulse. DEVICES ADDRESS AND W/R BIT Data transfers follow the format shown in Timing Diagram 1. After the Start condition, a first byte is sent which contains the Device Address and write/read bit. This address is a 7- bit long device address and only two device addresses (74H and 75H) are allowed for the EL5126. The first 6 bits (A6 to A1, MSBs) of the device address have been factory programmed and are always 111010. Only the least significant bit A0 is allowed to change the logic state, which can be tied to VSD or DGND. A maximum of two EL5126 may be used on the same bus at one time. The EL5126 monitors the bus continuously and waiting for the start condition followed by the device address. When a device recognizes its device address, it will start to accept data. An eighth bit is followed by the device address, which is a data direction bit (W/R). A "0" indicates a Write transmission and a "1" indicates a Read transmission. CONDITION 0 0 0 0 0 0 0 0 0 0 Data value = 0 1 0 0 0 0 0 0 0 0 0 Data value = 512 0 0 0 0 0 1 1 1 1 1 Data value = 31 1 1 1 1 1 1 1 1 1 1 Data value = 1023 When the W/R bit is high, the master can read the data from the EL5126. See Timing Diagram 1 for detail formats. REGISTER MODE The part operates at Register Mode if pin 28 (STD/REG) is held low. The Register Mode allows the user to program each output individually. Followed by the first byte, the second byte sets the register address for the programmed output channel. Bits R0 to R3 set the output channel address. For the unused bits in the R4 to R7 are "don't care". See Table 2 for program sample. The EL5126 also allows the user to read the data at Register Mode. See Timing Diagram 1 for detail formats. DIGITAL FILTER A user selectable digital filter can be used to filter noise spikes from the SCLK and SDA inputs. When the Filter pin (pin27) is high, the digital filter is enabled. When the Filter pin is low, the digital filter is disabled. The EL5126 can be operated as Standard mode and Register mode. See the I2C Timing Diagram 1 for detail formats. STANDARD MODE The part operates at Standard Mode if pin 28 (STD/REG) is held high. The Standard Mode allows the user to program the eight outputs at one time. Two data bytes are required for 10- TABLE 2. REGISTER ADDRESS DATA R3 R2 R1 R0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel A, Value = 0 X 0 0 1 1 0 0 0 0 0 0 0 0 0 Channel B, Value = 512 X 0 1 0 0 0 0 0 0 1 1 1 1 1 Channel C, Value = 31 X 1 1 1 1 1 1 1 1 1 1 1 1 1 Channel H, Value = 1023 FN7337 Rev 2.00 August 24, 2006 CONDITION Page 6 of 12 STANDARD MODE (STD/REG = HIGH) WRITE MODE I2C Data Start I2C Data In Device Address W A A6 A5 A4 A3 A2 A1 A0 I2C CLK In 1 2 3 4 5 6 7 8 EL5126 FN7337 Rev 2.00 August 24, 2006 I2C Timing Diagram 1 = don’t care Data 1 A Data 2 D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 A Data 3 Data 16 D7 D6 D5 A Stop D2 D1 D0 6 7 8 STANDARD MODE (STD/REG = HIGH) READ MODE I2C Data Start I2C Data In Device Address R A Data 1 A Data 2 A Data 3 Data 16 NA Stop A6 A5 A4 A3 A2 A1 A0 I2C Data Out I2C CLK In 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 D7 D6 D5 D2 D1 D0 6 7 8 REGISTER MODE (STD/REG = LOW) WRITE MODE I2C Data Start I2C Data In Device Address W A A6 A5 A4 A3 A2 A1 A0 I2C CLK In 1 2 3 4 5 6 7 8 Register Address A Data 1 A Data 2 A D7 D6 D5 D4 R3 R2 R1 R0 D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Stop REGISTER MODE (STD/REG = LOW) READ MODE I2C Data I2C Data In Start Device Address W A A6 A5 A4 A3 A2 A1 A0 Register Address D7 D6 D5 D4 R3 R2 R1 R0 A Start Device Address R A Page 7 of 12 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 A Data 2 A6 A5 A4 A3 A2 A1 A0 I2C Data Out I2C CLK In Data 1 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 NA Stop EL5126 I2C Timing Diagram 2 START CONDITION Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. tF tR STOP CONDITION DATA After power on, the chip will start with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. By setting pin 32 to high, the chip is on external clock mode. Setting pin 32 to low, the chip is on internal clock mode. CLOCK tS tH tS tH tR tF START, STOP & TIMING DETAILS OF I2C INTERFACE Analog Section TRANSFER FUNCTION The transfer function is: data V OUT IDEAL = V REFL + ------------- V REFH - V REFL 1024 where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5126 will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32k. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5126. GND < VREFH VS and GND VREFL VREFH. In some LCD applications that require more than 8 channels, the system can be designed such that one EL5126 will provide the Gamma correction voltages that are more positive than the VCOM potential. The second EL5126 can provide the Gamma correction voltage more negative than the VCOM potential. The Application Drawing shows a system connected in this way. CLOCK OSCILLATOR The EL5126 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn’t be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application FN7337 Rev 2.00 August 24, 2006 Page 8 of 12 EL5126 Block Diagram REFERENCE HIGH OUT OUT OUT OUT EIGHT CHANNEL MEMORY VOLTAGE SOURCES OUT OUT OUT OUT REFERENCE LOW REFERENCE DECOUPLE I2C DATA IN CONTROL IF I2C CLOCK IN FILTER STD/REG A0 OSCILLATOR OSCILLATOR INPUT/OUTPUT SELECT CHANNEL OUTPUTS POWER DISSIPATION Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 100mV of the power rails, (see Electrical Characteristics for details). With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125°C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5 and 50). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 48µs. In the worst-case scenario this will be 380µs, when the data has just missed the cycle. When a large change in output voltage is required, the change will occur in 2V steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16V can take between 3ms and 3.4ms depending on the absolute timing relative to the update cycle. FN7337 Rev 2.00 August 24, 2006 The maximum power dissipation allowed in a package is determined according to: T JMAX - T AMAX P DMAX = -------------------------------------------- JA where: • TJMAX = Maximum junction temperature • TAMAX = Maximum ambient temperature • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package Page 9 of 12 EL5126 The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads. POWER SUPPLY BYPASSING AND PRINTED CIRCUIT BOARD LAYOUT • i = 1 to total 8 Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5126. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5126 should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1µF ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7µF local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins. • VS = Supply voltage APPLICATION USING THE EL5126 • IS = Quiescent current In the first application drawing, the schematic shows the interconnect of a pair of EL5126 chips connected to give 8 gamma corrected voltages above the VCOM voltage, and 8 gamma corrected voltages below the VCOM voltage. P DMAX = V S I S + V S - V OUT i I LOAD i when sourcing, and: P DMAX = V S I S + V OUT i I LOAD i when sinking. Where: • VOUTi = Output voltage of the i channel • ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOAD's to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. © Copyright Intersil Americas LLC 2003-2006. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7337 Rev 2.00 August 24, 2006 Page 10 of 12 EL5126 Application Drawing +10V HIGH REFERENCE VOLTAGE REFH OUTA VS OUTB COLUMN (SOURCE) DRIVER 0.1µF +12V 0.1µF VSD +5V MICROCONTROLLER 0.1µF FILTER AO I2C DATA IN LCD TIMING CONTROLLER OUTD SDA I2C CLOCK HORIZONTAL RATE +5V LCD PANEL OUTC OUTE SCL OSC OSC_SEL OUTF CAP ADDRESS = H74 0.1µF OUT REFL STD GND OUTH EL5126 MIDDLE REFERENCE VOLTAGE +5.5V REFH OUTA OSC OSC_SEL VS OUTB +5V +12V 0.1µF VSD +5V OUTC FILTER 0.1µF I2C DATA IN I2C CLOCK AO SDA OUTD SCL OUTE ADDRESS = H75 CAP +1V 0.1µF LOW REFERENCE VOLTAGE OUTF REFL 0.1µF OUT STD GND OUTH EL5126 FN7337 Rev 2.00 August 24, 2006 Page 11 of 12 EL5126 QFN (Quad Flat No-Lead) Package Family QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A SYMBOL QFN44 QFN38 D B N (N-1) (N-2) 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW TOLERANCE NOTES A 0.90 0.90 0.90 QFN32 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 0.10 M C A B (N-2) (N-1) N b L PIN #1 I.D. 3 1 2 3 (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SYMBOL QFN28 QFN24 QFN20 QFN16 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 10 12/04 SEATING PLANE NOTES: 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" (c) 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. (L) A1 DETAIL X FN7337 Rev 2.00 August 24, 2006 2. Tiebar view shown is a non-functional feature. 4. N is the total number of terminals on the device. 2 A 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. SIDE VIEW C MDP0046 N LEADS 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. Page 12 of 12