TI BQ24161YFFT 2.5a, dual-input, single cell switchmode li-ion battery charger with power path Datasheet

bq24160, bq24161
bq24163, bq24168
www.ti.com
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
2.5A, Dual-Input, Single Cell Switchmode Li-Ion Battery Charger with Power Path
Management and I2C Interface
Check for Samples: bq24160, bq24161, bq24163, bq24168
FEATURES
APPLICATIONS
•
•
•
•
•
1
2
•
•
•
•
•
•
•
•
•
•
High-Efficiency Switch Mode Charger with
Separate Power Path Control
– Make a GSM Call with a Deeply Discharged
Battery or No Battery
– Instantly Start Up System from a Deeply
Discharged Battery or No Battery
Dual Input Charger
Highly Integrated Battery N-Channel MOSFET
Controller for Power Path Management
– 20 V input rating, with Overvoltage
Protection (OVP)
– 6.5 V for USB Input
– 10.5 V for IN input (bq24160/1/3)
– 6.5 V for IN input (bq24168)
– Integrated FETs for Up to 2.5A Charge Rate
– Up to 2.5 A from IN Input (input current
limit)
– Up to 1.5 A from USB Input (input
current limit)
Safe and Accurate Battery Management
Functions
– 0.5% Battery Regulation Accuracy
– 10% Charge Current Accuracy
Charge Parameters Programmed Using I2C™
Interface
– Charge Voltage, Current, Termination
Threshold, Input Current Limit, VINDPM
Threshold
Voltage Based, NTC Monitoring Input
– JEITA Compatible (bq24160/3/8)
Thermal Regulation Protection for Output
Current Control
Low Battery Leakage Current, BAT ShortCircuit Protection
Soft-Start Feature to Reduce Inrush Current
Thermal Shutdown and Protection
Available in small 2.8mm × 2.8mm 49-ball
WCSP or 4mm × 4mm QFN-24 Packages
Handheld Products
Portable Media Players
Portable Equipment
Netbook and Portable Internet Devices
DESCRIPTION
The bq24160/ bq24161/ bq24163/ bq24168 are highly
integrated single cell Li-Ion battery charger and
system power path management devices targeted for
space-limited, portable applications with high capacity
batteries. The single cell charger has dual inputs
which allow operation from either a USB port or
higher-power input supply (i.e., AC adapter or
wireless charging input) for a versatile solution. The
two inputs are fully isolated from each other and are
easily selectable using the I2C interface.
APPLICATION SCHEMATIC
AC Adapter or
Wireless Power
SW
IN
System
Load
PMIDI
USB
VBUS
D+
D–
GND
BOOT
SYS
PMIDU
D+
D–
BAT
SDA
SCL
HOST
INT
TS
PGND
TEMP PACK+
DRV
+
–
VSYS
PACK–
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of NXP Semiconductor.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
bq24160, bq24161
bq24163, bq24168
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The power path management feature allows the bq2416x to power the system from a high-efficiency DC-to-DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows for proper charge termination and timer operation. Under normal battery charging conditions, the
system voltage is approximately equal to the battery voltage, however if the battery is deeply discharged, the
system voltage does not drop below 3.5V. This minimum system voltage support enables the system to run with
a defective or absent battery pack and enables instant system turn-on even with a totally discharged battery or
no battery. The power-path management architecture also permits the battery to supplement the system current
requirements when the adapter cannot deliver the peak system currents. This enables the use of a smaller
adapter. The 2.5A input current capability allows for GSM phone calls as soon as the adapter is plugged in
regardless of the battery voltage. The charge parameters are programmable using the I2C interface.
The battery is charged in three phases: precharge, fast-charge constant current and constant voltage. In all
charge phases, an internal control loop monitors the IC junction temperature and reduces the charge current if
the internal temperature threshold is exceeded. Additionally, a voltage-based battery pack thermistor monitoring
input (TS) is included that monitors battery temperature for safe charging. The TS function for bq24160, bq24163
and bq24168 is JEITA compatible.
2
Copyright © 2011–2012, Texas Instruments Incorporated
bq24160, bq24161
bq24163, bq24168
www.ti.com
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
ORDERING INFORMATION
PART NUMBER
USB
OVP
IN OVP
USB
DETECTION
TIMERS
(Safety and
Watchdog)
NTC
MONITORING
VBATSHRT/
IBATSHRT
VMINSYS
PKG
bq24160YFFR
6.5V
10.5V
D+/D–
Yes
JEITA
3.0V
50mA
3.5V
WCSP
bq24160YFFT
6.5V
10.5V
D+/D–
Yes
JEITA
3.0V
50mA
3.5V
WCSP
bq24160RGER
6.5V
10.5V
D+/D–
Yes
JEITA
3.0V
50mA
3.5V
QFN
bq24160RGET
6.5V
10.5V
D+/D–
Yes
JEITA
3.0V
50mA
3.5V
QFN
bq24161YFFR
6.5V
10.5V
PSEL
Yes
Standard
2.0V
50mA
3.5V
WCSP
bq24161YFFT
6.5V
10.5V
PSEL
Yes
Standard
2.0V
50mA
3.5V
WCSP
bq24161RGER
6.5V
10.5V
PSEL
Yes
Standard
2.0V
50mA
3.5V
QFN
bq24161RGET
6.5V
10.5V
PSEL
Yes
Standard
2.0V
50mA
3.5V
QFN
bq24163RGER
6.5V
10.5V
D+/D–
Yes
JEITA
2.0V
50mA
3.2V
WCSP
bq24163YFFT
6.5V
10.5V
D+/D–
Yes
JEITA
2.0V
50mA
3.2V
WCSP
bq24163YFFR
6.5V
10.5V
D+/D–
Yes
JEITA
2.0V
50mA
3.2V
QFN
bq24163RGET
6.5V
10.5V
D+/D–
Yes
JEITA
2.0V
50mA
3.2V
QFN
bq24168YFFR
6.5V
6.5V
PSEL
No
JEITA
2.0V
50mA
3.5V
WCSP
bq24168YFFT
6.5V
6.5V
PSEL
No
JEITA
2.0V
50mA
3.5V
WCSP
Copyright © 2011–2012, Texas Instruments Incorporated
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SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
IN, USB
Pin voltage range (with
respect to VSS)
Input current (Continuous)
Output sink current
MAX
UNITS
–2
20
V
PMIDI, PMIDU, BOOT
–0.3
20
V
SW
–0.7
12
V
SDA, SCL, SYS, BAT, STAT, BGATE, DRV, TS, D+, D–, INT, PSEL, CD
–0.3
7
V
–0.3
7
V
BOOT to SW
Output current (Continuous)
MIN
SW
4.5
A
SYS, BAT
3.5
A
IN
2.75
A
USB
1.75
A
STAT
10
mA
INT
1
mA
Operating free-air temperature range
–40
85
°C
Junction temperature, TJ
–40
125
°C
Storage temperature, TSTG
–65
150
°C
Lead temperature (soldering, 10 s)
300
(1)
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
THERMAL INFORMATION
THERMAL METRIC (1)
bq2416x
49 PINS (YFF)
24 PINS (RGE)
θJA
Junction-to-ambient thermal resistance
49.8
32.6
θJCtop
Junction-to-case (top) thermal resistance
0.2
30.5
θJB
Junction-to-board thermal resistance
1.1
3.3
ψJT
Junction-to-top characterization parameter
1.1
0.4
ψJB
Junction-to-board characterization parameter
6.6
9.3
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
2.6
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VIN
VUSB
MIN
MAX
IN voltage range
4.2
18
IN operating voltage range (bq24160/1/3)
4.2
10
IN operating voltage range (bq24168)
4.2
6
USB voltage range
4.2
18
USB operating range
4.2
6
UNITS
V
V
IIN
Input current, IN input
2.5
A
IUSB
Input current USB input
1.5
A
ISYS
Ouput Current from SW, DC
3
A
Charging
2.5
A
Discharging, using internal battery FET
2.5
A
125
ºC
IBAT
TJ
4
Operating junction temperature range
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): bq24160 bq24161 bq24163 bq24168
bq24160, bq24161
bq24163, bq24168
www.ti.com
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS
Circuit of , VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY > VBAT+VSLP,
TJ = –40°C – 125°C and TJ = 25ºC for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENTS
VUVLO < VSUPPLY < VOVP and
VSUPPLY > VBAT+VSLP
PWM switching
ISUPPLY
Supply current for control (VIN or VUSB)
IBATLEAK
Leakage current from BAT to the Supply
0°C < TJ < 85°C, VBAT = 4.2V, VUSB = VIN = 0V
IBAT_HIZ
Battery discharge current in High Impedance mode,
(BAT, SW, SYS)
0°C< TJ < 85°C, VBAT = 4.2V, VSUPPLY = 5V or 0V,
SCL, SDA = 0 V or 1.8V, High-Z Mode
15
PWM NOT switching
mA
5
0°C < TJ < 85°C, High-Z Mode
175
μA
5
μA
55
μA
POWER-PATH MANAGEMENT
bq24160/1/8
VBAT < VMINSYS
VSYS(REG)
System regulation voltage
3.60
3.7
3.3
3.4
3.5
VBATREG
+ 1.5%
VBATREG
+ 3.0%
VBATREG
+ 4.17%
bq24160/1/8
3.4
3.5
3.62
V
bq24163
3.1
3.2
3.3
V
bq24163
Battery FET turned off
VMINSYS
VBAT < VMINSYS, Input current limit
or VINDPM active
Minimum system regulation voltage
3.82
V
VBSUP1
Enter supplement mode threshold
VBAT > 2.5V
VBAT
–30mV
VBSUP2
Exit supplement mode threshold
VBAT > 2.5V
VBAT
–10mV
V
ILIM(discharge)
Current limit, discharge or supplement mode
Current monitored in internal FET only.
7
A
tDGL(SC1)
Deglitch time, SYS short circuit during discharge or
supplement mode
Measured from (VBAT – VSYS) = 300mV to BAT highimpedance
250
μs
tREC(SC1)
Recovery time, SYS short circuit during discharge or
supplement mode
60
ms
Battery range for BGATE and supplement mode
operation
2.5
4.5
V
V
BATTERY CHARGER
RON(BAT-SYS)
Internal battery charger MOSFET on-resistance
Charge Voltage
VBATREG
Measured from BAT to SYS,
VBAT = 4.2V
YFF pkg
37
57
RGE pkg
50
70
mΩ
Operating in voltage regulation, Programmable range
Voltage regulation accuracy
Fast charge current range
VBATSHRT ≤ VBAT < VBAT(REG) programmable range
Fast charge current accuracy
0°C to 125°C
VBATSHRT
Battery short circuit threshold
100mV Hysteresis
IBATSHRT
Battery short circuit current
tDGL(BATSHRT)
Deglitch time for battery short circuit to fastcharge
transition
ITERM
Termination charge current accuracy
tDGL(TERM)
Deglitch time for charge termination
Both rising and falling, 2mV overdrive, tRISE, tFALL = 100ns
VRCH
Recharge threshold voltage
Below VBATREG
tDGL(RCH)
Deglitch time
VDETECT
Battery detection threshold
ICHARGE
3.5
4.44
–1%
1%
550
2500
–10%
+10%
bq24161/3/8
1.9
2.0
2.1
bq24160
2.9
3.0
3.1
mA
V
VBAT < VBATSHRT
ITERM = 50mA
–35%
ITERM ≥ 100mA
–15%
50
mA
32
ms
+35%
+15%
32
ms
120
mV
VBAT falling below VRCH, tFALL=100ns
32
ms
During battery detection source cycle
3.3
V
During battery detection sink cycle
3.0
2.5
mA
250
ms
IDETECT
Battery detection current before charge done (sink
current)
Termination enabled (EN_TERM = 1)
tDETECT
Battery detection time
Termination enabled (EN_TERM = 1)
VIH(CD)
CD Input high logic level
VIL(CD)
CD Input low logic level
1.3
V
0.4
Copyright © 2011–2012, Texas Instruments Incorporated
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SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
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ELECTRICAL CHARACTERISTICS (Continued)
Circuit of Figure 23, VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY > VBAT+VSLP,
TJ = -40°C – 125°C and TJ = 25ºC for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CURRENT LIMITING
IIN_USB
Input current limit threshold (USB input)
USB charge mode, VUSB = 5V,
DC Current pulled from SW
IUSBLIM = USB100
90
95
100
IUSBLIM = USB500
450
475
500
IUSBLIM = USB150
135
142.5
150
IUSBLIM = USB900
800
850
900
mA
IUSBLIM = USB800
IIN_IN
Input current limit threshold (IN input)
VIN_DPM
Input based DPM threshold range
700
750
800
IUSBLIM = 1.5A
1250
1400
1500
IINLIM = 1.5A
1.35
1.5
1.65
IINLIM = 2.5A
2.3
2.5
2.8
Charge mode, programmable via I2C, both inputs
4.2
4.76
–2
+2%
IN charge mode, VIN = 5V,
DC Current pulled from SW
VIN_DPM threshold accuracy
A
V
VDRV BIAS REGULATOR
VDRV
Internal bias regulator voltage
IDRV
DRV output current
VSUPPLY > 5.45V
VDO_DRV
DRV Dropout voltage (VSUPPLY – VDRV)
5
5.2
5.45
10
V
mA
ISUPPLY = 1A, VSUPPLY = 5V, IDRV = 10mA
450
mV
0.4
V
1
µA
STATUS OUTPUT (STAT, INT)
VOL
Low-level output saturation voltage
IO = 10mA, sink current
IIH
High-level leakage current
VSTAT = VINT = 5V
VUVLO
IC active threshold voltage
VIN rising
3.6
3.8
VUVLO_HYS
IC active hysteresis
VIN falling from above VUVLO
120
150
VSLP
Sleep-mode entry threshold, VSUPPLY-VBAT
2.0V ≤VBAT ≤VBATREG, VIN falling
VSLP_EXIT
Sleep-mode exit hysteresis
2.0V ≤VBAT ≤VBATREG
Deglitch time for supply rising above VSLP+VSLP_EXIT
Rising voltage, 2mV over drive, tRISE = 100ns
PROTECTION
VBAD_SOURCE
0
40
100
mV
100
175
mV
30
Bad source detection threshold
VBOVP
Input supply OVP threshold voltage
IN, VIN Rising (bq24160/1/3)
VOVP hysteresis
ms
6.3
6.5
6.7
10.3
10.5
10.7
6.3
6.5
6.7
1.025 ×
VBATREG
1.05 ×
VBATREG
Supply falling from VOVP
100
Battery OVP threshold voltage
VBAT threshold over VOREG to turn off charger during charge
VBOVP hysteresis
Lower limit for VBAT falling from above VBOVP
VBATUVLO
Battery undervoltage lockout threshold
VBAT rising, 100mV hysteresis
ILIMIT
Cycle-by-cycle current limit
VSYS shorted
TSHTDWN
Thermal trip
4.9
V
% of
VBATREG
2.5
4.1
V
mV
1.075 ×
VBATREG
1
V
5.6
165
Thermal hysteresis
TREG
V
32
IN, VIN Rising (bq24168)
VOVP(HYS)
ms
VIN_DPM
– 80 mV
USB, VUSB Rising
V
mV
40
Deglitch on bad source detection
VOVP
4
A
°C
10
Thermal regulation threshold
Charge current begins to cut off
Safety timer accuracy
(bq24160/1/3 Only)
120
–20%
°C
20%
PWM
Internal top reverse blocking MOSFET on-resistance
95
175
IIN_LIMIT = 500mA, Measured from IN to PMIDI
45
80
mΩ
Internal top N-channel Switching MOSFET onresistance
Measured from PMIDU to SW
100
175
Measured from PMIDI to SW
65
110
Internal bottom N-channel MOSFET on-resistance
Measured from SW to PGND
fOSC
Oscillator frequency
DMAX
Maximum duty cycle
DMIN
Minimum duty cycle
6
IIN_LIMIT = 500mA, Measured from USB to PMIDU
mΩ
1.35
65
115
mΩ
1.50
1.65
MHz
95%
0%
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bq24163, bq24168
www.ti.com
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (Continued)
Circuit of , VSUPPLY = VUSB or VIN (whichever is supplying the IC), VUVLO < VSUPPLY < VOVP and VSUPPLY > VBAT+VSLP,
TJ = -40°C – 125°C and TJ = 25ºC for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
29.7
30
30.5
UNIT
BATTERY-PACK NTC MONITOR
VHOT
High temperature threshold
VTS falling
VHYS(HOT)
Hysteresis on high threshold
VTS rising
VWARM
High temperature threshold
VTS falling
VHYS(WARM)
Hysteresis on high threshold
VTS rising
VCOOL
Low temperature threshold
VTS falling
VHYS(COOL)
Hysteresis on low threshold
VTS rising
VCOLD
Low temperature threshold
VTS falling
VHYS(COLD)
Hysteresis on low threshold
VTS rising
TSOFF
TS Disable threshold
VTS rising, 2%VDRV hysteresis
tDGL(TS)
Deglitch time on TS change
%VDRV
1
37.9
38.3
39.6
%VDRV
1
56
56.5
56.9
%VDRV
1
59.5
60
60.4
%VDRV
1
70
73
50
%VDRV
ms
D+/D– DETECTION (bq24160)
VD+_SRC
D+ Voltage Source
ID+_SRC
D+ Connection Check Current Source
0.5
ID-_SINK
D- Current Sink
ID_LKG
Leakage Current into D+/D-
0.6
7
50
100
0.7
V
14
µA
150
µA
D–, switch open
–1
1
µA
D+, switch open
–1
1
µA
VD+_LOW
D+ Low Comparator Threshold
0.8
VD-_LOWdatref
D- Low Comparator Threshold
250
400
mV
V
RD-_DWN
D- Pulldown for Connection Check
14.25
24.8
kΩ
BATGD OPERATION
VBATGD
Good Battery threshold
3.6
Deglitch for good battery threshold
VBAT rising to HIGH-Z mode, DEFAULT Mode Only
3.8
3.9
32
V
ms
I2C COMPATIBLE INTERFACE
VIH
Input low threshold level
VPULL-UP = 1.8V, SDA and SCL
VIL
Input low threshold level
VPULL-UP = 1.8V, SDA and SCL
0.4
VOL
Output low threshold level
IL = 10mA, sink current
0.4
IBIAS
High-Level leakage current
VPULL-UP = 1.8V, SDA and SCL
tWATCHDOG
Watchdog timer timeout
(bq24160/1/3 Only)
Copyright © 2011–2012, Texas Instruments Incorporated
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V
1
30
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BLOCK DIAGRAM
PMIDU
PMIDI
5.2-V Reference
DRV
IN
Q1
USB
5A
+
BOOT
CbC Current
Limit
IN IINLIM
USB IUSBLIM
IN VINDPM
DC-DC CONVERTER
PWM LOGIC,
COMPENSATION
AND
BATTERY FET CONTROL
USB VINDPM
VSYS(REG)
Q2
IBAT(REG)
SW
VBAT(REG)
DIE Temp
Regulation
Q3
PGND
VSUPPLY
IBAT
Termination Comparator
+
VINOVP
Enable Linear
Charge
Sleep Comparators
+
Hi-Z Mode
2
Supplement Comparator
I C
Interface
+
VBAT
bq24160/3
1.5A/USB100
DISABLE
TS COLD
bq24161/8
1C/0.5C
PSEL
bq24160/2/3
TS COOL
VBATREG – 0.14V
STAT
TS WARM
+
D–
USB
Adapter
Detection
Circuitry
VDRV
VBOVP Comparator
VBAT
VBATOVP
+
D+
VSYS
VBSUP
+
SCL
BGATE
+
SDA
Hi-Z Mode
+
CD
VBAT
VBATGD
VBATSC Comparator
VBAT
Enable
IBATSHRT
VBATSHRT
Good Battery
Circuit
+
VIN
VBAT + VSLP
VSYSREG Comparator
VSYS
VMINSYS
+
+
BAT
Recharge Comparator
VBATREG – 0.12V
VBAT
+
VUSB
VBAT + VSLP
Start Recharge
Cycle
Q4
+
OVP Comparators
VIN
SYS
+
VUSBOVP
References
SUPPLY_SEL
Termination
Reference
+
VUSB
+
DISABLE
TS HOT
INT
8
CHARGE
CONTROLLER
with Timers (160/1/3)
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bq24163, bq24168
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SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
19
20
21
23
22
24
19
20
22
21
23
PMIDI
BOOT
IN
USB
CD
PMIDU
PMIDI
BOOT
IN
USB
CD
PMIDU
24
PIN CONFIGURATION
D-
1
18 SW
N.C.
1
18 SW
D+
2
17 PGND
PSEL
2
17 PGND
SCL
3
16 SGND
SCL
3
SDA
4
15 PGND
SDA
4
PGND
5
14 SYS
GND
5
14 SYS
DRV
6
13 SYS
DRV
6
13 SYS
bq24160
bq24163
16 SGND
bq24161
bq24168
15 PGND
12 BAT
TS
11 BAT
10 BGATE
8 STAT
9
7 /BATGD
11 BAT
12 BAT
TS
10 BGATE
8 STAT
9
7 INT
Figure 1. 24-Pin QFN (RGE)
bq24160/3
(Top View)
1
2
3
4
A
IN
IN
IN
IN
B
PMIDI
PMIDI
PMIDI
C
SW
SW
D
PGND
E
bq24161/8
(Top View)
5
6
7
IN
USB
USB
USB
PMIDI
PMIDI
PMIDU
PMIDU
PMIDU
SW
SW
SW
SW
SW
SW
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PSEL
N.C.
CD
SDA
SCL
BOOT
SYS
SYS
SYS
SYS
BGATE
INT
DRV
BAT
BAT
BAT
BAT
TS
STAT
PGND
2
3
7
USB
USB
USB
A
IN
IN
IN
PMIDI
PMIDU
PMIDU
PMIDU
B
PMIDI
PMIDI
SW
SW
SW
SW
SW
C
SW
PGND
PGND
PGND
PGND
PGND
PGND
D
PGND
D+
D-
CD
SDA
SCL
BOOT
E
SYS
SYS
SYS
SYS
BGATE
INT
DRV
F
G
5
1
6
4
F
BAT
BAT
BAT
BAT
TS
STAT
PGND
G
Figure 2. 49-Ball 2.8mm x 2.8mm WCSP (YFF)
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PIN FUNCTIONS
PIN
NAME
PIN NO.
bq24160/3
PIN NO.
bq24161/8
I/O
DESCRIPTION
YFF
RGE
YFF
RGE
G1-G4
11, 12
G1-G4
11, 12
BGATE
F5
10
F5
10
O
External Discharge MOSFET Gate Connection – BGATE drives an external PChannel MOSFET to provide a very low-resistance discharge path. Connect BGATE
to the gate of the external MOSFET. BGATE is low during high impedance mode
and when no input is connected.
BOOT
E7
19
E7
19
I
High Side MOSFET Gate Driver Supply – Connect a 0.01µF ceramic capacitor
(voltage rating > 10V) from BOOT to SW to supply the gate drive for the high side
MOSFETs.
CD
E4
24
E4
24
I
IC Hardware Disable Input – Drive CD high to place the bq2416x in high-z mode.
Drive CD low for normal operation. Do not leave CD unconnected.
D+
E2
2
—
—
I
D–
E3
1
—
—
I
D+ and D– Connections for USB Input Adapter Detection – When a charge cycle
is initiated by the USB input, and a short is detected between D+ and D–, the USB
input current limit is set to 1.5A. If a short is not detected, the USB100 mode is
selected. The D+/D– detection has no effect on the IN input.
DRV
F7
6
F7
6
O
Gate Drive Supply – DRV is the bias supply for the gate drive of the internal
MOSFETs. Bypass DRV to PGND with a 1μF ceramic capacitor. DRV may be used
to drive external loads up to 10mA. DRV is active whenever the input is connected
and VSUPPLY > VUVLO and VSUPPLY > (VBAT + VSLP)
A1- A4
21
A1- A4
21
I
Input power supply – IN is connected to the external DC supply (AC adapter or
alternate power source). Bypass IN to PGND with at least a 1μF ceramic capacitor.
F6
7
F6
7
O
Status Output – INT is an open-drain output that signals charging status and fault
interrupts. INT pulls low during charging. INT is high impedance when charging is
complete or the charger is disabled. When a fault occurs, a 128μs pulse is sent out
as an interrupt for the host. INT is enabled/disabled using the EN_STAT bit in the
control register. Connect INT to a logic rail through a 100kΩ resistor to communicate
with the host processor.
PGND
D1-D7,
E1, G7
5, 15,
16, 17
D1-D7,
E1, G7
5, 15,
16, 17
—
Ground terminal – Connect to the thermal pad (for QFN only) and the ground plane
of the circuit.
PMIDI
B1-B4
20
B1-B4
20
O
Reverse Blocking MOSFET and High Side MOSFET Connection Point for High
Power Input – Bypass PMIDI to GND with at least a 4.7μF ceramic capacitor. Use
caution when connecting an external load to PMIDI. The PMIDI output is not current
limited. Any short on PMIDI will damage the IC.
PMIDU
B5-B7
23
B5-B7
23
O
Reverse Blocking MOSFET and High Side MOSFET Connection Point for USB
Input – Bypass PMIDU to GND with at least a 4.7μF ceramic capacitor. Use caution
when connecting an external load to PMIDU. The PMIDU output is not current
limited. Any short on PMIDU will damage the IC.
PSEL
—
—
E2
2
SCL
E6
3
E6
3
SDA
E5
4
E5
4
I/O I2C Interface Data – Connect SDA to the logic rail through a 10kΩ resistor.
STAT
G6
8
G6
8
O
Status Output – STAT is an open-drain output that signals charging status and fault
interrupts. STAT pulls low during charging. STAT is high impedance when charging
is complete or the charger is disabled. When a fault occurs, a 128μs pulse is sent
out as an interrupt for the host. STAT is enabled /disabled using the EN_STAT bit in
the control register. Pull STAT up to a logic rail thruogh an LED for visual indication
or through a 10kΩ resistor to communicate with the host processor.
SW
C1-C7
18
C1-C7
18
O
Inductor Connection – Connect to the switched side of the external inductor.
SYS
F1-F4
13, 14
F1-F4
13,14
I
System Voltage Sense and Charger FET Connection – Connect SYS to the
system output at the output bulk capacitors. Bypass SYS locally with at least 10μF.
A 47μF bypass capacitor is recommended for optimal transient response.
BAT
IN
INT
10
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I/O Battery Connection – Connect to the positive terminal of the battery. Additionally,
bypass BAT to GND with at least a 1μF capacitor.
USB Source Detection Input – Drive PSEL high to indicate that a USB source is
connected to the USB input. When PSEL is high, the IC starts up with a 100mA
input current limit for USB. Drive PSEL low to indicate that an AC Adapter is
connected to the USB input. When PSEL is low, the IC starts up with a 1.5A input
current limit for USB. PSEL has no effect on the IN input. Do not leave PSEL
unconnected.
I
I2C Interface Clock – Connect SCL to the logic rail through a 10kΩ resistor.
Copyright © 2011–2012, Texas Instruments Incorporated
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SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
PIN FUNCTIONS (continued)
PIN
NAME
TS
USB
Thermal
Pad
PIN NO.
bq24160/3
PIN NO.
bq24161/8
I/O
DESCRIPTION
9
I
Battery Pack NTC Monitor – Connect TS to the center tap of a resistor divider from
DRV to GND. The NTC is connected from TS to GND. The TS function provides 4
thresholds for JEITA compatibility (160/163/168 only). TS faults are reported by the
I2C interface. See the NTC Monitor section for more details on operation and
selecting the resistor values. Connect TS to DRV to disable the TS function.
A5-A7
22
I
USB Input Power Supply – USB is connected to the external DC supply (AC
adapter or USB port). Bypass USB to PGND with at least a 1μF ceramic capacitor.
—
Pad
—
There is an internal electrical connection between the exposed thermal pad and the
PGND pin of the device. The thermal pad must be connected to the same potential
as the PGND pin on the printed circuit board. Do not use the thermal pad as the
primary ground input for the device. PGND pin must be connected to ground at all
times.
YFF
RGE
YFF
RGE
G5
9
G5
A5-A7
22
—
Pad
TYPICAL APPLICATION CIRCUIT
ADAPTER
1.5 mH
IN
SW
PMIDI
1 mF
VBUS
D+
DGND
BOOT
USB
SYS
10 mF
PMIDU
1 mF
System
Load
0.01 mF
4.7 mF
PGND
4.7 mF
BGATE
DRV
BAT
1 mF
VDRV
1 mF
STAT
GSM
PA
PACK+
TS
TEMP
VSYS
(1.8V)
D+
DPACK-
HOST
bq24160
INT
SDA
GPIO1
SCL
SCL
SDA
Figure 3. bq24160, Shown with no External Discharge FET, PA Connected to Battery
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ADAPTER
1.5 mH
IN
SW
PMIDI
1 mF
System
Load
0.01 mF
4.7 mF
BOOT
VBUS
D+
DGND
USB
SYS
10 mF
PMIDU
1 mF
PGND
4.7 mF
BGATE
DRV
GSM
PA
BAT
1 mF
VDRV
1 mF
STAT
PACK+
TS
TEMP
VSYS
(1.8V)
PSEL
USB PHY
PACK-
HOST
bq24161
INT
SDA
GPIO1
SCL
SCL
SDA
Figure 4. – bq24161, Shown with External Discharge FET, PA Connected to System for GSM Call Support
with a Deeply Discharged or No Battery
TYPICAL CHARACTERISTICS
USB Plug-In with Battery Connected
Conditions: USB500, 925mA Charge Setting
Figure 5.
Adapter Detection USB
IN Plug-in with Battery Connected
Conditions: 1500mA ILIM, 1300mA Charge Setting
Figure 6.
Battery Insert During Battery Detection
Conditions: Termination Enabled
12
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SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
Figure 7.
Figure 8.
Battery Pull During Charging
Load Transient into DPPM
Conditions: Termination Enabled
Conditions: MINSYS Operation, USB1500, 200mA-1400mA Load
Step on SYS
Figure 10.
Figure 9.
OVP Fault
USB Input
Load Transient into Supplement Mode
VUSB
5 V/div
VSYS
5 V/div
VBAT
VSTAT/INT
1 V/div
5 V/div
VSW
IUSB
500 mA/div
1 A/div
IBAT
500 mA/div
IBAT
10 ms/div
4 ms/div
Conditions: MINSYS Operation, USB500, 200mA - 1400mA Load
Step on SYS
Figure 11.
Figure 12.
USB Efficiency
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
IN Efficiency
100
60
50
40
30
60
50
40
30
VIN = 5 V
VIN = 7 V
VIN = 9 V
20
10
0
0.1
1
System Current (A)
20
3
0
0.1
1
System Current (A)
G001
Conditions: Charge Disabled, SYS loaded, VBATREG = 3.6V, IN2500
ILIM
Figure 13.
Copyright © 2011–2012, Texas Instruments Incorporated
VUSB = 5 V
VUSB = 6 V
10
2
G002
Conditions: Charge Disabled, SYS loaded, VBATREG = 3.6V,
USB1500 ILIM
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
Battery Regulation vs Temperature
3.85
4.21
SYSREG Regulation
MINSYS Regulation
4.208
3.8
4.206
Battery Regulation (V)
SYSREG and MINSYS Regulation (V)
SYSREG and MINSYS Regulation vs. Temperature
3.9
3.75
3.7
3.65
3.6
3.55
4.204
4.202
4.2
4.198
4.196
3.5
4.194
3.45
4.192
3.4
−50
0
50
Temperature (°C)
100
4.19
150
0
Conditions: VBAT = 3V
USB Input Current Limit vs. Temperature
400
300
200
100
6.5
6.4
6.3
6.2
6.1
0
50
Temperature (°C)
100
6
−50
150
0
G005
50
Temperature (°C)
100
150
G006
Conditions: USB input and IN input (bq24168)
Figure 18.
10.5V OVP Threshold vs. Temperature
Charge Current vs. Battery Voltage
10.7
2.1
Falling Edge
Rising Edge
2.09
2.08
Charge Current (A)
10.5 V OVP Threshold (V)
G004
Falling Edge
Rising Edge
6.6
6.5 V OVP Threshold (V)
USB Input Current Limit (mA)
USB100 Current Limit
USB500 Current Limit
Conditions: USB100 and USB500 current limit, VUSB = 5V, VBAT =
3.6V
Figure 17.
10.5
10.4
10.3
10.2
2.07
2.06
2.05
2.04
2.03
2.02
10.1
10
−50
2.01
0
50
Temperature (°C)
Figure 19.
14
125
6.7
500
10.6
100
6.5V OVP Threshold vs. Temperature
700
0
−50
50
75
Temperature (°C)
Conditions: VBATREG = 4.2V, No load, Termination Disabled
Figure 16.
Figure 15.
600
25
G003
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100
150
2
2
2.5
G007
3
3.5
Battery Voltage (V)
4
4.5
G008
Conditions: ICHARGE = 2A, VIN = 5V, VBATREG = 4.44V
Figure 20.
Copyright © 2011–2012, Texas Instruments Incorporated
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bq24163, bq24168
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SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
TYPICAL CHARACTERISTICS (continued)
IBATSHRT vs. Battery Voltage
0.055
IBATSHRT (A)
0.054
0.053
0.052
0.051
0.05
0
0.5
1
1.5
2
Battery Voltage (V)
2.5
3
G009
Figure 21.
DETAILED DESCRIPTION
The bq24160/bq24161/bq24163/bq24168 are highly integrated single cell Li-Ion battery chargers and system
power path management devices targeted for space-limited, portable applications with high capacity batteries.
The dual-input, single-cell charger operates from either a USB port or alternate power source (i.e. wall adapter or
wireless power input) for a versatile solution.
The power path management feature allows the bq2416x to power the system from a high efficiency DC-to-DC
converter while simultaneously and independently charging the battery. The charger monitors the battery current
at all times and reduces the charge current when the system load requires current above the input current limit.
This allows proper charge termination and enables the system to run with a defective or absent battery pack.
Additionally, this enables instant system turn-on even with a totally discharged battery or no battery. The powerpath management architecture also permits the battery to supplement the system current requirements when the
adapter cannot deliver the peak system currents. This enables the use of a smaller adapter. The 2.5 A current
capability allows for GSM phone calls as soon as the adapter is plugged in regardless of the battery voltage. The
charge parameters are programmable using the I2C interface.
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CHARGE MODE OPERATION
Charge Profile
The internal battery MOSFET is used to charge the battery. When the battery is above the MINSYS votlage, the
the internal FET is on to maximize efficiency and the PWM converter regulates the charge current into the
battery. When battery is less than MINSYS, the SYS is regulated to VSYS(REG) and battery is charged using the
battery FET to regulate the charge current. There are 5 loops that influence the charge current:
• Constant current loop (CC)
• Constant voltage loop (CV)
• Thermal-regulation loop
• Minimum system-voltage loop (MINSYS)
• Input-voltage dynamic power-management loop (VIN-DPM)
During the charging process, all five loops are enabled and the one that is dominant takes control. The bq2416x
supports a precision Li-Ion or Li-Polymer charging system for single-cell applications. The Dynamic Power Path
Management (DPPM) feature regulates the system voltage to a minimum of VMINSYS, so that startup is enabled
even for a missing or deeply discharged battery. Figure 22 shows a typical charge profile including the minimum
system output voltage feature.
Precharge
Phase
Current Regulation
Phase
Voltage Regulation
Phase
Regulation
voltage
Charge Current
Regulation
Threshold
System Voltage
VSYS
V BATSHORT
Battery
Voltage
Charge Current
Termination
Current
Threshold
I BATSHORT
50mA Precharge to
Close Pack Protector
Linear Charge
to Maintain
Minimum
System
Voltage
Battery
FET
is OFF
Battery FET is ON
Figure 22. Typical bq2416x Charging Profile
PWM Controller in Charge Mode
The bq2416x provides an integrated, fixed-frequency 1.5MHz voltage-mode controller to power the system and
supply the charge current. The voltage loop is internally compensated and provides enough phase margin for
stable operation, allowing the use of small ceramic capacitors with very low ESR.
The input scheme for the bq2416x prevents battery discharge when the supply voltages are lower than VBAT
and also isolates the two inputs from each other. The high-side N-MOSFET (Q1/Q2) switches to control the
power delivered to the output. The DRV LDO provides a supply for the gate drive for the low side MOSFET,
while a bootstrap circuit (BST) with an external bootstrap capacitor is used to boost up the gate drive voltage for
Q1 and Q2.
16
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Both inputs are protected by a cycle-by-cycle current limit that is sensed through the high-side MOSFETs for Q1
and Q2. The threshold for the current limit is set to a nominal 5A peak current. The inputs also utilize an input
current limit that limits the current from the power source.
Battery Charging Process
When the battery is deeply discharged or shorted (VBAT < VBATSHRT), the bq2416x applies IBATSHRT to close the
pack protector switch and bring the battery voltage up to acceptable charging levels. During this time, the battery
FET is linearly regulated and the system output is regulated to VSYS(REG). Once the battery rises above VBATSHRT,
the charge current is regulated to the value set in the I2C register. The battery FET is linearly regulated to
maintain the system voltage at VSYS(REG). Under normal conditions, the time spent in this region is a very short
percentage of the total charging time, so the linear regulation of the charge current does not affect the overall
charging efficiency for very long. If the die temperature does rise, the thermal regulation circuit reduces the
charge current to maintain a die temperature less than 120°C. If the current limit for the SYS output is reached
(limited by the input current limit, or VIN_DPM), the SYS output drops to the VMINSYS output voltage. When this
happens, the charge current is reduced to provide the system with all the current that is needed while
maintaining the minimum system voltage. If the charge current is reduced to 0mA, pulling further current from
SYS causes the output to fall to the battery voltage and enter supplement mode. (See the Dynamic Power Path
Management section for more details.)
Once the battery is charged enough so that the system voltage begins to rise above VSYS(REG), the battery FET is
turned on fully and the battery is charged with the full programmed charge current set by the I2C interface,
ICHARGE. The slew rate for the fast-charge current is controlled to minimize current and voltage overshoot during
transients. The charge current is regulated to ICHARGE until the battery is charged to the regulation voltage. Once
the battery voltage is close to the regulation voltage, VBATREG, the charge current is tapered down as shown in
Figure 22 while the SYS output remains connected to the battery. The voltage-regulation feedback occurs by
monitoring the battery-pack voltage between the BAT and PGND pins. The bq2416x is a fixed single-cell voltage
version, with adjustable regulation voltage (3.5V to 4.44V), programmed using the I2C interface.
The bq2416x monitors the charging current during the voltage-regulation phase. Once the termination threshold,
ITERM, is detected and the battery voltage is above the recharge threshold, the bq2416x terminates charge and
turns off the battery charging FET. The system output is regulated to the VSYS(REG) and supports the full current
available from the input and the battery supplement mode is available. (See the Dynamic Power Path
Management section for more details.) The termination current level is programmable. To disable the charge
current termination, the host sets the charge termination bit (TE) of charge control register to 0, refer to I2C
section for details.
A new charge cycle is initiated when one of the following conditions is detected:
1. The battery voltage falls below the VBATREG-VRCH threshold.
2. VSUPPLY toggle
3. CE bit toggle or RESET bit is set
4. HI-Z bit toggle
Dynamic Power Path Management (DPPM)
The bq2416x features a SYS output that powers the external system load connected to the battery. This output is
active whenever a source is connected to IN, USB or BAT. The following sections discuss the behavior of SYS
with a source connected to the supply or a battery source only.
Input Source Connected
When a valid input source is connected, the buck converter turns on to power the load on SYS. The STAT/INT
pin outputs a 128µs interrupt pulse to alert the host that an input has been connected. The FAULT bits indicate a
normal condition, and the Supply Status register indicates that a new supply is connected. The CE bit (bit 1) in
the control register (0x02) indicates whether a charge cycle is initiated. By default, the bq2416x (CE=0) enables
a charge cycle when a valid input source is connected. When the CE bit is '1' and a valid input source is
connected, the battery FET is turned off and the SYS output is regulated to the VSYS(REG) programmed by the
VBATREG threshold in the I2C register. A charge cycle is initiated when the CE bit is written to a 0 value (cleared).
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When the CE bit is a 0 and a valid source is connected to IN or USB, the buck converter starts up and a charge
cycle is initiated. When VBAT is high enough that VSYS > VSYS(REG), the battery FET is turned on and the SYS
output is connected to BAT. If the SYS voltage falls to VSYS(REG), it is regulated to that point to maintain the
system output even with a deeply discharged or absent battery. In this mode, the SYS output voltage is regulated
by the buck converter and the battery FET linearly regulates the charge current into the battery. The current from
the supply is shared between charging the battery and powering the system load at SYS. The dynamic powerpath management (DPPM) circuitry of the bq2416x monitors the current limits continuously, and if the SYS
voltage falls to the VMINSYS voltage, it adjusts charge current to maintain the minimum system voltage and supply
the load on SYS. If the charge current is reduced to zero and the load increases further, the bq2416x enters
battery-supplement mode. During supplement mode, the battery FET is turned on and the battery supplements
the system load.
2000
mA
1800 mA
ISYS
800 mA
0 mA
1500
IIN
mA
~850 mA
0mA
1A
IBAT
0mA
-200 mA
VSYS(REG)
VMINSYS
DPPM loop active
VOUT
~3.1V
Supplement
Mode
Figure 23. Example DPPM Response (VSupply=5V, VBAT = 3.1V, 1.5A Input current limit)
VBAT(REG) should never be programmed less than VBAT. If the battery is ever 5% above the regulation threshold,
the battery OVP circuit shuts the PWM converter off and the battery FET is turned on to discharge the battery to
safe operating levels. Battery OVP errors are reported in the I2C status registers.
Battery Only Connected
When a battery voltage less than VBATUVLO is connected with no input source, the battery FET is turned on similar
to supplement mode. In this mode, the current is not regulated; however, there is a short circuit current limit. If
the short circuit limit is reached, the battery FET is turned off for the deglitch time. After the deglitch time, the
battery FET is turned on to test and see if the short has been removed. If it has not, the FET turns off and the
process repeats until the short is removed. This process is to protect the internal FET from over current. If an
external FET is used for discharge, the body diode prevents the load on SYS from being disconnected from the
battery. If the battery voltage is less than VBATUVLO, the battery FET (Q6) remains off and BAT is high-impedance.
This prevents further discharging of deeply-discharged batteries.
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Battery Discharge FET (BGATE)
The bq2416x contains a MOSFET driver to drive the gate of an external discharge FET between the battery and
the system output. This external FET provides a low impedance path when supplying the system from the
battery. Connect BGATE to the gate of the external discharge MOSFET. BGATE is on under the following
conditions:
1. No input supply connected.
2. HZ_MODE = 1
3. CD pin connected high
DEFAULT Mode
DEFAULT mode is used when I2C communication is not available. DEFAULT mode is entered in the following
situations:
1. When the charger is enabled and VBAT< VBATGD before I2C communication is established
2. When the watchdog timer expires without a reset from the I2C interface and the safety timer has not expired.
3. When the device comes out of any fault condition (sleep mode, OVP, faulty adapter mode, etc.) before I2C
communication is established
In DEFAULT mode, the I2C registers are reset to the default values. The 27-minute safety timer (no timer for
bq24168) is reset and starts when DEFAULT mode is entered. The default value for VBATREG is 3.6V, and the
default value for ICHARGE is 1A. The input current limit for the IN input is set to 1.5A. The input current limit for the
USB input is determined by the D+/D– detection (bq24160/3) or PSEL (bq24161/8). PSEL and D+/D– detection
have no effect on the IN input. Default mode is exited by programming the I2C interface. Once I2C
communication is established, PSEL has no effect on the USB input. Note that if termination is enabled and
charging has terminated, a new charge cycle is NOT initiated when entering DEFAULT mode.
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Safety Timer and Watchdog Timer (bq24160/ bq24161/ bq24163 only)
At the beginning of charging process, the bq24160/1/3 starts the safety timer. This timer is active during the
entire charging process. If charging has not terminated before the safety timer expires, charging is halted and the
CE bit is written to a “1”. The length of the safety timer is selectable using the I2C interface. A single 128μs pulse
is sent on the STAT and INT outputs and the STATx bits of the status registers are updated in the I2C. In
DEFAULT mode, the safety timer can be reset and a new charge initiated by removing/inserting the input supply
or toggling the CD pin. In HOST mode, the CE bit is set to a '1' when the safety timer expires. The CE bit must
be cleared to a '0' in order to resume charging and clear the safety timer fault. The safety timer duration is
selectable using the TMR_X bits in the Safety Timer Register/ NTC Monitor register. Changing the safety timer
duration resets the safety timer. This function prevents continuous charging of a defective battery.
In addition to the safety timer, the bq24160/1/3 contain a watchdog timer that monitors the host through the I2C
interface. Once a read/write is performed on the I2C interface, a 30-second timer (tWATCHDOG) is started. The 30second timer is reset by the host using the I2C interface. This is done by writing a “1” to the reset bit (TMR_RST)
in the control register. The TMR_RST bit is automatically set to “0” when the 30-second timer is reset. This
process continues until the battery is fully charged or the safety timer expires. If the 30-second timer expires, the
IC enters DEFAULT mode where the default register values are loaded, the safety timer restarts at 27 minutes
and charging continues. The I2C may be accessed again to reinitialize the desired values and restart the
watchdog timer. The watchdog timer flow chart is shown in Figure 24.
Start Safety Timer
Safety timer expired?
Yes
Safety timer
fault
No
Charge Done?
ICHG < ITERM
Yes
STAT = Hi
Update STAT
bits
Yes
STAT = Hi
Update STAT
bits
Charging suspended
Enter suspended
mode
Fault indicated in
STAT registers
No
No
I2C Read/Write
performed?
Yes
Start 30 second
watchdog timer
Charge Done?
ICHG < ITERM
Reset 30 second
watchdog timer
No
Yes
Safety timer
fault
Safety timer expired?
No
Charging suspended
Fault indicated in
STAT registers
No
30s timer expired?
Yes
No
Yes
Received SW watchdog
RESET?
Reset to default
values in I2C
register
Restart 27min
safety timer
Figure 24. The Watchdog Timer Flow Chart for bq2416x
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D+/D– Based Adapter Detection for the USB Input (D+/D–, bq24160/3)
The bq24160/3 contain a D+/D– based adapter detection circuit that is used to program the input current limit for
the USB input during DEFAULT mode. D+/D– detection is only performed in DEFAULT mode unless forced by
the D+/D–_EN bit in host mode.
By default the USB input current limit is set to 100mA. When USB is asserted the bq24160/3 performs a charger
source identification to determine if it is connected to an SDP (USB port) or CDP/DCP (dedicated charger). When
the detection is initated, the first step is the connection detection as described in BC1.2. This step detects when
the D+/D- lines are connected to the bq24160/3. Once this connection is made, the circuit moves to the Primary
Detection. If the connection detection has not completed within 500ms, the D+/D- detection selects 100mA for
the unknown input source.
The primary detection complies with the method described in BC1.2. During primary detection, the D+/D- lines
are tested to determine if the port is an SDP or CDP/DCP. If a CDP/DCP is detected the input current limit is
increased to 1.5A, if an SDP is detected the current limit remains at 100mA, until changed via the I2C interface.
Secondary detection is not performed.
Automatic detection is performed only if VD+ and VD– are less than 0.6V to avoid interfering with the USB
transceiver which may also perform D+/D– detection when the system is running normally. However, D+/D– can
be initiated at any time by the host by setting the D+/D– EN bit in the Control/Battery Voltage Register to 1. After
detection is complete the D+/D– EN bit is automatically reset to 0 and the detection circuitry is disconnected from
the D+/D– pins to avoid interference with USB data transfer.
When a command is written to change the input current limit in the I2C, this overrides the current limit selected by
D+/D– detection. D+/D– detection has no effect on the IN input.
USB Input Current Limit Selector Input (PSEL, bq24161/8 only)
The bq24161/8 contains a PSEL input that is used to program the input current limit for USB during DEFAULT
mode. Drive PSEL high to indicate that a USB source is connected to the USB input and program the 100mA
current limit for USB. Drive PSEL low to indicate that an AC Adapter is connected to the USB input. When PSEL
is low, the IC starts up with a 1.5A current limit for USB. PSEL has no effect on the IN input. Once an I2C write is
done, the PSEL has no effect on the input current limit until the watchdog timer expires.
Hardware Chip Disable Input (CD)
The bq2416x contains a CD input that is used to disable the IC and place the bq2416x into high-impedance
mode. Drive CD low to enable charge and enter normal operation. Drive CD high to disable charge and place the
bq2416x into high-impedance mode. Driving CD high during DEFAULT mode resets the safety timer. Driving CD
high during HOST mode resets the safety timer and places the bq2416x into high impedance mode. The CD pin
has precedence over the I2C control.
LDO Output (DRV)
The bq2416x contains a linear regulator (DRV) that is used to supply the internal MOSFET drivers and other
circuitry. Additionally, DRV supplies up to 10mA external loads to power the STAT LED or the USB transceiver
circuitry. The maximum value of the DRV output is 5.45V; ideal for protecting voltage sensitive USB circuits from
high voltage fluctuations in the supply. The LDO is on whenever a supply is connected to the IN or USB inputs of
the bq2416x. The DRV is disabled under the following conditions:
1. VSUPPLY < UVLO
2. VSUPPLY < VSLP
3. Thermal Shutdown
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External NTC Monitoring (TS)
The I2C interface allows the user to easily implement the JEITA standard for systems where the battery pack
thermistor is monitored by the host. Additionally, the bq2416x provides a flexible, voltage based TS input for
monitoring the battery pack NTC thermistor. The voltage at TS is monitored to determine that the battery is at a
safe temperature during charging. The bq24160/3/8 enables the user to easily implement the JEITA standard for
charging temperature while the bq24161 only monitors the hot and cold cutoff temperatures and leaves the
JEITA control to the host. The JEITA specification is shown in.
1°C
0.5°C
Portion of spec not covered by TS
Implementation on bq24160
4.25 V
4.15 V
4.1 V
T1
(0°C)
T2
(10°C)
T3
T4
(45°C) (50°C)
T5
(60°C)
Figure 25. Charge Current During TS Conditions
To satisfy the JEITA requirements, four temperature thresholds are monitored; the cold battery threshold (TNTC <
0°C), the cool battery threshold (0°C < TNTC < 10°C), the warm battery threshold (45°C < TNTC <L 60°C) and the
hot battery threshold (TNTC > 60°C). These temperatures correspond to the VCOLD, VCOOL, VWARM, and VHOT
thresholds. Charging is suspended and timers are suspended when VTS < VHOT or VTS > VCOLD. When VWARM <
VTS < VHOT, the battery regulation voltage is reduced by 140mV from the programmed regulation threshold.
When VCOLD < VTS < VCOOL, the charging current is reduced to half of the programmed charge current.
The TS function is voltage based for maximum flexibility. Connect a resistor divider from DRV to GND with TS
connected to the center tap to set the threshold. The connections are shown in Figure 31. The resistor values are
calculated using the following equations:
é 1
1 ù
VDRV ´ RCOLD ´ RHOT ´ ê
ú
ë VCOLD VHOT û
RLO =
éV
ù
é V
ù
RHOT ´ ê DRV - 1ú - RCOLD ´ ê DRV - 1ú
V
V
ë HOT
û
ë COLD
û
(1)
VDRV
-1
VCOLD
RHI =
1
1
+
RLO RCOLD
(2)
Where:
VCOLD = 0.60 × VDRV
VHOT = 0.30 × VDRV
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Where RHOT is the NTC resistance at the hot temperature and RCOLD is the NTC resistance at cold temperature.
For the bq24160/3/8, the WARM and COOL thresholds are not independently programmable. The COOL and
WARM NTC resistances for a selected resistor divider are calculated using the following equations:
RLO ´ 0.564 ´ RHI
RCOOL =
RLO - RLO ´ 0.564 - RHI ´ 0.564
(3)
RLO ´ 0.383 ´ RHI
RW ARM =
RLO - RLO ´ 0.383 - RHI ´ 0.383
(4)
VBAT(REG) 1 x Charge/
DISABLE -140 mV 0.5 x Charge
TS COLD
TS COOL
VDRV
+
+
TS WARM +
VDRV
TS HOT
RHI
+
TS
PACK+
TEMP
bq2416x
RLO
PACK-
Figure 26. TS Circuit
Thermal Regulation and Protection
During the charging process, to prevent chip overheating, the bq2416x monitors the junction temperature, TJ, of
the die and begins to taper down the charge current once TJ reaches the thermal regulation threshold, TREG. The
charge current is reduced to zero when the junction temperature increases about 10°C above TREG. Once the
charge current is reduced, the system current is reduced while the battery supplements the load to supply the
system. This may cause a thermal shutdown of the bq2416x if the die temperature rises too high. At any state, if
TJ exceeds TSHTDWN, the bq2416x suspends charging and disables the buck converter. During thermal shutdown
mode, the buck converter is turned off, all timers are suspended, and a single 128μs pulse is sent on the STAT
and INT outputs and the STATx and FAULT_x bits of the status registers are updated in the I2C. A new charging
cycle begins when TJ falls below TSHTDWN by approximately 10°C.
Input Voltage Protection in Charge Mode
Sleep Mode
The bq2416x enters the low-power sleep mode if the voltage on VSUPPLY falls below the sleep-mode entry
threshold, VBAT+VSLP, and VSUPPLY is higher than the undervoltage lockout threshold, VUVLO. This feature
prevents draining the battery during the absence of VSUPPLY. When VSUPPLY < VBAT+ VSLP, the bq2416x turns off
the PWM converter, turns the battery FET on and drives BGATE to GND, sends a single 128μs pulse on the
STAT and INT outputs and updates the STATx and FAULT_x bits in the status registers. Once VSUPPLY > VBAT+
VSLP, the STATx and FAULT_x bits are cleared and the device initiates a new charge cycle.
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Input Voltage Based DPM
During normal charging process, if the input power source is not able to support the programmed or default
charging current, the supply voltage decreases. Once the supply drops to VIN_DPM (default 4.2V for both inputs),
the input current limit is reduced to prevent further supply droop. When the IC enters this mode, the charge
current is lower than the set value and the DPM_STATUS bit is set (Bit 5 in Register 05H). This feature provides
IC compatibility with adapters with different current capabilities without a hardware change. Figure 27 shows the
VIN–DPM behavior to a current-limited source. In this figure the input source has a 750mA current limit and the
charging is set to 750mA. The SYS load is then increased to 1.2A.
Adapter Voltage Falls due
to Adapter Current Limit
VIN
5 V Adapter
rated for 750 mA
Input Current Reduced by VINDPM function
to Prevent Adapter from Crashing
IIN
VSYS
750 mA Charging
750 mA Charging
IBAT
Supplement Mode
1.2 A Load Step
ISYS
Figure 27. bq24160 VIN-DPM
Bad Source Detection
When a source is connected to IN or USB, the bq2416x runs a Bad Source Detection procedure to determine if
the source is strong enough to provide some current to charge the battery. A current sink is turned on (30mA for
USB input, 75mA for the IN input) for 32ms. If the source is valid after the 32ms (VBADSOURCE < VSUPPLY < VOVP),
the buck converter starts up and normal operation continues. If the supply voltage falls below VBAD_SOURCE during
the detection, the current sink shuts off for two seconds and then retries, a single 128μs pulse is sent on the
STAT and INT outputs and the STATx and FAULT_x bits of the status registers and the battery/supply status
registers are updated. The detection circuits retry continuously until either a new source is connected to the other
input or a valid source is detected after the detection time. If during normal operation the source falls to
VBAD_SOURCE, the bq2416x turns off the PWM converter, turns the battery FET on, sends a single 128μs pulse is
sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers, and the
battery/supply status registers are updated. Once a good source is detected, the STATx and FAULT_x bits are
cleared and the device returns to normal operation.
If two supplies are connected, the supply with precedence is checked first. If the supply detection fails once, the
device switches to the other supply for two seconds and then retries. This allows the priority supply to settle if the
connection was jittery or the supply ramp was too slow to pass detection. If the priority supply fails the detection
a second time, it is locked out and lower priority supply is used. Once the bad supply is locked out, it remains
locked out until the supply voltage falls below UVLO. This prevents continuously switching between a weak
supply and a good supply.
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Input Overvoltage Protection
The built-in input overvoltage protection to protect the device and other downstream components against
damage from overvoltage on the input supply (Voltage from VUSB or VIN to PGND). During normal operation, if
VSUPPLY > VOVP, the bq2416x turns off the PWM converter, turns the battery FET and BGATE on, sends a single
128μs pulse is sent on the STAT and INT outputs and the STATx and FAULT_x bits of the status registers and
the battery/supply status registers are updated. Once the OVP fault is removed, the STATx and FAULT_x bits
are cleared and the device returns to normal operation.
To allow operation with some unregulated adapters, the OVP circuit is not active during Bad Source Detection.
This provides some time for the current sink to pull the unregulated adapter down into an acceptable range. If the
adapter voltage is high at the end of the detection, the startup of the PWM converter does not occur. The OVP
circuit is active during normal operation, so if the system standby current plus the charge current is not enough to
pull down the source, operation is suspended.
Charge Status Outputs (STAT, INT)
The STAT output is used to indicate operation conditions for bq2416x. STAT is pulled low during charging when
EN_STAT bit in the control register (0x02h) is set to “1”. When charge is complete or disabled, STAT is high
impedance. When a fault occurs, a 128-µs pulse (interrupt) is sent out to notify the host. The status of STAT
during different operation conditions is summarized in Table 1. STAT drives an LED for visual indication or can
be connected to the logic rail for host communication. The EN_STAT bit in the control register (00H) is used to
enable/disable the charge status for STAT. The interrupt pulses are unaffected by EN_STAT and will always be
shown. The INT output is identical to STAT and is used to interface with a low voltage host processor.
Table 1. STAT Pin Summary
Charge State
STAT and INT behavior
Charge in progress and EN_STAT=1
Low
Other normal conditions
High-Impedance
Status Changes: Supply Status Change (plug in or removal), safety timer fault,
watchdog expiration, sleep mode, battery temperature fault (TS), battery fault
(OVP or absent), thermal shutdown
128-µs pulse, then High Impedance
Good Battery Monitor
The bq2416x contains a good battery monitor circuit that places the bq2416x into high-z mode if the battery
voltage is above the BATGD threshold while in DEFAULT mode. This function is used to enable compliance to
the battery charging standard that prevents charging from an un-enumerated USB host while the battery is above
the good battery threshold. If the bq2416x is in HOST mode, it is assumed that USB host has been enumerated
and the good battery circuit has no effect on charging.
SERIAL INTERFACE DESCRIPTION
The bq2416x uses an I2C-compatible interface to program charge parameters. I2C is a 2-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines
are pulled high. All I2C-compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A
master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible
for generating the SCL signal and device addresses. The master also generates specific conditions that indicate
the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of
the master device.
The bq2416x device works as a slave and supports the following data transfer modes, as defined in the I2C Bus
Specification: standard mode (100kbps) and fast mode (400kbps). The interface adds flexibility to the battery
charging solution, enabling most functions to be programmed to new values depending on the instantaneous
application requirements. Register contents remain intact as long as battery voltage remains above 2.5V
(typical). The I2C circuitry is powered from VBUS when a supply is connected. If the VBUS supply is not
connected, the I2C circuitry is powered from the battery through BAT. The battery voltage must stay above 2.5V
with no input connected in order to maintain proper operation.
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The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the
F/S-mode in this document. The bq2416x devices only support 7-bit addressing. The device 7-bit address is
defined as ‘1101011’ (6Bh).
F/S Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 28. All I2C-compatible devices should
recognize a start condition.
DATA
CLK
S
P
START Condition
STOP Condition
Figure 28. START and STOP Condition
The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 29). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 30) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
DATA
CLK
Data Line
Stable
Data Valid
Chang
of Data
Allowed
Figure 29. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 31). This releases the bus and stops the communication
link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section result in FFh being read out.
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Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
Figure 30. Acknowledge on the I2C Bus
Recognize START or
REPRATED START
Condition
Recognize STOP or
REPRATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
Acknowledgment
Signal From Slave
MSB
Sr
Address
R/W
SCL
S
or
Sr
ACK
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
Figure 31. Bus Protocol
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REGISTER DESCRIPTION
Status/Control Register (READ/WRITE)
Memory location: 00, Reset state: 0xxx 0xxx
BIT
NAME
Read/Write FUNCTION
B7 (MSB)
TMR_RST
Read/Write
Write: TMR_RST function, write “1” to reset the watchdog timer (auto clear)
Read: Always 0
(bq24160/1/3 only)
B6
STAT_2
Read only
B5
STAT_1
Read only
B4
STAT_0
Read only
000001010011100101110111-
B3
SUPPLY_SEL
Read/Write
0-IN has precedence when both supplies are connected
1-USB has precedence when both supplies are connected (default 0)
B2
FAULT_2
Read only
B1
FAULT_1
Read only
B0 (LSB)
FAULT_0
Read only
000-Normal
001- Thermal Shutdown
010- Battery Temperature Fault
011- Watchdog Timer Expired (bq24160/1/3 only)
100- Safety Timer Expired (bq24160/1/3 only)
101- IN Supply Fault
110- USB Supply Fault
111- Battery Fault
No Valid Source Detected
IN Ready (shows preferred source when both connected)
USB Ready (shows preferred source when both connected)
Charging from IN
Charging from USB
Charge Done
NA
Fault
SUPPLY_SEL Bit (Supply Precedence Selector)
The SUPPLY_SEL bit selects which supply has precedence when both supplies are present. In cases
where both supplies are connected, they must remain isolated from each other which means only one
is allowed to charge the battery. Write a “1” to SUPPLY_SEL to select the USB input to have
precedence. Write a “0” to select the IN input.
Battery/ Supply Status Register (READ/WRITE)
Memory location: 01, Reset state: xxxx 0xxx
BIT
NAME
Read/Write
FUNCTION
B7 (MSB)
INSTAT1
Read Only
B6
INSTAT0
Read Only
00-Normal
01-Supply OVP
10-Weak Source Connected (No Charging)
11- VIN<VUVLO
B5
USBSTAT1
Read Only
B4
USBSTAT0
Read Only
B3
OTG_LOCK
Read/Write
0 – No OTG supply present. Use USB input as normal.
1 – OTG supply present. Lockout USB input for charging.
(default 0)
B2
BATSTAT1
Read Only
B1
BATSTAT0
Read Only
00-Battery Present and Normal
01-Battery OVP
10-Battery Not Present
11- NA
B0 (LSB)
EN_NOBATOP
Read/ Write
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00-Normal
01-Supply OVP
01-Weak Source Connected (No Charging)
11- VUSB<VUVLO
0-Normal Operation
1-Enables No Battery Operation when termination is disabled (default 0)
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SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
OTG_LOCK Bit (USB Lockout)
The OTG_LOCK bit is used to prevent any charging from USB input regardless of the SUPPLY_SEL
bit and IN supply status. For systems using OTG supplies, it is not desirable to charge from an OTG
source. Doing so would mean draining the battery by allowing it to effectively charge itself. Write a “1”
to OTG_LOCK to lock out the USB input. Write a “0” to OTG_LOCK to return to normal operation.
During OTG lock, the USB input is ignored and DRV does not come up. The watchdog timer must be
reset while in USB_LOCK to maintain the USB lockout state. This prevents the USB input from being
permanently locked out for cases where the host loses I2C communication with OTG_LOCK set (i.e.,
discharged battery from OTG operation). See the Safety Timer and Watchdog Timer section for more
details.
EN_NOBATOP (No Battery Operation with Termination Disabled)
The EN_NOBATOP bit is used to enable operation when termination is disabled and no battery is
connected. This is useful for cases where the PA is connected to the BAT pin and it desired to do a
GSM calibration in the factory. For this application, the TE bit (Bit 2 in Register 0x02h) should be set to
a “0” to disable termination and the EN_NOBATOP should be set to a “1”. This feature should not be
used during normal operation as it disables the BATOVP and the reverse boost protection circuits.
Control Register (READ/WRITE)
Memory location: 02, Reset state: 1000 1100
BIT
NAME
Read/Write
B7 (MSB)
RESET
Write only
Write: 1 – Reset all registers to default values
0 – No effect
Read: always get “1”
B6
IUSB_LIMIT_2
Read/Write
B5
IUSB_LIMIT_1
Read/Write
B4
IUSB_LIMIT _0
Read/Write
000 – USB2.0 host with 100mA current limit
001 – USB3.0 host with 150mA current limit
010 – USB2.0 host with 500mA current limit
011 – USB host/charger with 800mA current limit
100 – USB3.0 host with 900mA current limit
101 – USB host/charger with 1500mA current limit
110–111 – NA (default 000 (1))
B3
EN_STAT
Read/Write
1 – Enable STAT output to show charge status,
0-Disable STAT output for charge status. Fault interrupts are still show even when
EN_STAT = 0. (default 1)
B2
TE
Read/Write
1 – Enable charge current termination,
0-Disable charge current termination (default 1)
B1
CE
Read/Write
1 – Charging is disabled
0 – Charging enabled (default 0)
B0 (LSB)
HZ_MODE
Read/Write
1 – High impedance mode
0 – Not high impedance mode (default 0)
(1)
FUNCTION
When in DEFAULT mode, the D+/D– (bq24160) or PSEL (bq24161/8) inputs determine the input current limit for the USB input.
RESET Bit
The RESET bit in the control register (0x02h) is used to reset all the charge parameters. Write “1” to
RESET bit to reset all the registers to default values and place the bq2416x into DEFAULT mode and
turn off the watchdog timer. The RESET bit is automatically cleared to zero once the bq2416x enters
DEFAULT mode.
CE Bit (Charge Enable)
The CE bit in the control register (0x02h) is used to disable or enable the charge process. A low logic
level (0) on this bit enables the charge and a high logic level (1) disables the charge. When charge is
disabled, the SYS output regulates to VSYS(REG) and battery is disconnected from the SYS.
Supplement mode is still available if the system load demands cannot be met by the supply.
Copyright © 2011–2012, Texas Instruments Incorporated
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29
bq24160, bq24161
bq24163, bq24168
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
www.ti.com
HZ_MODE Bit (High Impedance Mode Enable)
The HZ_MODE bit in the control register (0x02h) is used to disable or enable the high impedance
mode. A low logic level (0) on this bit enables the IC and a high logic level (1) puts the IC in a low
quiescent current state called high impedance mode. When in high impedance mode, the converter is
off and the battery FET and BGATE are on. The load on SYS is supplied by the battery.
Control/Battery Voltage Register (READ/WRITE)
Memory location: 03, Reset state: 0001 0100
•
BIT
NAME
Read/Write
FUNCTION
B7 (MSB)
VBREG5
Read/Write
Battery Regulation Voltage: 640 mV (default 0)
B6
VBREG4
Read/Write
Battery Regulation Voltage: 320 mV (default 0)
B5
VBREG3
Read/Write
Battery Regulation Voltage: 160 mV (default 0)
B4
VBREG2
Read/Write
Battery Regulation Voltage: 80 mV (default 1)
B3
VBREG1
Read/Write
Battery Regulation Voltage: 40 mV (default 0)
B2
VBREG0
Read/Write
Battery Regulation Voltage: 20 mV (default 1)
B1
IINLIMIT
Read/Write
Input Limit for IN input0 – 1.5A
1 – 2.5A (default 0)
B0 (LSB)
D+/D–_EN
Read/Write
0 – Normal state, D+/D- Detection done
1 – Force D+/D– Detection. Returns to “0” after detection is done. (default 0)
Charge voltage range is 3.5V–4.44V with the offset of 3.5V and step of 20mV (default 3.6V).
Vender/Part/Revision Register (READ only)
Memory location: 04, Reset state: 0100 0000
30
BIT
NAME
Read/Write
B7 (MSB)
Vender2
Read only
Vender Code: bit 2 (default 0)
B6
Vender1
Read only
Vender Code: bit 1 (default 1)
B5
Vender0
Read only
Vender Code: bit 0 (default 0)
B4
PN1
Read only
B3
PN0
Read only
For I2C Address 6Bh:
00: bq2416x
01–11: Future product spins
B2
Revision2
Read only
B1
Revision1
Read only
B0 (LSB)
Revision0
Read only
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FUNCTION
000: Revision 1.0
001: Revision 1.1
010: Revision 2.0
011: Revision 2.1
100: Revision 2.2
101: Revision 2.3
110-111: Future Revisions
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): bq24160 bq24161 bq24163 bq24168
bq24160, bq24161
bq24163, bq24168
www.ti.com
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
Battery Termination/Fast Charge Current Register (READ/WRITE)
Memory location: 05, Reset state: 0011 0010
•
•
BIT
NAME
Read/Write
FUNCTION
B7 (MSB)
ICHRG4
Read/Write
Charge current: 1200mA – (default 0)
B6
ICHRG3
Read/Write
Charge current: 600mA – (default 0)
B5
ICHRG2
Read/Write
Charge current: 300mA – (default 1)
B4
ICHRG1
Read/Write
Charge current: 150mA – (default 1)
B3
ICHRG0
Read/Write
Charge current: 75 mA (default 0)
B2
ITERM2
Read/Write
Termination current sense voltage: 200mA (default 0)
B1
ITERM1
Read/Write
Termination current sense voltage: 100mA (default 1)
B0 (LSB)
ITERM0
Read/Write
Termination current sense voltage: 50mA (default 0)
Charge current sense offset is 550mA and default charge current is 1000mA.
Termination threshold offset is 50mA and default termination current is 150mA
VIN-DPM Voltage/ DPPM Status Register
Memory location: 06, Reset state: xx00 0000
•
BIT
NAME
Read/Write
FUNCTION
B7(MSB)
MINSYS_STATUS
Read Only
1 – Minimum System Voltage mode is active (low battery condition)
0 – Minimum System Voltage mode is not active
B6
DPM_STATUS
Read Only
1 – VIN-DPM mode is active
0 – VIN-DPM mode is not active
B5
VINDPM2(USB)
Read/Write
USB input VIN-DPM voltage: 320mV (default 0)
B4
VINDPM1(USB)
Read/Write
USB input VIN-DPM voltage: 160mV (default 0)
B3
VINDPM0(USB)
Read/Write
USB input VIN-DPM voltage: 80mV (default 0)
B2
VINDPM2(IN)
Read/Write
IN input VIN-DPM voltage: 320mV (default 0)
B1
VINDPM1(IN)
Read/Write
IN input VIN-DPM voltage: 160mV (default 0)
B0(LSB)
VINDPM0(IN)
Read/Write
IN input VIN-DPM voltage: 80mV (default 0)
VIN-DPM voltage offset is 4.20V and default VIN-DPM threshold is 4.20V.
Copyright © 2011–2012, Texas Instruments Incorporated
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31
bq24160, bq24161
bq24163, bq24168
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
www.ti.com
Safety Timer/ NTC Monitor Register (READ/WRITE)
Memory location: 07, Reset state: 1001 1xxx
BIT
NAME
Read/Write
FUNCTION
B7 (MSB)
2XTMR_EN
Read/Write
1 – Timer slowed by 2x when in thermal regulation, input current limit, VIN_DPM or
DPPM
0 – Timer not slowed at any time (default 0) (bq24160/1 only)
B6
TMR_1
Read/Write
B5
TMR_2
Read/Write
Safety Timer Time Limit –
00 – 27 minute fast charge
01 – 6 hour fast charge
10 – 9 hour fast charge
11 – Disable safety timers (default 00) (bq24160/1 only)
B4
NA
Read/Write
NA
B3
TS_EN
Read/Write
0 – TS function disabled
1 – TS function enabled (default 1)
B2
TS_FAULT1
Read only
B1
TS_FAULT0
Read only
TS Fault Mode:
00 – Normal, No TS fault
01 – TS temp < TCOLD or TS temp > THOT(Charging suspended)
10 – TCOOL > TS temp > TCOLD (Charge current reduced by half, bq24160 only)
11 – TWARM < TS temp < THOT (Charge voltage reduced by 140mV, bq24160 only)
B0 (LSB)
LOW_CHG
Read/ Write
0 – Charge current as programmed in Register 0x05
1 – Charge current is half programmed value in Register 0x05
(default 0)
2xTMR_EN Bit (2x Timer Enable)
The 2xTMR_EN bit is used to slow down the timer when charge current is reduced by the system load.
When 2xTMR_EN is a "1", the safety timer is slowed to half speed effectively doubling the timer time.
The conditions that activate the 2x timer are: Input Current Limit, VINDPM, Thermal Regulation,
LOW_CHG, BATSHRT and TS Cool. When 2xTMR_EN is a "0", the timer operates at normal speed in
all conditions.
LOW_CHG Bit (Low Charge Mode Enable)
The LOW_CHG bit is used to reduce the charge current from the programmed value. This feature is
used by systems where battery NTC is monitored by the host and requires a reduced charge current
setting or by systems that need a “preconditioning” current for low battery voltages. Write a “1” to this
bit to charge at half of the programmed charge current (bq24160/1/3/8). Write a “0” to this bit to charge
at the programmed charge current.
32
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): bq24160 bq24161 bq24163 bq24168
bq24160, bq24161
bq24163, bq24168
www.ti.com
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
APPLICATION INFORMATION
Output Inductor and Capacitor Selection Guidelines
When selecting an inductor, several attributes must be examined to find the right part for the application. First,
the inductance value should be selected. The bq2416x is designed to work with 1.5µH to 2.2µH inductors. The
chosen value will have an effect on efficiency and package size. Due to the smaller current ripple, some
efficiency gain is reached using the 2.2µH inductor, however, due to the physical size of the inductor, this may
not be a viable option. The 1.5µH inductor provides a good tradeoff between size and efficiency.
Once the inductance has been selected, the peak current must be calculated in order to choose the current
rating of the inductor. Use Equation 5 to calculate the peak current.
æ %
ö
IPEA K = ILOAD(MAX) ´ ç1+ RIPPP LE ÷
2
è
ø
(5)
The inductor selected must have a saturation current rating greater than or equal to the calculated IPEAK. Due to
the high currents possible with the bq2416x, a thermal analysis must also be done for the inductor. Many
inductors have a 40°C temperature-rise rating. The DC component of the current can cause a 40°C temperature
rise above the ambient temperature in the inductor. For this analysis, the typical load current may be used
adjusted for the duty cycle of the load transients. For example, if the application requires a 1.5A DC load with
peaks at 2.5A 20% of the time, a Δ40°C temperature rise current must be greater than 1.7A:
ITEMPRISE = ILOAD + D ´ (IPEAK - ILOAD ) = 1.5A + 0.2 × (2.5A - 1 .5A ) = 1.7A
(6)
The bq2416x provides internal loop compensation. Using this scheme, the bq2416x is stable with 10µF to 200µF
of local capacitance on the SYS output. The capacitance on the SYS rail can be higher if distributed amongst the
rail. To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 10µF and 47µF is
recommended for local bypass to SYS. A 47µF bypass capacitor is recommended for optimal transient response.
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): bq24160 bq24161 bq24163 bq24168
33
bq24160, bq24161
bq24163, bq24168
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
www.ti.com
PCB Layout Guidelines
It is important to pay special attention to the PCB layout. Figure 32 provides a sample layout for the high current
paths of the bq2416x. A list of layout guidelines follows.
IN
PMIDU USB
PMIDI
SW
PGND
PGND
BOOT
SYS
BAT
SW
SYS
Figure 32. Recommended bq2416x PCB Layout for WCSP
•
•
•
•
•
•
•
•
34
To obtain optimal performance, the power input capacitors, connected from the PMID input to PGND, must be
placed as close as possible to the bq2416x
Minimize the amount of inductance between BAT and the postive connection of the battery terminal. If a large
parasitic board inductance on BAT is expected, increase the bypass capacitance on BAT.
Place 4.7µF input capacitor as close to PMID_ pin and PGND pin as possible to make high frequency current
loop area as small as possible. Place 1µF input capacitor GNDs as close to the respective PMID cap GND
and PGND pins as possible to minimize the ground difference between the input and PMID_.
The local bypass capacitor from SYS to GND should be connected between the SYS pin and PGND of the
IC. The intent is to minimize the current path loop area from the SW pin through the LC filter and back to the
PGND pin.
Place all decoupling capacitors close to their respective IC pins and as close as to PGND (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high-current paths.
The PCB should have a ground plane (return) connected directly to the return of all components through vias
(two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components). It is
also recommended to put vias inside the PGND pads for the IC, if possible. A star ground design approach is
typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noisecoupling and ground-bounce issues. A single ground plane for this design gives good results. With this small
layout and a single ground plane, there is no ground-bounce issue, and having the components segregated
minimizes coupling between signals.
The high-current charge paths into IN, USB, BAT, SYS and from the SW pins must be sized appropriately for
the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be
connected to the ground plane to return current through the internal low-side FET.
For high-current applications, the balls for the power paths should be connected to as much copper in the
board as possible. This allows better thermal performance because the board conducts heat away from the
IC.
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): bq24160 bq24161 bq24163 bq24168
bq24160, bq24161
bq24163, bq24168
www.ti.com
SLUSAO0A – NOVEMBER 2011 – REVISED MARCH 2012
Changes from Original (November 2011) to Revision A
Page
•
Changed VBATREG - Voltage regulation accuracy .................................................................................................................. 5
•
Changed the USB Pin numbers in the YFF pachkage for bq24160/3 From: A5-A6 To: A5-A7 ......................................... 11
•
Changed Figure 3 ............................................................................................................................................................... 11
•
Changed Figure 4 ............................................................................................................................................................... 12
Copyright © 2011–2012, Texas Instruments Incorporated
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Product Folder Link(s): bq24160 bq24161 bq24163 bq24168
35
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
(Requires Login)
BQ24160RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ24160RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ24160YFFR
ACTIVE
DSBGA
YFF
49
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ24160YFFT
ACTIVE
DSBGA
YFF
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ24161YFFR
ACTIVE
DSBGA
YFF
49
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ24161YFFT
ACTIVE
DSBGA
YFF
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ24163RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ24163RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ24163YFFR
PREVIEW
DSBGA
YFF
49
3000
TBD
Call TI
Call TI
BQ24163YFFT
PREVIEW
DSBGA
YFF
49
250
TBD
Call TI
Call TI
BQ24168RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ24168RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
BQ24168YFFR
ACTIVE
DSBGA
YFF
49
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BQ24168YFFT
ACTIVE
DSBGA
YFF
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2012
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ24160RGER
Package Package Pins
Type Drawing
VQFN
RGE
24
BQ24160RGET
VQFN
RGE
BQ24160YFFR
DSBGA
YFF
BQ24160YFFT
DSBGA
BQ24161YFFR
DSBGA
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
49
3000
180.0
8.4
2.93
2.93
0.81
4.0
8.0
Q1
YFF
49
250
180.0
8.4
2.93
2.93
0.81
4.0
8.0
Q1
YFF
49
3000
180.0
8.4
2.93
2.93
0.81
4.0
8.0
Q1
BQ24161YFFT
DSBGA
YFF
49
250
180.0
8.4
2.93
2.93
0.81
4.0
8.0
Q1
BQ24163RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24163RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24168RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24168RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24168YFFR
DSBGA
YFF
49
3000
180.0
8.4
2.93
2.93
0.81
4.0
8.0
Q1
BQ24168YFFT
DSBGA
YFF
49
250
180.0
8.4
2.93
2.93
0.81
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jun-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24160RGER
VQFN
RGE
24
3000
346.0
346.0
29.0
BQ24160RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24160YFFR
DSBGA
YFF
49
3000
210.0
185.0
35.0
BQ24160YFFT
DSBGA
YFF
49
250
210.0
185.0
35.0
BQ24161YFFR
DSBGA
YFF
49
3000
210.0
185.0
35.0
BQ24161YFFT
DSBGA
YFF
49
250
210.0
185.0
35.0
BQ24163RGER
VQFN
RGE
24
3000
346.0
346.0
29.0
BQ24163RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24168RGER
VQFN
RGE
24
3000
346.0
346.0
29.0
BQ24168RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24168YFFR
DSBGA
YFF
49
3000
210.0
185.0
35.0
BQ24168YFFT
DSBGA
YFF
49
250
210.0
185.0
35.0
Pack Materials-Page 2
X: Max = 2.791 mm, Min = 2.69 mm
Y: Max = 2.791 mm, Min = 2.69 mm
IMPORTANT NOTICE
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