Cypress CYNSE70032-83BGC Network search engine Datasheet

CYNSE70032
CYNSE70032
Network Search Engine
Cypress Semiconductor Corporation
Document #: 38-02042 Rev. *E
•
3901 North First Street
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San Jose, CA 95134
•
408-943-2600
Revised May 5, 2003
CYNSE70032
TABLE OF CONTENTS
1.0 OVERVIEW ..................................................................................................................................... 9
2.0 CYNSE70032 FEATURES .............................................................................................................. 9
3.0 BLOCK DIAGRAM ........................................................................................................................ 10
4.0 FUNCTIONAL DESCRIPTION ...................................................................................................... 10
4.1
4.2
4.3
4.4
4.5
Command Bus and DQ Bus ..................................................................................................... 10
Database Entry (Data Array and Mask Array) ......................................................................... 10
Arbitration Logic ....................................................................................................................... 10
Pipeline and SRAM Control ..................................................................................................... 11
Full Logic .................................................................................................................................. 11
5.0 SIGNAL DESCRIPTIONS ............................................................................................................. 11
6.0 CLOCKS ........................................................................................................................................ 13
7.0 REGISTERS .................................................................................................................................. 13
7.1 Comparand Registers .............................................................................................................. 13
7.2 Mask Registers ........................................................................................................................ 14
7.3 Search Successful Registers (SSR[0:7]) ................................................................................. 14
8.0 COMMAND REGISTER ................................................................................................................ 14
9.0 INFORMATION REGISTER .......................................................................................................... 15
9.1 Read Burst Address Register .................................................................................................. 16
9.2 Write Burst Address Register Description ................................................................................ 16
9.3 NFA Register ........................................................................................................................... 16
10.0 NSE ARCHITECTURE AND OPERATION OVERVIEW ............................................................ 17
11.0 DATA AND MASK ADDRESSING ............................................................................................. 18
12.0 COMMANDS ............................................................................................................................... 18
12.1
12.2
12.3
12.4
Command Codes ................................................................................................................... 18
Commands and Command Parameters ................................................................................ 19
Read Command ..................................................................................................................... 19
Write Command ..................................................................................................................... 21
13.0 SEARCH COMMAND ................................................................................................................. 24
13.1 68-bit Search on Tables Configured as ×68 using a Single CYNSE70032 Device ............... 24
13.2 68-bit Search on Tables Configured as ×68 Using up to Eight CYNSE70032 Devices ......... 26
13.3 68-bit Search on Tables Configured as ×68 Using up to 31 CYNSE70032 Devices ............. 31
13.4 136-bit Search on Tables Configured as ×136 Using a Single CYNSE70032 Device ........... 45
13.5 136-bit Search on Tables Configured as ×136 Using up to Eight CYNSE70032 Devices ..... 48
13.6 136-bit Search on Tables Configured as ×136 using up to 31 CYNSE70032 Devices ......... 54
13.7 272-bit Search on Tables Configured as ×272 using a Single CYNSE70032 Device ........... 69
13.8 272-bit Search on Tables Configured as ×272 and Using
up to Eight CYNSE70032 Devices .................................................................................................. 71
13.9 272-bit Search on Tables Configured as ×272 using up to 31 CYNSE70032 Devices ......... 76
13.10 Mixed-Size Searches on Tables Configured with Different Widths Using
an CYNSE70032 Device ................................................................................................................. 91
13.11 LRAM and LDEV Description ............................................................................................... 92
13.12 Learn Command .................................................................................................................. 92
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CYNSE70032
TABLE OF CONTENTS (continued)
14.0 DEPTH-CASCADING .................................................................................................................. 96
14.1 Depth-Cascading up to Eight Devices (One Block) ............................................................... 96
14.2 Depth-Cascading up to 31 Devices (Four Blocks) ................................................................. 97
14.3 Depth-Cascading for a FULL Signal ...................................................................................... 97
15.0 SRAM ADDRESSING ................................................................................................................. 98
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Generating an SRAM BUS Address ...................................................................................... 99
SRAM PIO Access ................................................................................................................. 99
SRAM Read with a Table of One Device ............................................................................... 99
SRAM Read with a Table of up to Eight Devices ................................................................. 100
SRAM Read with a Table of up to 31 Devices ..................................................................... 103
SRAM Write with a Table of One Device ............................................................................. 106
SRAM Write with a Table of up to Eight Devices ................................................................. 107
SRAM Write with Table(s) Consisting of up to 31 Devices .................................................. 110
16.0 POWER ..................................................................................................................................... 114
16.1 The Proper Power-up Sequence ......................................................................................... 114
17.0 APPLICATION .......................................................................................................................... 114
18.0 JTAG (1149.1) TESTING .......................................................................................................... 115
19.0 ELECTRICAL SPECIFICATIONS ............................................................................................. 116
20.0 AC TIMING WAVEFORMS ....................................................................................................... 117
21.0 PINOUT DESCRIPTIONS AND PACKAGE DIAGRAMS ......................................................... 120
22.0 ORDERING INFORMATION ..................................................................................................... 124
23.0 PACKAGE DIAGRAMS ............................................................................................................ 124
Document #: 38-02042 Rev. *E
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CYNSE70032
LIST OF FIGURES
Figure 6-1. CYNSE70032 Clocks (CLK2X and PHS_L) ...................................................................... 13
Figure 7-1. Comparand Register Selection during Search and Learn Instructions ............................. 13
Figure 7-2. Addressing the Global Mask Register Array ..................................................................... 14
Figure 10-1. CYNSE70032 Database Width Configuration ................................................................. 17
Figure 10-2. Multiwidth Database Configurations ................................................................................ 18
Figure 11-1. Addressing CYNSE70032 Data and Mask Arrays .......................................................... 18
Figure 12-1. Single-Location Read Cycle Timing ................................................................................ 20
Figure 12-2. Burst Read of the Data and Mask Arrays (BLEN = 4) ..................................................... 21
Figure 12-3. Single Write Cycle Timing ............................................................................................... 22
Figure 12-4. Burst Write of the Data and Mask Arrays (BLEN = 4) ..................................................... 23
Figure 13-1. Timing Diagram for 68-bit Search in ×68 Table (One Device) ........................................ 24
Figure 13-2. Hardware Diagram for a Table with a Single Device ....................................................... 25
Figure 13-3. ×68 Table with One Device ............................................................................................. 25
Figure 13-4. Hardware Diagram for a Table with Eight Devices .......................................................... 27
Figure 13-5. Timing Diagram for 68-bit Search Device Number 0 ....................................................... 28
Figure 13-6. Timing Diagram for 68-bit Search Device Number 1 ....................................................... 29
Figure 13-7. Timing Diagram for 68-bit Search Device Number 7 (Last Device) ................................ 30
Figure 13-8. ×68 Table with Eight Devices .......................................................................................... 31
Figure 13-9. Hardware Diagram for a Table with 31 Devices .............................................................. 32
Figure 13-10. Hardware Diagram for a Block of up to Eight Devices .................................................. 33
Figure 13-11. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ............... 34
Figure 13-12. Timing Diagram for Each Device Above the Winning Device in Block Number 1 ......... 35
Figure 13-13. Timing Diagram for Globally Winning Device in Block Number 1 ................................. 36
Figure 13-14. Timing Diagram for Devices Below the Winning Device in Block Number 1 ................. 37
Figure 13-15. Timing Diagram for Devices Above the Winning Device in Block Number 2 ................ 38
Figure 13-16. Timing Diagram for Globally Winning Device in Block Number 2 ................................. 39
Figure 13-17. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................. 40
Figure 13-18. Timing Diagram for Devices Above the Winning Device in Block Number 3 ................ 41
Figure 13-19. Timing Diagram for Globally Winning Device in Block Number 3 ................................. 42
Figure 13-20. Timing Diagram for Devices Below the Winning Device in Block Number 3
(Except the Last Device [Device Number 30]) ...................................................................................... 43
Figure 13-21. Timing Diagram for Device Number 6 in Block Number 3
(Device Number 30 in Depth-Cascaded Table) .................................................................................... 44
Figure 13-22. ×68 Table with 31 Devices ............................................................................................ 45
Figure 13-23. Timing Diagram for 136-bit Search (One Device) ......................................................... 46
Figure 13-24. Hardware Diagram for a Table With One Device .......................................................... 46
Figure 13-25. ×136 Table with One Device ......................................................................................... 47
Figure 13-26. Hardware Diagram for a Table with Eight Devices ........................................................ 49
Figure 13-27. Timing Diagram for 136-bit Search Device Number 0 ................................................... 50
Figure 13-28. Timing Diagram for 136-bit Search Device Number 1 ................................................... 51
Figure 13-29. Timing Diagram for 136-bit Search Device Number 7 (Last Device) ............................ 52
Figure 13-30. ×136 Table with Eight Devices ...................................................................................... 53
Figure 13-31. Hardware Diagram for a Table with 31 Devices ............................................................ 55
Figure 13-32. Hardware Diagram for a Block of up to Eight Devices .................................................. 56
Figure 13-33. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ............... 57
Figure 13-34. Timing Diagram for Each Device Above the Winning Device in Block Number 1 ......... 58
Figure 13-35. Timing Diagram for Globally Winning Device in Block Number 1 ................................. 59
Figure 13-36. Timing Diagram for Devices Below the Winning Device in Block Number 1 ................. 60
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CYNSE70032
LIST OF FIGURES (continued)
Figure 13-37. Timing Diagram for Devices Above the Winning Device in Block Number 2 ................ 61
Figure 13-38. Timing Diagram for Globally Winning Device in Block Number 2 ................................. 62
Figure 13-39. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................. 63
Figure 13-40. Timing Diagram for Devices Above the Winning Device in Block Number 3 ................ 64
Figure 13-41. Timing Diagram for Globally Winning Device in Block Number 3 ................................. 65
Figure 13-42. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device Number 30 (the Last Device) ........................................................................................ 66
Figure 13-43. Timing Diagram for Device Number 6 in Block Number 3
(Device Number 30 in Depth-Cascaded Table) .................................................................................... 67
Figure 13-44. X136 Table with 31 Devices .......................................................................................... 68
Figure 13-45. Timing Diagram for 272-bit Search (One Device) ......................................................... 69
Figure 13-46. Hardware Diagram for a Table With One Device .......................................................... 69
Figure 13-47. X272 Table with One Device ......................................................................................... 70
Figure 13-48. Hardware Diagram for a Table with Eight Devices ........................................................ 72
Figure 13-49. Timing Diagram for 272-bit Search Device Number 0 ................................................... 73
Figure 13-50. Timing Diagram for 272-bit Search Device Number 1 ................................................... 74
Figure 13-51. Timing Diagram for 272-bit Search Device Number 7 (Last Device) ............................ 75
Figure 13-52. X272 Table with Eight Devices ...................................................................................... 76
Figure 13-53. Hardware Diagram for a Table with 31 Devices ............................................................ 77
Figure 13-54. Hardware Diagram for a Block of up to Eight Devices .................................................. 78
Figure 13-55. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) ............... 79
Figure 13-56. Timing Diagram for Each Device Above the Winning Device in Block Number 1 ......... 80
Figure 13-57. Timing Diagram for Globally Winning Device in Block Number 1 ................................. 81
Figure 13-58. Timing Diagram for Devices Below the Winning Device in Block Number 1 ................. 82
Figure 13-59. Timing Diagram for Devices Above the Winning Device in Block Number 2 ................ 83
Figure 13-60. Timing Diagram for Globally Winning Device in Block Number 2 ................................. 84
Figure 13-61. Timing Diagram for Devices Below the Winning Device in Block Number 2 ................. 85
Figure 13-62. Timing Diagram for Devices Above the Winning Device in Block Number 3 ................ 86
Figure 13-63. Timing Diagram for Globally WInning Device in Block Number 3 ................................. 87
Figure 13-64. Timing Diagram for Devices Below the Winning Device
in Block Number 3 Except Device Number 30 (the Last Device) ......................................................... 88
Figure 13-65. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table) .......... 89
Figure 13-66. X272 Table with 31 Devices .......................................................................................... 90
Figure 13-67. Timing Diagram for Mixed Search (One Device) ........................................................... 91
Figure 13-68. Multiwidth Configurations Example ............................................................................... 91
Figure 13-69. Learn Timing Diagram (TLSZ = 00) ............................................................................... 93
Figure 13-70. Learn Timing Diagram (TLSZ = 01 [Except on the Last Device]) .................................. 94
Figure 13-71. Learn Timing Diagram on Device Number 7 (TLSZ = 01) ............................................. 95
Figure 14-1. Depth-Cascading to Form a Single Block ....................................................................... 96
Figure 14-2. Depth-Cascading Four Blocks ......................................................................................... 97
Figure 14-3. FULL Generation in a Cascaded Table ........................................................................... 98
Figure 15-1. SRAM Read ACCESS (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1) ..................... 100
Figure 15-2. Table of a Block of Eight Devices .................................................................................. 101
Figure 15-3. SRAM Read Through Device Number 0 in a Block of Eight Devices ............................ 102
Figure 15-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices ......................... 103
Figure 15-5. Table of 31 Devices Made of Four Blocks ..................................................................... 104
Figure 15-6. SRAM Read Through Device Number 0 in a Bank of 31 Devices
(Device Number 0 Timing) .................................................................................................................. 105
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CYNSE70032
LIST OF FIGURES (continued)
Figure 15-7. SRAM Readthrough Device Number 0 in a Bank of 31 Devices
(Device Number 30 Timing) ................................................................................................................ 106
Figure 15-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1) ......................... 107
Figure 15-9. Table of a Block of Eight Devices .................................................................................. 108
Figure 15-10. SRAM Write Through Device Number 0 in a Block of Eight Devices .......................... 109
Figure 15-11. SRAM Write Timing for Device Number 7 in a Block of Eight Devices ....................... 110
Figure 15-12. Table of 31 Devices (Four Blocks) .............................................................................. 111
Figure 15-13. SRAM Write Through Device Number 0 in a Bank of 31 Devices (Device 0 Timing) . 112
Figure 15-14. SRAM Write Through Device Number 0 in a Bank of 31 CYNSE70032 Devices
(Device Number 30 Timing) ................................................................................................................ 113
Figure 16-1. Power-up sequence ...................................................................................................... 114
Figure 17-1. Sample Switch/Router Using the CYNSE70032 Device ............................................... 115
Figure 20-1. Input Waveform for CYNSE70032 ................................................................................ 118
Figure 20-2. Output Load for CYNSE70032 ...................................................................................... 118
Figure 20-3. 2.5 I/O Output Load Equivalent for CYNSE70032 ........................................................ 118
Figure 20-4. AC Timing Waveforms with CLK2X ............................................................................... 119
Figure 21-1. Pinout Diagram (Top View) ........................................................................................... 120
Figure 23-1. Package ........................................................................................................................ 124
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CYNSE70032
LIST OF TABLES
Table 5-1. CYNSE70032 Signal Description ....................................................................................... 11
Table 7-1. Register Overview .............................................................................................................. 13
Table 7-2. Search Successful Register Description ............................................................................14
Table 8-1. Command Register Description .......................................................................................... 14
Table 9-1. Information Register Description ........................................................................................ 15
Table 9-2. Read Burst Register Description ........................................................................................ 16
Table 9-3. Write Burst Register Description ........................................................................................ 16
Table 9-4. NFA Register ...................................................................................................................... 16
Table 10-1. Bit Position Match ............................................................................................................. 17
Table 12-1. Command Codes .............................................................................................................. 18
Table 12-2. Command Parameters ..................................................................................................... 19
Table 12-3. Read Command Parameters ............................................................................................ 19
Table 12-4. Read Address Format for Data Array, Mask Array, or SRAM .......................................... 20
Table 12-5. Read Address Format for Internal Registers .................................................................... 21
Table 12-6. Read Address Format for Data and Mask Arrays ............................................................. 21
Table 12-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write) .................... 22
Table 12-8. Write Address Format for Internal Registers .................................................................... 22
Table 12-9. Write Address Format for Data and Mask Array (Burst Write) ......................................... 23
Table 13-1. Search Latency from Instruction to SRAM Access Cycle ................................................ 26
Table 13-2. Shift of SSF and SSV from SADR .................................................................................... 26
Table 13-3. HIT/MISS Assumption ...................................................................................................... 26
Table 13-4. Search latency from Instruction to SRAM Access Cycle .................................................. 31
Table 13-5. Shift of SSF and SSV from SADR .................................................................................... 31
Table 13-6. Hit/Miss Assumption ......................................................................................................... 32
Table 13-7. Search Latency from Instruction to SRAM Access Cycle ................................................. 45
Table 13-8. Shift of SSF and SSV from SADR .................................................................................... 45
Table 13-9. Search Latency from Instruction to SRAM Access Cycle ................................................. 47
Table 13-10. Shift of SSF and SSV from SADR .................................................................................. 47
Table 13-11. Hit/Miss Assumptions ..................................................................................................... 48
Table 13-12. Search Latency from Instruction to SRAM Access Cycle ............................................... 53
Table 13-13. Shift of SSF and SSV from SADR .................................................................................. 53
Table 13-14. Hit/Miss Assumptions ..................................................................................................... 54
Table 13-15. Search Latency from Instruction to SRAM Access Cycle ............................................... 68
Table 13-16. Shift of SSF and SSV from SADR .................................................................................. 68
Table 13-17. Search Latency from Instruction to SRAM Access Cycle ............................................... 70
Table 13-18. Shift of SSF and SSV from SADR .................................................................................. 70
Table 13-19. Hit/Miss Assumptions ..................................................................................................... 71
Table 13-20. Search Latency from Instruction to SRAM Access Cycle ............................................... 76
Table 13-21. Shift of SSF and SSV from SADR .................................................................................. 76
Table 13-22. Hit/Miss Assumptions ..................................................................................................... 77
Table 13-23. Search Latency from Instruction to SRAM Access Cycle ............................................... 90
Table 13-24. Shift of SSF and SSV from SADR .................................................................................. 90
Table 13-25. SRAM Write Cycle Latency from Second Cycle of Learn Instruction ............................. 95
Table 15-1. SRAM Bus Address .......................................................................................................... 99
Table 18-1. Supported Operations .................................................................................................... 115
Table 19-1. DC Electrical Characteristics for CYNSE70032 .............................................................116
Table 19-2. Operating Conditions for CYNSE70032 ......................................................................... 116
Table 18-2. TAP Device ID Register ................................................................................................. 116
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CYNSE70032
LIST OF TABLES (continued)
Table 19-3.
Table 20-1.
Table 20-2.
Table 21-1.
Table 22-1.
Operating Range for CYNSE70032 ................................................................................ 117
AC Timing Parameters with CLK2X ............................................................................... 117
Test Conditions of CYNSE70032 ...................................................................................117
Pinout Descriptions for Pinout Diagram ..........................................................................120
Ordering Information ....................................................................................................... 124
Document #: 38-02042 Rev. *E
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CYNSE70032
1.0
Overview
Cypress Semiconductor Corporation’s (Cypress’s) CYNSE70032 network search engine (NSE) incorporates patent-pending
Associative Processing Technology™ (APT) and is designed to be a high-performance, pipelined, synchronous, 16K-entry NSE.
The CYNSE70032 database entry size can be 68, 136, or 272 bits. In the 68-bit entry mode, the size of the database is 16K
entries. In the 136-bit mode, the size of the database is 8K entries, and in the 272-bit mode, the size of the database is 4K entries.
The CYNSE70032 is configurable to support multiple databases with different entry sizes. The 36-bit entry table can be implemented using the global mask registers (GMRs) building-database size of 32K entries with a single device.
The search engine can sustain 83 million transactions per second when the database is programmed or configured as 68 or 136
bits. When the database is programmed to have an entry size of 34 or 272 bits, the search engine will perform at 41.5 million
transactions per second. The CYNSE70032 can be used to accelerate network protocols such as longest-prefix match (CIDR),
address-resolution protocol (ARP), multiprotocol label switching (MPLS), and other layer 2, 3, and 4 protocols.
This high-speed, high-capacity NSE can be deployed in a variety of networking and communications applications. The performance and features of the CYNSE70032 device make it attractive in applications such as Enterprise local-area network (LAN)
switches and routers and broadband switching and/or routing equipment supporting multiple data rates at OC-48 and beyond.
The NSE is designed to be scalable in order to support network database sizes of up to 992K entries specifically for environments
that require large network policy databases. The block diagram for the CYNSE70032 device is shown on page 10.
2.0
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•
•
•
•
•
•
•
•
•
•
•
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CYNSE70032 Features
32K 34-bit entries in a single device
16K entries in 68-bit mode, 8K entries in 136-bit mode, 4K entries in 272-bit mode
83 million transactions per second in 68- and 136-bit configurations
41.5 million transactions in 34- and 272-bit configurations
Searches any subfield in a single cycle
Synchronous pipelined operation
Up to 31 NSEs can be cascaded
When cascaded, the database entries can range to 992K 36-bit entries
Multiple width tables in a single database bank
Glueless interface to industry standard SRAMs and/or SSRAMs
Simple hardware instruction interface
IEEE 1149.1 test access port
1.8V core voltage supply
2.5/3.3V I/O voltage supply
272-pin BGA package.
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CYNSE70032
3.0
Block Diagram
Comparand Register Pairs [15:0]
Global Mask Register Pairs [7:0]
Information and Command Register
Burst Read Register
Burst Write Register
Next-free Address Register
Search Successful Index Registers [7:0]
[All registers are 68 bits wide.]
PHS_L
CLK2X
DQ[67:0]
Compare/PIO Data
RST_L
TAP
Controller
TAP
SADR[21:0]
ACK
EOT
Command
Decode
and PIO Access
Configurable as
16K x 68
8K x 136
4K x 272
Data Array
Configurable as
16K x 68
8K x 136
4K x 272
Mask Array
Pipeline
Priority Encode
Match Logic
CMD[8:0]
CMDV
Address Decode
CMDCompare/PIO Data
and
SRAM
Control
OE_L
WE_L
CE_L
ALE_L
ID[4:0]
LHO[1:0]
LHI[6:0]
Arbitration
FULI[6:0]
BHI[2:0]
Full Logic
FULL
4.0
FULO[1:0]
Logic
BHO[2:0]
SSF
SSV
Functional Description
The following subsections contain the following descriptions: command (CMD) and DQ bus (command and databus), database
entry, arbitration logic, pipeline and SRAM control, and full logic.
4.1
Command Bus and DQ Bus
CMD[8:0] carries the command and its associated parameter. DQ[67:0] is used for data transfer to and from the database entries,
which is made up of data and mask fields that are organized as data and mask arrays. The DQ bus carries the Search data (of
the data and mask arrays and internal registers) during the Search command, as well as the address and data during Read or
Write operations. The DQ bus can also carry address information for the flow-through accesses to the external SRAMs or
SSRAMs.
4.2
Database Entry (Data Array and Mask Array)
Each database entry comprises a data and a mask field. The resultant value of the entry is “1,” “0,” or “X (don’t care),” depending
on the value in the data mask bit. The on-chip priority encoder selects the first matching entry in the database that is nearest to
location 0.
4.3
Arbitration Logic
When multiple search engines are cascaded to create large databases, the data being searched is presented simultaneously to
all search engines in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the search
engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the
SRAM bus.
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CYNSE70032
4.4
Pipeline and SRAM Control
Pipeline latency is added to give enough time to a cascaded system’s arbitration logic to determine the device that will drive the
index of the matching entry on the SRAM bus. Pipeline logic adds latency to both the SRAM access cycles and the SSF and SSV
signals in order to align them to the host ASIC that receives the associated data.
4.5
Full Logic
Bit[0] in each of the 68-bit entries has a special purpose for the Learn command (0 = empty, 1 = full). When all the data entries
have bit[0] set to 1, the database asserts the FULL flag, indicating that all the search engines in the depth-cascaded array are full.
5.0
Signal Descriptions
Table 5-1 lists and describes all CYNSE70032 signals.
Table 5-1. CYNSE70032 Signal Description
Parameter
Clocks and Reset
CLK2X
Type[1]
Description
I
Master Clock. CYNSE70032 samples all the data and control pins on the positive edge
of CLK2X. All signals are driven out of the device on the rising edge of CLK2X (when
PHS_L is low).
Phase. This signal runs at half the frequency of CLK2X and generates an internal clock
from CLK2X. See Section 6.0, “Clocks” on page 13.
Reset. Driving RST_L low initializes the device to a known state.
PHS_L
I
RST_L
Command and DQ Bus
CMD[8:0]
I
I
CMDV
I
DQ[67:0]
I/O
ACK[2]
T
EOT[2]
T
SSF
T
SSV
SRAM Interface
SADR[21:0]
T
T
CE_L
T
WE_L
T
Command Bus. [1:0] specifies the command and [8:2] contains the command parameters. The descriptions of individual commands explains the details of the parameters.
The encoding of commands based on the [1:0] field are:
00: PIO Read
01: PIO Write
10: Search
11: Learn.
Command Valid. This signal qualifies the command bus:
0: No command
1: Command.
Address/Data Bus. This signal carries the Read and Write address and data during
register, data, and mask array operations. It carries the compare data during Search
operations. It also carries the SRAM address during SRAM PIO accesses.
Read Acknowledge. This signal indicates that valid data is available on the DQ bus
during register, data, and mask array Read operations, or that the data is available on the
SRAM data bus during SRAM Read operations.
End of Transfer. This signal indicates the end of burst transfer to the data or mask array
during Read or Write burst operations.
Search Successful Flag. When asserted, this signal indicates that the device is the
global winner in a Search operation.
Search Successful Flag Valid. When asserted, this signal qualifies the SSF signal.
SRAM Address. This bus contains address lines to access off-chip SRAMs that contain
associative data. See Table 15-1 for the details of the generated SRAM address. In a
database of multiple CYNSE70032 devices, each corresponding bit of the SRAM address
from all cascaded devices must be connected.
SRAM Chip Enable. This is the chip-enable control for external SRAMs. In a database
of multiple CYNSE70032 devices, CE_L of all cascaded devices must be connected. This
signal is then driven by only one of the devices.
SRAM Write Enable. This is the write-enable control for external SRAMs. In a database
of multiple CYNSE70032 devices, WE_L of all cascaded devices must be connected
together. This signal is then driven by only one of the devices.
Notes:
1. I = Input only, I/O = Input or Output, O = Output only, T = three-state output.
2. ACK and EOT require a weak external pull-down such as 47KΩ or 100KΩ.
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CYNSE70032
Table 5-1. CYNSE70032 Signal Description (continued)
Parameter
OE_L
Type[1]
T
ALE_L
T
Cascade Interface
LHI[6:0]
I
LHO[1:0]
O
BHI[2:0]
I
BHO[2:0]
O
FULI[6:0]
I
FULO[1:0]
O
FULL
O
Device Identification
ID[4:0]
I
Description
SRAM Output Enable. This is the output-enable control for external SRAMs. Only the
last device drives this signal (with the LRAM bit set).
Address Latch Enable. When this signal is low, the addresses are valid on the SRAM
address bus. In a database of multiple CYNSE70032s, the ALE_L of all cascaded devices
must be connected. This signal is then driven by only one of the devices.
Local Hit In. These pins depth cascade the device to form a larger table. One signal of
this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block.
All unused LHI pins are connected to a logic 0. (For more information, see Section 14.0,
“Depth-Cascading” on page 96.)
Local Hit Out. LHO[1] and LHO[0] are the same logical signal. Either the LHO[1] or the
LHO[0] is connected to one input of the LHI bus of up to four downstream devices in a
block of up to eight. (For more information see Section 14.0, “Depth-Cascading” on
page 96.)
Block Hit In. Inputs from the previous block BHO[2:0] are tied to the BHI[2:0] of the current
device. In a four-block system, the last block can contain only seven devices because the
identification code 11111 is used for broadcast access.
Block Hit Out. These outputs from the last device in a block are connected to the BHI[2:0]
inputs of the devices in the downstream blocks.
Full In. Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device
to generate the FULL flag for the depth-cascaded block.
Full Out. FULO[1] and FULO[0] are the same logical signal. One of these two signals
must be connected to the FULI of up to four downstream devices in a depth-cascaded
table. Bit[0] in the data array indicates whether the entry is full (1) or empty (0).This signal
is asserted if all bits in the data array are 1s. (Refer to Section 14.0, “Depth-Cascading”
on page 96, for information on how to generate the FULL flag.)
Full Flag. When asserted, this signal indicates that the table of multiple depth-cascaded
devices is full.
Device Identification. The binary-encoded device identification for a depth-cascaded
system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast
address that selects all cascaded search engines in the system. On a broadcast
Read-only, the device with the LDEV bit set to 1 responds.
Supplies
VDD
VDDQ
Test Access Port
TDI
TCK
TDO
TMS
TRST_L
n/a
n/a
Document #: 38-02042 Rev. *E
I
I
T
I
I
Chip Core Supply. 1.8V.
Chip I/O Supply. 2.5V or 3.3V.
Test Access Port’s Test Data In.
Test Access Port’s Test Clock.
Test Access Port’s Test Data Out.
Test Access Port’s Test Mode Select.
Test Access Port’s Reset.
Page 12 of 126
CYNSE70032
6.0
Clocks
The CYNSE70032 device receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X and generate an
internal clock (CLK[3]), as shown in Figure 6-1. The CYNSE70032 device uses CLK2X and CLK for internal operations.
CLK2X
PHS_L
CLK[4]
Figure 6-1. CYNSE70032 Clocks (CLK2X and PHS_L)
7.0
Registers
All registers in the CYNSE70032 are 68 bits wide. The CYNSE70032 device contains sixteen pairs of comparand storage
registers, eight pairs of GMRs, eight search successful index registers and one each of command, information, burst Read, burst
Write, and next-free address registers. Table 7-1 provides an overview of all the CYNSE70032 registers. The registers are listed
in ascending address order. Each register group is then described in the subsections that follow.
Table 7-1. Register Overview
Address
Abbreviation
Type
Name
0–31
COMP0–31
R
Sixteen pairs of comparand registers that store comparands from the DQ bus
for learning later.
32–47
MASKS
RW
7.1
Eight GMR pairs.
48–55
SSR0–7
R
56
COMMAND
RW
Command register.
Eight search successful index registers.
57
INFO
R
Information register.
58
RBURREG
RW
Burst Read register.
59
WBURREG
RW
Burst Write register.
60
NFA
R
Next-free address register.
61–63
–
–
Reserved.
Comparand Registers
The device contains 32 68-bit comparand registers (sixteen pairs) dynamically selected in every Search operation to store the
comparand presented on the DQ bus. The Learn command will later use these registers when it is executed. The CYNSE70032
device stores the Search command’s cycle A comparand in the even-numbered register and its cycle B comparand in the
odd-numbered register, as shown in Figure 7-1.
Address 68
68
index
135
0
0
1
0
2
3
1
4
5
6
7
30
31
15
Figure 7-1. Comparand Register Selection during Search and Learn Instructions
Notes:
3. Any reference to “CLK” cycles means one cycle of CLK.
4. .“CLK” is an internal clock signal.
Document #: 38-02042 Rev. *E
Page 13 of 126
CYNSE70032
7.2
Mask Registers
The device contains sixteen 68-bit global mask registers (eight pairs) dynamically selected in every Search operation to select
the search subfield. The addressing of these registers is explained in Figure 7-2. The three-bit GMR Index supplied on the CMD
bus can apply eight pairs of global masks during the Search and Write operations, as shown below. Note. In 68-bit Search and
Write operations, the host ASIC must program both the even and odd mask registers with the same values.
68
68
Index
135
0
0
0
1
1
2
3
2
4
5
3
6
7
4
8
9
5
10
11
6
12
13
7
14
15
Search and Write Command Global Mask Selection
Figure 7-2. Addressing the Global Mask Register Array
Each mask bit in the GMRs is used during Search and Write operations. In Search operations, setting the mask bit to 1 enables
compares; setting the mask bit to 0 disables compares (forced match) at the corresponding bit position. In Write operations to
the data or mask array, setting the mask bit to 1 enables writes; setting the mask bit to 0 disables writes at the corresponding bit
position.
7.3
Search Successful Registers (SSR[0:7])
The device contains eight SSRs to hold the index of the location where a successful search occurred. The format of each register
is described in Table 7-2. The Search command specifies which SSR stores the index of a specific Search command in cycle B
of the Search instruction. Subsequently, the host ASIC can use this register to access that data array, mask array, or external
SRAM using the index as part of the indirect access address (see Table 7-2 and Table 8-1). The device with a valid bit set performs
a Read or Write operation. All other devices suppress the operation.
Table 7-2. Search Successful Register Description
Field
INDEX
Range
[13:0]
Initial Value
X
–
VALID
[30:14]
[31]
0
0
–
[67:32]
0
8.0
Description
Index. This is the address of the 68-bit entry where a successful Search occurs. The device
updates this field only when the Search is successful. If a hit occurs in a 136-bit entry-size
quadrant, the least significant bit (LSB) is 0. If a hit occurs in a 272-bit entry-size quadrant,
the two LSBs are 00. This index updates if the device is either a local or global winner in
a Search operation.
Reserved.
Valid. During a Search operation in a depth-cascaded configuration, the device that is a
global winner in a match sets this bit to 1. It updates only when the device is a global winner
in a Search operation.
Reserved.
Command Register
Table 8-1 describes the command register fields.
Table 8-1. Command Register Description
Field
SRST
Range
[0]
Initial Value
0
DEVE
[1]
0
Document #: 38-02042 Rev. *E
Description
Software Reset. If 1, this bit resets the device with the same effect as a hardware reset.
Internally, it generates a reset pulse lasting for eight CLK cycles. This bit automatically
resets to 0 after the reset has completed.
Device Enable. If 0, it keeps the SRAM bus (SADR, WE_L, CE_L, OE_L, and ALE_L),
SSF, and SSV signals in a three-state condition and forces the cascade interface output
signals LHO[1:0] and BHO[2:0] to 0. It also keeps the DQ bus in input mode. The purpose
of this bit is to make sure that there are no bus contentions when the devices power up
in the system.
Page 14 of 126
CYNSE70032
Table 8-1. Command Register Description (continued)
Field
TLSZ
Range
[3:2]
Initial Value
01
HLAT
[6:4]
000
LDEV
[7]
0
LRAM
[8]
0
CFG
[16:9]
00000000
[67:17]
0
9.0
Description
Table Size. The host ASIC must program this field to configure the chips into a table of
a certain size. This field affects the pipeline latency of the Search and Learn operations
as well as the Read and Write accesses to the SRAM (SADR[21:0], CE_L, OE_L, WE_L,
ALE_L, SSV, SSF, and ACK). Once programmed, the Search latency stays constant.
The latency by number of CLK cycles is as follows:
00: One device
4
01: Up to eight devices 5
10: Up to 31 devices
6
11: Reserved.
Latency of Hit Signals. This field further adds latency to the SSF and SSV signals by
the following number of CLK cycles during searches and ACKs in an SRAM Read access:
000: 0 100: 4
001: 1 101: 5
010: 2 110: 6
011: 3 111: 7.
Last Device in the Cascade. When set, this is the last device in the depth-cascaded
table and is the default driver for the SSF and SSV signals. In the event of a Search failure,
the device with this bit set drives the hit signals as follows: SSF = 0, SSV = 1.
During nonSearch cycles, the device with this bit set drives the signals as follows:
SSF = 0, SSV = 0.
Last Device on the SRAM Bus. When set, this device is the last device on the SRAM
bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and
ALE_L signals. In cycles where no CYNSE70032 device (in a depth-cascaded table)
drives these signals, the signals are driven as follows: SADR = 22’h3FFFFF, CE_L = 1,
WE_L = 1, and ALE_L = 1. OE_L is always driven by the device for which this bit is set.
Database Configuration. The device is divided internally into four partitions of 8K × 68
bits, each of which can be configured as 8K × 68 bits, 4K × 136 bits, or 2K × 272 bits, as
follows:
00: 4K × 68 bits
01: 2K × 136 bits
10: 1K × 272 bits
11: Reserved.
Bits[10:9] apply to configuring the first partition in the address space.
Bits[12:11] apply to configuring the second partition in the address space.
Bits[14:13] apply to configuring the third partition in the address space.
Bits[16:15] apply to configuring the fourth partition in the address space.
Reserved.
Information Register
Table 9-1 describes the information register fields.
Table 9-1. Information Register Description
Field
Range
Initial Value
Description
Revision
[3:0]
0001
Revision Number. This is the current device revision number. Numbers
start at one and increment by one for each revision of the device.
Implementation
[6:4]
000
Reserved
[7]
0
Device ID
[11:8]
0001
This is the device identification number.
Device ID
[12]
0 or 1
Reserved.
Device ID
[15:13]
000
MFID
[31:16]
1101_1100_0111_1111
Reserved
[67:32]
Document #: 38-02042 Rev. *E
This is the device implementation number.
Reserved.
These are the three most significant bits of the device identification
number.
Manufacturer ID. This field is the same as the manufacturer identification number and continuation bits in the TAP controller.
Reserved.
Page 15 of 126
CYNSE70032
9.1
Read Burst Address Register
Table 9-2 shows the Read burst address register (RBURREG) fields that must be programmed before a burst Read.
Table 9-2. Read Burst Register Description
Field
ADR
Range
[13:0]
Initial Value
0
BLEN
[18:14]
[27:19]
0
[67:28]
9.2
Description
Address. This is the starting address of the data or mask array during a burst Read
operation. It automatically increments by one for each successive Read of the data or
mask array. Once the operation is complete, the contents of this field must be reinitialized
for the next operation.
Reserved.
Length of Burst Access. The device provides the capability to Read from 4–511 locations
in a single burst. The BLEN decrements automatically. Once the operation is complete,
the contents of this field must be reinitialized for the next operation.
Reserved.
Write Burst Address Register Description
Table 9-3 describes the Write burst address register (WBURREG) fields that must be programmed before a burst Write.
Table 9-3. Write Burst Register Description
Field
ADR
Range
[13:0]
Initial Value
0
BLEN
[18:14]
[27:19]
0
[67:28]
9.3
Description
Address. This is the starting address of the data or mask array during a burst
Write operation. It automatically increments by one for each successive write of
the data or mask array. Once the operation is complete, the contents of this field
must be reinitialized for the next operation.
Reserved.
Length of Burst Access. The device provides the capability to write from 4–511
locations in a single burst. The BLEN decrements automatically. Once the
operation is complete, the contents of this field must be reinitialized for the next
operation.
Reserved.
NFA Register
Bit[0] of each 68-bit data entry is specially designated for use in the operation of the Learn command. For 68-bit-configured
quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). Every Write or Learn command loads
the address of the first 68-bit location containing a 0 into the entry’s bit[0]. This is stored in the NFA register (see Table 9-4). If all
the bits[0] in a device are set to 1, the CYNSE70032 asserts FULO[1:0] to 1.
For a 136-bit-configured quadrants, the LSB of the NFA register is always set to 0. The host ASIC must set both bit[0] and bit[68]
in a 136-bit word to either 0 or 1 to indicate full or empty status. Both bit[0] and bit[68] must be set to either 0 or 1, (that is, the 10
or 01 settings are invalid).
Table 9-4. NFA Register
Address
60
Document #: 38-02042 Rev. *E
67–14
Reserved
13–0
Index
Page 16 of 126
CYNSE70032
10.0
NSE Architecture and Operation Overview
16K
4K
Masks
Data
The CYNSE70032 device consists of 16K × 68-bit storage cells referred to as data bits. There is a mask cell corresponding to
each data cell. Figure 10-1 shows the three organizations of the device based on the value of the CFG bits in the command
register.
68
136
272
8K
Masks
Data
Masks
CFG = 10101010
Data
CFG = 01010101
CFG = 00000000
Figure 10-1. CYNSE70032 Database Width Configuration
During a Search operation, the Search data bit (S), the data array bit (D), the mask array bit (M), and the global mask bit (G) are
used in the following manner to generate a match at that bit position (see Table 10-1). The entry with a match on every bit position
results in a successful Search during a Search operation.
Table 10-1. Bit Position Match
G
0
1
1
1
1
1
M
X
0
1
1
1
1
D
X
X
0
1
0
1
S
X
X
0
0
1
1
Match
1
1
1
0
0
1
In order for a successful Search to make the device the local winner in the Search operation, all 68-bit positions within a device
must generate a match for a 68-bit entry in 68-bit-configured quadrants, or all 136-bit positions must generate a match for two
consecutive even and odd 68-bit entries in quadrants configured as 136 bits, or all 272-bit positions must generate a match for
four consecutive entries aligned to four entry-page boundaries of 68-bit entries in quadrants configured as 272 bits.
An arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a Search
cycle. The global winning device drives the SRAM bus, SSV, and the SSF signals. In the case of a Search failure, the device(s)
with LDEV and LRAM bits set drive the SRAM bus, SSF, and SSV signals.
The CYNSE70032 device can be configured to contain tables of different widths, even within the same chip. Figure 10-2 shows
a sample configuration of different widths.
Document #: 38-02042 Rev. *E
Page 17 of 126
CYNSE70032
68
4K
68
4K
2K
1K
136
272
CFG = 10010000
Figure 10-2. Multiwidth Database Configurations
11.0
Data and Mask Addressing
Figure 11-1 shows CYNSE70032 data and mask array addressing.
68
68
68
68
67
0
283
0
0
1
2
1
4
5
6
4K
2
3
16380 16381 16382
16K
68
68
135
0
0
0
2
4
6
3
7
16383
68
1
3
5
7
64K
CFG = 10101010
(272-bit configuration)
16383
16382 16383
CFG = 00000000
CFG = 01010101
(68-bit configuration)
(136-bit configuration)
Figure 11-1. Addressing CYNSE70032 Data and Mask Arrays
12.0
Commands
A master device such as an ASIC controller issues commands to the CYNSE70032 device using the command valid (CMDV)
signal and the CMD bus. The following subsections describe the operation of the commands.
12.1
Command Codes
The CYNSE70032 device implements four basic commands, shown in Table 12-1. The command code must be presented to
CMD[1:0] while keeping the CMDV signal high for two CLK2X cycles (cycles A and B). The controller ASIC must align the
instructions using the PHS_L signal. The CMD[8:2] field passes the parameters of the command in cycles A and B.
Table 12-1. Command Codes
Command Code
00
01
10
11
Command
Description
Read
Reads one of the following: data array, mask array, device registers, or external SRAM.
Write
Writes one of the following: data array, mask array, device registers, or external SRAM.
Search
Searches the data array for a desired pattern using the specified register from the GMR
array and local mask associated with each data cell.
Learn
The device has internal storage for up to 16 comparands that it can learn. The device
controller can insert these entries at the next free address (as specified by the NFA
register) using the Learn instruction.
Document #: 38-02042 Rev. *E
Page 18 of 126
CYNSE70032
12.2
Commands and Command Parameters
Table 12-2 lists the CMD bus fields that contain the CYNSE70032 command parameters and their respective cycles. Each
command is described separately in the subsections that follow.
Table 12-2. Command Parameters
Command
Read
CYC
A
8
SADR[21]
7
SADR[20]
6
SADR[19]
B
0
0
0
A
SADR[21]
SADR[20]
SADR[19]
B
0
0
0
Search
A
SADR[21]
SADR[20]
SADR[19]
[5]
B
A
B
Write
Learn
12.3
SADR[21]
0
SSR Index[2:0]
SADR[20]
SADR[19]
0
Mode
0: 68-bit
1: 136-bit
5
0
4
0
3
0
2
0 = Single
1 = Burst
0
0
0
0 = Single
1 = Burst
GMR Index [2:0]
0 = Single
1 = Burst
GMR Index [2:0]
0 = Single
1 = Burst
GMR Index 2:0]
68-bit or 136-bit: 0
272-bit:
1 in first cycle
0 in second cycle
Comparand Register Index
Comparand Register Index
Comparand Register Index
1
0
0
0
0
0
0
1
0
1
1
0
1
1
1
0
1
1
Read Command
The Read can be a single Read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst
Read of the data (CMD[2] = 1) or mask array locations using an internal autoincrementing address register (RBURADR).
A description of each type is provided in Table 12-3. A single-location Read operation lasts six cycles, as shown in Figure 12-1.
The burst Read adds two cycles for each successive Read. The SADR[21:19] bits supplied in Read instruction cycle A drive
SADR[21:19] signals during the Read of an SRAM location.
Table 12-3. Read Command Parameters
Command Parameter
CMD[2]
0
1
Read Command
Description
Single Read
Reads a single location of the data array, mask array, external SRAM, or device
registers. All access information is applied on the DQ bus.
Burst Read
Reads a block of locations from the data or mask arrays as a burst. The RBURADR
specifies the starting address and the length of the data transfer from the data or
mask array, and it autoincrements the address for each access. All other access
information is applied on the DQ bus. Note. The device registers and external
SRAM can only be read in single-Read mode.
Note:
5. The 272-bit-configured devices or 272-bit-configured quadrants within devices do not support the Learn instruction.
Document #: 38-02042 Rev. *E
Page 19 of 126
CYNSE70032
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
CMD[8:2]
DQ
Read
A
B
Address
X
Data
ACK
Figure 12-1. Single-Location Read Cycle Timing
The single Read operation takes six clock cycles that are performed in the following sequence.
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the DQ bus supplies
the address as shown in Table 12-4 and Table 12-5. The host ASIC selects the CYNSE70032 device for which ID[4:0] matches
the DQ[25:21] lines. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70032 with the LDEV bit set. The host ASIC also
supplies SADR[21:19] on CMD[8:6] in cycle A of the Read instruction if the Read is directed to the external SRAM.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[67:0] bus, and drives the ACK signal from Z to low.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus, and drives the ACK
signal high.
• Cycle 6: The selected device floats the DQ[67:0] to a three-state condition and drives the ACK signal low.
At the termination of cycle 6, the selected device releases the ACK line to a three-state condition. The Read instruction is
complete, and a new operation can begin. Note. The latency of the SRAM Read will be different than the one described above
(see Subsection 15.2, “SRAM PIO Access” on page 99). Table 12-4 lists and describes the format of the Read address for a data
array, mask array, or SRAM.
Table 12-5 describes the Read address format for the internal registers. Figure 12-2 illustrates the timing diagram for the burst
Read of the data or mask array.
Table 12-4. Read Address Format for Data Array, Mask Array, or SRAM
DQ
DQ
DQ
DQ
DQ
DQ
[67:30]
[29]
[28:26]
[25:21] [20:19]
[18:14]
DQ[13:0]
Reserved 0: Direct SSR Index
ID
00: Data Reserved If DQ[29] is 0, this field carries the address of the data array
1: Indirect (applicable if
Array
location. If DQ[29] is 1, the SSR Index specified on
DQ[29] is
DQ[28:26] is used to generate the address of the data array
indirect)
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.[6]
Reserved 0: Direct SSR Index
ID
01: Mask Reserved If DQ[29] is 0, this field carries the address of the mask array
1: Indirect (applicable if
Array
location. If DQ[29] is 1, the SSR Index specified on
DQ[29] is
DQ[28:26] is used to generate the address of the mask array
indirect)
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.[6]
Reserved 0: Direct SSR Index
ID
10:
Reserved If DQ[29] is 0, this field carries the address of the SRAM
1: Indirect (applicable if
External
location. If DQ[29] is 1, the SSR Index specified on
DQ[29] is
SRAM
DQ[28:26] is used to generate the address of the SRAM
indirect)
location: {SSR[13:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}.[6]
Note:
6. “ | ” stands for logical OR operation. “{}” stands for concatenation operator.
Document #: 38-02042 Rev. *E
Page 20 of 126
CYNSE70032
Table 12-5. Read Address Format for Internal Registers
DQ[67:26]
Reserved
DQ[25:21]
ID
DQ[20:19]
11: Register
DQ[18:6]
Reserved
DQ[5:0]
Register Address
cycle cyclecycle cyclecyclecycle cycle cyclecyclecycle cyclecycle
1
2
3
4
5
6
7
8
9 10 11 12
CLK2X
PHS_L
CMDV
CMD[1:0]
Read
CMD[8:2]
A B
DQ
Address
FF Data0 FF Data1 FF Data2 FF Data3
ACK
EOT
Figure 12-2. Burst Read of the Data and Mask Arrays (BLEN = 4)
The read operation lasts 4 + 2n CLK cycles (where n is the number of accesses in the burst specified by the BLEN field of the
RBURREG) in the sequence shown below. This operation assumes that the host ASIC has programmed the RBURREG with the
ADR and the BLEN before initiating a burst Read command.
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address supplied
on the DQ bus as shown in Table 12-6. The host ASIC selects the CYNSE70032 device where ID[4:0] matches the DQ[25:21]
lines. If DQ[25:21] = 11111, the host ASIC selects the CYNSE70032 device with the LDEV bit set.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[67:0] bus, and drives ACK and EOT from Z to low.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[67:0] bus and drives the ACK signal
high.
Cycles 4 and 5 repeat for each additional access until all the accesses specified in the BLEN field of the RBURREG are complete.
On the last transfer, the CYNSE70032 device drives the EOT signal high.
• Cycle (4 + 2n): The selected device drives the DQ[67:0] to a three-state condition, and drives the ACK and EOT signals low.
At the termination of cycle (4 + 2n), the selected device floats the ACK line to a three-state condition. The burst Read instruction
is complete, and a new operation can begin. Table 12-6 describes the Read address format for data and mask arrays for burst
Read operations.
Table 12-6. Read Address Format for Data and Mask Arrays
DQ[67:26] DQ[25:21]
DQ[20:19]
DQ[18:14]
DQ[13:0]
Reserved
ID
00: Data Array Reserved Do not care. These fifteen bits come from the internal RBURADR, which
increments for each access.
Reserved
ID
01: Mask Array Reserved Do not care. These fifteen bits come from the internal RBURADR, which
increments for each access.
12.4
Write Command
The Write command can be a single Write of a data array, mask array, register, or an external SRAM location (CMD[2] = 0). It
can also be a burst Write (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data or mask
array locations. A single-location Write is a three-cycle operation as shown in Figure 12-3. The burst Write adds one extra cycle
for each successive location Write.
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Page 21 of 126
CYNSE70032
cycle 1
cycle 0
cycle 2
cycle 3
cycle 4
CLK2X
PHS_L
CMDV
CMD[1:0]
Write
CMD[8:2]
A
DQ
B
Address
Data
X
Figure 12-3. Single Write Cycle Timing
The following is the Write operation sequence, and Table 12-7 shows the Write address format for the data array, the mask array,
or the single-Write SRAM. Table 12-8 shows the Write address format for the internal registers.
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the address supplied
on the DQ bus. The host ASIC also supplies the GMR Index to mask the write to the data or mask array location on CMD[5:3].
For SRAM Writes, the host ASIC must supply SADR[21:19] on CMD[8:6].
• Cycle 1B: The host ASIC continues to apply the Write instruction to CMD[1:0] (CMD[2] = 0) using CMDV = 1 and the address
supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask array
locations in CMD[5:3]. The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the devices
when DQ[25:21] = 11111.
• Cycle 2: The host ASIC drives the DQ[67:0] with the data to be written to the data array, the mask array, or the register location
of the selected device.
• Cycle 3: Idle cycle.
At the termination of cycle 3, another operation can begin. Note. The latency of the SRAM Write will be different than the one
described above (see Subsection 15.2, “SRAM PIO Access” on page 99).
Figure 12-4 shows the timing diagram of a burst Write operation of the data or mask array.
Table 12-7. Write Address Format for Data Array, Mask Array, or SRAM (Single Write)
DQ
DQ
DQ
DQ
[67:30]
[29]
[28:26]
[25:21]
Reserved 0: Direct SSR (applicable if
ID
1: Indirect DQ[29] is indirect)
DQ
[20:19]
00:
Data
Array
Reserved 0: Direct SSR (applicable if
1: Indirect DQ[29] is indirect)
ID
01:
Mask
Array
Reserved 0: Direct SSR (applicable if
1: Indirect DQ[29] is indirect)
ID
10:
External
SRAM
DQ
[18:14]
DQ[13:0]
Reserved If DQ[29] is 0, this field carries the address of the data
array location. If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of the data
array location: {SSR[13:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}.[6]
Reserved If DQ[29] is 0, this field carries the address of the
mask array location. If DQ[29] is 1, the SSR specified
on DQ[28:26] is used to generate the address of the
mask array location: {SSR[13:2], SSR[1] | DQ[1],
SSR[0] | DQ[0]}.[6]
Reserved If DQ[29] is 0, this field carries the address of the
SRAM location. If DQ[29] is 1, the SSR specified on
DQ[28:26] is used to generate the address of the
SRAM location: {SSR[13:2], SSR[1] | DQ[1], SSR[0]
| DQ[0]}.[6]
Table 12-8. Write Address Format for Internal Registers
DQ[67:26]
Reserved
DQ[25:21]
ID
Document #: 38-02042 Rev. *E
DQ[20:19]
11: Register
DQ[18:6]
Reserved
DQ[5:0]
Register address
Page 22 of 126
CYNSE70032
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
Write
CMD[8:2]
A
B
Address Data0 Data1 Data2 Data3
DQ
X
EOT
Figure 12-4. Burst Write of the Data and Mask Arrays (BLEN = 4)
The burst Write operation lasts for (n + 2) CLK cycles. n signifies the number of accesses in the burst as specified in the BLEN
field of the WBURREG. The following is the block Write operation sequence. This operation assumes that the host ASIC has
programmed the WBURREG with the ADR and the BLEN before initiating a burst Write command.
• Cycle 1A: The host ASIC applies the Write instruction to CMD[1:0] (CMD[2] = 1) using CMDV = 1, and the address supplied
on the DQ bus, as shown in Table 12-9. The host ASIC also supplies the GMR Index to mask the Write to the data or mask
array locations in CMD[5:3].
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] (CMD[2] = 1) using CMDV = 1 and the address
supplied on the DQ bus. The host ASIC continues to supply the GMR Index to mask the Write to the data or mask array
locations in CMD[5:3]. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. It selects all the devices
when DQ[25:21] = 11111.
• Cycle 2: The host ASIC drives the DQ[67:0] with the data to be written to the data or mask array location of the selected device.
The CYNSE70032 device writes the data from the DQ[67:0] bus only to the subfield that has the corresponding mask bit set
to 1 in the GMR specified by the index CMD[5:3]supplied in cycle 1.
• Cycles 3 to n + 1: The host ASIC drives DQ[67:0] with the data to be written to the next data or mask array location of the
selected device (addressed by the auto-increment ADR field of the WBURREG register).
The CYNSE70032 device writes the data on the DQ[67:0] bus only to the subfield that has the corresponding mask bit set to 1
in the GMR that is specified by the index CMD[5:3] supplied in cycle 1. The CYNSE70032 device drives the EOT signal low from
cycle 3 to cycle n; the CYNSE70032 device drives the EOT signal high in cycle n + 1 (n is specified in the BLEN field of the
WBURREG).
• Cycle n + 2: TheCYNSE70032 drives the EOT signal low.
At the termination of cycle n + 2, the CYNSE70032 device floats the EOT signal to a three-state operation, and a new instruction
can begin.
Table 12-9. Write Address Format for Data and Mask Array (Burst Write)
DQ
[67:26]
Reserved
DQ
[25:21]
ID
DQ
[20:19]
00: Data array
DQ
[18:14]
Reserved
Do not care. These fifteen bits come from the internal
Reserved
ID
01: Mask array
Reserved
Do not care. These fifteen bits come from the internal
DQ[13:0]
WBURADR, which increments with each access.
WBURADR, which increments with each access.
Document #: 38-02042 Rev. *E
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CYNSE70032
13.0
Search Command
This subsection will describe the following searches.
•
•
•
•
•
•
•
•
•
•
68-bit Search on tables configured as ×68 using one device
68-bit Search on tables configured as ×68 using up to eight devices
68-bit Search on tables configured as ×68 using up to 31 devices
136-bit Search on tables configured as ×136 using one device
136-bit Search on tables configured as ×136 using up to eight devices
136-bit Search on tables configured as ×136 using up to 31 devices
272-bit Search on tables configured as ×272 using one device
272-bit Search on tables configured as ×272 using up to eight devices
272-bit Search on tables configured as ×272 using up to 31 devices
Mixed-size searches on tables configured with different widths using an CYNSE70032.
13.1
68-bit Search on Tables Configured as ×68 using a Single CYNSE70032 Device
Figure 13-1 shows the timing diagram for a Search command in a 68-bit-configured table (CFG = 00000000) consisting of a single
device for one set of parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. The hardware diagram for this Search
subsystem is shown in Figure 13-2.
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
D1
DQ
SADR[21:0]
D2
D3
D4
A1
A3
1
0
1
0
1
ALE_L
1
0
1
0
1
WE_L
1
1
1
1
1
OE_L
0
0
0
0
0
SSV
0
SSF
0
CE_L
1
1
0
0
1
0
CFG = 00000000, HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1.
Search1 Search3
Search2 Search4
Hit Miss Hit Miss
Figure 13-1. Timing Diagram for 68-bit Search in ×68 Table (One Device)
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CYNSE70032
BHI[2:0]
DQ[67:0]
6
5
CMDV, CMD[8:0]
4
3
LHI
2
1
0
SRAM
CYNSE70032
SSF, SSV
BHI[2:0]
LHO[1]
LHO[0]
Figure 13-2. Hardware Diagram for a Table with a Single Device
The following is the sequence of operation for a single 68-bit Search command (also refer to “Command and Command Parameters,” Subsection 12.2 on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven by the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same
bits that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to be compared.
The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive CMDV high and to apply Search command (10) on CMD[1:0]. CMD[5:2] must be
driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A and
B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry
and the hit flag (see page 14 for information on SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be compared.
Note. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B. The even
and odd GMR pairs selected for the compare must be programmed with the same value.
The logical 68-bit Search operation is shown in Figure 13-3. The entire table of 68-bit entries is compared to a 68-bit word K
(presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective GMR
is the 68-bit word specified by the identical value in both even and odd GMR pairs selected by the GMR Index in the command’s
cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the command) is also stored in both even and
odd comparand register pairs selected by the Comparand Register Index in the command’s cycle B. In a ×68 configuration, only
the even comparand register can subsequently be used by the Learn command. The word K (presented on the DQ bus in both
cycles A and B of the command) is compared with each entry in the table, starting at location 0. The first matching entry’s location
address L is the winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing”
on page 98).
0
67
GMR
K
Location 67
address
0
67
0
1
Comparand Register (even)
2
K
3
Comparand Register (odd)
K
L
0
(First matching entry)
16383
CFG = 00000000
(68-bit configuration)
Figure 13-3. ×68 Table with One Device
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (which is two CLK2X cycles) is shown in Table 13-1.
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Page 25 of 126
CYNSE70032
Table 13-1. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
16K × 68 bits
128K × 68 bits
496K × 68 bits
Latency in CLK Cycles
4
5
6
Search latency from command to SRAM access cycle is 4 for a single device in the table with TLSZ = 00. In addition, SSV and
SSF shift further to the right for different values of HLAT as specified in Table 13-2.
Table 13-2. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
13.2
Number of CLK Cycles
0
1
2
3
4
5
6
7
68-bit Search on Tables Configured as ×68 Using up to Eight CYNSE70032 Devices
The hardware diagram of the Search subsystem of eight devices is shown in Figure 13-4. The following are the parameters
programmed into the eight devices.
• First seven devices (devices 0–6): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 00000000, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1.
Note. All eight devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table (device
number 7 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 6 in
this case) must be programmed with LRAM = 0 and LDEV = 0.
Figure 13-5 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 0.
Figure 13-6 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 1.
Figure 13-7 shows the timing diagram for a Search command in the 68-bit-configured table of eight devices for device number 7
(the last device in this specific table). For these timing diagrams four 68-bit searches are performed sequentially. HIT/MISS
assumptions were made as shown below in Table 13-3.
Table 13-3. HIT/MISS Assumption
Search Number
Device 0
Device 1
Devices 2–6
Device 7
Document #: 38-02042 Rev. *E
1
Hit
Miss
Miss
Miss
2
Miss
Hit
Miss
Miss
3
Hit
Hit
Miss
Hit
4
Miss
Miss
Miss
Hit
Page 26 of 126
CYNSE70032
SRAM
6
3
LHI
CYNSE70032 #0
2
6 5 4 3
CYNSE70032 #1 LHI
2
6 5 4 3
LHI
CYNSE70032 #2
2
BHI[2:0]
LHO[1]
SSF, SSV
BHI[2:0]
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
BHI[2:0]
5
4
LHO[1]
BHI[2:0]
1
0
LHO[0]
0
6 5 4 3
2
LHI
CYNSE70032 #3
LHO[0]
1
0
6 5 4
3
CYNSE70032 #4
LHI
LHO[0]
1
0
BHI[2:0] 3
2 1
LHI
0
6 5
4
CYNSE70032 LHI
#5
LHO[0]
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70032 #6
LHO[0]
1
LHI
LHO[0]
LHO[0]
BHI[2:0]
2
0
1
LHO[1]
BHI[2:0]3
1
0
5
4
LHI
CYNSE70032 #7
2
6
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 13-4. Hardware Diagram for a Table with Eight Devices
Document #: 38-02042 Rev. *E
Page 27 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
D1
DQ
D2
D3
D4
0
|(LHI[6:0])
LHO[1:0]
z
SADR[21:0]
z
CE_L
z
ALE_L
z
WE_L
A1
0
0
1
z
z
z
z
A3
0
0
z
z
z
1
z
OE_L
z
SSV
z
1
z
1
z
SSF
z
1
z
1
z
CFG = 00000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search3
(This device (This device
is the global is the global
winner.)
winner.)
Search4
Search2
(Miss on
(Miss on
this device.) this device.)
Figure 13-5. Timing Diagram for 68-bit Search Device Number 0
Document #: 38-02042 Rev. *E
Page 28 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
D1
DQ
D2
D3
D4
|(LHI[6:0])
LHO[1:0]
SADR[21:0]
z
CE_L
z
ALE_L
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 00000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
A2
z
0
z
0
z
1
Search1
(Miss on
this device.)
Search3
(Local but
not global
winner.)
Search4
Search2
(This device (Miss on
this device.)
is global
winner.)
Figure 13-6. Timing Diagram for 68-bit Search Device Number 1
Document #: 38-02042 Rev. *E
Page 29 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
D1
DQ
D2
D3
D4
|(LHI[6:0])
LHO[1:0]
z
SADR[21:0]
CE_L
ALE_L
WE_L
OE_L
SSV
SSF
0
0
1
0
0
0
CFG = 00000000, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
A4
z
0
z
0
1
z
z
1
0
z
1
0
Search1
Search3
(Miss on
(Local but
this device.) not global
winner.)
Search2 Search4
(Global
(Miss on
this device.) winner.)
Figure 13-7. Timing Diagram for 68-bit Search Device Number 7 (Last Device)
The following is the sequence of operation for a single 68-bit Search command (also refer to “Command and Command Parameters,” Subsection 12.2 on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) to CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same
bits that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to be compared.
The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive CMDV high and to apply Search command (10) on CMD[1:0]. CMD[5:2] must be
driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A and
B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry
and hit flag (see page 14 for a description of SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be compared.
Note. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B. The even
and odd GMR pairs selected for the comparison must also be programmed with the same value.
The logical 68-bit Search operation is shown in Figure 13-8. The entire table of eight devices of 68-bit entries is compared to a
68-bit word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and local mask bits. The effective
GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and selected
by the GMR Index in the command’s cycle A. The 68-bit word K (presented on the DQ bus in both cycles A and B of the command)
is also stored in both even and odd comparand register pairs (selected by the Comparand Register Index in command cycle B)
in each of the eight devices. In the ×68 configuration, only the even comparand register can subsequently be used by the Learn
command in one of the devices (the first non-full device only). The word K (presented on the DQ bus in both cycles A and B of
Document #: 38-02042 Rev. *E
Page 30 of 126
CYNSE70032
the command) is compared with each entry in the table, starting at location 0. The first matching entry’s location address L is the
winning address that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 98). The
global winning device will drive the bus in a specific cycle. On a global miss cycle the device with LRAM = 1 (default driving device
for the SRAM bus) and LDEV = 1 (default driving device for SSF and SSV signals) will be the default driver for such missed cycles.
0
67
Must be same in each of the eight
devices
0
67
Comparand Register (Even)
K
Comparand Register (Odd)
K
GMR
K
Location 67
address
0
0
1
2
3
L
(First matching entry)
Will be the same in each of the eight131071
devices
CFG = 00000000
(68-bit configuration)
Figure 13-8. ×68 Table with Eight Devices
The Search command is a pipelined operation and executes a Search at half the rate of the frequency of CLK2X for 68-bit
searches in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command
cycle (two CLK2X cycles) is shown in Table 13-4.
Table 13-4. Search latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
16K × 68 bits
128K × 68 bits
496K × 68 bits
Latency in CLK Cycles
4
5
6
Search latency from command to SRAM access cycle is 5 for up to eight devices in the table (TLSZ = 01). SSV and SSF also
shift further to the right for different values of HLAT as specified in Table 13-5.
Table 13-5. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
13.3
Number of CLK Cycles
0
1
2
3
4
5
6
7
68-bit Search on Tables Configured as ×68 Using up to 31 CYNSE70032 Devices
The hardware diagram of the Search subsystem of 31 devices is shown in Figure 13-9. Each of the four blocks in the diagram
represents eight CYNSE70032 devices (except the last, which has seven devices). The diagram for a block of eight devices is
shown in Figure 13-10. The following are the parameters that are programmed into the 31 devices.
• First thirty devices (devices 0–29): CFG = 00000000, TLSZ = 10, HLAT = 001, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 00000000, TLSZ = 10, HLAT = 001, LRAM = 1, and LDEV = 1.
Note. All devices must be programmed with the same values for TLSZ and HLAT. Only the last device in the table (device
number 30 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 29
in this case) must be programmed with LRAM = 0 and LDEV = 0.
Document #: 38-02042 Rev. *E
Page 31 of 126
CYNSE70032
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions defined in Table 13-6. For the purpose of
illustrating timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. Figure 13-11
shows the timing diagram for a Search command in the 68-bit-configured table of 31 devices for each of the eight devices in block
number 0. Figure 13-12 shows a timing diagram for a Search command in the 68-bit-configured table of 31 devices for all the
devices in block number 1 (above the winning device in that block). Figure 13-13 shows the timing diagram for the globally winning
device (defined as the final winner within its own and all blocks) in block number 1. Figure 13-14 shows the timing diagram for
all the devices below the globally winning device in block number 1. Figure 13-15, Figure 13-16, and Figure 13-17, respectively,
show the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below
the globally winning device for block number 2. Figure 13-18, Figure 13-19, Figure 13-20, and Figure 13-21, respectively, show
the timing diagrams of the devices above the globally winning device, the globally winning device, and the devices below the
globally winning device except the last device (device 30) for block number 3.
The 68-bit Search operation is pipelined and executed as follows. Four cycles from the Search command, each of the devices
knows the outcome internal to it for that operation. In the fifth cycle after the Search command, the devices in a block arbitrate
for a winner amongst them (a “block” being defined as less than or equal to eight devices resolving the winner between them
using the LHI[6:0] and LHO[1:0] signalling mechanisms). In the sixth cycle after the Search command, the blocks resolve the
winning block through the BHI[2:0] and BHO[2:0] signalling mechanisms. The winning device within the winning block is the global
winning device for a Search operation.
Table 13-6. Hit/Miss Assumption
Search Number
Block 0
Block 1
Block 2
Block 3
1
Miss
Miss
Miss
Hit
2
Miss
Miss
Hit
Hit
BHI[2]
SSF, SSV
3
Miss
Hit
Hit
Miss
BHI[1]
BHI[0] GND
Block of 8 CYNSE70032s Block 0 (devices 0–7)
BHO[2]
BHO[1]
BHO[0]
4
Miss
Miss
Miss
Miss
SRAM
BHI[2]
BHI[1]
BHI[0] GND
Block of 8 CYNSE70032s Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70032s Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70032s Block 3 (devices 24–30)
DQ[67:0]
BHO[2]
BHO[1]
BHO[0]
CMD[8:0], CMDV
Figure 13-9. Hardware Diagram for a Table with 31 Devices
Document #: 38-02042 Rev. *E
Page 32 of 126
CYNSE70032
SRAM
BHI[2:0]
BHI[2:0]
6
3
LHI
CYNSE70032 #0
2
6 5 4 3
CYNSE70032 #1 LHI
2
6 5 4 3
LHI
CYNSE70032 #2
2
LHO[1]
BHI[2:0]
DQ[67:0]
CMDV
CMD[8:0]
LHO[1]
BHI[2:0]
5
4
LHO[1]
BHI[2:0]
0
LHO[0]
6 5 4 3
2
LHI
CYNSE70032 #3
LHO[0]
1
0
6 5 4
3
CYNSE70032 #4
LHI
LHO[0]
1
0
2 1
LHI
0
6 5
4
CYNSE70032 LHI
#5
LHO[0]
BHI[2:0] 3
2
1
LHI
0
6
5
4
LHI
CYNSE70032 #6
LHO[0]
1
LHI
1
0
BHI[2:0] 3
2
LHO[0]
LHO[0]
BHI[2:0]
BHI[2:0]3
0
1
LHO[1]
SSV, SSF
1
0
5 4
LHI
CYNSE70032 #7
2
6
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 13-10. Hardware Diagram for a Block of up to Eight Devices
Document #: 38-02042 Rev. *E
Page 33 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search3
(Miss on
(Miss on
this device.) this device.)
Search2 Search4
(Miss on
(Miss on
this device.) this device.)
Figure 13-11. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
Document #: 38-02042 Rev. *E
Page 34 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search3
(Miss on
(Miss on
this device.) this device.)
Search2 Search4
(Miss on (Miss on
this device.)this device.)
Figure 13-12. Timing Diagram for Each Device Above the Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 35 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
D2
D3
D4
z
A3
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search3
(Miss on
(This device is
this device.)global winner.)
Search2 Search4
(Miss on
(Miss on
this device.) this device.)
Figure 13-13. Timing Diagram for Globally Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 36 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
z
SSF
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search3
(Miss on
(Miss on
this device.) this device.)
Search2 Search4
(Miss on
(Miss on
this device.) this device.)
Figure 13-14. Timing Diagram for Devices Below the Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 37 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
Search1 Search3
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
(Miss on
(Miss on
this device.) this device.)
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Search2 Search4
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
(Miss on
(Miss on
this device.) this device.)
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Figure 13-15. Timing Diagram for Devices Above the Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 38 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
z
D2
D3
D4
A2
z
z
z
0
z
z
0
1
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
Search1 Search3
(Miss on
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
(Hit but not
this device.) winner.)
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Search2 Search4
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
(Miss on
(Global
Note: Each bit in BHO[2:0] is the same logical signal.
winner.) this device.)
Note: Each bit in LHO[1:0] is the same logical signal.
Figure 13-16. Timing Diagram for Globally Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 39 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on
(Miss on
this device.) this device.)
Search2 Search4
(Miss on (Miss on
this device.)this device.)
Figure 13-17. Timing Diagram for Devices Below the Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 40 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
Search1 Search3
(Miss on
(Miss on
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
this device.) this device.)
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Search2 Search4
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
(Miss on
(Miss on
this device.) this device.)
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Figure 13-18. Timing Diagram for Devices Above the Winning Device in Block Number 3
Document #: 38-02042 Rev. *E
Page 41 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
CMD[1:0]
z
D2
D3
D4
A1
z
z
z
0
z
z
0
WE_L
z
OE_L
z
SSV
z
1
z
z
1
z
SSF
1
z
Search1 Search3
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
(Global (Miss on
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
winner.) this device.)
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Search2
Search4
(Miss on
(Hit but not
Note: Each bit in BHO[2:0] is the same logical signal.
global winner.)this device.)
Note: Each bit in LHO[1:0] is the same logical signal.
Figure 13-19. Timing Diagram for Globally Winning Device in Block Number 3
Document #: 38-02042 Rev. *E
Page 42 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
01
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2
Search4
(Miss on
(Miss on
this device.) this device.)
Figure 13-20. Timing Diagram for Devices Below the Winning Device in Block Number 3
(Except the Last Device [Device Number 30])
Document #: 38-02042 Rev. *E
Page 43 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
Search3
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
LHO[1:0]
0
0
I(BHI[2:0])
0
BHO[2:0]
0
D2
D3
D4
SADR[21:0]
CE_L
0
ALE_L
0
WE_L
OE_L
1
0
SSV
0
SSF
z
z
0
z
1
z
z
0
CFG = 00000000, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
0
z
1
0
Search1
Search3
(Hit on some (Hit on some
device above.)device above.)
Search2
Search4
(Hit on some
(Global miss;
device above.)
this device
default driver.)
Figure 13-21. Timing Diagram for Device Number 6 in Block Number 3
(Device Number 30 in Depth-Cascaded Table)
The following is the sequence of operation for a single 68-bit Search command (also refer to “Command and Command Parameters,” Subsection 12.2 on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same
bits that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data to be compared.
The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive CMDV high and applies Search command (10) on CMD[1:0]. CMD[5:2] must be
driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A and
B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry
and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] continues to carry the 68-bit data to be compared.
Note. For 68-bit searches, the host ASIC must supply the same 68-bit data on DQ[67:0] during both cycles A and B. The even
and odd GMR pairs selected for the compare must be programmed with the same value.
The logical 68-bit Search operation is shown in Figure 13-22. The entire table (31 devices of 68-bit entries) is compared to a 68-bit
word K (presented on the DQ bus in both cycles A and B of the command) using the GMR and the local mask bits. The effective
GMR is the 68-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and selected
Document #: 38-02042 Rev. *E
Page 44 of 126
CYNSE70032
by the GMR Index in the command’s cycle A. The 68-bit word K (presented on the DQ bus in cycles A and B of the command)
is also stored in both even and odd comparand register pairs in each of the eight devices (and selected by the Comparand
Register Index in command’s cycle B). In the x68 configuration, the even comparand register can subsequently be used by the
Learn command, but only in the first non-full device. The word K (presented on the DQ bus in cycles A and B of the command)
is compared with each entry in the table, starting at location 0. The first matching entry’s location address L is the winning address
that is driven as part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 98). The global winning
device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 and LDEV = 1 will be the default
driver for such missed cycles.
0
67
Must be same in each of the eight
devices
GMR
K
Location 67
address
Comparand Register (even)
0
K
1
2
Comparand Register (odd)
3
K
67
0
0
Will be same in each of the eight
devices
L
(First matching entry)
507903
CFG = 00000000
(68-bit configuration)
Figure 13-22. ×68 Table with 31 Devices
The Search command is a pipelined operation and executes a search at half the rate of the frequency of CLK2X for 68-bit searches
in ×68-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 68-bit Search command cycle (two
CLK2X cycles) is shown in Table 13-7.
Table 13-7. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
16K × 68 bits
128K × 68 bits
496K × 68 bits
Latency in CLK Cycles
4
5
6
For up to 31 devices in the table (TLSZ = 10), search latency from command to SRAM access cycle is 6. In addition, SSV and
SSF shift further to the right for different values of HLAT as specified in Table 13-8.
Table 13-8. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
13.4
Number of CLK Cycles
0
1
2
3
4
5
6
7
136-bit Search on Tables Configured as ×136 Using a Single CYNSE70032 Device
Figure 13-23 shows the timing diagram for a Search command in the 136-bit-configured table (CFG = 01010101) consisting of a
single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, LDEV = 1. The hardware diagram for this Search
subsystem is shown in Figure 13-24.
Document #: 38-02042 Rev. *E
Page 45 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search3
01
01
01
Search2
Search4
CMD[8:2]
A B A B A B A B
DQ
A B A B A B A B
D1 D2 D3 D4
SADR[21:0]
A1
A3
1
0
1
0
1
ALE_L
1
0
1
0
1
WE_L
1
1
1
1
1
OE_L
0
0
0
0
0
SSV
0
1
SSF
0
1
CE_L
0
1
0
0
Search1 Search3
Hit
Hit
Search2 Search4
Miss
Miss
CFG = 01010101, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1.
Figure 13-23. Timing Diagram for 136-bit Search (One Device)
DQ[67:0]
6
BHI[2:0]
CMDV, CMD[8:0]
SSF, SSV
5
4
3
LHI
2
1
0
SRAM
CYNSE70032
BHI[2:0]
LHO[1]
LHO[0]
Figure 13-24. Hardware Diagram for a Table With One Device
The following is the operation sequence for a single 136-bit Search command (also refer to “Command and Command Parameters,” Subsection 12.2 on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) to CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same
bits that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data ([135:68]) to
be compared against all even locations. The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive CMDV high and applies Search command code (10) on CMD[1:0]. CMD[5:2] must
be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A
and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
entry and hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0]), compared to
all odd locations.
Document #: 38-02042 Rev. *E
Page 46 of 126
CYNSE70032
Note. For 136-bit searches, the host ASIC must supply two distinct 68-bit data words on DQ[67:0] during cycles A and B. The
even-numbered GMR of the pair specified by the GMR Index is used for masking the word in cycle A. The odd-numbered GMR
of the pair specified by the GMR Index is used for masking the word in cycle B.
The logical 136-bit search operation is shown in Figure 13-25. The entire table of 136-bit entries is compared to a 136-bit word K
(presented on the DQ bus in cycles A and B of the command) using the GMR and local mask bits. The GMR is the 136-bit word
specified by the even and odd global mask pair selected by the GMR Index in the command’s cycle A. The 136-bit word K
(presented on the DQ bus in cycles A and B of the command) is also stored in both even and odd comparand register pairs
selected by the Comparand Register Index in the command’s cycle B. The two comparand registers can subsequently be used
by the Learn command with the even comparand register stored in an even location, and the odd comparand register stored in
an adjacent odd location. The word K (presented on the DQ bus in cycles A and B of the command) is compared with each entry
in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the
SRAM address on SADR[21:0] lines (see “SRAM Addressing” on page 98). Note. The matching address is always going to be
an even address for a 136-bit Search.
0
135
Even
A
135
Location
address
0
67
0
2
Comparand Register (even)
4
A
6
Comparand Register (odd)
B
L
GMR
K
Odd
B
0
(First matching entry)
16382
CFG = 01010101
(136-bit configuration)
Figure 13-25. ×136 Table with One Device
The Search command is a pipelined operation that executes searches at half the rate of the frequency of CLK2X for 136-bit
searches in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search
command cycle (two CLK2X cycles) is shown in Table 13-9.
Table 13-9. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
8K × 136 bits
64K × 136 bits
248K × 136 bits
Latency in CLK Cycles
4
5
6
For a single device in the table with TLSZ = 00, the Search latency from command to SRAM access cycle is 4. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 13-10.
Table 13-10. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02042 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 47 of 126
CYNSE70032
13.5
136-bit Search on Tables Configured as ×136 Using up to Eight CYNSE70032 Devices
The hardware diagram of the Search subsystem of eight devices is shown in Figure 13-26. The following are parameters
programmed into the eight devices.
• First seven devices (devices 0–6): CFG = 01010101, TLSZ = 01, HLAT = 010, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 01010101, TLSZ = 01, HLAT = 010, LRAM = 1, and LDEV = 1.
Note. All eight devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table (device
number 7 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 6 in
this case) must be programmed with LRAM = 0 and LDEV = 0.
Figure 13-27 shows the timing diagram for a Search command in the 136-bit-configured table of eight devices for device
number 0. Figure 13-28 shows the timing diagram for a Search command in the 136-bit-configured table consisting of eight
devices for device number 1. Figure 13-29 shows the timing diagram for a Search command in the 136-bit configured table
consisting of eight devices for device number 7 (the last device in this specific table). For these timing diagrams, four 136-bit
searches are performed sequentially, and the following Hit/Miss assumptions were made (see Table 13-11).
Table 13-11. Hit/Miss Assumptions
Search Number
Device 0
Device 1
Device 2–6
Device 7
Document #: 38-02042 Rev. *E
1
Hit
Miss
Miss
Miss
2
Miss
Hit
Miss
Miss
3
Hit
Hit
Miss
Hit
4
Miss
Miss
Miss
Hit
Page 48 of 126
CYNSE70032
SRAM
BHI[2:0]
SSF, SSV
6 5 4 3
LHI
CYNSE70032 #0
LHO[1]
2
6 5 4 3
CYNSE70032 #1 LHI
2
6 5 4 3
LHI
CYNSE70032 #2
2
BHI[2:0]
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
BHI[2:0]
LHO[1]
BHI[2:0]
1
0
LHO[0]
0
6 5 4 3
2
LHI
CYNSE70032 #3
LHO[0]
1
0
6 5 4
3
CYNSE70032 #4
LHI
LHO[0]
1
0
BHI[2:0] 3
2 1
LHI
0
6 5
4
CYNSE70032 LHI
#5
LHO[0]
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70032 #6
LHO[0]
1
LHI
LHO[0]
LHO[0]
BHI[2:0]
2
0
1
LHO[1]
BHI[2:0]3
1
0
5
4
LHI
CYNSE70032 #7
2
6
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 13-26. Hardware Diagram for a Table with Eight Devices
Document #: 38-02042 Rev. *E
Page 49 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search3
01
01
01
Search2
Search4
CMD[8:2]
A B A B A B A B
DQ
A B A B A B A B
D1 D2 D3 D4
0
|(LHI[6:0])
LHO[1:0]
z
SADR[21:0]
z
CE_L
z
ALE_L
z
WE_L
A1
0
0
1
z
z
z
z
A3
0
0
z
z
z
1
z
OE_L
z
SSV
z
1
z
1
z
SSF
z
1
z
1
z
CFG = 01010101, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search3
(This device is (This device is
global winner.) global winner.)
Search4
Search2
(Miss on
(Miss on
this device.) this device.)
Figure 13-27. Timing Diagram for 136-bit Search Device Number 0
Document #: 38-02042 Rev. *E
Page 50 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
CMD[8:2]
Search3
01
01
01
Search2
Search4
A B A B A B A B
A B A B A B A B
D1 D2 D3 D4
DQ
LHI[6:0]
LHO[1:0]
SADR[21:0]
z
CE_L
z
ALE_L
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 01010101, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
A2
z
0
z
0
z
1
Search1 Search3
(Local but not
(Miss
on this global winner.)
device.)
Search4
Search2
(Miss
This device
is global winner.) on this
device.)
Figure 13-28. Timing Diagram for 136-bit Search Device Number 1
Document #: 38-02042 Rev. *E
Page 51 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
Search3
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
LHO[1:0]
SADR[21:0]
A4
CE_L
0
ALE_L
0
WE_L
1
OE_L
0
SSV
0
SSF
0
CFG = 01010101, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
z
0
z
0
1
z
z
1
0
z
1
0
Search3
Search1
(Miss on (Local but not
this device.)global winner.)
Search4
Search2
(Miss on
(Global winner.)
this device.)
Figure 13-29. Timing Diagram for 136-bit Search Device Number 7 (Last Device)
The following is the sequence of operation for a single 136-bit Search command (also see Subsection 12.2, “Commands and
Command Parameters” on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the same
bits that will be driven by this device on SADR[21:19] if it has a hit. DQ[67:0] must be driven with the 68-bit data ([135:68]) in
order to be compared against all even locations. The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive CMDV high and to apply Search command code (10) on CMD[1:0]. CMD[5:2] must
be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A
and B. CMD[8:6] signals must be driven with the SSR index that will be used for storing the address of the matching entry and
the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0]) compared against all
odd locations.
The host ASIC continues to drive CMDV high and to apply Search command code (10) on CMD[1:0]. CMD[5:2] must be driven
by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A and B. CMD[8:6]
signals must be driven with the SSR index that will be used for storing the address of the matching entry and the hit flag (see
page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0]) compared against all odd locations.
The logical 136-bit Search operation is shown in Figure 13-30. The entire table (eight devices of 136-bit entries) is compared to
a 136-bit word K (presented on the DQ bus in cycles A and B of the command) using the GMR and local mask bits. The GMR is
the 136-bit word specified by the even and odd global mask pair selected by the GMR Index in the command’s cycle A.
Document #: 38-02042 Rev. *E
Page 52 of 126
CYNSE70032
The 136-bit word K (presented on the DQ bus in cycles A and B of the command) is also stored in the even and odd comparand
registers specified by the Comparand Register Index in the command’s cycle B. In ×136 configurations, the even and odd
comparand register can subsequently be used by the Learn command in only one of the devices (the first non-full device). The
word K (presented on the DQ bus in cycles A and B of the command) is compared to each entry in the table, starting at location 0.
The first matching entry’s location address L is the winning address that is driven as part of the SRAM address on the SADR[21:0]
lines (see “SRAM Addressing” on page 98). The global winning device will drive the bus in a specific cycle. On global miss cycles,
the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default driving device for SSF and
SSV signals) will be the default driver for such missed cycles. Note. During 136-bit searches of 136-bit-configured tables, the
Search hit will always be at an even address.
0
135
Must be same in each of the eight
devices
Even
Odd
GMR
B
A
K
Location 135
address
0
67
0
2
Comparand Register (even)
4
A
6
Comparand Register (odd)
B
L
0
(First matching entry)
Will be same in each of the eight
devices
131070
CFG = 01010101
(136-bit configuration)
Figure 13-30. ×136 Table with Eight Devices
The Search command is a pipelined operation and executes a Search at half the rate of the CLK2X frequency for 136-bit searches
in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search command cycle
(two CLK2X cycles) is shown in Table 13-12.
Table 13-12. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
8K × 136 bits
64K × 136 bits
248K × 136 bits
Latency in CLK Cycles
4
5
6
For one to eight devices in the table and TLSZ = 01, Search latency from command to SRAM access cycle is 5. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 13-13.
Table 13-13. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02042 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 53 of 126
CYNSE70032
13.6
136-bit Search on Tables Configured as ×136 using up to 31 CYNSE70032 Devices
The hardware diagram of the Search subsystem of 31 devices is shown in Figure 13-31. Each of the four blocks in the diagram
represents a block of eight CYNSE70032 devices (except the last, which has seven devices). The diagram for a block of eight
devices is shown in Figure 13-32. The following are the parameters programmed into the 31 devices.
• First 30 devices (devices 0–29): CFG = 01010101, TLSZ = 10, HLAT = 001, LRAM = 0, and LDEV = 0.
• 31st device (device 30): CFG = 01010101, TLSZ = 10, HLAT = 001, LRAM = 1, and LDEV = 1.
Note. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table (device number
30 in this case) must be programmed with LRAM = 1 and LDEV = 1. All other upstream devices (devices 0 through 29 in this
case) must be programmed with LRAM = 0 and LDEV = 0.
The timing diagrams referred to in this paragraph reference the Hit/Miss assumptions listed in Table 13-14. For the purpose of
illustrating timings, it is further assumed that the there is only one device with a matching entry in each of the blocks. Figure 13-33
shows the timing diagram for a Search command in the 136-bit-configured table (31 devices) for each of the eight devices in
block number 0. Figure 13-34 shows the timing diagram for Search command in the 68-bit-configured table (31 devices) for all
devices above the winning device in block number 1. Figure 13-35 shows the timing diagram for the globally winning device (the
winner within its own and all blocks) in block number 1. Figure 13-36 shows the timing diagram for all devices below the globally
winning device in block number 1. Figure 13-37, Figure 13-38, and Figure 13-39, respectively, show the timing diagrams of the
devices above globally winning device, the globally winning device, and the devices below the globally winning device for block
number 2. Figure 13-40, Figure 13-41, Figure 13-42, and Figure 13-43, respectively, show the timing diagrams of the devices
above the globally winning device, the globally winning device, and the devices below the globally winning device except the last
device (device 30) for block number 3, and then the last device (device 30) for block number 3.
The 136-bit Search operation is pipelined and executes as follows. Four cycles from the Search command, each of the devices
knows the outcome internal to it for that operation. In the fifth cycle after the Search command, the devices in a block arbitrate
for a winner from among them (a “block” being less than or equal to eight devices resolving the winner by using LHI[6:0] and
LHO[1:0] signalling mechanisms). In the sixth cycle after the Search command, the blocks of devices resolve the winning block
through the BHI[2:0] and BHO[2:0] signalling mechanisms. The winning device in the winning block is the global winning device
for a Search operation.
Table 13-14. Hit/Miss Assumptions
Search Number
Block 0
Block 1
Block 2
Block 3
Document #: 38-02042 Rev. *E
1
Miss
Miss
Miss
Hit
2
Miss
Miss
Hit
Hit
3
Miss
Hit
Hit
Miss
4
Miss
Miss
Miss
Miss
Page 54 of 126
CYNSE70032
BHI[2]
SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70032s Block 0 (devices 0–7)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
BHI[1]
BHI[0]
SRAM
GND
Block of 8 CYNSE70032s Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
GND
Block of 8 CYNSE70032s Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
DQ[67:0]
CMD[8:0], CMDV
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70032s Block 3 (devices 24–30)
BHO[2]
BHO[1]
BHO[0]
Figure 13-31. Hardware Diagram for a Table with 31 Devices
Document #: 38-02042 Rev. *E
Page 55 of 126
CYNSE70032
SRAM
BHI[2:0]
BHI[2:0]
6
LHO[1]
BHI[2:0]
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
3
LHI
CYNSE70032 #0
6
BHI[2:0]
5
5
4
4
LHO[1]
BHI[2:0]
2
6 5 4 3
LHI
CYNSE70032 #2
2
0
LHO[0]
0
6 5 4 3
2
LHI
CYNSE70032 #3
LHO[0]
1
0
6 5 4
3
CYNSE70032 #4
LHI
LHO[0]
1
0
2 1
LHI
0
6 5
4
CYNSE70032 LHI
#5
LHO[0]
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70032 #6
LHO[0]
1
LHI
1
1
BHI[2:0] 3
2
0
LHO[0]
BHI[2:0]
BHI[2:0]3
1
LHO[0]
3
LHI
CYNSE70032 #1
LHO[1]
SSV, SSF
2
0
5 4
LHI
CYNSE70032 #7
2
6
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 13-32. Hardware Diagram for a Block of up to Eight Devices
Document #: 38-02042 Rev. *E
Page 56 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
D1
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
D2
D3
D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2 Search4
(Miss on (Miss on
this device.)this device.)
Figure 13-33. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
Document #: 38-02042 Rev. *E
Page 57 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2 Search4
(Miss on
(Miss on
this device.)this device.)
Figure 13-34. Timing Diagram for Each Device Above the Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 58 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
z
z
A3
0
0
z
z
z
WE_L
z
OE_L
z
SSV
z
1
SSF
z
1
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
1
z
z
zz
Search1
Search3
(Miss on
(This device
this device.)global winner.)
Search2
(Miss on
this device.)
Search4
(Miss on
this device.)
Figure 13-35. Timing Diagram for Globally Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 59 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI(6:0) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2 Search4
(Miss on (Miss on
this device.)this device.)
Figure 13-36. Timing Diagram for Devices Below the Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 60 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2 Search4
(Miss on (Miss on
this device.)this device.)
Figure 13-37. Timing Diagram for Devices Above the Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 61 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
z
A2
z
z
z
0
z
z
0
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
1
Search1 Search3
(Miss on
(Hit but not
this device.) winner.)
Search2 Search4
(Global winner.) (Miss on
this device.)
Figure 13-38. Timing Diagram for Globally Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 62 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2 Search4
(Miss on
(Miss on
this device.) this device.)
Figure 13-39. Timing Diagram for Devices Below the Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 63 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2 Search4
(Miss on (Miss on
this device.)this device.)
Figure 13-40. Timing Diagram for Devices Above the Winning Device in Block Number 3
Document #: 38-02042 Rev. *E
Page 64 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search3
A B A B A B A B
D1 D2 D3 D4
z
A1
z
0
z
z
z
z
0
WE_L
z
OE_L
z
SSV
z
1
z
z
1
z
SSF
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
1
z
Search1 Search3
(Global (Miss on
winner.) this device.)
Search2 Search4
(Miss on
(Hit but not
global winner.) this device.)
Figure 13-41. Timing Diagram for Globally Winning Device in Block Number 3
Document #: 38-02042 Rev. *E
Page 65 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
Search2
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search3
(Miss on (Miss on
this device.)this device.)
Search2 Search4
(Miss on (Miss on
this device.)this device.)
Figure 13-42. Timing Diagram for Devices Below the Winning Device in Block Number 3
Except Device Number 30 (the Last Device)
Document #: 38-02042 Rev. *E
Page 66 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
Search3
01
01
01
01
Search2
Search4
A B A B A B A B
CMD[1:0]
CMD[8:2]
A B A B A B A B
D1 D2 D3 D4
DQ
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
z
SADR[21:0]
CE_L
0
ALE_L
0
WE_L
1
OE_L
z
0
z
0
z
1
0
SSV
0
SSF
0
z
z
1
0
CFG = 01010101, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0)] stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search3
(Hit on some (Hit on some
device above.)device above.)
Search4
Search2
(Global miss;
(Hit on some
device above.) this device is
default driver.)
Figure 13-43. Timing Diagram for Device Number 6 in Block Number 3
(Device Number 30 in Depth-Cascaded Table)
The following is the sequence of operation for a single 136-bit Search command (also refer to “Command and Command
Parameters,” Subsection 12.2 on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair for use in this Search operation. CMD[8:6] signals must be driven with the bits
that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data ([135:68]) in order
to be compared against all even locations. The CMD[2] signal must be driven to logic 0.
• Cycle B: The host ASIC continues to drive CMDV high and to apply Search command code (10) on CMD[1:0]. CMD[5:2] must
be driven by the index of the comparand register pair for storing the 136-bit word presented on the DQ bus during cycles A
and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching
Document #: 38-02042 Rev. *E
Page 67 of 126
CYNSE70032
entry and the hit flag (see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with 68-bit data ([67:0])to be compared
against all odd locations.
A logical 136-bit Search operation is shown in Figure 13-44. The entire table made up of 31 devices and consisting of 136-bit
entries is compared against a 136-bit word K that is presented on the DQ bus (using the GMR and local mask bits) in cycles A
and B of the command. The GMR is the 136-bit word specified by the even and odd global mask pair selected by the GMR Index
in the command’s cycle A.
The 136-bit word K that is presented on the DQ bus in cycles A and B of the command is also stored in the even and odd
comparand registers specified by the Comparand Register Index in the command’s cycle B. In ×136 configurations, the even and
odd comparand registers can subsequently be used by the Learn command in the first non-full device only. Note. The Learn
command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one
block. The word K that is presented on the DQ bus in cycles A and B of the command is compared with each entry in the table,
starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the SRAM
address on the SADR[21:0] lines (see Section 15.0, “SRAM Addressing” on page 98). The global winning device will drive the
bus in a specific cycle. In global miss cycles, the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV
= 1 (the default driving device for SSF and SSV signals) will be the default driver for such missed cycles. Note. During 136-bit
searches of 136-bit-configured tables, the Search hit will always be at an even address.
Must be same in each of the 31
devices
0
135
GMR
K
Even
A
Odd
B
Location 135
address
0
67
0
2
Comparand Register (even)
4
A
6
Comparand Register (odd)
B
L
0
(First matching entry)
Will be same in each of the 31
devices
507902
CFG = 01010101
(136-bit configuration)
Figure 13-44. x136 Table with 31 Devices
The Search command is a pipelined operation. It executes a Search at half the rate of the frequency of CLK2X for 136-bit searches
in ×136-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 136-bit Search command cycle
(two CLK2X cycles) is shown in Table 13-15.
Table 13-15. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
8K × 136 bits
64K × 136 bits
248K × 136 bits
Latency in CLK Cycles
4
5
6
Search latency from command to SRAM access cycle is 6 for 1–31 devices in the table and TLSZ = 10. In addition, SSV and
SSF shift further to the right for different values of HLAT, as specified in Table 13-16.
Table 13-16. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02042 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 68 of 126
CYNSE70032
13.7
272-bit Search on Tables Configured as ×272 using a Single CYNSE70032 Device
Figure 13-45 shows the timing diagram for a Search command in the 272-bit-configured table (CFG = 10101010) consisting of
a single device for one set of parameters: TLSZ = 00, HLAT = 001, LRAM = 1, and LDEV = 1. The hardware diagram for this
search subsystem is shown in Figure 13-46.
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search2
Search1
01
CMD[1:0]
01
CMD[2]
CMD[8:2]
A B A B A B A B
DQ
A B C D A B C D
D2
D1
SADR[21:0]
A1
CE_L
ALE_L
WE_L
1
0
1
1
0
1
1
0
OE_L
1
0
SSV
0
1
0
1
SSF
1
0
0
1
0
0
CFG = 10101010, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1.
Search1 Search2
Hit
Miss
Figure 13-45. Timing Diagram for 272-bit Search (One Device)
6
BHI[2:0]
DQ[67:0]
CMDV, CMD[8:0]
5
4
3
LHI
2
1
0
SRAM
CYNSE70032
SSF, SSV
BHI[2:0]
LHO[1]
LHO[0]
Figure 13-46. Hardware Diagram for a Table With One Device
The following is the sequence of operation for a single 136-bit Search command (also refer to Subsection 12.2, “Commands and
Command Parameters” on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair used for bits [271:136] of the data being searched. DQ[67:0] must be driven
with the 68-bit data ([271:204]) to be compared to all locations 0 in the four 68-bits-word page. The CMD[2] signal must be
driven to logic 1. Note. CMD[2] = 1 signals that the search is a x272-bit search. CMD[8:3] in this cycle is ignored.
Document #: 38-02042 Rev. *E
Page 69 of 126
CYNSE70032
• Cycle B: The host ASIC continues to drive CMDV high and continues to apply Search command code (10) on CMD[1:0]. The
DQ[67:0] is driven with the 68-bit data ([203:136]) to be compared to all locations 1 in the four 68-bits-word page.
• Cycle C: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair used for bits [135:0] of the data being searched. CMD[8:6] signals must be
driven with the bits that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data
([135:68]) to be compared to all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0.
• Cycle D: The host ASIC continues to drive the CMDV high and applies Search command code (10) on CMD[1:0]. CMD[8:6]
signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and hit flag
(see page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations
3 in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for x272 tables.
Note. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
The GMR index in cycle A selects a pair of GMRs that apply to DQ data in cycles A and B. The GMR index in cycle C selects a
pair of GMRs that apply to DQ data in cycles C and D.
The logical 272-bit Search operation is shown in Figure 13-47. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C. The 272-bit
word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared with each entry in the table starting
at location 0. The first matching entry’s location address L is the winning address that is driven as part of the SRAM address on
SADR[21:0] lines (see “SRAM Addressing” on page 98). Note. The matching address is always going to be location 0 in a
four-entry page for a 272-bit Search (two LSBs of the matching index will be 00).
271
0
GMR
A
K
Location 271
address
0
4
8
12
0
1
B
2
C
3
D
0
L
(First matching entry)
16380
CFG = 10101010
(272-bit configuration)
Figure 13-47. x272 Table with One Device
The Search command is a pipelined operation and executes at one-fourth the rate of the frequency of CLK2X for 272-bit searches
in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search command
(measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 13-17.
Table 13-17. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
4K × 272 bits
32K × 272 bits
124K × 272 bits
Latency in CLK Cycles
4
5
6
Search latency from command to SRAM access cycle is 4 for a single device in the table and TLSZ = 00. In addition, SSV and
SSF shift further to the right for different values of HLAT, as specified in Table 13-18.
Table 13-18. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
Document #: 38-02042 Rev. *E
Number of CLK Cycles
0
1
2
3
Page 70 of 126
CYNSE70032
Table 13-18. Shift of SSF and SSV from SADR (continued)
HLAT
100
101
110
111
13.8
Number of CLK Cycles
4
5
6
7
272-bit Search on Tables Configured as ×272 and Using up to Eight CYNSE70032 Devices
The hardware diagram of the Search subsystem of eight devices is shown in Figure 13-48. The following are the parameters
programmed into the eight devices.
• First seven devices (devices 0–6): CFG = 10101010, TLSZ = 01, HLAT = 000, LRAM = 0, and LDEV = 0.
• Eighth device (device 7): CFG = 10101010, TLSZ = 01, HLAT = 000, LRAM = 1, and LDEV = 1.
Note. All eight devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 7 in this case). All other upstream devices must be programmed with
LRAM = 0 and LDEV = 0 (devices 0 through 6 in this case).
Figure 13-49 shows the timing diagram for a Search command in the 272-bit-configured table of eight devices for device
number 0. Figure 13-50 shows the timing diagram for a Search command in the 272-bit-configured table of eight devices for
device number 1. Figure 13-51 shows the timing diagram for a Search command in the 272-bit-configured table of eight devices
for device number 7 (the last device in this specific table). For these timing diagrams, three 272-bit searches are performed
sequentially. The following Hit/Miss assumptions were made, as shown in Table 13-19.
Table 13-19. Hit/Miss Assumptions
Search Number
Device 0
Device 1
Devices 2–6
Device 7
Document #: 38-02042 Rev. *E
1
Hit
Miss
Miss
Miss
2
Miss
Hit
Miss
Miss
3
Miss
Miss
Miss
Miss
Page 71 of 126
CYNSE70032
SRAM
BHI[2:0]
6
LHO[1]
SSF, SSV
BHI[2:0]
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
3
LHI
CYNSE70032 #0
6
BHI[2:0]
5
5
4
4
LHO[1]
BHI[2:0]
2
6 5 4 3
LHI
CYNSE70032 #2
2
1
0
LHO[0]
1
0
6 5 4 3
2
LHI
CYNSE70032 #3
LHO[0]
1
0
6 5 4
3
CYNSE70032 #4
LHI
LHO[0]
1
0
BHI[2:0] 3
2 1
LHI
0
6 5
4
CYNSE70032 LHI
#5
LHO[0]
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70032 #6
LHO[0]
1
LHI
0
LHO[0]
BHI[2:0]
2
1
LHO[0]
3
LHI
CYNSE70032 #1
LHO[1]
BHI[2:0]3
2
0
5
4
LHI
CYNSE70032 #7
2
6
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 13-48. Hardware Diagram for a Table with Eight Devices
Document #: 38-02042 Rev. *E
Page 72 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
0
|(LHI[6:0])
LHO[1:0]
z
SADR[21:0]
z
CE_L
z
ALE_L
0
0
z
z
z
1
z
z
1
z
z
1
z
z
WE_L
A1
z
OE_L
SSV
SSF
CFG = 10101010, HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search2
Search3
(This device(Miss on (Miss on
is the globalthis device.)this device.)
winner.)
Figure 13-49. Timing Diagram for 272-bit Search Device Number 0
Document #: 38-02042 Rev. *E
Page 73 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
SADR[21:0]
z
CE_L
z
A2
0
z
ALE_L
0
z
WE_L
z
OE_L
z
SSV
z
1
z
SSF
z
1
z
CFG = 10101010, HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
1
Search1
(Miss on
this device.)
z
Search3
(Miss on
this device.)
Search2
(This device
is global winner.)
Figure 13-50. Timing Diagram for 272-bit Search Device Number 1
Document #: 38-02042 Rev. *E
Page 74 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
A B A B A B A B A B A B
CMD[8:2]
A B C D A B C D A B C D
D3
D2
D1
DQ
|(LHI[6:0])
LHO[1:0]
SADR[21:0]
CE_L
ALE_L
WE_L
z
z
z
z
0
0
0
0
1
OE_L
0
SSV
0
1
z
z
z
z
0
0
1
0
0
z
z
SSF
1
0
0
CFG = 10101010, HLAT = 000, TLSZ = 01, LRAM = 1, LDEV = 1.
Note: |(LHI[6:0]) stands for the boolean ‘OR’ of the entire bus LHI[6:0].
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search2 Search3
(Miss on
(Miss on (Global
this device.)this device.)miss.)
Figure 13-51. Timing Diagram for 272-bit Search Device Number 7 (Last Device)
The following is the sequence of operation for a single 272-bit Search command (also see “Commands and Command Parameters” on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair used for bits [271:136] of the data being searched in this operation. DQ[67:0]
must be driven with the 68-bit data ([271:204]) to be compared against all locations 0 in the four-word 68-bit page. The CMD[2]
signal must be driven to logic 1. Note. CMD[2] = 1 signals that the search is a x272 bit search. CMD[8:3] in this cycle is ignored.
• Cycle B: The host ASIC continues to drive CMDV high and applies Search command code (10) on CMD[1:0]. The DQ[67:0]
is driven with the 68-bit data ([203:136]) to be compared against all locations 1 in the four 68-bits-word page.
• Cycle C: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair used for bits [135:0] of the data being searched. CMD[8:6] signals must be
driven with the bits that will be driven on SADR[21:19] by this device if it has a hit. DQ[67:0] must be driven with the 68-bit data
([135:68]) to be compared against all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0.
• Cycle D: The host ASIC continues to drive CMDV high and applies Search command code (10) on CMD[1:0]. CMD[8:6] signals
must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag (see
page 14 for the description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations 3
in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for ×272 tables.
Note. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
The GMR index in cycle A selects a pair of GMRs in each of the eight devices that apply to DQ data in cycles A and B. The GMR
index in cycle C selects a pair of GMRs in each of the eight devices that apply to DQ data in cycles C and D.
Document #: 38-02042 Rev. *E
Page 75 of 126
CYNSE70032
The logical 272-bit Search operation is shown in Figure 13-52. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and the local mask bits. The GMR is
the 272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C in each of
the eight devices. The 272-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to
each entry in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as
part of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 98). Note. The matching address is always
going to be a location 0 in a four-entry page for 272-bit Search (two LSBs of the matching index will be 00).
271
0
0
A
GMR
K
1
B
2
C
Must be same in each of the eight
devices
3
D
Location 271
address
0
4
8
12
0
L
(First matching entry)
131068
CFG = 10101010
(272-bit configuration)
Figure 13-52. x272 Table with Eight Devices
The Search command is a pipelined operation and executes a Search at one-fourth the rate of the frequency of CLK2X for 272-bit
searches in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search
command (measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 13-20.
Table 13-20. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
4K × 272 bits
32K × 272 bits
124K × 272 bits
Latency in CLK Cycles
4
5
6
Search latency from command to SRAM access cycle is 5 for only a single device in the table and TLSZ = 01. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 13-21.
Table 13-21. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
13.9
Number of CLK Cycles
0
1
2
3
4
5
6
7
272-bit Search on Tables Configured as ×272 using up to 31 CYNSE70032 Devices
The hardware diagram of the search subsystem of 31 devices is shown in Figure 13-53. Each of the four blocks in the diagram
represents a block of eight CYNSE70032 devices, except the last which has seven devices. The diagram for a block of eight
devices is shown in Figure 13-54. The following are the parameters programmed into the 31 devices.
• First thirty devices (devices 0–29): CFG = 10101010, TLSZ = 10, HLAT = 000, LRAM = 0, and LDEV = 0.
• Thirty-first device (device 30): CFG = 10101010, TLSZ = 10, HLAT = 000, LRAM = 1, and LDEV = 1.
Document #: 38-02042 Rev. *E
Page 76 of 126
CYNSE70032
Note. All 31 devices must be programmed with the same value of TLSZ and HLAT. Only the last device in the table must be
programmed with LRAM = 1 and LDEV = 1 (device number 30 in this case). All other upstream devices must be programmed
with LRAM = 0 and LDEV = 0 (devices 0 through 29 in this case).
The timing diagrams referred to in this paragraph reference the HIT/MISS assumptions defined in Table 13-22. For the purpose
of illustrating the timings, it is further assumed that there is only one device with the matching entry in each block. Figure 13-55
shows the timing diagram for a Search command in the 272-bit-configured table consisting of 31 devices for each of the eight
devices in block number 0. Figure 13-56 shows the timing diagram for a Search command in the 272-bit-configured table of 31
devices for all devices above the winning device in block number 1. Figure 13-57 shows the timing diagram for the globally winning
device (the final winner within its own and all blocks) in block number 1. Figure 13-58 shows the timing diagram for all the devices
below the globally winning device in block number 1. Figure 13-59, Figure 13-60, and Figure 13-61, respectively, show the timing
diagrams of the devices above the globally winning device, the globally winning device, and the devices below the globally winning
device for block number 2. Figure 13-62, Figure 13-63, Figure 13-64, and Figure 13-65, respectively, show the timing diagrams
of the device above the globally winning device, the globally winning device, the devices below the globally winning device (except
device 30), and last device (device 30) for block number 3.
The 272-bit Search operation is pipelined and executes as follows. Four cycles from the last cycle of the Search command each
of the devices knows the outcome internal to it for that operation. In the fifth cycle from the Search command, the devices in a
block (less than or equal to eight devices resolving the winner within them using an LHI[6:0] and LHO[1:0] signalling mechanism)
arbitrate for a winner. In the sixth cycle after the Search command, the blocks of devices resolve the winning block through a
BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device for the
Search operation.
Table 13-22. Hit/Miss Assumptions
Search Number
Block 0
Block 1
Block 2
Block 3
1
Miss
Miss
Miss
Hit
2
Miss
Miss
Hit
Hit
BHI[2]
SSF, SSV
BHI[1]
3
Miss
Hit
Hit
Miss
BHI[0] GND
Block of 8 CYNSE70032s block 0 (devices 0–7)
BHO[1]
BHO[0]
BHO[2]
SRAM
BHI[2]
BHI[1]
BHI[0] GND
Block of 8 CYNSE70032s block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
GND
Block of 8 CYNSE70032s block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70032s block 3 (devices 24–30)
BHO[2]
BHO[1]
BHO[0]
CMD[8:0], CMDV
DQ[67:0]
Figure 13-53. Hardware Diagram for a Table with 31 Devices
Document #: 38-02042 Rev. *E
Page 77 of 126
CYNSE70032
SRAM
BHI[2:0]
6
BHI[2:0]
LHO[1]
BHI[2:0]
4
3
LHI
CYNSE70032 #0
6
5
BHI[2:0]
6
4
3
LHI
3
LHI
CYNSE70032 #2
LHO[1]
SSV, SSF
6
5
4
CYNSE70032 #3
LHO[1]
BHI[2:0]
6
5
CYNSE70032 #4
2 1
LHI
0
2
1
0
2
1
0
1
0
1
0
LHO[0]
BHI[2:0]
BHI[2:0] 3
1
LHO[0]
4
5
2
LHO[0]
CYNSE70032 #1
LHO[1]
DQ[67:0]
CMDV
CMD[8:0]
5
0
6
3
2
LHI
LHO[0]
4
3
LHI
LHO[0]
5
2
4
LHI
CYNSE70032 #5
LHO[0]
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70032 #6
LHO[0]
BHI[2:0]3
2
1
LHI
0
6
5 4
LHI
CYNSE70032 #7
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 13-54. Hardware Diagram for a Block of up to Eight Devices
Document #: 38-02042 Rev. *E
Page 78 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D2
D1
D3
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search2 Search3
Search1
(Miss on (Miss on (Miss on
this device.)this device.)this device.)
Figure 13-55. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device)
Document #: 38-02042 Rev. *E
Page 79 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search2 Search3
(Miss on (Miss on (Miss on
this device.)this device.)this device.)
Figure 13-56. Timing Diagram for Each Device Above the Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 80 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
z
SADR[21:0]
CE_L
ALE_L
z
z
WE_L
z
OE_L
z
SSV
z
A3
0
0
1
1
z
1
SSF
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Search1 Search2 Search3
Note: Each bit in BHO[2:0] is the same logical signal.
(Miss on
(Miss on (This device is
this device.) this device.)global winner.)
Note: Each bit in LHO[1:0] is the same logical signal.
Figure 13-57. Timing Diagram for Globally Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 81 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D1
D2
D3
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
BHO[2:0]
SADR[21:0]
CE_L
ALE_L
0
0
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search2 Search3
(Miss on
(Miss on (Miss on
this device.)this device.)this device.)
Figure 13-58. Timing Diagram for Devices Below the Winning Device in Block Number 1
Document #: 38-02042 Rev. *E
Page 82 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D1
D2
D3
|(LHI[6:0])
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
0
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search2 Search3
(Miss on (Miss on
(Miss on
this device.) this device.)this device.)
hit in block 0
or block 1.)
Figure 13-59. Timing Diagram for Devices Above the Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 83 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D1
D2
D3
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
z
z
A2
z
z
z
0
z
z
z
0
ALE_L
WE_L
z
OE_L
z
SSV
SSF
z
1
z
z
1
z
z
1
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search2 Search3
(Miss on
(Global (Hit but
this device.) winner.) not winner.)
Figure 13-60. Timing Diagram for Globally Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 84 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
LHO[1:0]
0
0
I(BHI[2:0])
0
BHO[2:0]
0
|(LHI[6:0])
SADR[21:0]
CE_L
ALE_L
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search2 Search3
(Miss on (Miss on (Miss on
this device.)this device.)this device.)
Figure 13-61. Timing Diagram for Devices Below the Winning Device in Block Number 2
Document #: 38-02042 Rev. *E
Page 85 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
0
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1 Search2 Search3
(Miss on (Miss on (Miss on
this device.)this device.)this device.)
Figure 13-62. Timing Diagram for Devices Above the Winning Device in Block Number 3
Document #: 38-02042 Rev. *E
Page 86 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
z
SADR[21:0]
CE_L
ALE_L
z
z
A1
z
z
0
z
0
1
z
z
1
z
z
1
z
WE_L
z
OE_L
z
SSV
SSF
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0].
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0].
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search2 Search3
(Global (Hit but not (Miss on
winner.) global winner.)this device.)
Figure 13-63. Timing Diagram for Globally WInning Device in Block Number 3
Document #: 38-02042 Rev. *E
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CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0])
LHO[1:0]
0
0
I(BHI[2:0])
0
BHO[2:0]
0
SADR[21:0]
CE_L
ALE_L
z
z
z
WE_L
z
OE_L
z
SSV
z
SSF
z
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
Search1
Search2 Search3
(Miss on (Miss on
(Miss on
this device.) this device.)this device.)
Figure 13-64. Timing Diagram for Devices Below the Winning Device
in Block Number 3 Except Device Number 30 (the Last Device)
Document #: 38-02042 Rev. *E
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CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1
01
CMD[1:0]
Search2
Search3
01
01
CMD[2]
CMD[8:2]
A B A B A B A B A B A B
DQ
A B C D A B C D A B C D
D3
D2
D1
|(LHI[6:0)]
0
LHO[1:0]
0
I(BHI[2:0])
0
BHO[2:0]
0
CE_L
ALE_L
WE_L
OE_L
SSV
SSF
z
z
SADR[21:0]
0
0
1
z
z
z
0
0
1
z
z
z
0
0
1
0
0
0
CFG = 10101010, HLAT = 000, TLSZ = 10, LRAM = 1, LDEV = 1.
Note: |(BHI[2:0]) stands for the boolean ‘OR’ of the entire bus BHI[2:0]
Note: |(LHI[6:0]) stands for the boolean ‘OR’ for the entire bus LHI[6:0]
Note: Each bit in BHO[2:0] is the same logical signal.
Note: Each bit in LHO[1:0] is the same logical signal.
z
z
0
0
z
z
0
0
Search1
Search2 Search3
(Hit on some (Hit on some (Hit on some
device above.)
device above.)
device above.)
Figure 13-65. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table)
The following is the sequence of operation for a single 272-bit Search command (also refer to Subsection 12.2, “Commands and
Command Parameters” on page 19).
• Cycle A: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair used for bits[271:136] of the data being searched. DQ[67:0] must be driven with
the 68-bit data ([271:204]) to be compared to all locations 0 in the four 68-bits-word page. The CMD[2] signal must be driven
to logic 1. Note. CMD[2] = 1 signals that the search is a x272-bit Search. CMD[8:6] is ignored in this cycle.
• Cycle B: The host ASIC continues to drive CMDV high and applies Search command (10) on CMD[1:0]. The DQ[67:0] is
driven with the 68-bit data ([203:136]) to be compared to all locations 1 in the four 68-bits-word page.
• Cycle C: The host ASIC drives CMDV high and applies Search command code (10) on CMD[1:0] signals. CMD[5:3] signals
must be driven with the index to the GMR pair used for the bits [135:0] of the data being searched. CMD[8:6] signals must be
driven with the bits that will be driven by this device on SADR[21:19] if it has a hit. DQ[67:0] must be driven with the 68-bit data
([135:68]) to be compared to all locations 2 in the four 68-bits-word page. The CMD[2] signal must be driven to logic 0.
Document #: 38-02042 Rev. *E
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CYNSE70032
• Cycle D: The host ASIC continues to drive CMDV high and to apply Search command code (10) on CMD[1:0]. CMD[8:6]
signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag
(see page 14 for a description of SSR[0:7]). The DQ[67:0] is driven with the 68-bit data ([67:0]) to be compared to all locations 3
in the four 68-bits-word page. CMD[5:2] is ignored because the Learn instruction is not supported for ×272 tables.
Note. For 272-bit searches, the host ASIC must supply four distinct 68-bit data words on DQ[67:0] during cycles A, B, C, and D.
The GMR Index in cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles A and B. The GMR
Index in cycle C selects a pair of GMRs in each of the 31 devices that apply to DQ data in cycles C and D.
The logical 272-bit Search operation is as shown in Figure 13-66. The entire table of 272-bit entries is compared to a 272-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
272-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command’s cycles A and C in each of the
31 devices. The 272-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to each
entry in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part
of the SRAM address on the SADR[21:0] lines (see “SRAM Addressing” on page 98). Note. The matching address is always going
to be location 0 in a four-entry page for 272-bit search (two LSBs of the matching index will be 00).
0
271
Must be same in each of the 31
devices
2
3
0
1
GMR
D
C
B
A
K
Location 271
address
0
4
8
12
0
L
(First matching entry)
507900
CFG = 10101010
(272-bit configuration)
Figure 13-66. x272 Table with 31 Devices
The Search command is a pipelined operation that executes a Search at one-fourth the rate of the frequency of CLK2X for 272-bit
searches in ×272-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 272-bit Search
command (measured in CLK cycles) from the CLK2X cycle containing the C and D cycles is shown in Table 13-23.
Table 13-23. Search Latency from Instruction to SRAM Access Cycle
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Max Table Size
4K × 272 bits
32K × 272 bits
124K × 272 bits
Latency in CLK Cycles
4
5
6
Search latency from command to SRAM access cycle is 6 only for a single device in the table with TLSZ = 10. In addition, SSV
and SSF shift further to the right for different values of HLAT, as specified in Table 13-24.
Table 13-24. Shift of SSF and SSV from SADR
HLAT
000
001
010
011
100
101
110
111
Document #: 38-02042 Rev. *E
Number of CLK Cycles
0
1
2
3
4
5
6
7
Page 90 of 126
CYNSE70032
13.10
Mixed-Size Searches on Tables Configured with Different Widths Using an CYNSE70032 Device
This subsection will cover mixed searches (×68, ×136, and ×272) with tables of different widths (×68, ×136, ×272). The sample
operation shown is for a single device with CFG = 10010000 containing three tables of ×68, ×136, and ×272 widths. The operation
can be generalized to a block of 8–31 devices using four blocks; the timing and the pipeline operation is the same as described
previously for fixed searches on a table of one-width-size.
Figure 13-67 shows three sequential searches: first, a 68-bit Search on the table configured as ×68, then a 136-bit search on a
table configured as ×136, and finally a 272-bit search on the table configured as ×272 bits. Each results in a hit. Note. The
DQ[67:66] will be 00 in each of the two A and B cycles of the ×68-bit Search (Search1). DQ[67:66] is 01 in each of the A and B
cycles of the ×136-bit Search (Search2). DQ[67:66] is 10 in each of the A, B, C, and D cycles of the ×272-bit Search (Search3).
By having table designation bits, the CYNSE70032 device enables the creation of many tables of different widths in a bank of
search engines.
Figure 13-68 shows the sample table. Two bits in each 68-bit entry need to designated as table number bits. One example choice
might be: the 00 values for the table configured as ×68, 01 values for tables configured as ×136, and 10 values for tables
configured as ×272. For the above explanation, it is further assumed that bits[67:66] for each entry will be designed as such table
designation bits.
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Search1 Search3
01
01
01
Search2
CMD[1:0]
CMD[2]
CMD[8:2]
A B A B A B A B
DQ
A B A B A B C D
D3
D1 D2
SADR[21:0]
A1
A3
A2
CE_L
1
0
1
0
1
ALE_L
1
0
1
0
1
WE_L
1
0
OE_L
1
0
SSV
0
1
0
1
0
SSF
0
1
0
1
0
1
0
Search3
CFG = 1010101010101010, HLAT = 010, TLSZ = 00, LRAM = 1, LDEV = Search1
1 ×68 hitSearch2
×136 hit
×272 hit
Figure 13-67. Timing Diagram for Mixed Search (One Device)
68
8K
2K
1K
136
272
CFG = 10010000
Figure 13-68. Multiwidth Configurations Example
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CYNSE70032
13.11
LRAM and LDEV Description
When search engines are cascaded using multiple CYNSE70032 devices, the SADR, CE_L, and WE_L (three-state signals) are
all tied together. To eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For
non-Search or non-Learn cycles (see Subsection 13.12, “Learn Command” on page 92) or Search cycles with a global miss, the
SADR, CE_L, and WE_L signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of
cascaded search engines have this bit set. Failure to do so will cause contention on SADR, CE_L, and WE_L, and can potentially
cause damage to the device(s).
Similarly, when search engines using multiple CYNSE70032 devices are cascaded, SSF and SSV (also three-state signals) are
tied together. To eliminate external pull-up and pull downs, one device in a bank is designated as the default driver. For nonSearch
cycles or Search cycles with a global miss, the SSF and SSV signals are driven by the device with the LDEV bit set. It is important
that only one device in a bank of cascaded search engines have this bit set. Failure to do so will cause contention on SSV and
SSF and can potentially cause damage to the device(s).
13.12
Learn Command
Bit[0] of each 68-bit data location specifies whether an entry in the database is occupied. If all the entries in a device are occupied,
the device asserts FULO signal to inform the downstream devices that it is full. The result of this communication between
depth-cascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines
the fullness of the depth-cascaded table.
The device contains sixteen pairs of internal, 68-bit-wide comparand registers that store the comparands as the device executes
searches. On a miss by the Search (signalled to ASIC through the SSV and SSF signals [SSV = 1, SSF = 0]), the host ASIC can
apply the Learn command to Learn the entry from a comparand register to the next-free location (see Subsection 9.3, “NFA
Register” on page 16). The NFA updates to the next-free location following each Write or Learn command.
In a depth-cascaded table, only a single device will Learn the entry through the application of a Learn instruction. The determination of the Learn device is based on the FULI and FULO signalling between the devices. The first non-full device learns the
entry by storing the contents of the specified comparand registers to the location(s) pointed to by NFA.
In a ×68-configured table the Learn command writes a single 68-bit location. In a ×136-configured table the Learn command
writes the next even and odd 68-bit locations. In 136-bit mode, bit[0] of the even and odd 68-bit locations is 0, indicating that they
are cascaded empty, or 1, which indicates that they are occupied.
The global FULL signal indicates to the table controller (the host ASIC) that all entries within a block are occupied and that no
more entries can be learned. The CYNSE70032 device updates the signal to a data array after each Write or Learn command.
Also using the NFA register as part of the SRAM address, the Learn command generates a Write cycle to the external SRAM
(see Section 15.0, “SRAM Addressing” on page 98).
The Learn command is supported on a single block containing up to eight devices if the table is configured as either a ×68 or a
×136. The Learn command is not supported for ×272-configured tables.
Learn is a pipelined operation and lasts for two CLK cycles where TLSZ = 00, as shown in Figure 13-69, and TLSZ = 01 as shown
in Figure 13-70 and Figure 13-71. Figure 13-70 and Figure 13-71 assume that the device performing the Learn operation is not
the last device in the table and has its LRAM bit set to 0. Note. The OE_L for the device with the LRAM bit set goes high for two
cycles for each Learn (one during the SRAM Write cycle, and one during the cycle before it). The latency of the SRAM Write cycle
from the second cycle of the instruction is shown in Table 13-25.
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CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Learn1 X Learn2 X
CMD[1:0]
Comp2
Comp1
X
X
CMD[8:2]
1A 1B
DQ
SADR[21:0]
z
X
X
X
X
z
z
CE_L
1
WE_L
1
OE_L
0
SSV
0
SSF
0
A1
0
0
z
z
A2
0
0
1
1
1
0
TLSZ = 00, LRAM = 1, LDEV = 1.
Figure 13-69. Learn Timing Diagram (TLSZ = 00)
Document #: 38-02042 Rev. *E
Page 93 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Learn1 X Learn2 X
CMD[1:0]
Comp2
Comp1
X
X
CMD[8:2]
1A 1B
DQ
SADR[21:0]
z
X
X
z
CE_L
z
WE_L
z
OE_L
z
SSV
z
SSF
z
X
X
z
A1
z
A2
0
0
0
0
z
TLSZ = 01, LRAM = 0, LDEV = 0.
Figure 13-70. Learn Timing Diagram (TLSZ = 01 [Except on the Last Device])
Document #: 38-02042 Rev. *E
Page 94 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
2
3
4
5
6
7
8
9
10
1
CLK2X
PHS_L
CMDV
Learn1 X Learn2 X
CMD[1:0]
Comp2
Comp1
X
X
CMD[8:2]
1A 1B
DQ
SADR[21:0]
CE_L
WE_L
z
X
X
X
X
z
z
z
z
1
z
1
OE_L
0
SSV
0
SSF
0
z
1
1
z
z
z
1
1
1
0
TLSZ = 01, LRAM = 1, LDEV = 1.
Figure 13-71. Learn Timing Diagram on Device Number 7 (TLSZ = 01)
Table 13-25. SRAM Write Cycle Latency from Second Cycle of Learn Instruction
Number of Devices
1 (TLSZ = 00)
1–8 (TLSZ = 01)
1–31 (TLSZ = 10)
Latency in CLK Cycles
4
5
6
The Learn operation lasts two CLK cycles. The sequence of operation is as follows.
• Cycle 1A: The host ASIC applies the Learn instruction on CMD[1:0] using CMDV = 1. The CMD[5:2] field specifies the index
of the comparand register pair that will be written to the data array in the 136-bit-configured table. For a Learn in a 68-bit-configured table, the even-numbered comparand specified by this index will be written. CMD[8:6] carries the bits that will be driven
on SADR[21:19] in the SRAM Write cycle.
• Cycle 1B: The host ASIC continues to drive CMDV to 1, CMD[1:0] to 11, and CMD[5:2] with the comparand pair index. CMD[6]
must be set to 0 if the Learn is being performed on a 68-bit-configured table, and to 1 if the Learn is being performed on a
136-bit-configured table.
• Cycle 2: The host ASIC drives CMDV to 0.
Document #: 38-02042 Rev. *E
Page 95 of 126
CYNSE70032
At the end of cycle 2, a new instruction can begin. SRAM Write latency is the same as the Search to the SRAM read cycle (it is
measured from the second cycle of the Learn instruction).
14.0
Depth-Cascading
The search engine application can depth-cascade the devices to various table sizes of different widths (68 bits, 136 bits, or 272
bits). The devices perform all the necessary arbitration to decide which device will drive the SRAM bus. Search latency increases
as table size increases; the Search rate itself remains constant.
14.1
Depth-Cascading up to Eight Devices (One Block)
Figure 14-1 shows how up to eight devices can be cascaded to form 256K × 68-bit, 128K × 136-bit, or 64K × 272-bit tables. It
also shows the interconnection between devices for depth-cascading. Each search engine asserts LHO[1] and LHO[0] signals
to inform downstream devices of its results. The LHI[6:0] signals for a device are connected to LHO signals of the upstream
devices. The host ASIC must program the TLSZ to 01 for each of up to eight devices in a block. A single device alone drives the
SRAM bus in any single cycle.
SRAM
BHI[2:0]
6 5 4 3 2 1 0
CYNSE70032 #0
LHI
LHO[1]
LHO[0]
SSF, SSV
BHI[2:0]
DQ[67:0]
CMDV
CMD[8:0]
6
5
4
CYNSE70032 #1
LHO[1]
BHI[2:0]
6
4
5
CYNSE70032 #2
LHO[1]
BHI[2:0]
LHO[1]
BHI[2:0]
5
6
5
CYNSE70032 #4
BHI[2:0] 3
2 1
LHI
0
BHI[2:0] 3
2
1
LHI
0
BHI[2:0]3
6
4
CYNSE70032 #3
2
1
LHI
6
3
LHI
2
3
LHI
2
1
LHO[0]
1
0
1
0
1
0
LHO[0]
3
2
LHI
LHO[0]
4
3
LHI
LHO[0]
0
2
5
4
LHO[0]
LHI
CYNSE70032 #5
6
5
CYNSE70032 #6LHI
4
LHO[0]
0
6
5
CYNSE70032 #7
LHI
4
BHO[0]
BHO[1]
BHO[2]
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 14-1. Depth-Cascading to Form a Single Block
Document #: 38-02042 Rev. *E
Page 96 of 126
CYNSE70032
14.2
Depth-Cascading up to 31 Devices (Four Blocks)
Figure 14-2 shows how to cascade up to four blocks. Each block except the last contains up to eight CYNSE70032 devices. The
interconnection within each has been shown in the previous subsection with the cascading of up to eight devices in a block. Note.
The interconnection between blocks for depth-cascading is important. For each Search, a block asserts BHO[2], BHO[1], and
BHO[0]. The BHO[2:0] signals for a block are taken only from the last device in the block. For all other devices within that block,
these signals stay open and floating. The host ASIC must program the TLSZ field to 10 in each of the devices for cascading up
to 31 devices (in up to four blocks).
BHI[2]
SSF, SSV
BHI[1]
BHI[0] GND
Block of 8 CYNSE70032s Block 0 (devices 0–7)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
BHI[2]
BHI[1]
BHI[0]
SRAM
GND
Block of 8 CYNSE70032s Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
GND
Block of 8 CYNSE70032s Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70032s Block 3 (devices 24-30)
DQ[67:0]
BHO[2]
BHO[1]
BHO[0]
CMD[8:0], CMDV
Figure 14-2. Depth-Cascading Four Blocks
14.3
Depth-Cascading for a FULL Signal
Bit[0] of each of the 68-bit entries is designated as a special bit (1 = occupied; 0 = empty). For each Learn or PIO Write to the
data array, each device asserts FULO[1] and FULO[0] if it does not have any empty locations within it (see Figure 14-3). Each
device combines the FULO signals from the devices above it with its own full status to generate a FULL signal, which will then
give a full status of the table up to the device asserting the FULL signal. Figure 14-3 shows the hardware connection diagram for
generating the FULL signal that goes back to the ASIC. In a depth-cascaded block of up to eight devices, the FULL signal from
the last device should be fed back to the ASIC controller to indicate the fullness of the table. The FULL signal of the other devices
should be left open. Note. The Learn instruction is supported for up to eight devices, whereas FULL cascading is allowed for one
block in tables containing more than eight devices. In tables for which a Learn instruction will not be used, the bit[0] of each 68-bit
entry should always be set to 1.
Document #: 38-02042 Rev. *E
Page 97 of 126
CYNSE70032
VDDQ
DQ[67:0]
6
5
4 3
FULI
CYNSE70032
2
FULO[1]
1
0
FULO[0]
FULL
6
5
4 3
FULI
CYNSE70032
2
1
VDDQ
0
FULO[0]
FULO[1]
FULL
6
5
4 3
FULI
CYNSE70032
FULO[1]
2
1
VDDQ
0
FULO[0]
6
5
4 3
FULI
CYNSE70032
FULO[1]
2
1
FULL
VDDQ
FULL
VDDQ
FULL
VDDQ
FULL
VDDQ
0
FULO[0]
6
5
4 3
FULI
CYNSE70032
2
1
0
FULO[0]
3
2 1
FULI
0
6
4 FULI
5
CYNSE70032
FULO[0]
3
2 1
FULI
0
6
5
CYNSE70032
4
FULI
FULO[0]
FULL
3
2 1
FULI
0
6
5
CYNSE70032
4
FULI
FULL
FULO[1] FULO[0]
Figure 14-3. FULL Generation in a Cascaded Table
15.0
SRAM Addressing
Table 15-1 describes the commands used to generate addresses on the SRAM address bus. The index[13:0] field contains the
address of a 68-bit entry that results in a hit in 68-bit-configured partition. It is the address of the 68-bit entry that lies at the 136-bit
page, and the 272-bit page boundaries in 136-bit- and 272-bit-configured quadrants, respectively.
Section 7.0, “Registers” on page 13 of this specification, describes the NFA and SSR registers. ADR[13:0] contains the address
supplied on the DQ bus during PIO access to the CYNSE70032. Command bits 8, and 7 {CMD[8:6]} are passed from the
command to the SRAM address bus. See Section 12.0, “Commands” on page 18, for more information. ID[4:0] is the ID of the
device driving the SRAM bus (see Section 21.0, “Pinout Descriptions and Package Diagrams” on page 120, for more information).
Document #: 38-02042 Rev. *E
Page 98 of 126
CYNSE70032
15.1
Generating an SRAM BUS Address
Table 15-1 details SRAM bus address generation.
Table 15-1. SRAM Bus Address
Command
Search
Learn
PIO Read
PIO Write
Indirect Access
15.2
SRAM Operation
Read
Write
Read
Write
Write/Read
21
C8
C8
C8
C8
C8
20
C7
C7
C7
C7
C7
19
C6
C6
C6
C6
C6
[18:14]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
ID[4:0]
[13:0]
Index[13:0]
NFA[13:0]
ADR13:0]
ADR[13:0]
SSR[13:0]
SRAM PIO Access
The remainder of Section 15.0 describes SRAM Read and SRAM Write operations.
SRAM Read enables Read access to the off-chip SRAM that contains associative data. The latency from the issuance of the
Read instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the value programmed for the TLSZ parameter in the device configuration register. The latency of the ACK from the Read
instruction is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed into the
configuration register. Note. SRAM Read is a blocking operation—no new instruction can begin until the ACK is returned by the
selected device performing the access.
SRAM Write enables Write access to the off-chip SRAM containing associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed into the device configuration register. Note. SRAM Write is a pipelined operation—new
instruction can begin right after the previous command has ended.
15.3
SRAM Read with a Table of One Device
SRAM Read enables Read access to the off-chip SRAM that contains associative data. The latency from the issuance of the
Read instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction and will depend
on the TLSZ value parameter programmed into the device configuration register. The latency of the ACK from the Read instruction
is the same as the latency of the Search instruction to the SRAM address plus the HLAT programmed into the configuration
register. The following explains the SRAM Read operation in a table with only one device and having the following parameters:
TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 15-1 shows the associated timing diagram. For the following
description, the selected device refers only to the device in the table because it is the only device to be accessed.
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. During this cycle, the host ASIC also supplies SADR[21:19] on CMD[8:6].
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address with DQ[20:19] set to 10 to select the SRAM address.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0] and drives ACK from High-Z to LOW.
• Cycle 5: The selected device drives the Read address on SADR[21:0]; it also drives ACK HIGH, CE_L LOW, and ALE_L LOW.
• Cycle 6: The selected device drives CE_L HIGH, ALE_L HIGH, the SADR bus, the DQ bus in a three-state condition, and
ACK LOW.
At the end of cycle 6, the selected device floats ACK in a three-state condition, and a new command can begin.
Document #: 38-02042 Rev. *E
Page 99 of 126
CYNSE70032
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
Read
CMD[8:2]
A
Address
DQ
OE_L
WE_L
B
z
z
0
1
CE_L
1
0
1
ALE_L
1
0
1
SADR
z
ACK
z
SSV
0
SSF
0
Address
0
1
z
z
0
DQ driven by CYNSE70032.
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1.
Figure 15-1. SRAM Read ACCESS (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
15.4
SRAM Read with a Table of up to Eight Devices
The following explains the SRAM Read operation completed through a table of up to eight devices using the following parameter:
TLSZ = 01. Figure 15-2 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved
through CYNSE70032 device number 0. Figure 15-3 and Figure 15-4 show timing diagrams for device number 0 and device
number 7, respectively.
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. During this cycle the host ASIC also supplies SADR[21:19] on CMD[8:6].
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10 to select the SRAM address.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0].
• Cycle 5: The selected device continues to drive DQ[67:0] and drives ACK from high-Z to low.
• Cycle 6: The selected device drives the Read address on SADR[21:0]. It also drives ACK high, CE_L low, WE_L high, and
ALE_L low.
• Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and DQ bus in a three-state condition. It continues to drive ACK low.
At the end of cycle 7, the selected device floats ACK in a three-state condition, and a new command can begin.
Document #: 38-02042 Rev. *E
Page 100 of 126
CYNSE70032
SRAM
BHI[2:0]
6
LHO[1]
SSF, SSV
DQ[67:0]
CMDV
CMD[8:0]
BHI[2:0]
5
4
3
LHI
CYNSE70032 #0
6
5
6
BHI[2:0]
4
5
3
LHI
3
LHI
4
LHO[1]
2
1
0
2
1
0
1
0
1
0
LHO[0]
BHI[2:0]
6
5
4
CYNSE70032 #3
LHO[1]
BHI[2:0]
6
5
CYNSE70032 #4
2 1
LHI
0
LHO[0]
CYNSE70032 #2
BHI[2:0] 3
1
LHO[0]
CYNSE70032 #1
LHO[1]
2
0
6
3
2
LHI
LHO[0]
4
3
LHI
LHO[0]
5
2
4
LHI
CYNSE70032 #5
LHO[0]
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70032 #6
LHO[0]
BHI[2:0]3
2
1
LHI
0
6
5
LHI
4
BHO[0]
BHO[1]
BHO[2]
CYNSE70032 #7
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 15-2. Table of a Block of Eight Devices
Document #: 38-02042 Rev. *E
Page 101 of 126
CYNSE70032
cycle
2
cycle
1
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
CLK2X
PHS_L
CMDV
CMD[1:0]
Read
CMD[8:2]
A
B
Address
DQ
OE_L
z
WE_L
z
CE_L
z
z
z
1
z
z
0
ALE_L
z
z
0
SADR
z
Address
z
0
SSV
z
SSF
z
TLSZ = 01, HLAT = 000, LRAM = 0, LDEV = 0.
1
0
DQ Driven by Selected CYNSE70032.
Figure 15-3. SRAM Read Through Device Number 0 in a Block of Eight Devices
Document #: 38-02042 Rev. *E
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CYNSE70032
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
Read
CMD[8:2]
A
Address
DQ
OE_L
WE_L
B
z
0
1
z
1
CE_L
1
z
1
ALE_L
1
z
z
z
1
SADR
ACK
z
SSV
z
SSF
z
TLSZ = 01, HLAT = 000, LRAM = 1, LDEV = 1.
Figure 15-4. SRAM Read Timing for Device Number 7 in a Block of Eight Devices
15.5
SRAM Read with a Table of up to 31 Devices
The following explains the SRAM Read operation accomplished through a table of up to 31 devices using the following parameters: TLSZ = 10. The diagram of this table is shown in Figure 15-5. The following assumes that SRAM access is being accomplished through CYNSE70032 device number 0 and that device number 0 is the selected device. Figure 15-6 and Figure 15-7
show the timing diagrams for device number 0 and device number 30, respectively.
• Cycle 1A: The host ASIC applies the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. During this cycle, the host ASIC also supplies SADR[21:19] on CMD[8:6].
• Cycle 1B: The host ASIC continues to apply the Read instruction to CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address.
• Cycle 2: The host ASIC floats DQ[67:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[67:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[67:0].
• Cycles 5 to 6: The selected device continues to drive DQ[67:0].
• Cycle 7: The selected device continues to drive DQ[67:0] and drives an SRAM Read cycle.
• Cycle 8: The selected device drives ACL from Z to LOW.
• Cycle 9: The selected device drives ACK to HIGH.
• Cycle 10: The selected device drives ACK from HIGH to LOW.
At the end of cycle 10, the selected device floats ACL in a three-state condition.
Document #: 38-02042 Rev. *E
Page 103 of 126
CYNSE70032
BHI[2]
BHI[1]
BHI[0] GND
Block of 8 CYNSE70032s Block 0 (devices 0–7)
BHO[2]
BHO[1]
BHO[0]
SSF, SSV
BHI[2]
BHI[1]
BHI[0]
BHI[2]
BHI[1]
BHI[0] GND
SRAM
GND
Block of 8 CYNSE70032s Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
Block of 8 CYNSE70032s Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
DQ[67:0]
CMD[8:0], CMDV
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70032s Block 3 (devices 24–30)
BHO[2]
BHO[1]
BHO[0]
Figure 15-5. Table of 31 Devices Made of Four Blocks
Document #: 38-02042 Rev. *E
Page 104 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Read
00
CMD[1:0]
CMD[8:2]
A B
Address
DQ
OE_L
WE_L
z
z
CE_L
z
ALE_L
z
SADR[21:0]
z
ACK
z
1
z
z
0
z
0
Address
z
0
SSV
z
SSF
z
TLSZ = 10, HLAT = 010, LRAM = 0, LDEV = 0.
1
0
z
DQ driven by the selected CYNSE70032
Figure 15-6. SRAM Read Through Device Number 0 in a Bank of 31 Devices
(Device Number 0 Timing)
Document #: 38-02042 Rev. *E
Page 105 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Read
00
CMD[1:0]
CMD[8:2]
A B
Address
DQ
OE_L
WE_L
CE_L
ALE_L
0
1
z
1
1
z
1
1
z
z
1
SADR[21:0]
ACK
z
SSV
0
SSF
0
TLSZ = 10, HLAT = 010, LRAM = 1, LDEV = 1
Figure 15-7. SRAM Readthrough Device Number 0 in a Bank of 31 Devices
(Device Number 30 Timing)
15.6
SRAM Write with a Table of One Device
SRAM Write enables write access to the off-chip SRAM that contains associative data. The latency from the second cycle of the
Write instruction to the address appearing on the SRAM bus is the same as the latency of the Search instruction, and will depend
on the TLSZ value parameter programmed into the device configuration register. The following explains the SRAM Write operation
accomplished through a table of only one device with the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and
LDEV = 1. Figure 15-8 shows the timing diagram. For the following description, the selected device refers to the only device in
the table as this is the only device that will be accessed.
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write,
because burst Writes into the SRAM are not supported.
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write, because burst
Writes into the SRAM are not supported.
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
At the end of cycle 3, a new command can begin. The write is a pipelined operation; however, the Write cycle appears at the
SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command).
Document #: 38-02042 Rev. *E
Page 106 of 126
CYNSE70032
cycle
1
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
CLK2X
PHS_L
CMDV
CMD[1:0]
Write
CMD[8:2]
A
B
Address
DQ
x
xx
OE_L
0
WE_L
1
0
CE_L
1
0
ALE_L
SADR
ACK
1
z
1
0
Address
z
SSV
0
SSF
0
TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1
Figure 15-8. SRAM Write Access (TLSZ = 00, HLAT = 000, LRAM = 1, LDEV = 1)
15.7
SRAM Write with a Table of up to Eight Devices
The following explains the SRAM Write operation done via a table(s) of up to eight devices with the following parameters:
TLSZ = 01. The diagram of this table is shown in Figure 15-9. The following assumes that SRAM access is getting done through
CYNSE70032 device number 0. Figure 15-10 and Figure 15-11 show the timing diagram for the device number 0 and device
number 7, respectively.
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write,
because burst Writes into the SRAM are not supported.
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write, because burst
Writes into the SRAM are not supported.
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation; however, the Write cycle appears at the
SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command).
Document #: 38-02042 Rev. *E
Page 107 of 126
CYNSE70032
SRAM
BHI[2:0]
6
LHO[1]
SSF, SSV
DQ[67:0]
CMDV
CMD[8:0]
BHI[2:0]
5
4
3
LHI
CYNSE70032 #0
6
5
6
BHI[2:0]
4
5
3
LHI
3
LHI
4
LHO[1]
2
1
0
2
1
0
1
0
1
0
LHO[0]
BHI[2:0]
6
5
4
CYNSE70032 #3
LHO[1]
BHI[2:0]
6
5
CYNSE70032 #4
2 1
LHI
0
LHO[0]
CYNSE70032 #2
BHI[2:0] 3
1
LHO[0]
CYNSE70032 #1
LHO[1]
2
0
6
3
2
LHI
LHO[0]
4
3
LHI
LHO[0]
5
2
4
LHI
CYNSE70032 #5
LHO[0]
BHI[2:0] 3
2
1
LHI
0
6
5 4
LHI
CYNSE70032 #6
LHO[0]
BHI[2:0]3
2
1
LHI
0
6
5
LHI
4
BHO[0]
BHO[1]
BHO[2]
CYNSE70032 #7
BHO[0]
BHO[1]
BHO[2]
LHO[1] LHO[0]
Figure 15-9. Table of a Block of Eight Devices
Document #: 38-02042 Rev. *E
Page 108 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Write
01
CMD[1:0]
CMD[8:2]
A B
Address
x
DQ
OE_L
z
WE_L
z
CE_L
x
z
0
z
0
ALE_L
z
SADR[21:0]
z
ACK
z
SSV
z
SSF
z
0
Address
z
z
z
z
TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0
Figure 15-10. SRAM Write Through Device Number 0 in a Block of Eight Devices
Document #: 38-02042 Rev. *E
Page 109 of 126
CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Write
01
CMD[1:0]
CMD[8:2]
A B
Address
x
DQ
OE_L
WE_L
CE_L
x
0
0
1
1
z
1
1
z
1
1
z
1
ALE_L
z
SADR[21:0]
ACK
z
SSV
0
SSF
0
TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1
Figure 15-11. SRAM Write Timing for Device Number 7 in a Block of Eight Devices
15.8
SRAM Write with Table(s) Consisting of up to 31 Devices
The following explains the SRAM Write operation done via a table(s) of up to 31 devices and with the following parameters:
TLSZ = 10. The diagram of this table(s) is shown in Figure 15-12. The following assumes that SRAM access is accomplished
through CYNSE70032 device number 0 (the selected device). Figure 15-13 and Figure 15-14 show the timing diagram for device
number 0 and device number 30, respectively.
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle. Note. CMD[2] must be set to 0 for SRAM Write,
because burst Writes into the SRAM are not supported.
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address. Note. CMD[2] must be set to 0 for SRAM Write, because burst
WriteS into the SRAM are not supported.
• Cycle 2: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
• Cycle 3: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation; however, the Write cycle appears at the
SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command).
Document #: 38-02042 Rev. *E
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CYNSE70032
BHI[2]
BHI[1]
BHI[0] GND
Block of 8 CYNSE70032s Block 0 (devices 0–7)
BHO[2]
BHO[1]
BHO[0]
SSF, SSV
BHI[2]
BHI[1]
BHI[0]
BHI[2]
BHI[1]
BHI[0]
SRAM
GND
Block of 8 CYNSE70032s Block 1 (devices 8–15)
BHO[2]
BHO[1]
BHO[0]
GND
Block of 8 CYNSE70032s Block 2 (devices 16–23)
BHO[2]
BHO[1]
BHO[0]
DQ[67:0]
CMD[8:0], CMDV
BHI[2]
BHI[1]
BHI[0]
Block of 7 CYNSE70032s Block 3 (devices 24–30)
BHO[2]
BHO[1]
BHO[0]
Figure 15-12. Table of 31 Devices (Four Blocks)
Document #: 38-02042 Rev. *E
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CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Write
01
CMD[1:0]
CMD[8:2]
A B
Address
x
DQ
OE_L
z
WE_L
z
CE_L
z
ALE_L
z
SADR[21:0]
z
ACK
z
SSV
z
SSF
z
x
z
0
0
0
Address
z
z
z
z
TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0.
Figure 15-13. SRAM Write Through Device Number 0 in a Bank of 31 Devices (Device 0 Timing)
Document #: 38-02042 Rev. *E
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CYNSE70032
cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1
2
3
4
5
6
7
8
9
10
CLK2X
PHS_L
CMDV
Write
01
CMD[1:0]
CMD[8:2]
A B
Address
x
DQ
OE_L
WE_L
CE_L
ALE_L
x
0
1
1
z
1
1
z
1
1
z
1
z
SADR[21:0]
ACK
z
SSV
0
SSF
0
TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1.
Figure 15-14. SRAM Write Through Device Number 0 in a Bank of 31 CYNSE70032 Devices
(Device Number 30 Timing)
Document #: 38-02042 Rev. *E
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CYNSE70032
16.0
Power
16.1
The Proper Power-up Sequence
Proper power-up sequence is required to correctly initialize the Cypress Network Search Engines before functional access to the
device can begin. RST_L and TRST_L should be held low before the power supplies ramp-up. RST_L must be set low for a
duration of time afterward and then set high. The following steps describe the proper power-up sequence.
1. Set RST_L and TRST_L low.
2. Power up VDD, VDDQ and start running CLK2X and PHS_L. The order in which these signals (including VDD and VDDQ) are
applied is not critical.
3. Hold RST_L low for a minimum of 64 CLK2X cycles. The counting starts on the first rising edge of CLK2X when PHS_L is
high, after both VDD and VDDQ have reached their steady state voltages. Set RST_L high afterward to complete the power-up
sequence. For JTAG reset, TRST_L can be brought high after both VDD and VDDQ have reached their steady state voltages.
Figure 16-1 illustrates the proper sequences of the power-up operation.
VDD
VDDQ
CLK2x
PHS_L
TRST_L
RST_L
64 CLK2x
cycles
Figure 16-1. Power-up Sequence
17.0
Application
Figure 17-1 shows how a search engine subsystem can be formed using a host ASIC and Cypress’s CYNSE70032 bank. It also
shows how this search engine subsystem is integrated in a switch or router. The CYNSE70032 can access synchronous as well
as asynchronous SRAMs by allowing the host ASIC to set the same HLAT parameter in the all search engines within a bank of
search engines.
Document #: 38-02042 Rev. *E
Page 114 of 126
CYNSE70032
AM k
SR a n
B
ch
ar ne
Se ngi
E
m
ra ry
og mo
r
P e
M
Syst
t
os
H SIC
A
em B
us
h r
itc so
Sw ces
o
Pr
Net
wor
k
L in e
Inte
h
itc ic
Sw abr
F
rf a c
es
Figure 17-1. Sample Switch/Router Using the CYNSE70032 Device
18.0
JTAG (1149.1) Testing
The CYNSE70032 supports the Test Access Port (TAP) and Boundary Scan Architecture, as specified in the IEEE JTAG standard
1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L.
Table 18-1 describes the operations that the test access port controller supports, and Table 18-2 describes the TAP Device ID
Register. Note. To disable JTAG functionality, connect the TCK, TMS and TDI pins to VDDQ through a pull-up, and TRST_L to
ground through a pull-down.
Table 18-1. Supported Operations
Instruction
SAMPLE/PRELOAD
Type
Mandatory
EXTEST
Mandatory
BYPASS
Mandatory
IDCODE
Optional
CLAMP
HIghZ
Optional
Optional
Document #: 38-02042 Rev. *E
Description
Sample/Preload. This operation loads the values of signals going to and from I/O
pins into the boundary scan shift register to provide a snapshot of the normal
functional operation, and to initialize the boundary scan.
External Test. This operation uses boundary scan values shifted in from TAP to
test connectivity external to the device.
This operation loads a single bit shift register between TDI and TDO and
provides a minimum-length serial path when no test operation is required.
This operation selects the Identification register between TDI and TDO and
allows the “idcode” to be read serially through TDO.
This operation drives preset values onto the outputs of devices.
This operation leaves the device output pins in a high impedance state.
Page 115 of 126
CYNSE70032
Table 18-2. TAP Device ID Register
Field
Range
Initial Value
Revision
[31:28]
0001
Part Number
[27:12]
0000 0000 0000 0001
MFID
[11:1]
000_1101_1100
LSB
[0]
1
19.0
Description
Revision Number. This is the current device revision number.
Numbers start from 1 and increment by 1 for each revision of the
device.
This is the part number of the device.
Manufacturer ID. This field is the same as the manufacturer ID used
in the TAP controller.
Least significant bit.
Electrical Specifications
This section describes the electrical specifications, capacitance, operating conditions, DC characteristics, and AC timing parameters for the CYNSE70032, as shown in Table 19-1 and Table 19-2.
Operating Conditions for CYNSE70032
Table 19-1. DC Electrical Characteristics for CYNSE70032
Parameter
ILI
ILO
VIL
VIL
VIH
VIH
VOL
VOL
VOH
VOH
IDD2
IDD2
IDD2
IDD2
IDDl
IDDl
Description
Input leakage current
Output leakage current
Input LOW voltage (VDDQ = 3.3V)
Input LOW voltage (VDDQ = 2.5V)
Input HIGH voltage (VDDQ = 3.3V)
Input HIGH voltage (VDDQ = 2.5V)
Output LOW voltage (VDDQ = 3.3V)
Output LOW voltage (VDDQ = 2.5V)
Output HIGH voltage (VDDQ = 3.3V)
Output HIGH voltage (VDDQ = 2.5V)
3.3V supply current at VDD Max
3.3V supply current at VDD Max
2.5V supply current at VDD Max
2.5V supply current at VDD Max
1.8V supply current at VDD Max
1.8V supply current at VDD Max
Test Conditions
VDDQ = VDDQ Max., VIN= 0 to VDDQ Max.
VDDQ = VDDQ Max., VIN= 0 to VDDQ Max.
Min.
–10
–10
–0.3
–0.3
2.0
2.0
VDDQ = VDDQ Min., IOL = 8 mA
VDDQ = VDDQ Min., IOL = 8 mA
VDDQ = VDDQ Min., IOH = 8 mA
VDDQ = VDDQ Min., IOH = 8.mA
83-MHz search rate, lOUT = 0 mA
66-MHz search rate, lOUT = 0 mA
83-MHz search rate, lOUT = 0 mA
66-MHz search rate, lOUT = 0 mA
83-MHz search rate
66-MHz search rate
Max.
10
10
0.8
0.8
VDDQ + 0.3
VDDQ + 0.3
0.4
0.4
2.4
2.4
300
240
180
150
1250
1000
Parameter
Description
Max.
Unit
CIN
Input capacitance
6
pF[7]
COUT
Output capacitance
6
pF[8]
Unit
µA
µA
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Table 19-2. Operating Conditions for CYNSE70032
Parameter
Description
Min.
(3.3V)
Max.
(3.3V)
Min.
(2.5V)
Max.
(2.5V)
Unit
VDDQ
Operating voltage for IO
3.135
3.465
2.4
2.6
V
VDD
Operating supply voltage
1.7
1.9
1.7
1.9
V
VIH
Input HIGH
voltage[9]
2.0
VDDQ+ 0.3
1.7
VDDQ+ 0.3
V
VIL
Input LOW voltage[10]
–0.3
0.8
–0.3
0.7
V
Supply voltage tolerance
–5%
+5%
–5%
+5%
Notes:
7. f = 1 MHz, VIN = 0V.
8. f = 1 MHz, VOUT = 0V.
9. Maximum allowable applies to overshoot only (VDDQ is 2.5V supply).
10. Minimum allowable applies to undershoot only.
Document #: 38-02042 Rev. *E
Page 116 of 126
CYNSE70032
Table 19-3. Operating Range for CYNSE70032
20.0
Range
Ambient Temperature
VCC
Commercial
0°C to +70°C
+2.5V to +3.3V ±5%
Industrial
–40°C to +85°C
+2.5V to +3.3V ±5%
AC Timing Waveforms
Table 20-1 shows the AC timing parameters for the CYNSE70032 device; Table 20-2 shows the same parameters but for 2.5V.
Figure 20-1 shows the device’s input wave form, and Figure 20-2 and Figure 20-3 show the device’s output load. Figure 20-4
shows a timing waveform diagram.
Table 20-1. AC Timing Parameters with CLK2X
CYNSE70032-066 CYNSE70032-083
Parameter
FCLOCK
tCLK
Description
Min.
CLK2X frequency
7.5
pulse[11]
TCKHI
CLK2X high
CLK2X low pulse[11]
Min.
133
CLK2X period
TCKLO
Max.
edge[11]
TISCH
Input set-up time to CLK2X rising
TIHCH
Input hold time to CLK2X rising edge[11]
[11]
TICSCH
Cascaded input set-up time to CLK2X rising edge
TICHCH
Cascaded input hold time to CLK2X rising edge[11]
TCKHOV
Rising edge of CLK2X to LHO, FULO, BHO, FULL
TCKHDV
Rising edge of CLK2X to DQ valid[12]
Rising edge of CLK2X to DQ
TCKHSV
Rising edge of CLK2X to SRAM bus valid[12]
Rising edge of CLK2X to SRAM bus High-Z
TCKHSLZ
Rising edge of CLK2X to SRAM bus Low-Z[13]
166
MHz
ns
3.0
2.4
ns
3.0
2.4
ns
2.5
1.8
ns
0.6
0.6
ns
4.2
3.5
ns
0.6
0.6
ns
valid[12]
[13]
TCKHSHZ
Unit
6.0
High-Z[13]
TCKHDZ
Max.
8.5
7.0
ns
9.0
7.5
ns
8.5
7.0
ns
9.0
7.5
ns
6.0
ns
6.5
7.0
6.5
ns
Table 20-2. Test Conditions of CYNSE70032
Conditions
Input pulse levels (VDDQ = 3.3V)
Input pulse levels (VDDQ = 2.5V)
Input rise and fall times measured at 0.3V and 2.7V (VDDQ = 3.3V)
Input rise and fall times measured at 0.25V and 2.25V (VDDQ = 2.5V)
Input timing reference levels (VDDQ = 3.3V)
Input timing reference levels (VDDQ = 2.5V)
Output reference levels (VDDQ = 3.3V)
Output reference levels (VDDQ = 2.5V)
Output load
Results
GND to 3.0V
GND to 2.5V
≤ 2 ns (see Figure 20-1)
≤ 2 ns (see Figure 20-1)
1.5V
1.25V
1.5V
1.25V
See Figure 20-2 and Figure 20-3
Notes:
11. Values are based on 50% signal levels.
12. Based on an AC load of CL = 30 pF (see Figure 20-1, Figure 20-2, and Figure 20-3).
13. These parameters are sampled but not 100% tested, and are based on an AC load of 5 pF.
Document #: 38-02042 Rev. *E
Page 117 of 126
CYNSE70032
+2.5V VDDQ = 2.5V / +3.0V VDDQ = 3.3V
90%
90%
10%
GND
10%
Figure 20-1. Input Waveform for CYNSE70032
DOUT
Z0 = 50Ω
AC Load
50Ω
VL = 1.25V for VCCIO = 2.5V
VL = 1.5V for VCCIO = 3.3V
CL
Figure 20-2. Output Load for CYNSE70032
+2.5V or +3.3V
208Ω (2.5V)
158Ω (3.3V)
Q
192Ω (2.5V)
175Ω (3.3V)
5 pF
For HIGH-Z and VOL/VOH[14, 15]
Figure 20-3. 2.5 I/O Output Load Equivalent for CYNSE70032
Notes:
14. Output loading is specified with CL = 5 pF, as in Figure 20-3. Transition is measured at ± 200 mV from steady-state voltage.
15. The load used for VOH, VOL testing is shown in Figure 20-3.
Document #: 38-02042 Rev. *E
Page 118 of 126
CYNSE70032
cycle
0
cycle
1
cycle
2
cycle cycle
3
4
cycle cycle
5
6
cycle
7
cycle
8
cycle cycle
9
10
cycle
11
cycle
12
CLK2X
CLK
tIHCH
tISCH
Signal
Group 0
tIHCH
tISCH
Signal
tISCH
Group 1
tIHCH
tIHCH
tICHCH
Signal
Group 2
tICSCH
tCKHOV
Signal
Group 3
tCKHOV
tCKHSHZ
Signal
Group 4
tCKHSV
tCKHDZ
tCKHSLZ
Signal
Group 5
tCKHDV
Signal Group 0: PHS_L, RST_L.
Signal Group 1: DQ, CMD, CMDV.
Signal Group 2: LHI, BHI, FULI.
Signal Group 3: LHO, BHO, FULO, FULL.
Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV.
Signal Group 5: DQ, ACK, EOT.
Figure 20-4. AC Timing Waveforms with CLK2X
Document #: 38-02042 Rev. *E
Page 119 of 126
CYNSE70032
21.0
Pinout Descriptions and Package Diagrams
In the following figure and table the CYNSE70032 device pinout diagram and pinout descriptions are shown.
Y
W
V
U
T
1
NC
GND
EOT
NC
NC
2
NC
NC
ACK
FULL
NC
3
DQ64
NC
NC
4
DQ62
NC
VDD
5
DQ60 VDDQ
6
VDD
7
DQ50 VDDQ DQ52 DQ54
8
9
10
NC
NC
NC
R
N
FULO1 NC
L
K
NC
J
H
G
F
E
D
C
B
A
BHI0
LHI6
NC
VDD
ID2
ID0
TDO
NC
NC
1
LHI3
LHI2
ID3
TMS
TDI
VDD
NC
2
LHO1 LHI4 VDDQ LHIO
ID1
TCK
NC
NC
DQ65
3
ID4 TRST_L GND DQ63 DQ61 DQ57
4
DQ67 DQ59
DQ53
5
VDDQ DQ55 DQ49 VDD
6
DQ47 VDDQ DQ51 VDDQ
7
GND
DQ45 DQ43
8
VDD DQ37
9
FULI6 FULI2 BHO1 BHI2 VDDQ LHI5
NC
VDDQ BHO2 VDD
NC FULO0 GND FULI3 FULI0 BHI1
DQ66
LHO0
GND LHI1
TOP
DQ56 DQ58
DQ46 DQ48 GND
DQ40 DQ42 VDDQ DQ44
VDD
M
VDD FULI5 FULI4 FULI1 BHO0 VDD
VDDQ VDD VDDQ
GND RSTL
P
NC
DQ36 DQ38
GND
GND
GND GND
GND
GND
GND GND
DQ41 DQ39
LEFT
11
12
VDDQ DQ35 DQ33 DQ31
10
DQ29 VDD
11
DQ23 DQ25 DQ27
12
GND DQ19 VDDQ DQ21
13
RIGHT
VDDQ DQ34 DQ32 DQ30
NC
DQ28 VDDQ DQ26
GND
GND
GND GND
VDDQ
GND
GND
GND GND
NC
13
DQ24 VDD DQ20 GND
14
DQ22 DQ16 DQ14 VDDQ
VDDQ
15
VDD DQ18 VDDQ DQ6
16
NC
DQ12
17
DQ10
NC
18
DQ2
DQ4
VDD
19
NC
NC
NC
20
NC
NC
Y
W
DQ8
DQ0
VDDQ GND
BOTTOM
NC
SSF CMD6 CMD3 CMD0 ALE_L OE_L SAD21 SAD18 SAD16 SAD12 SAD9 SAD7 SAD6
SSV CMD5 CMD1 CMDV VDDQ PHS_L VDDQ SAD19 VDDQ
U
T
Document #: 38-02042 Rev. *E
R
NC
CE_L
NC
NC SAD10 SAD11 NC
VDD SAD20 SAD17 SAD14 SAD13 VDD
P
N
M
L
K
J
H
G
Figure 21-1. Pinout Diagram (Top View)
F
NC
DQ15 DQ17
14
DQ9
DQ11 DQ13 VDD
15
DQ1
DQ5
DQ7
NC
16
NC
NC
VDDQ
17
SAD0
VDD
DQ3
18
NC
NC
19
NC
20
CMD4 CMD2 GND WE_L CLK2X VDD SAD15 GND VDDQ SAD5 VDDQ GND
CMD8 CMD7 VDDQ VDD
V
NC
NC
NC
NC
SAD4 SAD3
SAD8 VDDQ SAD2 SAD1
E
D
C
B
A
Page 120 of 126
CYNSE70032
Table 21-1. Pinout Descriptions for Pinout Diagram
Package Ball
Number
Signal Name
Package Ball
Number
Signal Name
Signal Type
A1
A2
NC
C4
DQ63
I/O
NC
C5
DQ59
I/O
A3
DQ65
I/O
C6
DQ55
I/O
A4
DQ57
I/O
C7
VDDQ
3.3V/2.5V
A5
DQ53
I/O
C8
NC
A6
VDD
1.8V
C9
DQ39
I/O
A7
VDDQ
3.3V/2.5V
C10
DQ35
I/O
A8
DQ43
I/O
C11
NC
Signal Type
A9
DQ37
I/O
C12
DQ23
I/O
A10
DQ31
I/O
C13
DQ19
I/O
A11
VDD
1.8V
C14
NC
A12
DQ27
I/O
C15
DQ11
I/O
A13
DQ21
I/O
C16
DQ5
I/O
A14
DQ17
I/O
C17
NC
A15
VDD
1.8V
C18
SAD0
Output-T
A16
NC
C19
SAD3
Output-T
A17
VDDQ
3.3V/2.5V
C20
SAD2
Output-T
A18
DQ3
I/O
D1
ID0
Input
A19
NC
D2
TMS
Input
A20
NC
D3
TCK
Input
B1
NC
B2
VDD
B3
NC
B4
DQ61
D4
GND
Ground
1.8V
D5
DQ67
I/O
D6
VDDQ
3.3V/2.5V
I/O
D7
DQ47
I/O
B5
NC
D8
GND
Ground
B6
DQ49
I/O
D9
DQ41
I/O
B7
DQ51
I/O
D10
VDDQ
3.3V/2.5V
B8
DQ45
I/O
D11
VDDQ
3.3V/2.5V
B9
VDD
1.8V
D12
NC
B10
DQ33
I/O
D13
GND
Ground
B11
DQ29
I/O
D14
VDDQ
3.3V/2.5V
B12
DQ25
I/O
D15
DQ9
I/O
B13
VDDQ
3.3V/2.5V
D16
DQ1
I/O
B14
DQ15
I/O
D17
GND
Ground
B15
DQ13
I/O
D18
NC
B16
DQ7
I/O
D19
SAD4
Output-T
B17
NC
B18
VDD
D20
VDDQ
3.3V/2.5V
1.8V
E1
ID2
Input
E2
ID3
Input
E3
ID1
Input
B19
NC
B20
SAD1
Output-T
C1
TDO
Output-T
E4
TRST_L
Input
C2
TDI
Input
E17
VDDQ
3.3V/2.5V
C3
NC
E18
SAD6
Output-T
Document #: 38-02042 Rev. *E
Page 121 of 126
CYNSE70032
Table 21-1. Pinout Descriptions for Pinout Diagram (continued)
Package Ball
Number
Signal Name
Package Ball
Number
E19
NC
Signal Name
Signal Type
L2
BHO1
Output
E20
SAD8
F1
VDD
Output-T
L3
BHO2
Output
1.8V
L4
FULI0
Input
F2
LHI2
Input
L17
CLK2X
Input
F3
LHI0
Input
L18
SAD21
Output-T
Signal Type
F4
ID4
Input
L19
VDDQ
3.3V/2.5V
F17
SAD5
Output-T
L20
VDD
1.8V
F18
SAD7
Output-T
M1
FULI1
Input
F19
SAD11
Output-T
M2
FULI2
Input
F20
VDD
1.8V
G1
NC
M3
VDDQ
3.3V/2.5V
M4
FULI3
Input
G2
LHI3
Input
M17
WE_L
Output-T
G3
VDDQ
3.3V/2.5V
M18
OE_L
Output-T
Input
G4
LHI1
Input
M19
PHS_L
G17
VDDQ
3.3V/2.5V
M20
NC
G18
SAD9
Output-T
N1
FULI4
Input
G19
SAD10
Output-T
N2
FULI6
Input
G20
SAD13
Output-T
N3
NC
H1
LHI6
Input
N4
GND
H2
LHI5
Input
N17
GND
Ground
H3
LHI4
Input
N18
ALE_L
Output-T
Ground
H4
GND
Ground
N19
VDDQ
3.3V/2.5V
H17
GND
Ground
N20
CE_L
Output-T
H18
SAD12
Output-T
P1
FULI5
Input
H19
NC
P2
NC
H20
SAD14
Output-T
P3
NC
J1
BHI0
Input
P4
FULO0
J2
VDDQ
3.3V/2.5V
P17
CMD2
Input
J3
LHO1
Output
P18
CMD0
Input
Input
Output
J4
LHO0
Output
P19
CMDV
J17
SAD15
Output-T
P20
NC
J18
SAD16
Output-T
R1
VDD
1.8V
J19
VDDQ
3.3V/2.5V
R2
FULO1
Output
J20
SAD17
Output-T
R3
VDDQ
3.3V/2.5V
K1
VDD
1.8V
R4
NC
K2
BHI2
Input
R17
CMD4
Input
K3
VDD
1.8V
R18
CMD3
Input
K4
BHI1
Input
R19
CMD1
Input
K17
VDD
1.8V
R20
VDD
1.8V
K18
SAD18
Output-T
T1
NC
K19
SAD19
Output-T
T2
NC
K20
SAD20
Output-T
T3
VDD
1.8V
L1
BHO0
Output
T4
RSTL
Input
Document #: 38-02042 Rev. *E
Page 122 of 126
CYNSE70032
Table 21-1. Pinout Descriptions for Pinout Diagram (continued)
Package Ball
Number
Signal Name
T17
NC
Signal Type
Package Ball
Number
Signal Name
Signal Type
V20
CMD8
Input
Ground
T18
CMD6
Input
W1
GND
T19
CMD5
Input
W2
NC
T20
VDDQ
3.3V/2.5V
W3
NC
U1
NC
W4
NC
U2
FULL
Output
W5
VDDQ
U3
VDDQ
3.3V/2.5V
W6
NC
3.3V/2.5V
U4
GND
Ground
W7
VDDQ
3.3V/2.5V
U5
DQ66
I/O
W8
DQ46
I/O
U6
DQ58
I/O
W9
DQ42
I/O
U7
DQ54
I/O
W10
NC
U8
GND
Ground
W11
DQ34
I/O
U9
DQ44
I/O
W12
DQ28
I/O
U10
DQ38
I/O
W13
VDD
1.8V
U11
DQ30
I/O
W14
DQ16
I/O
U12
DQ26
I/O
W15
DQ18
I/O
U13
GND
Ground
W16
DQ12
I/O
U14
VDDQ
3.3V/2.5V
W17
NC
U15
DQ6
I/O
W18
DQ4
U16
DQ0
I/O
W19
NC
U17
GND
Ground
W20
NC
I/O
U18
SSF
Output-T
Y1
NC
U19
SSV
Output-T
Y2
NC
U20
CMD7
Input
Y3
DQ64
I/O
V1
EOT
Output-T
Y4
DQ62
I/O
V2
ACK
Output-T
Y5
DQ60
I/O
V3
NC
Y6
VDD
1.8V
V4
VDD
Y7
DQ50
I/O
V5
NC
Y8
NC
V6
DQ56
I/O
Y9
DQ40
I/O
V7
DQ52
I/O
Y10
VDD
1.8V
3.3V/2.5V
1.8V
V8
DQ48
I/O
Y11
VDDQ
V9
VDDQ
3.3V/2.5V
Y12
NC
V10
DQ36
I/O
Y13
DQ24
I/O
V11
DQ32
I/O
Y14
DQ22
I/O
V12
VDDQ
3.3V/2.5V
Y15
VDD
1.8V
V13
DQ20
I/O
Y16
NC
V14
DQ14
I/O
Y17
DQ10
I/O
V15
VDDQ
3.3V/2.5V
Y18
DQ2
I/O
V16
DQ8
I/O
Y19
NC
V17
VDDQ
3.3V/2.5V
Y20
NC
V18
VDD
1.8V
V19
NC
Document #: 38-02042 Rev. *E
J9
GND
Ground
J10
GND
Ground
Page 123 of 126
CYNSE70032
Table 21-1. Pinout Descriptions for Pinout Diagram (continued)
Package Ball
Number
Signal Name
Signal Type
Package Ball
Number
Signal Name
Signal Type
J11
GND
Ground
L10
GND
Ground
J12
GND
Ground
L11
GND
Ground
K9
GND
Ground
L12
GND
Ground
22.0
K10
GND
Ground
M9
GND
Ground
K11
GND
Ground
M10
GND
Ground
K12
GND
Ground
M11
GND
Ground
L9
GND
Ground
M12
GND
Ground
Ordering Information
Table 22-1 provides ordering information.
Table 22-1. Ordering Information
Part Number
Description
Frequency
Temperature Range
CYNSE70032-66BGC
Search Engine
66 MHz
Commercial
CYNSE70032-66BGI
Search Engine
66 MHz
Industrial
CYNSE70032-83BGC
Search Engine
83 MHz
Commercial
Document #: 38-02042 Rev. *E
Page 124 of 126
CYNSE70032
23.0
Package Diagrams
272-Lead Ball Grid Array (27 × 27 × 2.33 mm) BG272
51-85130-*A
Figure 23-1. Package
Associative Processing Technology (APT) is a trademark of Cypress Semiconductor. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #: 38-02042 Rev. *E
Page 125 of 126
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CYNSE70032
Document History Page
Document Title: CYNSE70032 Network Search Engine
Document Number: 38-02042
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
111441
02/12/02
AFX
New Data Sheet
*A
116611
07/10/02
OOR
Added industrial temp parts
*B
118152
9/19/02
OOR
Added power section that covers the power-up sequence
Updating JTAG section with supported operations table
*C
121027
12/17/02
ED
Added note to power-up sequence instructions
Removed CYNSE70128-/256-specific power-up instructions
Removed Alternative power-up sequence from TOC
Removed references to Alternative power-up sequence instructions including
timing Figure 16-1
*D
123685
02/20/03
KOS
Removed TEST from Signal Description Table 5-1
Add Pin A10 to the pinout descriptions Table 21-1
Add ”Output-T” in the Signal Type field of the Pin E18 Table 21-1
Change F1 Signal Name and Type from VDDQ to VDD and 3.3V/2.5V to 1.8V
Table 21-1
Add “1.8V” in the Signal Type field of Pin F20 Table 21-1
Change U6 Package Ball Number from U6I/O to U6 Table 21-1
Re-order the pinouts list Table 21-1
*E
126019
05/07/03
ITL
Document #: 38-02042 Rev. *E
Updated Figure 16-1 on page 114 to relect the correct waveforms. Also
corrected the power-up sequence description above the figure.
Page 126 of 126