Zarlink MAR2901CD Radiation hard 4-bit microprocessor slice Datasheet

Obsolescence Notice
This product is obsolete.
This information is available for your
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FEBRUARY
1995
MA2901
DS3576-3.3
MA2901
RADIATION HARD 4-BIT MICROPROCESSOR SLICE
The MA2901 is an industry standard 4-bit microprocessor
slice It provides a set of ALU functions selected by microcode
data applied to the inputs. The device is cascadable to handle
any word length. It can be used as a building block in the
construction of microcomputers and controllers tailored to
meet specialised applications.
Dual Address Architecture
Machine cycles are saved by simultaneous, independent
access to two working registers.
ALU has Eight Functions
Operations performed are addition, two subtractions and five
logic functions on two source operands.
Four State Flags
Zero, negative, carry and overflow.
Left / Right Shift is Independent of ALU
Only one cycle taken for add and shift operations.
Expandable
Any number of MA2901 units can be connected together to
achieve longer word lengths.
Micro Programmable
Three groups, each of three bits, for ALU function, source
operand and destination control.
FEATURES
■ Fully Compatible with Industry Standard 2901
■ CMOS SOS Technology
■ High SEU Immunity and Latch-up Free
■ High Speed
■ Low Power
OPERATION
A detailed block diagram of the microprogrammable
microprocessor structure is shown in figure 1. The circuit is a
four-bit slice, cascadable to any number of bits. Therefore, all
data paths within the circuit are four bits wide. The two key
elements in the figure 1 are the 16-word by 4-bit 2-port RAM
and the high speed ALU.
Data from any of the 16 words of the Random Access
Memory (RAM) can be read from the A-port of the RAM as
controlled by the 4-bit A-address field input. Likewise, data
from any of the 16 words of the RAM as defined by the Baddress field input can be simultaneously read from the B-port
of the RAM. The same code can be applied to the A-select field
and B-select field in which case the identical file data will
appear at both the RAM A-port and B-port outputs
simultaneously.
When enabled by the RAM write enable (RAM EN), new
data is always written into the file (word) defined by the Baddress field of the RAM. The RAM data input field is driven by
a 3-input multiplexer. This configuration is used to shift the
ALU output data (F) if desired. This three-input multiplexer
scheme allows the data to be shifted up one bit position,
shifted down one bit position, or not shifted in either direction.
The RAM A-port data outputs and RAM B-port data outputs
drive separate 4-bit latches. These latches hold the RAM data
while the clock input is LOW. This eliminates any possible race
conditions that could occur while new data is being written into
the RAM.
The high-speed Arithmetic Logic Unit (ALU) can perform
three binary arithmetic and five logic operations on the two 4bit input words R and S. The R input field is driven from a 2input multiplexer, while S input field is driven from a 3-input
multiplexer. Both multiplexers also have an inhibit capability;
that is, no data is passed. This is equivalent to a “zero” source
operand.
The ALU R-input multiplexer has the RAM A-port and the
direct data inputs (D) connected as inputs. Likewise, the ALU
S-input multiplexer has the RAM A-port, the RAM B-port and
the Q register connected as inputs.
1
MA2901
Cn
G
P
Cn+4
OVR
F=0
F3
OE
Figure 1: Block Diagram
2
MA2901
This multiplexer scheme gives the capability of selecting
various pairs of the A, B, D, Q and “0” inputs as source
operands to the ALU. These five inputs, when taken two at a
time, result in ten possible combinations of source operand
pairs. These combinations include AB, AD, AQ, A0, BD, BQ,
B0, DQ, D0 and Q0. It is apparent the AD, AQ and A0 are
somewhat redundant with BD, BQ and B0 in that if the A
address and B address are the same, the identical function
results. Thus, there are only seven completely non-redundant
sourced operand pairs for the ALU. The MA2901
microprocessor implements eight of these pairs. The
microinstruction inputs used to select the ALU source
operands are the l0, I1, and I2 inputs. The definition of l0, I1, and
I2 for the eight source operand combinations are as shown in
figure 2. Also shown is the octal code for each selection.
The two source operands not fully described as yet are the
D input and Q input. The D input is the four-bit wide direct data
field input. This port is used to insert all data into the working
registers inside the device. Likewise this input can be used in
the ALU to modify any of the internal data files. The Q register
is a separate 4-bit file intended primarily for multiplication and
division routines but it can also be used as an accumulator or
holding register for some applications.
The ALU itself is a high speed arithmetic/logic operator
capable of performing three binary arithmetic and five logic
functions. The I3, I4, and I 5 microinstruction inputs are used to
select the ALU function. The definition of these inputs is shown
in Figure 3. The octal code is also shown for reference. The
normal technique for cascading ALU of several devices is in a
look-ahead carry mode. Carry generate, GN, and carry
propagate, PN, are outputs of the device for use with a carrylook-ahead-generator. A carry-out Cn + 4, is also generated
and is available as an output for use as the carry flag in a
status register. Both carry-in (Cn) and carry-out (Cn+4) are
active HIGH.
Microcode
The ALU has three other status-oriented outputs. These
are F 3, F=0, and overflow (OVR). The F3 output is the most
significant (sign) bit of the ALU and can be used to determine
positive or negative results without enabling the three-state
data outputs. F3 is non-inverted with respect to the sign bit
output Y3. The F = 0 output is used for zero detect. It is an
open-collector output and can be wire OR’ed between
microprocessor slices. F = 0 is HIGH when all F outputs are
LOW. The overflow output (OVR) is used to flag arithmetic
operations that exceed the available two’s complement
number range. The overflow output (OVR) is HIGH when
overflow exists. That is when Cn + 3 and Cn + 4 are not the
same polarity.
The ALU data output is routed to several destinations. It
can be a data output of the device and it can also be stored in
the RAM or the Q register. Eight possible combinations of ALU
destination functions are available as defined by the I6, I7, and
I8 microinstruction inputs. These combinations are shown in
figure 4.
The four-bit data output field (Y) features three-state
outputs and can be directly bus organised. An output control
(OEN) is used to enable the three-state outputs. When OEN is
HIGH, the Y outputs are in the high impedance state.
A two-input multiplexer is also used at the data output
such that either the A-port of the RAM or the ALU outputs (F)
are selected at the device Y outputs. This selection is
controlled by the I6, I7, and I8 microinstruction inputs.
As was discussed previously, the RAM inputs are driven
from a three-input multiplexer. This allows the ALU outputs to
be entered non-shifted, shifted up one position (x 2) or shifted
down one position (÷ 2). The shifter has two ports; labeled
RAM0 and RAM3. Both of these ports consist of a buffer-driver
with a three-state output and an input to the multiplexer.
ALU Source
Operands
Microcode
ALU
Function
Symbol
Octal
Code
I2
I1
I0
Octal
Code
R
S
L
L
0
A
C
L
L
L
0
R plus S
R+S
L
L
L
H
1
A
B
L
L
H
1
S minus R
S-R
L
H
L
2
0
Q
L
H
L
2
R minus S
R-S
L
H
H
3
0
B
L
H
H
3
R OR S
R∨S
H
L
L
4
0
A
H
L
L
4
RN AND S
RN ∧ S
H
L
H
5
D
A
H
L
H
5
R AND S
R∧ S
H
H
L
6
D
Q
H
H
L
6
R EX-OR S
R∇S
H
H
H
7
D
0
H
H
H
7
R EX-NOR S
RN ∇ SN
Figure 2: ALU Source Operand Control
I5
I4
I3
+ = plus; - = minus; V = OR; Λ = AND; ∇ = EX-OR
Figure 2: ALU Function Control
3
MA2901
In the shift up mode, the RAM3 buffer is enabled and the
RAM0 multiplexer input is enabled. Likewise, in the shift down
mode, the RAM0 buffer and RAM3 input are enabled. In the noshift mode, both buffers are in the high-impedance state and
the multiplexer inputs are not selected. The shifter is controlled
from the I6, I7 and I8 microinstruction inputs as defined in Figure
4.
Similarly, the Q register is driven from a 3-input
multiplexer. In the non-shift mode, the multiplexer enters the
ALU data into the Q register. In either the shift-up or shift-down
mode, the multiplexer selects the Q register data appropriately
shifted up or down. The Q shifter also has two ports; one is
labeled Q0 and the other is Q 3. The operation of these two
ports is similar to the RAM shifter and is also controlled from I6,
I7 and I8 as shown in Figure 4.
The clock input shown in Figure 1 controls the RAM, the Q
resister and the A and B data latches. When enabled, data is
clocked into the Q register on the LOW-to-HlGH transition of
the clock. When the clock input is HIGH, the A and B latches
are open and will pass whatever data is present at the RAM
outputs. When the clock input is LOW, the latches are closed
and will retain the last data entered. If the RAM-EN is enabled
new data will be written into the RAM file (word) defined by the
B address field when the clock input is LOW.
Microcode
I8
L
L
L
L
H
H
H
H
I7
L
L
H
H
L
L
H
H
I6
L
H
L
H
L
H
L
H
RAM Function
Octal
Code
0
1
2
3
4
5
6
7
Shift
X
X
None
None
Down
Down
Up
Up
SOURCE OPERANDS & ALU FUNCTION
Any one of eight source operand pairs can be selected by
instruction inputs lo, l 1 and I 2 for use by the ALU; instruction
inputs I3, I4, and I5 then control function selection for the ALU five logic and three arithmetic functions. In the arithmetic
mode, the carry input (Cn) also affects the ALU functions; the
carry input has no effect on the ‘F’ result in the logic mode.
These control parameters (I6 - l0 and Cn) are summarised in
Figure 5 to completely define the ALU/source operand
functions.
The ALU functions can also be examined on a task basis:
that is, add, subtract, AND, OR, and so on. Again, in the
arithmetic mode, the carry input still affects the result, whereas
in the logic mode it will not. Figures 6 and 7, respectively,
define the various logic and arithmetic functions of the ALU;
both carry states (Cn = 0 / Cn = 1) are defined in the function
matrices.
Q-Reg Function
Load
None
None
F→ B
F→ B
F/2→ B
F/2→ B
2F→ B
2F→ B
Shift
None
X
X
X
Q/2 → Q
X
Up
X
Load
F→ Q
None
None
None
F
None
2Q→ Q
None
Y
Output
F
F
A
F
F
F
F
RAM Shifter
RAM0
X
X
X
X
F0
F0
IN0
IN0
Q Shifter
RAM3
X
X
X
X
IN3
IN3
F3
F3
Q0
X
X
X
X
Q0
Q0
IN3
X
Q3
X
X
X
X
IN3
X
Q3
Q3
X = Don't Care. Electrically, the shift pin is a TTL input internally connected to a TRI-STATE output which is in the high-impedance state.
B = Register addressed by 8 inputs. Up is towards MSB, Down is towards LSB.
Figure 4: ALU Destination Control
Oct al
I 5,4,3
0
1
2
3
4
5
6
7
I 2,1,0Oc ta l
ALU Source
/ALU
Function
C n =L
R plus S
C n =H
Cn=L
S minus R
C n =H
C n =L
R minus S
C n =H
R or S
R and S
RN and S
R EX-OR S
R EX NOR S
0
1
2
3
4
5
6
7
A,Q
A,B
0,Q
0,B
0,A
D,A
D,Q
D,0
A+Q
A+B
Q
B
A
D+A
D+Q
D
A+Q+1
Q-A-1
A+B+1
B-A-1
Q +1
Q -1
B+1
B-1
A+1
A-1
D+A+1
A - D1
D+Q+1
Q-D-1
D+1
-D - 1
Q-A
A-Q-1
B-A
A-B-1
Q
-Q-1
B
-B-1
A
-A-1
A-D
D - A -1
Q-D
D-Q-1
-D
D-1
A-Q
AVQ
AΛ Q
AN Λ Q
A∇Q
AN ∇ QN
A-B
AVB
AΛ B
AN Λ B
A∇B
AN ∇ BN
-Q
Q
0
Q
Q
Q
-B
B
0
B
B
B
-A
A
0
A
A
A
D-A
DV A
DΛ A
DN Λ A
D∇ A
DN ∇ AN
D-Q
DV Q
DΛ Q
DN Λ Q
D∇ Q
DN ∇ QN
D
D
0
0
D
DN
+ = plus; - = minus; V = OR; Λ = AND; ∇ = EX-OR
Figure 5: Source Operand and ALU Function Matrix
4
MA2901
Octal
Group
I 5,4,3 /I 2,1,0
40
41
45
46
30
31
35
36
60
61
65
66
70
71
75
76
72
73
74
77
62
63
64
67
32
33
34
37
40
43
44
47
50
51
55
56
Function
A ΛQ
A ΛB
DΛA
DΛQ
AVQ
AVB
DV A
DV Q
A∇Q
A∇B
D∇ A
D∇ Q
AN ∇ QN
AN ∇ BN
DN ∇ AN
DN ∇ QN
Q
B
A
D
Q
B
A
D
Q
B
A
D
0
0
0
0
AN Λ Q
AN Λ B
DN Λ A
DN Λ Q
AND
OR
EX-OR
EX-NOR
INVERT
PASS
PASS
‘ZERO’
AND
+ = plus; - = minus; V = OR; Λ = AND; ∇ = EX-OR
Figure 6: ALU Logic Mode Functions (Cn Irrelevant)
Octal
I 5,4,3/I 2,1,0
00
01
05
06
02
03
04
07
12
13
14
27
22
23
24
17
10
11
15
16
20
21
25
26
Cn=0(Low)
Group
ADD
PASS
Decrement
1s comp
SUBTRACT
(1s comp)
Function
A+Q
A+B
D+A
D+Q
Q
B
A
D
Q-1
B-1
A-1
D-1
-Q-1
-B-1
-A-1
-D-1
Q - A -1
B - A-1
A - D-1
Q - D-1
A - Q-1
A - B-1
D - A-1
D - Q-1
Cn = 1 (High)
Group
ADD
plus one
Increment
PASS
2s comp
(negate)
SUBTRACT
(2s comp)
Function
A + Q +1
A + B +1
D + A +1
D+Q+1
Q +1
B+1
A+1
D+1
Q
B
A
D
-Q
-B
-A
-D
Q-A
B-A
A-D
Q-D
A-Q
A-B
D-A
D-Q
Figure 7: ALU Arithmetic Mode Functions
5
MA2901
PIN DESCRIPTION
Name
A0-3
I/O
I
B0-3
I
I 0-8
I
Q3
RAM3
I/O
Q0
RAM0
I/O
D0-3
I
Y0-3
O
OEN
I
GN,PN
O
OVR
O
F=0
O
F3
Cn
Cn + 4
CP
O
I
O
I
Description
The four address inputs to the register stack used to select one register whose
contents are displayed through the A port
The four address inputs to the register stack used to select one register whose
contents are displayed through the B port and into which new data can be written
when the clock goes LOW
The nine instruction control lines. Used to determine what data sources will be
applied to the ALU(I 0,1,2), what function the ALU will perform (I 3,4,5), and what
data is to be deposited in the Q-register or the register stack (I 6,7,8)
The shift line at the MSB of the Q-register (Q3) and the register stack (RAM3).
Electrically these lines are three-state outputs connected to TTL inputs internal to
the device. When the destination code on I 6,7,8 indicates an up shift (Octal 6 or 7)
the three state outputs are enabled and the MSB of the Q-register is available on
the Q3 pin and the MSB of the ALU output is available on the RAM 3 pin.
Otherwise, the three state outputs are electrically OFF (high impedance) and the
pins are electrically LS-TTL inputs. When the destination code calls for a down
shift, the pins are used as the data inputs to the MSB of the Q-register (Octal 4)
and RAM (Octal 4 or 5)
Shift lines like Q 3 and RAM 3, but at the LSB of the Q-register and RAM. These
pins are tied to the Q 3 and RAM 3 pins of the adjacent device to transfer data
between devices for up and down shifts of the Q-register and ALU data.
Direct data inputs. A four-bit data field which may be selected as one of the ALU
data sources for entering data into the device D 0 is the LSB
The four data outputs. These are three-state output lines. When they are enabled,
they display either the four outputs of the ALU or the data on the A-port of the
register stack, as determined by the destination code I 6,7,8.
Output enable. When OEN is HIGH, the Y outputs are OFF; when OEN is LOW, the
Y outputs are active (HIGH or LOW)
The carry generate and propagate outputs of the internal ALU. These signals are
used with the MA2901 for carry lookahead.
Overflow. This pin is logically the Exclusive OR of the carry-in and carry-out of the
MSB of the ALU. At the most significant end of the word, this pin indicates that the
result of an arithmetic two’s complement operation has overflowed into the sign-bit
This is an open collector output which goes HIGH(OFF) if the data on the four ALU
outputs F 0-3 are all LOW. In positive logic, it indicates that the result of the ALU
operation is zero
The most significant ALU output bit.
The carry-in to the internal ALU.
The carry-out of the ALU internal ALU.
The clock input. The Q-register and register stack outputs change on the clock
LOW - to HIGH transition. The clock LOW time is internally the write enable to the
16 x 4 RAM which compromises the “master” latches of the register stack. While
the clock is LOW, the “slave” latches on the RAM outputs are closed, storing the
data previously on the RAM outputs. This allows synchronous master-slave
operation of the register stack.
Figure 8: Pin Description
6
MA2901
DC CHARACTERISTICS AND RATINGS
Parameter
Min
Max
Units
Supply Voltage
-0.5
7
V
Input Voltage
-0.3
VDD+0.3
V
Current Through Any Pin
-20
+20
mA
Operating Temperature
-55
125
°C
Storage Temperature
-65
150
°C
Note: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these conditions, or at
any other condition above those indicated in the operations
section of this specification, is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Figure 9: Absolute Maximum Ratings
Subgroup
Definition
1
Static characteristics specified in Figure 11 at +25°C
2
Static characteristics specified in Figure 11 at +125°C
3
Static characteristics specified in Figure 11 at -55°C
7
Functional characteristics at +25°C
8A
Functional characteristics at +125°C
8B
Functional characteristics at -55°C
9
Switching characteristics specified in Figures 12, 13 and 14 at +25°C
10
Switching characteristics specified in Figures 12, 13 and 14 at +125°C
11
Switching characteristics specified in Figures 12, 13 and 14 at -55°C
Figure 10: Definition of Subgroups
Total dose radiation not
exceeding 3x105 Rad(Si)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
5.5
V
VDD
Supply Voltage
-
4.5
5.0
VIH
Input High Voltage
-
2.4
-
-
V
VIL
Input Low Voltage
-
-
-
0.8
V
VOH
Output High Voltage
IOH = -6mA
2.4
-
-
V
VOL
Output Low Voltage
IOL = 10mA
-
-
0.4
V
IIN
Input Leakage Current (Note 1)
VDD = 5.5V,
VIN = VSS or VDD
-
-
±10
µA
IOZ
Output Leakage Current (Note 1)
VDD = 5.5V,
VIN = VSS or VDD
-
-
±50
µA
IDD
Power Supply Current
Static, VDD = 5.5V
-
0.1
10
mA
VDD = 5V±10%, over full operating temperature range.
Mil-Std-883, method 5005, subgroups 1, 2, 3
Notes: 1. Guaranteed but not measured at -55°C
Figure 11: Operating Electrical Characteristics
7
MA2901
AC ELECTRICAL CHARACTERISTICS
Read-Modify-Write Cycle (from selection of A,B registers to end of a cycle
40ns
Maximum Clock Frequency to shift Q(50% duty cycle, I = 432 or 632)
25MHz
Minimum Clock LOW time
20ns
Minimum Clock HIGH time
20ns
Minimum Clock Period
40ns
Note: 1. These timings are applied during functional tests and are not routinely measured.
Figure 12: Cycle Time and Clock Characteristics
To Output
From Input
A,B Address
D
Cn
I 0,1,2
I 3,4,5
I 6,7,8
A Bypass ALU(I=2xx)
Clock
Note: All timings in ns
Y
F3
Cn + 4
G,P
F=0
OVR
RAM 0
Q0
65
55
60
70
60
45
45
55
55
40
40
50
45
50
60
50
35
55
50
55
55
50
55
45
50
70
65
55
70
65
50
65
55
35
55
50
55
RAM 3
65
55
50
65
65
30
55
Q3
30
35
Figure 13: Combinational Propagation Delays
Input
CP:
Set-up Time
Hold Time
Before H → L
After H → L
A,B Source Address
25
5
B Destination Address
25
No change
D
Cn
I 0,1,2
I 3,4,5
I 6,7,8
10
No change
RAM0,3, Q0,3
MIL-STD-883, method 5005, subgroups 9, 10, 11
Note:
1. VDD = 5V ±10%, over full operational temperature range
2. CL = 50 pF
Set-up Time
Before L → H
30
No change
40
40
45
45
No change
15
Figure 14: Set-up and Hold Times Relative to Clock (CP) Input
8
Hold Time
After L → H
5
0
0
0
0
10
10
MA2901
OUTLINES AND PIN ASSIGNMENTS
Millimetres
Ref
Inches
Min.
Nom.
Max.
Min.
Nom.
Max.
A
-
-
5.715
-
-
0.225
A1
0.38
-
1.53
0.015
-
0.060
b
0.35
-
0.59
0.014
-
c
0.20
-
0.36
0.008
-
D
-
-
51.31
-
-
2.020
e
-
2.54 Typ.
-
-
0.100 Typ.
-
e1
-
15.24 Typ.
-
-
0.600 Typ.
H
4.71
-
5.38
0.185
-
Me
-
-
15.90
-
-
0.626
Z
-
-
1.27
-
-
0.050
W
-
-
1.53
-
-
0.060
A3
1
40 OE
A2
2
39 Y3
0.023
A1
3
38 Y2
0.014
A0
4
37 Y1
I6
5
36 Y0
-
I8
6
35 P
0.212
I7
7
34 OVR
RAM3
8
33 Cn+4
RAM0
9
Top
View
VDD 10
XG405
F = 0 11
D
20
1
21
32 G
31 F3
30 VSS
I0 12
29 Cn
I1 13
28 I4
I2 14
27 I5
CP 15
26 I3
Q3 16
25 D0
B0 17
24 D1
B1 18
23 D2
B2 19
22 D3
B3 20
21 Q0
40
W
ME
Seating Plane
A1
A
C
H
e1
e
b
Z
15°
Figure 15: 40-Lead Ceramic DIL (Solder Seal) - Package Style C
9
MA2901
Millimetres
Inches
I8 1
42 I6
Min.
Max.
Min.
Max.
I7 2
41 A0
A
1.75
2.49
0.070
0.098
RAM3 3
40 A1
b
0.43
0.53
0.017
0.023
NC 4
39 A2
c
0.15
0.25
0.006
0.010
RAM0 5
38 A3
D
26.67
27.69
1.050
1.080
VCC 6
37 OE
E
15.75
16.76
0.620
0.660
F=0 7
36 Y3
E1
-
17.27
-
0.630
I0 8
35 Y2
E2
13.21
-
0.520
-
I1 9
34 Y1
E3
0.76
-
0.030
-
e
1.14
1.40
0.045
0.055
I2 10
33 Y0
L
7.87
9.40
0.310
0.370
CP 11
32 P
L1
32.51
34.54
1.250
1.360
NC 12
31 OVR
Q3 13
30 Cn+4
B0 14
29 G
B1 15
28 F3
B2 16
27 GND
B3 17
26 Cn
Q0 18
25 I4
D3 19
24 I5
D2 20
23 I3
D1 21
22 D0
Ref
Q
S
S1
0.76
1.52
-
1.14
0.13
-
0.030
0.060
-
0.045
0.005
-
XG136
L1
S
e
H
D
b
S1
E2
A
Q
L
E3
E
E1
Figure 16: 42-Lead Flatpack (Solder Seal)
10
c
MA2901
RADIATION TOLERANCE
Total Dose Radiation Testing
For product procured to guaranteed total dose radiation
levels, each wafer lot will be approved when all sample
devices from each lot pass the total dose radiation test.
The sample devices will be subjected to the total dose
radiation level (Cobalt-60 Source), defined by the ordering
code, and must continue to meet the electrical parameters
specified in the data sheet. Electrical tests, pre and post
irradiation, will be read and recorded.
GEC Plessey Semiconductors can provide radiation
testing compliant with Mil-Std-883 method 1019 Ionizing
Radiation (total dose) test.
Total Dose (Function to specification)*
3x105 Rad(Si)
Transient Upset (Stored data loss)
5x1010 Rad(Si)/sec
Transient Upset (Survivability)
>1x1012 Rad(Si)/sec
Neutron Hardness (Function to specification)
>1x1015 n/cm2
Single Event Upset**
1x10-10 Errors/bit day
Latch Up
Not possible
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Figure 17: Radiation Hardness Parameters
ORDERING INFORMATION
Unique Circuit Designator
Radiation Tolerance
S
R
Q
MAx2901xxxxx
Radiation Hard Processing
100 kRads (Si) Guaranteed
300 kRads (Si) Guaranteed
Package Type
C
F
QA/QCI Process
(See Section 9 Part 4)
Test Process
(See Section 9 Part 3)
Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Assembly Process
(See Section 9 Part 2)
Reliability Level
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
L
C
D
E
B
S
Rel 0
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S
11
MA2901
HEADQUARTERS OPERATIONS
CUSTOMER SERVICE CENTRES
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire, SN2 2QW, United Kingdom.
Tel: (01793) 518000
Fax: (01793) 518411
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road, Scotts Valley,
California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
Tel: (01793) 518527/518566 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1995 Publication No. DS3576-3.3 February 1995
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to
be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide
only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of
any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose
failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
12
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