ATMEL ATA6020X-YYY-TKQ Low-current microcontroller for watchdog function Datasheet

Features/Benefits
•
•
•
•
•
•
•
•
Programmable System Clock with Prescaler and Three Different Clock Sources
Very Low Sleep Current (< 1 µA)
Very Low Power Consumption in Active, Power-down and Sleep Mode
2-Kbyte ROM, 256 ´ 4-bit RAM
12 Bi-directional I/Os
Up to 6 External/Internal Interrupt Sources
Synchronous Serial Interface (2-wire, 3-wire)
Multifunction Timer/Counter with
– Watchdog, POR and Brown-out Function
– Voltage Monitoring Inclusive Lo_BAT Detection
– Flash Controller ATAM893 Available (SSO20)
– Code-efficient Instruction Set
– High-level Language Programming with qFORTH Compiler
Description
The ATA6020N is a member of Atmel’s 4-bit single-chip microcontroller family. It contains ROM, RAM, parallel I/O por ts, one 8-bit programmable multifunction
timer/counter with modulator function, voltage supervisor, interval timer with watchdog
function and a sophisticated on-chip clock generation with external clock input and
integrated RC-oscillators.
Low-current
Microcontroller
for Watchdog
Function
ATA6020N
Figure 1. Block Diagram
VDD
VSS
OSC1
Brown-out protect
RESET
Voltage monitor
External input
External
clock input
RC
oscillators
Clock management
VMI
ROM
2 K x 8 bit
BP23
Data direction
BP22
Port 2
BP21
RAM
Timer 2
8/12-bit timer
256 x 4 bit
T2I
T2O
with modulator
MARC4
BP20/NTE
UTCM
Timer 1
interval- and
watchdog timer
SD
SSI
4-bit CPU core
Serial interface
SC
I/O bus
Data direction +
alternate function
Data direction +
interrupt control
Port 4
BP42
BP40
INT3
T2O
SC
BP41
BP43
VMI
INT3
SD
T2I
Port 5
BP50
INT6
BP52
INT1
BP51
INT6
BP53
INT1
Rev. 4708C–4BMCU–02/04
Pin Configuration
Figure 2. Pinning SSO20 Package
1
20
VSS
BP40/INT3/SC
2
19
BP43/INT3/SD
BP53/INT1
3
18
BP42/T2O
BP52/INT1
4
17
BP41/VMI/T2I
BP51/INT6
5
16
BP23
BP50/INT6
6
15
BP22
NC
7
14
BP21
OSC1
8
13
BP20/NTE
NC
9
12
NC
NC
10
11
NC
VDD
ATA6020N
Pin Description
2
Name
Type
Function
Alternate Function
Pin Number SS020
Reset State
VDD
–
Supply voltage
–
1
NA
VSS
–
NC
–
Circuit ground
–
20
NA
Not connected
–
10
–
NC
–
Not connected
–
11
–
BP20
I/O
Bi-directional I/O line of Port 2.0
NTE test mode enable, see also
section ''Master Reset''
13
Input
BP21
I/O
Bi-directional I/O line of Port 2.1
–
14
Input
BP22
I/O
Bi-directional I/O line of Port 2.2
–
15
Input
BP23
I/O
Bi-directional I/O line of Port 2.3
–
16
Input
BP40
I/O
Bi-directional I/O line of Port 4.0
SC serial clock or INT3 external
interrupt input
2
Input
BP41
I/O
Bi-directional I/O line of Port 4.1
VMI voltage monitor input or T2I
external clock input Timer 2
17
Input
BP42
I/O
Bi-directional I/O line of Port 4.2
T2O Timer 2 output
18
Input
19
Input
BP43
I/O
Bi-directional I/O line of Port 4.3
SD serial data I/O or INT3
external interrupt input
BP50
I/O
Bi-directional I/O line of Port 5.0
INT6 external interrupt input
6
Input
BP51
I/O
Bi-directional I/O line of Port 5.1
INT6 external interrupt input
5
Input
BP52
I/O
Bi-directional I/O line of Port 5.2
INT1 external interrupt input
4
Input
BP53
I/O
Bi-directional I/O line of Port 5.3
INT1 external interrupt input
3
Input
NC
–
Not connected
–
9
–
NC
–
Not connected
–
12
–
7
–
8
Input
NC
–
Not connected
OSC1
I
Oscillator input
–
External clock input or external
trimming resistor input
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Introduction
The ATA6020N is a member of Atmel’s 4-bit single-chip microcontroller family. It contains ROM, RAM, parallel I/O ports, one 8-bit programmable multifunction timer/counter,
voltage supervisor, interval timer with watchdog function and a sophisticated on-chip
clock generation with integrated RC-oscillators.
MARC4 Architecture
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and
on-chip peripherals. The CPU is based on the HARVARD architecture with physically
separated program memory (ROM) and data memory (RAM). Three independent
buses, the instruction bus, the memory bus and the I/O bus, are used for parallel communication between ROM, RAM and peripherals. This enhances program execution
speed by allowing both instruction prefetching, and a simultaneous communication to
the on-chip peripheral circuitry. The extremely powerful integrated interrupt controller
with associated eight prioritized interrupt levels supports fast and efficient processing of
hardware events. The MARC4 is designed for the high-level programming language
qFORTH. The core includes both, an expression and a return stack. This architecture
enables high-level language programming without any loss of efficiency or code density.
Figure 3. MARC4 Core
MARC4 CORE
Reset
Program
PC
memory
Reset
Clock
X
Y
SP
RP
Instruction
bus
Memory bus
Instruction
decoder
System
clock
Sleep
RAM
256 x 4-bit
Interrupt
controller
TOS
CCR
ALU
I/O bus
On-chip peripheral modules
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Components of MARC4
Core
The core contains ROM, RAM, ALU, a program counter, RAM address registers, an
instruction decoder and interrupt controller. The following sections describe each functional block in more detail:
ROM
The program memory (ROM) is mask programmed with the customer application program during the fabrication of the microcontroller. The ROM is addressed by a 12-bit
wide program counter, thus predefining a maximum program bank size of 2 Kbytes. An
additional 1-Kbyte of ROM exists, which is reserved for quality control self-test software
The lowest user ROM address segment is taken up by a 512-byte Zero page which contains predefined start addresses for interrupt service routines and special subroutines
accessible with single byte instructions (SCALL).
The corresponding memory map is shown in Figure 4. Look-up tables of constants can
also be held in ROM and are accessed via the MARC4's built-in TABLE instruction.
Figure 4. ROM Map of ATA6020N
1F8h
1F0h
1E8h
1E0h
7FFh
SCALL addresses
ROM
(2 K x 8 bit)
020 h
018h
010h
008h
000 h
1FFh
Zero page
000h
RAM
Z er o
p age
1E0h
I NT 7
1C0h
I NT 6
180h
I NT 5
140h
I NT 4
100h
I NT 3
0C0h
I NT 2
080h
I NT 1
040h
I NT 0
008h
000h
$R E SE T
$A U T O SL E E P
The ATA6020N contains 256 x 4-bit wide static random access memory (RAM), which is
used for the expression stack. The return stack and data memory are used for variables
and arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers
SP, RP, X and Y.
Figure 5. RAM Map
RAM
(256 x 4-bit)
Autosleep
Expression stack
3
Global
variables
RAM address register
X
4
0
TOS
TOS-1
TOS-2
FFh
FCh
SP
4-bit
Y
SP
TOS-1
Expression
stack
Return stack
11
0
RP
Return
stack
RP
04h
00h
07h
03h
Global
v
variables
12-bit
ATA6020N
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ATA6020N
Expression Stack
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All
arithmetic, I/O and memory reference operations take their operands, and return their
results to the expression stack. The MARC4 performs the operations with the top of
stack items (TOS and TOS-1). The TOS register contains the top element of the expression stack and works in the same way as an accumulator. This stack is also used for
passing parameters between subroutines and as a scratch pad area for temporary storage of data.
Return Stack
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for
storing return addresses of subroutines, interrupt routines and for keeping loop index
counts. The return stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of
the expression stack and the return stack. The two stacks within the RAM have a user
definable location and maximum depth.
Registers
The MARC4 controller has seven programmable registers and one condition code register. They are shown in the following programming model.
Program Counter (PC)
The program counter is a 12-bit register which contains the address of the next instruction to be fetched from ROM. Instructions currently being executed are decoded in the
instruction decoder to determine the internal micro-operations. For linear code (no calls
or branches) the program counter is incremented with every instruction cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address. The program counter is also used with the TABLE instruction to fetch 8-bit wide ROM constants.
Figure 6. Programming Model
11
0
PC
Program counter
0
7
0
RP
0
Return stack pointer
0
7
SP
Expression stack pointer
7
0
7
0
X
RAM address register (X)
Y
RAM address register (Y)
3
0
Top of stack register
TOS
3
CCR
C
0
--
B
I
Condition code register
Interrupt enable
Branch
Reserved
Carry/borrow
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RAM Address Registers
The RAM is addressed with the four 8-bit wide RAM address registers: SP, RP, X and Y.
These registers allow access to any of the 256 RAM nibbles.
Expression Stack Pointer (SP)
The stack pointer contains the address of the next-to-top 4-bit item (TOS-1) of the
expression stack. The pointer is automatically pre-incremented if a nibble is moved onto
the stack or post-decremented if a nibble is removed from the stack. Every post-decrement operation moves the item (TOS-1) to the TOS register before the SP is
decremented. After a reset, the stack pointer has to be initialized with >SP S0 to allocate
the start address of the expression stack area.
Return Stack Pointer (RP)
The return stack pointer points to the top element of the 12-bit wide return stack. The
pointer automatically pre-increments if an element is moved onto the stack, or it postdecrements if an element is removed from the stack. The return stack pointer increments and decrements in steps of 4. This means that every time a 12-bit element is
stacked, a 4-bit RAM location is left unwritten. This location is used by the qFORTH
compiler to allocate 4-bit variables. After a reset the return stack pointer has to be initialized via >RP FCh.
RAM Address Registers
(X and Y)
The X and Y registers are used to address any 4-bit item in RAM. A fetch operation
moves the addressed nibble onto the TOS. A store operation moves the TOS to the
addressed RAM location. By using either the pre-increment or post-decrement addressing mode arrays in RAM can be compared, filled or moved.
Top of Stack (TOS)
The top of stack register is the accumulator of the MARC4. All arithmetic/logic, memory
reference and I/O operations use this register. The TOS register receives data from the
ALU, ROM, RAM or I/O bus.
Condition Code Register (CCR)
The 4-bit wide condition code register contains the branch, the carry and the interrupt
enable flag. These bits indicate the current state of the CPU. The CCR flags are set or
reset by ALU operations. The instructions SET_BCF, TOG_BF, CCR! and DI allow
direct manipulation of the condition code register.
Carry/Borrow (C)
The carry/borrow flag indicates that the borrowing or carrying out of the arithmetic logic
unit (ALU) occurred during the last arithmetic operation. During shift and rotate operations, this bit is used as a fifth bit. Boolean operations have no effect on the C-flag.
Branch (B)
The branch flag controls the conditional program branching. Should the branch flag has
been set by a previous instruction a conditional branch will cause a jump. This flag is
affected by arithmetic, logic, shift, and rotate operations.
Interrupt Enable (I)
The interrupt enable flag globally enables or disables the triggering of all interrupt routines with the exception of the non-maskable reset. After a reset or on executing the DI
instruction, the interrupt enable flag is reset thus disabling all interrupts. The core will not
accept any further interrupt requests until the interrupt enable flag has been set again by
either executing an EI or SLEEP instruction.
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ATA6020N
ALU
The 4-bit ALU performs all the arithmetic, logical, shift and rotate operations with the top
two elements of the expression stack (TOS and TOS-1) and returns the result to the
TOS. The ALU operations affects the carry/borrow and branch flag in the condition code
register (CCR).
Figure 7. ALU Zero-address Operations
RAM
SP
TOS-1
TOS
TOS-2
TOS-3
TOS-4
ALU
CCR
I/O Bus
The I/O ports and the registers of the peripheral modules are I/O mapped. All communication between the core and the on-chip peripherals take place via the I/O bus and the
associated I/O control. With the MARC4 IN and OUT instructions, the I/O bus allows a
direct read or write access to one of the 16 primary I/O addresses. More about the I/O
access to the on-chip peripherals is described in the section “Peripheral Modules”. The
I/O bus is internal and is not accessible by the customer on the final microcontroller
device, but it is used as the interface for the MARC4 emulation (see section
“Emulation”).
Instruction Set
The MARC4 instruction set is optimized for the high level programming language
qFORTH. Many MARC4 instructions are qFORTH words. This enables the compiler to
generate a fast and compact program code. The CPU has an instruction pipeline allowing the controller to prefetch an instruction from ROM at the same time as the present
instruction is being executed. The MARC4 is a zero address machine, the instructions
containing only the operation to be performed and no source or destination address
fields. The operations are implicitly performed on the data placed on the stack. There
are one- and two-byte instructions which are executed within 1 to 4 machine cycles. A
MARC4 machine cycle is made up of two system clock cycles (SYSCL). Most of the
instructions are only one byte long and are executed in a single machine cycle. For
more information refer to the “MARC4 Programmer’s Guide”.
Interrupt Structure
The MARC4 can handle interrupts with eight different priority levels. They can be generated from the internal and external interrupt sources or by a software interrupt from the
CPU itself. Each interrupt level has a hard-wired priority and an associated vector for the
service routine in ROM (see Table 1 on page 9). The programmer can postpone the processing of interrupts by resetting the interrupt enable flag (I) in the CCR. An interrupt
occurrence will still be registered, but the interrupt routine only starts after the I-flag is
set. All interrupts can be masked, and the priority individually software configured by
programming the appropriate control register of the interrupting module (see section
“Peripheral Modules”).
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Figure 8. Interrupt Handling
INT7
7
INT7 active
Priority Level
RTI
INT5
6
5
INT5 active
RTI
INT3
4
INT2
3
INT3 active
RTI
2
INT2 pending
INT2 active
RTI
1
SWI0
0
INT0 pending
INT0 active
RTI
Main /
Autosleep
Main /
Autosleep
Time
Interrupt Processing
In order to process the eight interrupt levels, the MARC4 includes an interrupt controller
with two 8-bit wide interrupt pending and interrupt active registers. The interrupt controller samples all interrupt requests during every non-I/O instruction cycle and latches
these in the interrupt pending register. If no higher priority interrupt is present in the
interrupt active register, it signals the CPU to interrupt the current program execution. If
the interrupt enable bit is set, the processor enters an interrupt acknowledge cycle. During this cycle a short call (SCALL) instruction to the service routine is executed and the
current PC is saved on the return stack. An interrupt service routine is completed with
the RTI instruction. This instruction resets the corresponding bits in the interrupt pending/active register and fetches the return address from the return stack to the program
counter. When the interrupt enable flag is reset (triggering of interrupt routines are disabled), the execution of new interrupt service routines is inhibited but not the logging of
the interrupt requests in the interrupt pending register. The execution of the interrupt is
delayed until the interrupt enable flag is set again. Note that interrupts are only lost if an
interrupt request occurs while the corresponding bit in the pending register is still set
(i.e., the interrupt service routine is not yet finished).
It should be noted that automatic stacking of the RBR is not carried out by the hardware
and so if ROM banking is used, the RBR must be stacked on the expression stack by
the application program and restored before the RTI. After a master reset (power-on,
brown-out or watchdog reset), the interrupt enable flag and the interrupt pending and
interrupt active register are all reset.
Interrupt Latency
8
The interrupt latency is the time from the occurrence of the interrupt to the interrupt service routine being activated. This is extremely short (taking between 3 to 5 machine
cycles depending on the state of the core).
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Table 1. Interrupt Priority Table
Interrupt
Priority
ROM Address
Interrupt Opcode
Function
INT0
lowest
040h
C8h (SCALL 040h)
Software interrupt (SWI0)
INT1
|
080h
D0h (SCALL 080h)
External hardware interrupt, any
edge at BP52 or BP53
INT2
|
0C0h
D8h (SCALL 0C0h)
Timer 1 interrupt
INT3
|
100h
E8h (SCALL 100h)
SSI interrupt or external
hardware interrupt at BP40 or
BP43
INT4
|
140h
E8h (SCALL 140h)
Timer 2 interrupt
INT5
|
180h
F0h (SCALL 180h)
Software interrupt (SW15)
INT6
¯
1C0h
F8h (SCALL 1C0h)
External hardware interrupt, at
any edge at BP50 or BP51
INT7
highest
1E0h
FCh (SCALL 1E0h)
Voltage monitor (VM) interrupt
Table 2. Hardware Interrupts
Interrupt Mask
Interrupt
Register
Bit
Interrupt Source
INT1
P5CR
P52M1, P52M2
P53M1, P53M2
Any edge at BP52
Any edge at BP53
INT2
T1M
T1IM
Timer 1
INT3
SISC
SIM
SSI buffer full/empty or
BP40/BP43 interrupt
INT4
T2CM
T2IM
INT6
P5CR
P50M1, P50M2
P51M1, P51M2
INT7
VCM
VIM
Timer 2 compare match/overflow
Any edge at BP50
Any edge at BP51
External/internal voltage
monitoring
Software Interrupts
The programmer can generate interrupts by using the software interrupt instruction
(SWI), which is supported in qFORTH by predefined macros named SWI0...SWI7. The
software triggered interrupt operates exactly like any hardware triggered interrupt. The
SWI instruction takes the top two elements from the expression stack and writes the corresponding bits via the I/O bus to the interrupt pending register. Therefore, by using the
SWI instruction, interrupts can be re-prioritized or lower priority processes scheduled for
later execution.
Hardware Interrupts
In the ATA6020N, there are eleven hardware interrupt sources with seven different levels. Each source can be masked individually by mask bits in the corresponding control
registers. An overview of the possible hardware configurations is shown in Table 2.
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Master Reset
The master reset forces the CPU into a well-defined condition. It is unmaskable and is
activated independent of the current program state. It can be triggered by either initial
supply power-up, a short collapse of the power supply, the brown-out detection circuitry,
a watchdog time-out, or an external input clock supervisor stage (see Figure 9). A master reset activation will reset the interrupt enable flag, the interrupt pending register and
the interrupt active register. During the power-on reset phase, the I/O bus control signals
are set to reset mode, thereby, initializing all on-chip peripherals. All bi-directional ports
are set to input mode.
Attention: During any reset phase, the BP20/NTE input is driven towards VDD by an
additional internal strong pull-up transistor. This pin must not be pulled down to VSS during reset by any external circuitry representing a resistor of less than 150 kW.
Releasing the reset results in a short call instruction (opcode C1h) to the ROM address
008h. This activates the initialization routine $RESET which in turn has to initialize all
necessary RAM variables, stack pointers and peripheral configuration registers.
Figure 9. Reset Configuration
VVDD
DD
Pull-up
CL
CL
NRST
res
res
Reset
Reset
timer
timer
Internal
Internal
reset
reset
CL=SYSCL/4
CL=SYSCL/4
Power-on
Power-on
reset
reset
Brown-out
Brown-out
detection
detection
Power-on Reset and
Brown-out Detection
V
VDD
DD
V
VSS
SS
VDD
DD
VSS
SS
WatchWatchres
dog
dog res
CWD
CWD
Ext.
Ext. clock
clock
supervisor
supervisor
ExIn
ExIn
The ATA6020N has a fully integrated power-on reset and brown-out detection circuitry.
For reset generation no external components are needed.
These circuits ensure that the core is held in the reset state until the minimum operating
supply voltage has been reached. A reset condition will also be generated should the
supply voltage drop momentarily below the minimum operating level except when a
power-down mode is activated (the core is in SLEEP mode and the peripheral clock is
stopped). In this power-down mode the brown-out detection is disabled.
Two values for the brown-out voltage threshold are programmable via the BOT bit in the
SC-register.
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4708C–4BMCU–02/04
ATA6020N
A power-on reset pulse is generated by a VDD rise across the default BOT voltage level
(3.0 V). A brown-out reset pulse is generated when VDD falls below the brown-out voltage threshold. Two values for the brown-out voltage threshold are programmable via
the BOT-bit in the SC-register. When the controller runs in the upper supply voltage
range with a high system clock frequency, the high threshold must be used. When it
runs with a lower system clock frequency, the low threshold and a wider supply voltage
range may be chosen. For further details, see the electrical specification and the SCregister description for BOT programming.
Figure 10. Brown-out Detection
VDD
4.0 V
3.0 V
td
CPU
Reset
t
BOT = 1
td
CPU
Reset
td
BOT = 0
td = 1.5 ms (typically)
BOT = 1, low brown-out voltage threshold. (3.0 V is the reset value).
BOT = 0, high brown-out voltage threshold (4.0 V).
Watchdog Reset
The watchdog's function can be enabled at the WDC-register and triggers a reset with
every watchdog counter overflow. To suppress the watchdog reset, the watchdog
counter must be regularly reset by reading the watchdog register address (CWD). The
CPU reacts in exactly the same manner as a reset stimulus from any of the above
sources.
External Clock Supervisor
The external input clock supervisor function can be enabled if the external input clock is
selected within the CM- and SC-registers of the clock module. The CPU reacts in
exactly the same manner as a reset stimulus from any of the above sources.
Voltage Monitor
The voltage monitor consists of a comparator with internal voltage reference. It is used
to supervise the supply voltage or an external voltage at the VMI pin. The comparator for
the supply voltage has two internal programmable thresholds: one lower threshold
(4.0 V) and one higher threshold (5.0 V). For external voltages at the VMI pin, the comparator threshold is set to VBG = 1.25 V. The VMS-bit indicates if the supervised voltage
is below (VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated
when the VMS-bit is set or reset to detect a rising or falling slope. A voltage monitor
interrupt (INT7) is enabled when the interrupt mask bit (VIM) is reset in the
VMC-register.
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Figure 11. Voltage Monitor
VDD
Voltage monitor
BP41/
VMI
VMC
VM2
INT7
OUT
IN
VM1 VM0
VMST
-
-
VIM
res VMS
Voltage Monitor
Control/Status Register
Primary register address:
’F’hex
Bit 3
Bit 2
Bit 1
Bit 0
VMC: Write
VM2
VM1
VM0
VIM
Reset value: 1111b
VMST: Read
—
—
reserved
VMS
Reset value: xx11b
VM2: Voltage monitor Mode bit 2
VM1: Voltage monitor Mode bit 1
VM0: Voltage monitor Mode bit 0
Table 3. Voltage Monitor Modes
VM2
VM1
VM0
Function
1
1
1
Disable voltage monitor
1
1
0
External (VIM input), internal reference threshold (1.25 V), interrupt
with negative slope
1
0
1
Not allowed
1
0
0
External (VMI input), internal reference threshold (1.25 V), interrupt
with positive slope
0
1
1
Internal (supply voltage), high threshold (5.0 V), interrupt with
negative slope
0
1
0
Not allowed
0
0
1
Internal (supply voltage), low threshold (4.0 V), interrupt with negative
slope
0
0
0
Not allowed
VIM Voltage Interrupt Mask bit
•
VIM = 0, voltage monitor interrupt is enabled
•
VIM = 1, voltage monitor interrupt is disabled
VMS Voltage Monitor Status bit
12
•
VMS = 0, the voltage at the comparator input is below VRef
•
VMS = 1, the voltage at the comparator input is above VRef
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Figure 12. Internal Supply Voltage Supervisor
Low threshold
VMS = 1
High threshold
VDD
5.0 V
4.0 V
Low threshold
VMS = 0
High threshold
Figure 13. External Input Voltage Supervisor
Internal reference level
VMI
Negative slope
Interrupt positive slope
VMS = 1
VMS = 1
VMS = 0
VMS = 0
1.25 V
Positive slope
Interrupt negative slope
t
Clock Generation
Clock Module
The ATA6020N contains a clock module with two different internal RC-oscillator types.
OSC1 can be used as input for external clocks or to connect an external trimming resistor for RC-oscillator 2. All necessary circuitry, except the trimming resistor, is integrated
on-chip. One of these oscillator types or an external input clock can be selected to generate the system clock (SYSCL).
In applications that do not require exact timing, it is possible to use the fully integrated
RC-oscillator 1 without any external components. The RC-oscillator 1 center frequency
tolerance is better than ±50%. RC-oscillator 2 is a trimmable oscillator whereby the
oscillator frequency can be trimmed with an external resistor attached between OSC1
and GND. In this configuration, RC-oscillator 2 frequency can be maintained stable to
within a tolerance of ±15% over the full operating temperature and voltage range.
The clock module is programmable via software with the clock management register
(CM) and the system configuration register (SC). The required oscillator configuration
can be selected with the OS1-bit and the OS0-bit in the SC-register. A programmable
4-bit divider stage allows the adjustment of the system clock speed. A special feature of
the clock management is that an external oscillator may be used and switched on and
off via a port pin for the power-down mode. Before the external clock is switched off, the
internal RC-oscillator 1 must be selected with the CCS-bit and then the SLEEP mode
may be activated. In this state an interrupt can wake up the controller with the RC-oscillator, and the external oscillator can be activated and selected by software. A
synchronization stage avoids clock periods that are too short if the clock source or the
clock speed is changed. If an external input clock is selected, a supervisor circuit monitors the external input and generates a hardware reset if the external clock source fails
or drops below 500 kHz for more than 1 ms.
13
4708C–4BMCU–02/04
Figure 14. Clock Module
RC
oscillator 1
OSC1
Oscin
SYSCL
Ext. clock
ExOut
Stop
ExIn
RCOut1
Control
Stop
IN1
Cin
/2
/2
/2
/2
IN2
Divider
RC oscillator2
RCOut2
Stop
RTrim
Cin/16
Osc-Stop
CM
SC
BOT
---
OS1
Sleep
WDL
NSTOP
SUBCL
CCS
CSS1
CSS0
OS0
Table 4. Clock Modes
Clock Source for SYSCL
Mode
OS1
OS0
CCS = 1
CCS = 0
Clock Source
for SUBCL
1
1
1
RC-oscillator 1
(internal)
External input clock
Cin/16
2
0
1
RC-oscillator 1
(internal)
RC-oscillator 2 with
external trimming resistor
Cin/16
The clock module generates two output clocks. One is the system clock (SYSCL) and
the other the periphery (SUBCL). The SYSCL can supply the core and the peripherals
and the SUBCL can supply only the peripherals with clocks. The modes for clock
sources are programmable with the OS1-bit and OS0-bit in the SC-register and the
CCS-bit in the CM-register.
Oscillator Circuits and
External Clock Input Stage
The ATA6020N consists of two different internal RC-oscillators and one external clock
input stage.
RC-oscillator 1 Fully Integrated
For timing insensitive applications, it is possible to use the fully integrated
RC-oscillator 1. It operates without any external components and saves additional
costs. The RC-oscillator 1 center frequency tolerance is better than ±50% over the full
temperature and voltage range.
The basic center frequency of the RC-oscillator 1 is fO » 4.0 MHz The RC-oscillator 1 is
selected by default after power-on reset.
14
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Figure 15. RC-oscillator 1
RC-oscillator 1
RcOut1
RcOut1
Osc-Stop
Stop
Control
External Input Clock
The OSC1 can be driven by an external clock source provided it meets the specified
duty cycle, rise and fall times and input levels. Additionally, the external clock stage contains a supervisory circuit for the input clock. The supervisor function is controlled via
the OS1, OS0-bit in the SC-register and the CCS-bit in the CM-register. If the external
input clock fails and CCS = 0 is set in the CM-register, the supervisory circuit generates
a hardware reset. The input clock has failed if the frequency is less than 500 kHz for
more than 1 ms.
Figure 16. External Input Clock
Ext. input clock
ExOut
OSC1
Ext.
Clock
ExIn
Stop
RcOut1
Osc-Stop
CCS
Clock monitor
Res
Table 5. Supervisor Function Control Bits
RC-oscillator 2 with External
Trimming Resistor
OS1
OS0
CCS
Supervisor Reset Output (Res)
1
1
0
Enable
1
1
1
Disable
x
0
x
Disable
The RC-oscillator 2 is a high resolution trimmable oscillator whereby the oscillator frequency can be trimmed with an external resistor between OSC1 and V DD. In this
configuration, the RC-oscillator 2 frequency can be maintained stable to within a tolerance of ±10% over the full operating temperature and voltage range from VDD = 3.5 V to
5.5 V.
For example: An output frequency at the RC-oscillator 2 of 1.6 MHz, can be obtained by
connecting a resistor Rext = 47 kW (see Figure 17 on page 16).
15
4708C–4BMCU–02/04
Figure 17. RC-oscillator 2
RC-oscillator 2
RcOut2
RcOut2
OSC1
RTrim
Rext
Clock Management
Osc-Stop
Stop
The clock management register controls the system clock divider and synchronization
stage. Writing to this register triggers the synchronization cycle.
Clock Management Register
(CM)
Auxiliary register address: ’3’hex
CM
Bit 3
Bit 2
Bit 1
Bit 0
NSTOP
CCS
CSS1
CSS0
Reset value: 1111b
NSTOP
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
CCS
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, an external clock source or the RC-oscillator 2 with the external
resistor at OSC1 generates SYSCL dependent on the setting of OS0
and OS1 in the system configuration register
CSS1
Core Speed Select 1
CSS0
Core Speed Select 0
Table 6. Core Speed Select
16
CSS1
CSS0
Divider
Note
0
0
16
–
1
1
8
Reset value
1
0
4
–
0
1
2
–
ATA6020N
4708C–4BMCU–02/04
ATA6020N
System Configuration Register
(SC)
Primary register address: ’3’hex
Bit 3
Bit 2
Bit 1
Bit 0
SC: write
BOT
–
OS1
OS0
BOT
Brown-Out Threshold
BOT = 1, low brown-out voltage threshold (3.0 V)
BOT = 0, high brown-out voltage threshold (4.0 V)
OS1
Oscillator Select 1
OS0
Oscillator Select 0
Reset value: 1x11b
Table 7. Oscillator Select
Mode
OS1
OS0
Input for SUBCL
1
1
1
Cin/16
RC-oscillator 1 and external input clock
0
1
Cin/16
RC-oscillator 1 and RC-oscillator 2
2
Note:
Power-down Modes
Selected Oscillators
If bit CCS = 0 in the CM-register, the RC-oscillator 1 always stops.
The sleep mode is a shut-down condition which is used to reduce the average system
power consumption in applications where the microcontroller is not fully utilized. In this
mode, the system clock is stopped. The sleep mode is entered via the SLEEP instruction. This instruction sets the interrupt enable bit (I) in the condition code register to
enable all interrupts and stops the core. During the sleep mode the peripheral modules
remain active and are able to generate interrupts. The microcontroller exits the sleep
mode by carrying out any interrupt or a reset.
The sleep mode can only be kept when none of the interrupt pending or active register
bits are set. The application of the $AUTOSLEEP routine ensures the correct function of
the sleep mode.
The total power consumption is directly proportional to the active time of the microcontroller. For a rough estimation of the expected average system current consumption, the
following formula should be used:
Itotal (VDD,fsyscl) = ISleep + (IDD ´ tactive/ttotal)
IDD depends on VDD and fsyscl
The ATA6020N has various power-down modes. During the sleep mode the clock for
the MARC4 core is stopped. With the NSTOP-bit in the clock management register
(CM), it is programmable if the clock for the on-chip peripherals is active or stopped during the sleep mode. If the clock for the core and the peripherals is stopped the selected
oscillator is switched off.
Table 8. Power-down Modes
Mode
CPU Core
Osc-Stop(1)
Brown-out
Function
RC-oscillator 1
RC-oscillator 2
External Input
Clock
Active
RUN
NO
Active
RUN
YES
Power-down
SLEEP
NO
Active
RUN
YES
SLEEP
SLEEP
YES
STOP
STOP
STOP
Note:
1. Osc-Stop = SLEEP and NSTOP and WDL
17
4708C–4BMCU–02/04
Peripheral Modules
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O bus (see Figure 18). The IN or
OUT instructions allow direct addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted to enable direct addressing of the primary register. To address the auxiliary register, the access must be switched with an auxiliary
switching module. Thus, a single IN (or OUT) to the module address will read (or write
into) the modules primary register. Accessing the auxiliary register is performed with the
same instruction preceded by writing the module address into the auxiliary switching
module. Byte wide registers are accessed by multiple IN (or OUT) instructions. For more
complex peripheral modules, with a larger number of registers, extended addressing is
used. In this case, a bank of up to 16 subport registers are indirectly addressed with the
subport address. The first OUT-instruction writes the subport address to the
sub-address register, the second IN or OUT instruction reads data from or writes data to
the addressed subport.
Figure 18. Example of I/O Addressing
Module M1
Module ASW
(Address Pointer)
Subaddress Reg.
Module M2
Bank of
Primary Regs.
Auxiliary Switch
Module
Subport FH
1
Module M3
Aux. Reg.
5
Subport EH
Subport 1
Primary Reg.
Primary Reg.
Primary Reg.
Subport 0
2
3
6
4
I/O bus
to other modules
Indirect Subport Access
Dual Register Access
(Primary Register Write)
(Subport Register Write)
1
Addr. (SPort) Addr. (M1) OUT
2
SPort_Data
Addr. (M1)
Example of
qFORTH
Program
Code
Addr. (SPort) Addr. (M1) OUT
2
Prim._Data Addr. (M2) OUT
4
Addr. (M2) Addr. (ASW) OUT
5
Aux._Data Addr. (M2) OUT
6
(Auxiliary Register Write)
Addr. (M1) IN
Prim._Data Addr. (M3) OUT
(Primary Register Read)
6
Addr. (M3) IN
(Primary Register Read)
3
(Subport Register Write Byte)
1
Addr. (SPort) Addr. (M1) OUT
2
SPort_Data (lo) Addr. (M1)
Addr. (M2) IN
(Auxiliary Register Read )
2
SPort_Data (hi) Addr. (M1)
OUT
OUT
4
5
(Subport Register Read Byte)
1
(Primary Register Write)
3
OUT
(Subport Register Read)
1
Single Register Access
Addr. (SPort) Addr. (M1) OUT
Addr. (M2) Addr. (ASW) OUT
Addr. (M2) IN
(Auxiliary Register Write Byte)
4
Addr. (M2) Addr. (ASW) OUT
2
Addr. (M1) IN (hi)
5
Aux._Data (lo) Addr. (M2)
OUT
2
Addr. (M1) IN (lo)
5
Aux._Data (hi) Addr. (M2)
OUT
Addr. (ASW) = Auxililiary Switch Module Address
Addr. (Mx) = Module Mx Address
Addr. (SPort) = Subport Address
Prim._Data = Data to be written into Primary Register
Aux._Data = Data to be written into Auxiliary Register
Aux._Data (hi) = Data to be written into Auxiliary Register (high nibble)
SPort_Data (lo) = Data to be written into Subport (low nibble)
SPort_Data (hi) = Data to be written into Subport (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)
Aux._Data (lo) = Data to be written into Auxiliary Register (low nibble)
18
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Table 9. Peripheral Addresses
Port Address
2
Aux.
3
Aux.
4
Aux.
5
Aux.
Name
Write/Read
Reset Value
Register Function
Module Type
See Page
M2
21
P2DAT
W/R
1111b
Port 2 - data register/pin data
P2CR
W
1111b
Port 2 - control register
SC
W
1x11b
Port 3 - system configuration register
M3
17
CWD
R
xxxxb
Watchdog reset
M3
11
CM
21
W
1111b
Port 3 - clock management register
M2
16
P4DAT
W/R
1111b
Port 4 - data register/pin data
M2
24
P4CR
W
1111 1111b
Port 4 - control register (byte)
P5DAT
W/R
1111b
Port 5 - data register/pin data
P5CR
W
1111 1111b
Port 5 - control register (byte)
6
—
7
T12SUB
24
M2
23
23
Reserved
W
—
Data to Timer 1/2 subport
M1
18
Support address
0
T2C
W
0000b
Timer 2 control register
M1
35
1
T2M1
W
1111b
Timer 2 mode register 1
M1
35
2
T2M2
W
1111b
Timer 2 mode register 2
M1
37
3
T2CM
W
0000b
Timer 2 compare mode register
M1
38
4
T2CO1
W
1111b
Timer 2 compare register 1
M1
38
5
T2CO2
W
1111 1111b
Timer 2 compare register 2 (byte)
M1
38
6
—
—
—
Reserved
7
—
—
—
Reserved
8
T1C1
W
1111b
Timer 1 control register 1
M1
27
9
T1C2
W
x111b
Timer 1 control register 2
M1
27
A
WDC
W
1111b
Watchdog control register
M1
28
ASW
18
M2
48
B-F
Reserved
8
ASW
W
1111b
9
STB
W
xxxx xxxxb
Serial transmit buffer (byte)
SRB
R
xxxx xxxxb
Serial receive buffer (byte)
48
Aux.
SIC1
W
1111b
Serial interface control register 1
46
SISC
W/R
1x11b
Serial interface status/control register
Aux.
SIC2
W
1111b
Serial interface control register 2
A
Auxiliary/switch register
B
—
Reserved
C
—
Reserved
D
RBR
E
—
F
VMC
W
1111b
VMST
R
xx11b
W
0000b
—
ROM bank switch register
M2
48
47
M3
6
Voltage monitor control register
M3
12
Voltage monitor status register
M3
12
Reserved
19
4708C–4BMCU–02/04
Bi-directional Ports
Ports 2, 4 and 5 are 4 bits wide. All ports may be used for data input or output. All ports
are equipped with Schmitt trigger inputs and a variety of mask options for open-drain,
open-source, full-complementary outputs, pull-up and pull-down transistors. All Port
Data Registers (PxDAT) are I/O mapped to the primary address register of the respective port address and the Port Control Register (PxCR), to the corresponding auxiliary
register.
There are three different directional ports available:
Bi-directional Port 2
Port 2
4-bit wide bitwise-programmable I/O port.
Port 5
4-bit wide bitwise-programmable bi-directional port with optional static
pull-ups and programmable interrupt logic.
Port 4
4-bit wide bitwise-programmable bi-directional port also provides the I/O
interface to Timer 2, SSI, voltage monitor input and external interrupt input.
This, and all other bi-directional ports include a bitwise-programmable Control Register
(P2CR), which enables the individual programming of each port bit as input or output. It
also opens up the possibility of reading the pin condition when in output mode. This is a
useful feature for self-testing and for serial bus applications.
Port 2, however, has an increased drive capability and an additional low resistance pullup/-down transistor mask option.
Care should be taken connecting external components to BP20/NTE. During any reset
phase, the BP20/NTE input is driven towards VDD by an additional internal strong pull-up
transistor. This pin must not be pulled down (active or passive) to VSS during reset by
any external circuitry representing a resistor of less than 150 kW. This prevents the circuit from unintended switching to test mode enable through the application circuitry at
pin BP20/NTE. Resistors less than 150 kW might lead to an undefined state of the internal test logic thus disabling the application firmware.
To avoid any conflict with the optional internal pull-down transistors, BP20 handles the
pull-down options in a different way than all other ports. BP20 is the only port that
switches off the pull-down transistors during reset.
Figure 19. Bi-directional Port 2
VDD
I/O Bus
Pull-up
(1)
(Data out)
(1)
Static
Pull-up
(1)
I/O Bus
D
Q
P2DATy
BP2y
S
VDD
(1)
Master reset
I/O Bus
(1)
D S Q
(1)
Static
Pull-down
P2CRy
Pull-down
(Direction)
20
(1) Mask
options
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Port 2 Data Register (P2DAT)
Primary register address: ’2’hex
P2DAT
Bit 3
Bit 2
Bit 1
Bit 0
P2DAT3
P2DAT2
P2DAT1
P2DAT0
Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB
Port 2 Control Register (P2CR)
Auxiliary register address: ’2’hex
P2CR
Bit 3
Bit 2
Bit 1
Bit 0
P2CR3
P2CR2
P2CR1
P2CR0
Reset value: 1111b
Value: 1111b means all pins in input mode
Table 10. Port 2 Control Register
Bi-directional Port 5
Code
3210
Function
xxx1
BP20 in input mode
xxx0
BP20 in output mode
xx1x
BP21 in input mode
xx0x
BP21 in output mode
x1xx
BP22 in input mode
x0xx
BP22 in output mode
1xxx
BP23 in input mode
0xxx
BP23 in output mode
This, and all other bi-directional ports include a bitwise-programmable Control Register
(P5CR), which allows individual programming of each port bit as input or output. It also
opens up the possibility of reading the pin condition when in output mode. This is a useful feature for self testing and for serial bus applications.
The port pins can also be used as external interrupt inputs (see Figure 20 on page 22
and Figure 21 on page 22). The interrupts (INT1 and INT6) can be masked or independently configured to trigger on either edge. The interrupt configuration and port direction
is controlled by the Port 5 Control Register (P5CR). An additional low resistance pullup/-down transistor mask option provides an internal bus pull-up for serial bus
applications.
The Port 5 Data Register (P5DAT) is I/O mapped to the primary address register of
address '5'h and the Port 5 Control Register (P5CR) to the corresponding auxiliary register. The P5CR is a byte-wide register and is configured by writing first the low nibble
then the high nibble (see section “Addressing Peripherals”).
21
4708C–4BMCU–02/04
Figure 20. Bi-directional Port 5
VDD
I/O Bus
VDD
Pull-up
(1)
(1)
Static pull-up
VDD
(Data out)
(1)
I/O Bus
D
Q
P5DATy
BP5y
VDD
(1)
S
Master reset
(1)
IN enable
(1)
(1)
Static pull-down
Pull-down
Mask options
Figure 21. Port 5 External Interrupts
INT1
INT6
Data in
BP52
Data in
Bi-directional
Port
Bi-directional
Port
IN_Enable
IN_Enable
I/O-bus
I/O-bus
Data in
Data in
BP53
Bi-directional
Port
IN_Enable
Bi-directional
Port
IN_Enable
Decoder
P5CR
22
BP51
Decoder
Decoder
BP50
Decoder
P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Port 5 Data Register (P5DAT)
Primary register address:’5’hex
P5DAT
Bit 3
Bit 2
Bit 1
Bit 0
P5DAT3
P5DAT2
P5DAT1
P5DAT0
Reset value: 1111b
Port 5 Control Register (P5CR)
Byte Write
Auxiliary register address:’5’hex
P5CR
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
Bit 0
P51M2
P51M1
P50M2
P50M1
Bit 7
Bit 6
Bit 5
Bit 4
P53M2
P53M1
P52M2
P52M1
Reset value: 1111b
Reset value: 1111b
P5xM2, P5xM1 – Port 5x Interrupt Mode/Direction Code
Table 11. Port 5 Control Register
Auxiliary Address:’5’hex
Code
3210
First Write Cycle
Second Write Cycle
Code
3210
Function
Function
xx11
BP50 in input mode - interrupt disabled
xx11
BP52 in input mode – interrupt disabled
xx01
BP50 in input mode - rising edge interrupt
xx01
BP52 in input mode – rising edge interrupt
xx10
BP50 in input mode - falling edge interrupt
xx10
BP52 in input mode – falling edge interrupt
xx00
BP50 in output mode - interrupt disabled
xx00
BP52 in output mode – interrupt disabled
11xx
BP51 in input mode - interrupt disabled
11xx
BP53 in input mode – interrupt disabled
01xx
BP51 in input mode - rising edge interrupt
01xx
BP53 in input mode – rising edge interrupt
10xx
BP51 in input mode - falling edge interrupt
10xx
BP53 in input mode – falling edge interrupt
00xx
BP51 in output mode - interrupt disabled
00xx
BP53 in output mode – interrupt disabled
Bi-directional Port 4
The bi-directional Port 4 is both a bitwise configurable I/O port and provides the external
pins for the Timer 2, SSI and the voltage monitor input (VMI). As a normal port, it performs in exactly the same way as bi-directional Port 2 (see Figure 19 on page 20). Two
additional multiplexes allow data and port direction control to be passed over to other
internal modules (Timer 2, VM or SSI). The I/O-pins for the SC and SD lines have an
additional mode to generate an SSI-interrupt.
All four Port 4 pins can be individually switched by the P4CR-register. Figure 22 on page
24 shows the internal interfaces to bi-directional Port 4.
23
4708C–4BMCU–02/04
Figure 22. Bi-directional Port 4
I/O Bus
VDD
Intx
(1)
PxMRy
PIn
(1)
Static pull-up
VDD
POut
Pull-up
(1)
I/O Bus
D
Q
BPxy
PxDATy
S
(1)
VDD
Master reset
(Direction)
I/O Bus
D
S
(1)
(1)
Static pull-down
Q
PxCRy
Pull-down
PDir
(1) Mask
options
Port 4 Data Register (P4DAT)
Primary register address: ’4’hex
P4DAT
Bit 3
Bit 2
Bit 1
Bit 0
P4DAT3
P4DAT2
P4DAT1
P4DAT0
Reset value: 1111b
Port 4 Control Register (P4CR)
Byte Write
Auxiliary register address: ’4’hex
P4CR
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
Bit 0
P41M2
P41M1
P40M2
P40M1
Bit 7
Bit 6
Bit 5
Bit 4
P43M2
P43M1
P42M2
P42M1
Reset value: 1111b
Reset value: 1111b
P4xM2, P4xM1 – Port 4x Interrupt Mode/Direction Code
Table 12. Port 4 Control Register
Auxiliary Address: ’4’hex
First Write Cycle
Second Write Cycle
Code
3210
Function
Code
3210
Function
xx11
BP40 in input mode
xx11
BP42 in input mode
xx10
BP40 in output mode
xx10
BP42 in output mode
xx01
BP40 enable alternate function (SC for SSI)
xx0x
BP42 enable alternate function (T2O for Timer 2)
xx00
BP40 enable alternate function (falling edge interrupt
input for INT3)
11xx
BP43 in input mode
11xx
BP41 in input mode
10xx
BP43 in output mode
10xx
BP41 in output mode
01xx
BP43 enable alternate function (SD for SSI)
01xx
BP41 enable alternate function (VMI for voltage
monitor input)
00xx
BP43 enable alternate function (falling edge interrupt
input for INT3)
00xx
BP41 enable alternate function (T2I external clock
input for Timer 2)
24
–
–
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Universal Timer/Counter/
Communication Module
(UTCM)
The Universal Timer/counter/Communication Module (UTCM) consists of Timer 1,
Timer 2 and a Synchronous Serial Interface (SSI).
•
Timer 1 is an interval timer that can be used to generate periodical interrupts and as
prescaler for Timer 2, the serial interface and the watchdog function.
•
Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).
•
The SSI operates as a two-wire serial interface or as a shift register for modulation.
The modulator units work together with the timers and shift the data bits out of the
shift register.
There is a multitude of modes in which the timers and the serial interface can work
together.
Figure 23. UTCM Block Diagram
SYSCL
from clock module
SUBCL
Timer 1
NRST
Watchdog
MUX
INT2
Interval/Prescaler
Timer 2
T1OUT
4-bit Counter 2/1
MUX
Compare 2/1
Modulator 2
T2O
I/O bus
T2I
Control
POUT
8-bit Counter 2/2
MUX
DCG
INT4
Compare 2/2
TOG2
SSI
SCL
Receive-buffer
MUX
8-bit Shift-register
Transmit-buffer
Timer 1
SC
SD
Control
INT3
Timer 1 is an interval timer which can be used to generate periodic interrupts and as a
prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.
Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or
SYSCL. The timer output signal can be used as a prescaler clock or as SUBCL and as
source for the Timer 1 interrupt. Because of other system requirements Timer 1 output
T1OUT is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU
core -> sleep and OSC-Stop -> yes) the output T1OUT is stopped (T1OUT = 0). Nevertheless, Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The interrupt
is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit of the
T1C2 register. The time interval for the timer output can be programmed via the Timer 1
control register T1C1.
This timer starts running automatically after any power-on reset! If the watchdog function is not activated, the timer can be restarted by writing into the T1C1 register with
T1RM = 1.
25
4708C–4BMCU–02/04
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The
watchdog timer is a 3-bit counter that is supplied by a separate output of Timer 1. It generates a system reset when the 3-bit counter overflows. To avoid this, the 3-bit counter
must be reset before it overflows. The application software has to accomplish this by
reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initialization routine. There are two watchdog modes, in one mode the watchdog can be
switched on and off by software, in the other mode the watchdog is active and locked.
This mode can only be stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be
programmed via the watchdog control register (WDC).
Figure 24. Timer 1 Module
SYSCL
WDCL
MUX
SUBCL
CL1
14-bit
Prescaler
4-bit
Watchdog
NRST
INT2
T1CS
T1BP
T1IM
T1OUT
T1MUX
Figure 25. Timer 1 and Watchdog
T1C2
T1C1 T1RM T1C2 T1C1 T1C0
T1BP T1IM
3
Write of the
T1C1 register
T1IM=0
T1MUX
Decoder
INT2
MUX for interval timer
T1IM=1
T1OUT
RES Q1 Q2 Q3 Q4 Q5
CL1
CL
Q6
Q8
Q11
Q14 SUBCL
Q8
Q11
Q14
Watchdog
Divider/8
Decoder
MUX for watchdog timer
2
WDC WDL
WDR WDT1 WDT0
WDCL
RESET
(NRST)
RES
Watchdog
mode control
26
Divider
RESET
Read of the
CWD register
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Timer 1 Control Register 1
(T1C1)
Address: '7'hex – Subaddress: '8'hex
T1C1
Bit 3
Bit 2
Bit 1
Bit 0
T1RM
T1C2
T1C1
T1C0
Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB
T1RM
Timer 1 Restart Mode
T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
Note: If WDL = 0, Timer 1 restart is impossible
T1C2
Timer 1 Control bit 2
T1C1
Timer 1 Control bit 1
T1C0
Timer 1 Control bit 0
The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval
depends on this divider and the timer 1 input clock source. The timer input can be supplied by the system clock or via clock management. If the clock management generates
the SUBCL, the selected input clock from the RC oscillator or an external clock is
divided by 16
.
Table 13. Timer 1 Control Bits
T1C2
T1C1
T1C0
Divider
Time Interval with SUBCL
from Clock Management
Time Interval with
SYSCL = 2/1 MHz
0
0
0
2
Tin ´ 32
1 µs/2 µs
0
0
1
4
Tin ´ 64
2 µs/4 µs
4 µs/8 µs
0
1
0
8
Tin ´ 128
0
1
1
16
Tin ´ 256
8 µs/16 µs
1
0
0
32
Tin ´ 512
16 µs/32 µs
1
0
1
256
Tin ´ 4096
128 µs/256 µs
1
1
0
2048
Tin ´ 32768
1024 µs/2048 µs
1
1
1
16384
Tin ´ 262144
8192 µs/16384 µs
Note:
Tin: input clock period = 1/Cin (see Figure 14 on page 14)
Timer 1 Control Register 2
(T1C2)
Address: '7'hex – Subaddress: '9'hex
T1C2
Bit 3
Bit 2
Bit 1
Bit 0
–
T1BP
T1CS
T1IM
Reset value: x111b
Bit 3 = MSB, Bit 0 = LSB
T1BP
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
T1CS
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see Figure 28 on page 30)
T1CS = 0, CL1 = SYSCL (see Figure 28 on page 30)
T1IM
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
27
4708C–4BMCU–02/04
Watchdog Control Register
(WDC)
Address: ’7’hex – Subaddress: ’A’hex
WDC
Bit 3
Bit 2
Bit 1
Bit 0
WDL
WDR
WDT1
WDT0
Reset value: 1111b
Bit 3 = MSB, Bit 0 = LSB
WDL
WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no
effect. After the WDL-bit is cleared, the watchdog is active until a system
reset or power-on reset occurs.
WDR
WatchDog Run and stop mode
WDR = 1, the watchdog is stopped/disabled
WDR = 0, the watchdog is active/enabled
WDT1
WatchDog Time 1
WDT0
WatchDog Time 0
Both these bits control the time interval for the watchdog reset
Table 14. Watchdog Time Control Bits
Note:
Timer 2
Divider
Delay Time to Reset with
tin = 1/(2/1 MHz)
0
512
0.256 ms/0.512 ms
1
2048
1.024 ms/2.048 ms
1
0
16384
8.2 ms/16.4 ms
1
1
131072
65.5 ms/131 ms
WDT1
WDT0
0
0
tin: input clock period = 1/Cin (see Figure 14 on page 14)
8-/12 Bit Timer for:
•
Interrupt, square-wave, pulse and duty cycle generation
•
Baud rate generation for the internal shift register
•
Manchester and Bi-phase modulation together with the SSI
•
Carrier frequency generation and modulation together with the SSI
Timer 2 can be used as an interval timer for interrupt generation, as signal generator or
as baud rate generator and modulator for the serial interface. It consists of a 4-bit and
an 8-bit up counter stage which both have compare registers. The 4-bit counter stages
of Timer 2 are cascadable as a 12-bit timer or as an 8-bit timer with a 4-bit prescaler.
The timer can also be configured as an 8-bit timer and a separate 4-bit prescaler.
The Timer 2 input can be supplied via the system clock, the external input clock (T2I),
the Timer 1 output clock or the shift clock of the serial interface. The external input clock
T2I is not synchronized with SYSCL. Therefore, it is possible to use Timer 2 with a
higher clock speed than SYSCL. Furthermore; with that input clock Timer 2 operates in
the power-down mode SLEEP (CPU core -> sleep and OSC-Stop -> yes) as well as in
the POWER-DOWN (CPU core -> sleep and OSC-Stop -> no). All other clock sources
supplied no clock signal in SLEEP. The 4-bit counter stages of Timer 2 have an additional clock output (POUT).
28
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Its output has a modulator stage that allows the generation of pulses as well as the generation and modulation of carrier frequencies. Timer 2 output can modulate with the shift
register internal data output to generate Bi-phase- or Manchester-code.
If the serial interface is used to modulate a bit-stream, the 4-bit stage of Timer 2 has a
special task. The shift register can only handle bit-stream lengths divisible by 8. For
other lengths, the 4-bit counter stage can be used to stop the modulator after the right
bit-count is shifted out.
If the timer is used for carrier frequency modulation, the 4-bit stage works together with
an additional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty cycle. The 8-bit counter is used to enable and disable the modulator
output for a programmable count of pulses.
The timer has a 4-bit and an 8-bit compare register for programming the time interval, t.
For programming the timer function, it has four mode and control registers. The comparator output of stage 2 is controlled by a special compare mode register (T2CM). This
register contains mask bits for the actions (counter reset, output toggle, timer interrupt)
which can be triggered by a compare match event or the counter overflow. This architecture enables the timer function for various modes.
Timer 2 compare data values.
Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2).
Both these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register and 4-bit compare register.
For 12-bit compare data value:
m = x +1
0 £ x £ 4095
For 8-bit compare data value:
n = y +1
0 £ y £ 255
For 4-bit compare data value:
l = z +1
0 £ z £ 15
Figure 26. Timer 2
I/O-bus
P4CR
T2M1
T2M2
T2I
DCGO
SYSCL
T1OUT
CL2/1
SCL
CL2/2
4-bit Counter 2/1
RES
OVF1
POUT
T2O
DCG
8-bit Counter 2/2
RES
OUTPUT
OVF2
TOG2
T2C
Compare 2/1
Control
M2
Compare 2/2
MOUT
to
Modulator 3
INT4
Bi-phase
Manchester
Modulator
CM1
T2CO1
T2CM
T2CO2
Timer 2
modulator
output-stage
SSI POUT
SO
Control
I/O-bus
SSI
SSI
29
4708C–4BMCU–02/04
Timer 2 Modes
Mode 1: 12-bit Compare Counter
The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A compare match signal of the 4-bit and the 8-bit stage generates the signal for the counter
reset, toggle flip-flop or interrupt. The compare action is programmable via the compare
mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output
(POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.
Figure 27. 12-bit Compare Counter
POUT (CL2/1 /16)
CL2/1
4-bit counter
DCG
OVF2
8-bit counter
RES
TOG2
RES
INT4
4-bit compare
CM2
8-bit compare
CM1
4-bit register
Timer 2
output mode
and T2OTM-bit
T2D1, 0
8-bit register
T2RM
T2OTM
T2IM
T2CTM
Mode 2: 8-bit Compare Counter with 4-bit Programmable Prescaler
The 4-bit stage is used as a programmable prescaler for the 8-bit counter stage. In this
mode, a duty cycle stage is also available. This stage can be used as an additional 2-bit
prescaler or for generating duty cycles of 25%, 33% and 50%. The 4-bit compare output
(CM1) supplies the clock output (POUT) with clocks.
Figure 28. 8-bit Compare Counter
DCGO
POUT
CL2/1
4-bit counter
DCG
OVF2
8-bit counter
RES
TOG2
RES
INT4
4-bit compare
8-bit compare
CM2
CM1
4-bit register
Timer 2
output mode
and T2OTM-bit
T2D1, 0
8-bit register
T2RM
T2OTM
T2IM
T2CTM
Mode 3/4: 8-bit Compare Counter and 4-bit Programmable Prescaler
In these modes the 4-bit and the 8-bit counter stages work independently as a 4-bit
prescaler and an 8-bit timer with a 2-bit prescaler or as a duty cycle generator. Only in
mode 3 and mode 4 can the 8-bit counter be supplied via the external clock input (T2I)
which is selected via the P4CR register. The 4-bit prescaler is started by activating
mode 3 and stopped and reset in mode 4. Changing mode 3 and 4 has no effect for the
8-bit timer stage. The 4-bit stage can be used as a prescaler for the SSI or to generate
the stop signal for modulator 2.
30
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Figure 29. 4-/8-bit Compare Counter
DCGO
T2I
CL2/2
SYSCL
DCG
OVF2
8-bit counter
TOG2
RES
INT4
8-bit compare
CM2
Timer 2
output mode
and T2OTM-bit
P4CR P41M2, 1
T2D1, 0
8-bit register
T2RM
T2OTM
T2IM
T2CTM
T1OUT
SYSCL
MUX
CL2/1
4-bit counter
RES
SCL
4-bit compare
T2CS1, 0
Timer 2 Output Modes
POUT
CM1
4-bit register
The signal at the timer output is generated via Modulator 2. In the toggle mode, the compare match event toggles the output T2O. For high resolution duty cycle modulation 8
bits or 12 bits can be used to toggle the output. In the duty cycle burst modulator modes
the DCG output is connected to T2O and switched on and off either by the toggle flipflop
output or the serial data line of the SSI. Modulator 2 also has 2 modes to output the content of the serial interface as Bi-phase or Manchester code.
The modulator output stage can be configured by the output control bits in the T2M2
register. The modulator is started with the start of the shift register (SIR = 0) and
stopped either by carrying out a shift register stop (SIR = 1) or compare match event of
stage 1 (CM1) of Timer 2. For this task, Timer 2 mode 3 must be used and the prescaler
has to be supplied with the internal shift clock (SCL).
Figure 30. Timer 2 Modulator Output Stage
DCGO
SO
TOG2
T2O
RE
SSI
CONTROL
FE
Bi-phase/
Manchester
modulator
Toggle
S1
S3
M2
S2
RES/SET
OMSK
M2
T2M2
T2OS2, 1, 0 T2TOP
31
4708C–4BMCU–02/04
Timer 2 Output Signals
Timer 2 Output Mode 1
Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Figure 31. Interrupt Timer/Square Wave Generator — Output Toggles with Each Edge
Compare Match Event
Input
Counter 2
T2R
0
0
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
Counter 2
CMx
INT4
T2O
Toggle Mode B: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Figure 32. Pulse Generator — Timer Output Toggles with Timer Start If T2TS-Bit is Set
Input
Counter 2
T2R
0
0
0
1
2
3
4
5
6
7
4095/
255 0
1
2
3
4
5
6
Counter 2
CMx
INT4
T2O
Toggle
by start
T2O
Timer 2 Output Mode 1
Toggle Mode C: A Timer 2 compare match toggles the output flip-flop (M2) -> T2O
Figure 33. Pulse Generator — Timer Toggles with Timer Overflow and Compare Match
Input
Counter 2
T2R
0
0
0
1
2
3
4
5
6
7
4095/
255 0
1
2
3
4
5
6
Counter 2
CMx
OVF2
INT4
T2O
32
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Timer 2 Output Mode 2
Duty Cycle Burst Generator 1: The DCG output signal (DCGO) is given to the output,
and gated by the output flip-flop (M2)
Figure 34. Carrier Frequency Burst Modulation with Timer 2 Toggle Flip-Flop Output
DCGO
1 2 0 1 2 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5
Counter 2
TOG2
M2
T2O
Counter = compare register (=2)
Timer 2 Output Mode 3
Duty Cycle Burst Generator 2: The DCG output signal (DCGO) is given to the output,
and gated by the SSI internal data output (SO)
Figure 35. Carrier Frequency Burst Modulation with SSI Data Output
DCGO
1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter 2
Counter = compare register (=2)
TOG2
SO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
T2O
Timer 2 Output Mode 4
Bi-phase Modulator: Timer 2 modulates the SSI internal data output (SO) to Bi-phase
code.
Figure 36. Bi-phase Modulation
TOG2
SC
8-bit SR-Data
SO
0
0
1
1
0
1
0
Bit 7
T2O
0
1
Bit 0
0
1
1
0
1
0
1
Data: 00110101
33
4708C–4BMCU–02/04
Timer 2 Output Mode 5
Manchester Modulator: Timer 2 modulates the SSI internal data output (SO) to
Manchester code.
Figure 37. Manchester Modulation
TOG2
SC
8-bit SR-Data
0
SO
0
1
1
0
1
0
1
Bit 7
Bit 0
0
T2O
0
1
1
0
1
0
1
Bit 7
Bit 0
Data: 00110101
Timer 2 Output Mode 7
PWM Mode: Pulse-width modulation output on Timer 2 output pin (T2O)
In this mode the timer overflow defines the period and the compare register defines the
duty cycle. During one period only the first compare match occurrence is used to toggle
the timer output flip-flop, until overflow occur all further compare match are ignored. This
avoids the situation that changing the compare register causes the occurrence of several compare match during one period. The resolution at the pulse-width modulation
Timer 2 mode 1 is 12-bit and all other Timer 2 modes are 8-bit.
Figure 38. PWM Modulation
Input clock
Counter 2/2
T2R
0
0
50
255 0
100
255 0
150
255 0 50
255 0
100
Counter 2/2
CM2
OVF2
load the next
compare value
INT4
T2O
T1
T2
T
Timer 2 Registers
34
T2CO2=150
load
T3
T
load
T1
T
T2
T
T
Timer 2 has 6 control registers to configure the timer mode, the time interval, the input
clock and its output function. All registers are indirectly addressed using extended
addressing as described in section “Addressing Peripherals”. The alternate functions of
the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of
the Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42.
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Timer 2 Control Register (T2C)
Address: ’7’hex – Subaddress: ’0’hex
Bit 3
Bit 2
Bit 1
Bit 0
T2C
T2CS1
T2CS0
T2TS
T2R
T2CS1
Timer 2 Clock Select bit 1
T2CS0
Timer 2 Clock Select bit 0
Reset value: 0000b
Table 15. Timer 2 Clock Select Bits
T2CS1
T2CS0
Input Clock (CL 2/1) of Counter Stage 2/1
0
0
System clock (SYSCL)
0
1
Output signal of Timer 1 (T1OUT)
1
0
Internal shift clock of SSI (SCL)
1
1
Reserved
T2TS
Timer 2 Toggle with Start
T2TS = 0, the output flip–flop of Timer 2 is not toggled with the timer start
T2TS = 1, the output flip–flop of Timer 2 is toggled when the timer is started with
T2R
T2R
Timer 2 Run
T2R = 0, Timer 2 stop and reset
T2R = 1, Timer 2 run
Timer 2 Mode Register 1 (T2M1)
Address: ’7’hex – Subaddress: ’1’hex
Bit 3
Bit 2
Bit 1
Bit 0
T2M1
T2D1
T2D0
T2MS1
T2MS0
T2D1
Timer 2 Duty cycle bit 1
T2D0
Timer 2 Duty cycle bit 0
Reset value: 1111b
Table 16. Timer 2 Duty Cycle Bits
Function of Duty Cycle Generator
(DCG)
Additional Divider
Effect
1
Bypassed (DCGO0)
/1
1
0
Duty cycle 1/1 (DCGO1)
/2
0
1
Duty cycle 1/2 (DCGO2)
/3
T2D1
T2D0
1
T2MS1
Timer 2 Mode Select bit 1
T2MS0
Timer 2 Mode Select bit 0
35
4708C–4BMCU–02/04
Table 17. Timer 2 Mode Select Bits
Mode
T2MS1
T2MS0
1
1
1
12-bit compare counter, the
4-bit counter overflow (OVF1) DCG have to be bypassed
in this mode
0
4-bit compare output (CM1)
8-bit compare counter with
4-bit programmable
prescaler and duty cycle
generator
4-bit compare output (CM1)
8-bit compare counter
clocked by SYSCL or the
external clock input T2I, 4bit prescaler run, the
counter 2/1 starts after
writing mode 3
4-bit compare output (CM1)
8-bit compare counter
clocked by SYSCL or the
external clock input T2I, 4bit prescaler stop and
resets
2
3
4
Duty Cycle Generator
1
0
0
1
0
Clock Output (POUT)
Timer 2 Modes
The duty cycle generator generates duty cycles from 25%, 33% or 50%. The frequency
at the duty cycle generator output depends on the duty cycle and the Timer 2 prescaler
setting. The DCG-stage can also be used as an additional programmable prescaler for
Timer 2.
Figure 39. DCG Output Signals
DCGIN
DCGO0
DCGO1
DCGO2
DCGO3
36
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Timer 2 Mode Register 2 (T2M2)
Address: ’7’hex – Subaddress: ’2’hex
Bit 3
Bit 2
Bit 1
Bit 0
T2M2
T2TOP
T2OS2
T2OS1
T2OS0
T2TOP
Timer 2 Toggle Output Preset
This bit allows the programmer to preset the Timer 2 output T2O.
T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)
T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)
Note: If T2R = 1, no output preset is possible
T2OS2
Timer 2 Output Select bit 2
T2OS1
Timer 2 Output Select bit 1
T2OS0
Timer 2 Output Select bit 0
Reset value: 1111b
Table 18. Timer 2 Output Select Bits
Output
Mode
T2OS2
T2MS1
T2MS0
1
1
1
1
Toggle mode: a Timer 2 compare match
toggles the output flip-flop (M2) -> T2O
2
1
1
0
Duty cycle burst generator 1: the DCG output
signal (DCG0) is given to the output and
gated by the output flip-flop (M2)
3
1
0
1
Duty cycle burst generator 2: the DCG output
signal (DCGO) is given to the output and
gated by the SSI internal data output (SO)
4
1
0
0
Bi-phase modulator: Timer 2 modulates the
SSI internal data output (SO) to Bi-phase
code
5
0
1
1
Manchester modulator: Timer 2 modulates
the SSI internal data output (SO) to
Manchester code
6
0
1
0
SSI output: T2O is used directly as SSI
internal data output (SO)
7
0
0
1
PWM mode: an 8/12-bit PWM mode
8
0
0
0
Not allowed
Note:
Timer 2 Compare and Compare
Mode Registers
Clock Output (POUT)
If one of these output modes is used the T2O alternate function of Port 4 must also be
activated.
Timer 2 has two separate compare registers, T2CO1 for the 4-bit stage and T2CO2 for
the 8-bit stage of Timer 2. The timer compares the contents of the compare register current counter value and if it matches it generates an output signal. Depending on the
timer mode, this signal is used to generate a timer interrupt, to toggle the output flip-flop
as SSI clock or as a clock for the next counter stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and T2CO2 bits 4 to 11 of the 12-bit
compare value. In all other modes, the two compare registers work independently as a
4-bit and 8-bit compare register. When assigned to the compare register a compare
event will be suppressed.
37
4708C–4BMCU–02/04
Timer 2 Compare Mode
Register (T2CM)
Address: ’7’hex – Subaddress: ’3’hex
T2CM
Bit 3
Bit 2
Bit 1
Bit 0
T2OTM
T2CTM
T2RM
T2IM
Reset value: 0000b
T2OTM
Timer 2 Overflow Toggle Mask bit
T2OTM = 0, disable overflow toggle
T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles the output
flip-flop (TOG2). If the T2OTM-bit is set, only a counter overflow
can generate an interrupt except on the Timer 2 output mode 7.
T2CTM
Timer 2 Compare Toggle Mask bit
T2CTM = 0, disable compare toggle
T2CTM = 1, enable compare toggle, a match of the counter with the compare
register toggles output flip-flop (TOG2). In Timer 2 output mode 7
and when the T2CTM-bit is set, only a match of the counter with the
compare register can generate an interrupt.
T2RM
Timer 2 Reset Mask bit
T2RM = 0, disable counter reset
T2RM = 1, enable counter reset, a match of the counter with the compare register
resets the counter
T2IM
Timer 2 Interrupt Mask bit
T2IM = 0, disable Timer 2 interrupt
T2IM = 1, enable Timer 2 interrupt
Table 19. Timer 2 Toggle Mask Bits
Timer 2 Output Mode
T2OTM
T2CTM
1, 2, 3, 4, 5 and 6
0
x
1, 2, 3, 4, 5 and 6
1
x
Overflow (OVF2)
7
x
1
Compare match (CM2)
Timer 2 COmpare Register 1
(T2CO1)
Timer 2 Interrupt Source
Compare match (CM2)
Address: ’7’hex – Subaddress: ’4’hex
T2CO1
Write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: 1111b
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Timer 2 COmpare Register 2
(T2CO2) Byte Write
Address: ’7’hex – Subaddress: ’5’hex
T2CO2
38
First write
cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: 1111b
Second write
cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: 1111b
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4708C–4BMCU–02/04
ATA6020N
Synchronous Serial Interface (SSI)
SSI Features
•
SSI Peripheral Configuration
–
2- and 3-wire NRZ
–
2-wire mode
With Timer 2:
–
Bi-phase modulation
–
Manchester modulation
–
Pulse-width demodulation
–
Burst modulation
The synchronous serial interface (SSI) can be used either for serial communication with
external devices such as EEPROMs, shift registers, display drivers, other microcontrollers, or as a means for generating and capturing on-chip serial streams of data. External
data communication takes place via Port 4’s (BP4) multi-functional port which can be
software configured by writing the appropriate control word into the P4CR register. The
SSI can be configured in any one of the following ways:
1. 2-wire external interface for bi-directional data communication with one data terminal and one shift clock. The SSI uses Port BP43 as a bi-directional serial data
line (SD) and BP40 as a shift clock line (SC).
2. 3-wire external interface for simultaneous input and output of serial data, with a
serial input data terminal (SI), a serial output data terminal (SO) and a shift clock
(SC). The SSI uses BP40 as a shift clock (SC), while the serial data input (SI) is
applied to BP43 (configured in P4CR as input). Serial output data (SO) in this
case is passed through to BP42 (configured in P4CR to T2O) via Timer 2 output
stage (T2M2 configured in mode 6).
3. Timer/SSI combined modes – the SSI used together with Timer 2 is capable of
performing a variety of data modulation and functions (see section ’’Timer’’). The
modulating data is converted by the SSI into a continuous serial stream of data
which is in turn modulated in one of the timer functional blocks.
Figure 40. Block Diagram of the Synchronous Serial Interface
I/O-bus
Timer 2
SIC1
SIC2
SISC
SO
Control
SC
TOG2
POUT
T1OUT
SYSCL
SI SCI
INT3
SC
SSI-Control
Output
SO
/2
Shift_CL
MSB
8-bit Shift Register
STB
SI
LSB
SD
SRB
Transmit
Buffer
Receive
Buffer
I/O-bus
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4708C–4BMCU–02/04
General SSI Operation
The SSI is comprised essentially of an 8–bit shift register with two associated 8–bit buffers - the receive buffer (SRB) for capturing the incoming serial data and a transmit buffer
(STB) for intermediate storage of data to be serially output. Both buffers are directly
accessable by software. Transferring the parallel buffer data into and out of the shift register is controlled automatically by the SSI control, so that both single byte transfers or
continuous bit streams can be supported.
The SSI can generate the shift clock (SC) either from one of several on-chip clock
sources or accept an external clock. The external shift clock is output on, or applied to
the Port BP40. Selection of an external clock source is performed by the Serial Clock
Direction control bit (SCD). In the combinational modes, the required clock is selected
by the corresponding timer mode.
The SSI can operate in three data transfer modes – synchronous 8-bit shift mode, a
9-bit Multi-Chip Link mode (MCL), containing 8-bit data and 1-bit acknowledge, and a
corresponding 8-bit MCL mode without acknowledge. In both MCL modes the data
transmission begins after a valid start condition and ends with a valid stop condition.
External SSI clocking is not supported in these modes. The SSI should thus generate
and have full control over the shift clock so that it can always be regarded as an
MCL-bus master device.
All directional control of the external data port used by the SSI is handled automatically
and is dependent on the transmission direction set by the Serial Data Direction (SDD)
control bit. This control bit defines whether the SSI is currently operating in transmit (TX)
mode or receive (RX) mode.
Serial data is organized in 8-bit telegrams which are shifted with the most significant bit
first. In the 9-bit MCL mode, an additional acknowledge bit is appended to the end of the
telegram for handshaking purposes (see ’’MCL protocol’’).
At the beginning of every telegram, the SSI control loads the transmit buffer into the shift
register and proceeds immediately to shift data serially out. At the same time, incoming
data is shifted into the shift register input. This incoming data is automatically loaded
into the receive buffer when the complete telegram has been received. Data can, if
required thus be simultaneously received and transmitted.
Before data can be transferred, the SSI must first be activated. This is performed by
means of the SSI reset control (SIR) bit. All further operation then depends on the data
directional mode (TX/RX) and the present status of the SSI buffer registers shown by
the Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates the
(empty/full) status of either the transmit buffer (in TX mode), or the receive buffer (in RX
mode). The control logic ensures that data shifting is temporarily halted at any time, if
the appropriate receive/transmit buffer is not ready (SRDY = 0). The SRDY status will
then automatically be set back to '1' and data shifting resumed as soon as the application software loads the new data into the transmit register (in TX mode) or frees the shift
register by reading it into the receive buffer (in RX mode).
A further activity status (ACT) bit indicates the present status of serial communication.
The ACT bit remains high for the duration of the serial telegram or if MCL stop or start
conditions are currently being generated. Both the current SRDY and ACT status can be
read in the SSI status register. To deactivate the SSI, the SIR bit must be set high.
40
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8-bit Synchronous Mode
Figure 41. 8-bit Synchronous Mode
SC
(rising edge)
SC
(falling edge)
0
DATA
0
1
1
0
1
0
Bit 7
SD/TO2
0
1
Bit 0
0
Bit 7
1
1
0
1
0
1
Bit 0
Data: 00110101
In the 8-bit synchronous mode, the SSI can operate as either a 2- or 3-wire interface
(see ’’SSI Peripheral Configuration’’). The serial data (SD) is received or transmitted in
NRZ format, synchronized to either the rising or falling edge of the shift clock (SC). The
choice of clock edge is defined by the Serial Mode Control bits (SM0, SM1). It should be
noted that the transmission edge refers to the SC clock edge with which the SD
changes. To avoid clock skew problems, the incoming serial input data is shifted in with
the opposite edge.
When used together with one of the timer modulator or demodulator stages, the SSI
must be set in the 8-bit synchronous mode 1.
In RX mode, as soon as the SSI is activated (SIR = 0), 8 shift clocks are generated and
the incoming serial data is shifted into the shift register. This first telegram is automatically transferred into the receive buffer and the SRDY flag is set to 0 indicating that the
receive buffer contains valid data. At the same time an interrupt (if enabled) is generated. The SSI then continues shifting in the following 8-bit telegram. If, during this time
the first telegram has been read by the controller, the second telegram will also be transferred in the same way into the receive buffer and the SSI will continue clocking in the
next telegram. Should, however, the first telegram not have been read (SRDY = 1), then
the SSI will stop, temporarily holding the second telegram in the shift register until a certain point in time when the controller is able to service the receive buffer. In this way no
data is lost or overwritten.
Deactivating the SSI (SIR = 1) in mid-telegram will immediately stop the shift clock and
latch the present contents of the shift register into the receive buffer. This can be used
for clocking in a data telegram of less than 8 bits in length. Care should be taken to read
out the final complete 8-bit data telegram of a multiple word message before deactivating the SSI (SIR = 1) and terminating the reception. After termination, the shift register
contents will overwrite the receive buffer.
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4708C–4BMCU–02/04
Figure 42. Example of 8-bit Synchronous Transmit Operation
SC
msb
lsb
7 6 5 4 3 2 1
SD
msb
0
lsb msb
lsb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
tx data 1
tx data 2
0
tx data 3
SIR
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Write STB
(tx data 1)
Write STB
(tx data 2)
Write STB
(tx data 3)
Figure 43. Example of 8-bit Synchronous Receive Operation
SC
lsb
msb
SD
msb
lsb
msb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
rx data 1
lsb
7 6 5 4 3 2 1 0 7 6 5 4
rx data 2
rx data 3
SIR
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Read SRB
(rx data 1)
9-bit Shift Mode
Read SRB
(rx data 2)
Read SRB
(rx data 3)
In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It
always operates as an MCL master device, i.e., SC is always generated and output by
the SSI. Both the MCL start and stop conditions are automatically generated whenever
the SSI is activated or deactivated by the SIR-bit. In accordance with the MCL protocol,
the output data is always changed in the clock low phase and shifted in on the high
phase.
Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate
data direction for the first word must be set using the SDD control bit. The state of this
bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data
bits are, depending on the selected direction, either clocked into or out of the shift register. During the 9th clock period, the port direction is automatically switched over so that
the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the
acknowledge bit received from the device is captured in the SSI Status Register (TACK)
where it can be read by the controller. A receive mode, the state of the acknowledge bit
to be returned to the device is predetermined by the SSI Status Register (RACK).
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Changing the directional mode (TX/RX) should not be performed during the transfer of
an MCL telegram. One should wait until the end of the telegram which can be detected
using the SSI interrupt (IFN = 1) or by interrogating the ACT status.
A 9-bit telegram, once started will always run to completion and will not be prematurely
terminated by the SIR bit. So, if the SIR-bit is set to '1' in with telegram, the SSI will complete the current transfer and terminate the dialog with an MCL stop condition.
Figure 44. Example of MCL Transmit Dialog
Start
Stop
SC
lsb
msb
SD
7 6 5 4 3 2 1 0 A
msb
lsb
7 6 5 4 3 2 1 0 A
tx data 1
tx data 2
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
SIR
SDD
Write STB
(tx data 1)
Write STB
(tx data 2)
Figure 45. Example of MCL Receive Dialog
Start
Stop
SC
lsb
msb
SD
7 6 5 4 3 2 1 0 A
tx data 1
msb
lsb
7 6 5 4 3 2 1 0 A
rx data 2
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
SIR
SDD
Write STB
(tx data 1)
Read SRB
(rx data 2)
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4708C–4BMCU–02/04
8-bit Pseudo MCL Mode
In this mode, the SSI exhibits all the typical MCL operational features except for the
acknowledge-bit which is never expected or transmitted.
MCL Bus Protocol
The MCL protocol constitutes a simple 2-wire bi-directional communication highway via
which devices can communicate control and data information. Although the MCL protocol can support multi-master bus configurations, the SSI, in MCL mode is intended for
use purely as a master controller on a single master bus system. So all reference to
multiple bus control and bus contention will be omitted at this point.
All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit.
Normally the communication channel is opened with a so-called start condition, which
initializes all devices connected to the bus. This is then followed by a data telegram,
transmitted by the master controller device. This telegram usually contains an 8-bit
address code to activate a single slave device connected onto the MCL bus. Each slave
receives this address and compares it with its own unique address. The addressed
slave device, if ready to receive data will respond by pulling the SD line low during the
9th clock pulse. This represents a so-called MCL acknowledge. The controller on
detecting this affirmative acknowledge then opens a connection to the required slave.
Data can then be passed back and forth by the master controller, each 8-bit telegram
being acknowledged by the respective recipient. The communication is finally closed by
the master device and the slave device put back into standby by applying a stop condition onto the bus.
Figure 46. MCL Bus Protocol 1
(1) (2)
(4)
(4)
(3) (1)
SC
SD
Start
condition
44
Data
valid
Data
change
Data
valid
Stop
condition
Bus not busy (1)
Both data and clock lines remain HIGH.
Start data transfer (2)
A HIGH to LOW transition of the SD line while the clock (SC)
is HIGH defines a START condition.
Stop data transfer (3)
A LOW to HIGH transition of the SD line while the clock (SC)
is HIGH defines a STOP condition.
Data valid (4)
The state of the data line represents valid data when, after
START condition, the data line is stable for the duration of the
HIGH period of the clock signal.
Acknowledge
All address and data words are serially transmitted to and
from the device in eight-bit words. The receiving device
returns a zero on the data line during the ninth clock cycle to
acknowledge word receipt.
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Figure 47. MCL Bus Protocol 2
SC
1
SD
SSI Interrupt
Start
1st Bit
n
8
9
8th Bit
ACK
Stop
The SSI interrupt INT3 can be generated either by an SSI buffer register status (i.e.,
transmit buffer empty or receive buffer full) at the end of an SSI data telegram or on the
falling edge of the SC/SD pins on Port 4 (see P4CR). SSI interrupt selection is performed by the Interrupt Function control bit (IFN). The SSI interrupt is usually used to
synchronize the software control of the SSI and inform the controller of the present SSI
status. Port 4 interrupts can be used together with the SSI or, if the SSI itself is not
required, as additional external interrupt sources. In either case this interrupt is capable
of waking the controller out of sleep mode.
To enable and select the SSI relevant interrupts use the SSI interrupt mask (SIM) and
the Interrupt Function (IFN) while Port 4 interrupts are enabled by setting appropriate
control bits in P4CR register.
Modulation
If the shift register is used together with Timer 2 for modulation purposes, the 8-bit synchronous mode must be used. In this case, the unused Port 4 pins can be used as
conventional bi-directional ports.
The modulation stage, if enabled, operates as soon as the SSI is activated (SIR = 0)
and ceases when deactivated (SIR = 1).
Due to the byte-orientated data control, the SSI (when running normally) generates
serial bit-streams which are submultiples of 8 bits. However, an SSI output masking
(OMSK) function permits, however, the generation of bit-streams of any length. The
OMSK signal is derived indirectly from the 4-bit prescaler of the Timer 2 and masks out
a programmable number of unrequired trailing data bits during the shifting out of the
final data word in the bit stream. The number of non-masked data bits is defined by the
value pre-programmed in the prescaler compare register. To use output masking, the
modulator stop mode bit (MSM) must be set to '0' before programming the final data
word into the SSI transmit buffer. This in turn, enables shift clocks to the prescaler when
this final word is shifted out. On reaching the compare value, the prescaler triggers the
OMSK signal and all following data bits are blanked.
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4708C–4BMCU–02/04
Figure 48. SSI Output Masking Function
Timer 2
CL2/1
4-bit counter 2/1
SCL
Compare 2/1
CM1
OMSK
SO
Control
SC
SSI-control
Output
TOG2
POUT
T1OUT
SYSCL
SO
/2
Shift_CL
MSB
SI
8-bit shift register
LSB
Serial Interface Registers
Serial Interface Control Register
1 (SIC1)
Auxiliary register address: ’9’hex
Bit 3
Bit 2
Bit 1
Bit 0
SIC1
SIR
SCD
SCS1
SCS0
SIR
Serial Interface Reset
SIR = 1, SSI inactive
SIR = 0, SSI active
SCD
Serial Clock Direction
SCD = 1, SC line used as output
SCD = 0, SC line used as input
Note: This bit has to be set to '1' during the MCL mode
SCS1
Serial Clock source Select bit 1
SCS0
Serial Clock source Select bit 0
Reset value: 1111b
Note: with SCD = '0' the bits SCS1 and SCS0 are insignificant
Table 20. Serial Clock Source Select Bits
46
SCS1
SCS0
1
1
SYSCL/2
Internal Clock for SSI
1
0
T1OUT/2
0
1
POUT/2
0
0
TOG2/2
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ATA6020N
•
In transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded
(SRDY = 1).
•
Setting SIR-bit loads the contents of the shift register into the receive buffer
(synchronous 8-bit mode only).
•
In MCL modes, writing a 0 to SIR generates a start condition and writing a 1
generates a stop condition.
Serial Interface Control Register
2 (SIC2)
Auxiliary register address: ’A’hex
Bit 3
Bit 2
Bit 1
Bit 0
SIC2
MSM
SM1
SM0
SDD
MSM
Modular Stop Mode
MSM = 1, modulator stop mode disabled (output masking off)
MSM = 0, modulator stop mode enabled (output masking on) - used in modulation
modes for generating bit streams which are not sub–multiples of 8 bit.
SM1
Serial Mode control bit 1
SM0
Serial Mode control bit 0
Reset value: 1111b
Table 21. Serial Mode Control Bits
Mode
SM1
SM0
1
1
1
2
1
0
8-bit NRZ-Data changes with the falling edge of SC
3
0
1
9-bit two-wire MCL compatible
4
0
0
8-bit two-wire pseudo MCL compatible (no
acknowledge)
SDD
SSI Mode
8-bit NRZ-Data changes with the rising edge of SC
Serial Data Direction
SDD = 1, transmit mode - SD line used as output (transmit data). SRDY is set by a
transmit buffer write access
SDD = 0, receive mode - SD line used as input (receive data). SRDY is set by a
receive buffer read access
SDD controls port directional control and defines the reset function for the SRDY-flag
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4708C–4BMCU–02/04
Serial Interface Status and
Control Register (SISC)
Primary register address: ’A’hex
Bit 3
SISC
write
SISC
read
–
Bit 2
Bit 1
Bit 0
RACK
SIM
IFN
Reset value: 1111b
TACK
ACT
SRDY
Reset value: xxxxb
RACK
Receive ACKnowledge status/control bit for MCL mode
RACK = 0, transmit acknowledge in next receive telegram
RACK = 1, transmit no acknowledge in last receive telegram
TACK
Transmit ACKnowledge status/control bit for MCL mode
TACK = 0, acknowledge received in last transmit telegram
TACK = 1, no acknowledge received in last transmit telegram
SIM
Serial Interrupt Mask
SIM = 1, disable interrupts
SIM = 0, enable serial interrupt. An interrupt is generated.
IFN
Interrupt FuNction
IFN = 1, the serial interrupt is generated at the end of the telegram
IFN = 0, the serial interrupt is generated when the SRDY goes low
(i.e., buffer becomes empty/full in transmit/receive mode)
SRDY
Serial interface buffer ReaDY status flag
SRDY = 1, in receive mode: receive buffer empty
in transmit mode: transmit buffer full
SRDY = 0, in receive mode: receive buffer full
in transmit mode: transmit buffer empty
ACT
Transmission ACTive status flag
ACT = 1, transmission is active, i.e., serial data transfer. Stop or start
conditions are currently in progress.
ACT = 0, transmission is inactive
Serial Transmit Buffer (STB) –
Byte Write
Primary register address: ’9’hex
STB
First write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: xxxxb
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the
shift register and starts shifting with the most significant bit.
Serial Receive Buffer (SRB) –
Byte Read
Primary register address: ’9’hex
SRB
First read cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
Second read cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: xxxxb
The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most
significant bit first) and loads content into the receive buffer when complete telegram
has been received.
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Combination Modes
The UTCM consists of one timer (Timer 2) and a serial interface. There is a multitude of
modes in which the timers and serial interface can work together. The 8-bit wide serial
interface operates as shift register for modulation. The modulator units work together
with the timers and shift the data bits into or out of the shift register.
Combination Mode Timer 2 and
SSI
Figure 49. Combination Timer 2 and SSI
I/O-bus
P4CR
T2M1
T2M2
T2I
DCGO
SYSCL
T1OUT
reserved
SCL
CL2/1
4-bit Counter 2/1
RES
T2C
OVF1
T2O
CL2/2
DCG
POUT
Compare 2/1
8-bit Counter 2/2
RES
Timer 2 - control
OUTPUT
OVF2
TOG2
Compare 2/2
MOUT
INT4
POUT
T2CO1
Bi-phase
Manchester
Modulator
CM1
T2CM
T2CO2
TOG2
SO
Timer 2
modulator
output-stage
Control
I/O-bus
SIC1
SIC2
SISC
Control
TOG2
POUT
T1OUT
SYSCL
INT3
SCLI
SCL
SO
SC
SSI-control
Output
SO
SI
Shift_CL
MSB
8-bit shift register
STB
SD
LSB
SRB
Transmit
buffer
Receive
buffer
I/O-bus
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4708C–4BMCU–02/04
Combination Mode 1 Burst Modulation
SSI mode 1:
8-bit NRZ and internal data SO output to the Timer 2
modulator stage
Timer 2 mode 1, 2, 3 or 4:
8-bit compare counter with 4-bit programmable prescaler
and DCG
Timer 2 output mode 3:
Duty cycle burst generator
Figure 50. Carrier Frequency Burst Modulation with the SSI Internal Data Output
DCGO
1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter 2
Counter = compare register (=2)
TOG2
SO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
T2O
Combination Mode 2: Bi-phase Modulation 1
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2
modulator stage
Timer 2 mode 1, 2, 3 or 4:
8-bit compare counter with 4-bit programmable prescaler
Timer 2 output mode 4:
The Modulator 2 of Timer 2 modulates the SSI internal
data out put to Bi-phase code
Figure 51. Bi-phase Modulation 1
TOG2
SC
8-bit SR-data
SO
0
0
1
1
0
1
0
Bit 7
T2O
0
1
Bit 0
0
1
1
0
1
0
1
Data: 00110101
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Combination Mode 3: Manchester Modulation 1
SSI mode 1:
8-bit shift register internal data output (SO) to Timer 2
modulator stage
Timer 2 mode 1, 2, 3 or 4:
8-bit compare counter with 4-bit programmable prescaler
Timer 2 output mode 5:
The Modulator 2 of Timer 2 modulates the SSI internal
data out put to Manchester code
Figure 52. Manchester Modulation 1
TOG2
SC
8-bit SR-data
0
SO
0
1
1
0
1
0
1
Bit 7
Bit 0
0
T2O
0
1
1
0
1
0
1
Bit 7
Bit 0
Data: 00110101
Combination Mode 4: Manchester Modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2
modulator stage
Timer 2 mode 3:
Timer 2 output mode 5:
8-bit compare counter and 4-bit prescaler
The Modulator 2 of Timer 2 modulates the SSI data
output to Manchester code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special mode to supply the prescaler with the shift-clock. The
control output signal (OMSK) of the SSI is used as stop signal for the modulator. Figure
53 is an example for a 12-bit Manchester telegram.
Figure 53. Manchester Modulation 2
SCLI
Buffer full
SIR
Bit 7 Bit 6
SO
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SC
MSM
Timer 2
Mode 3
SCL
Counter 2/1
0
0
0
0
0
Counter 2/1 = Compare Register 2/1 (= 4)
0
0
0
0
1
2
3
4
0
1
2
3
OMSK
T2O
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4708C–4BMCU–02/04
Combination Mode 5: Bi-phase Modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to Timer 2
modulator stage
Timer 2 mode 3:
Timer 2 output mode 4:
8-bit compare counter and 4-bit prescaler
The modulator 2 of Timer 2 modulates the SSI data
output to Bi-phase code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for Modulator 2. The SSI has a special mode to supply the prescaler via the shift-clock. The
control output signal (OMSK) of the SSI is used as a stop signal for the modulator. Figure 54 is an example for a 13-bit Bi-phase telegram.
Figure 54. Bi-phase Modulation
SCLI
Buffer full
SIR
Bit 7 Bit 6
SO
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SC
MSM
Timer 2
Mode 3
SCL
2/1
0
0
0
0
0
Counter 2/1 = Compare Register 2/1 (= 5)
0
0
0
0
1
2
3
4
5
0
1
2
OMSK
T2O
52
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ATA6020N
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All inputs and outputs are protected against high electrostatic voltages or electric fields. However, precautions to minimize the build-up of
electrostatic charges during handling are recommended. Reliability of operation is enhanced if unused inputs are connected to an
appropriate logic voltage level (e.g., VDD).
Voltages are given relative to VSS
Parameters
Symbol
Value
Unit
Supply voltage
VDD
-0.3 to +6.5
V
Input voltage (on any pin)
VIN
VSS -0.3 £ VIN £ VDD +0.3
V
Output short circuit duration
tshort
Indefinite
s
Operating temperature range
Tamb
-40 to +85
°C
Storage temperature range
Tstg
-40 to +130
°C
Thermal resistance (SSO20)
RthJA
140
K/W
Soldering temperature (t £ 10 s)
Tsld
260
°C
Operating Characteristics
VDD = 5 V, VSS = 0 V, Tamb = -40 to 85°C unless otherwise specified
Parameters
Test Conditions
Symbol
Active current
CPU active
Rext = 47 kW
fSYSCL = fRCext /2
fSYSCL = fRCext /4
IDD
Power down current
(CPU sleep, RC-oscillator active)
Rext = 47 kW
fSYSCL = fRCext /2
fSYSCL = fRCext /4
fSYSCL = fRCext /16
IPD
Sleep current
(CPU sleep, RC-oscillator inactive)
VDD = 6.5 V
Min.
Typ.
Max.
Unit
330
170
370
190
µA
µA
40
35
30
45
40
35
µA
µA
µA
0.5
0.8
µA
Typ.
Max.
Unit
370
190
410
210
µA
µA
45
40
35
50
45
40
µA
µA
µA
Power supply
ISleep
VDD = 5.5 V, VSS = 0 V, Tamb = -40 to +85°C unless otherwise specified.
Parameters
Test Conditions
Symbol
Active current
CPU active
Rext = 47 kW
fSYSCL = fRCext/2
fSYSCL = fRCext/4
IDD
Power down current
(CPU sleep, RC oscillator active)
Rext = 47 kW
fSYSCL = fRCext/2
fSYSCL = fRCext/4
fSYSCL = fRCext/16
IPD
Min.
53
4708C–4BMCU–02/04
VSS = 0 V, Tamb = 25°C unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
V
Power-on Reset Threshold Voltage
POR threshold voltage
BOT = 1
VPOR
2.5
3.0
3.5
POR threshold voltage
BOT = 0
VPOR
3.5
4.0
4.5
POR hysteresis
VPOR
50
5.0
V
mV
Voltage Monitor Threshold Voltage
VM high threshold voltage
VDD > VM, VMS = 1
VMThh
VM high threshold voltage
VDD < VM, VMS = 0
VMThh
VM low threshold voltage
VDD > VM, VMS = 1
VMThl
VM low threshold voltage
VDD < VM, VMS = 0
VMThl
VMI
VMI > VBG, VMS = 1
VVMI
VMI
VMI < VBG, VMS = 0
VVMI
4.5
5.5
5.0
4.0
3.5
V
V
4.5
4.0
V
V
External Input Voltage
1.25
1.1
1.4
1.25
V
V
All Bi-directional Ports
VSS = 0 V, Tamb = -40°C to +85°C unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
Input voltage LOW
VDD = 3.5 V to 6.5 V
VIL
Input voltage HIGH
VDD = 3.5V to 6.5 V
Input LOW current
(dynamic pull-up)
Max.
Unit
VSS
0.2 ´
VDD
V
VIH
0.8 ´
VDD
VDD
V
VDD = 3.5 V, VIL= VSS
VDD = 6.5 V
IIL
-15
-50
-30
-100
-50
-200
µA
µA
Input HIGH current
(dynamic pull-down)
VDD = 3.5 V, VIH = VDD
VDD = 6.5 V
IIH
15
50
30
100
50
200
µA
µA
Input LOW current
(static pull-up)
VDD = 3.5 V, VIL= VSS
VDD = 6.5 V
IIL
-120
-300
-250
-600
-500
-1200
µA
µA
Input LOW current
(static pull-down)
VDD = 3.5 V, VIH= VDD
VDD = 6.5 V
IIH
120
300
250
600
500
1200
µA
µA
Output LOW current
VOL = 0.2 VDD
VDD = 3.5 V,
VDD = 6.5 V
IOL
3
8
5
15
8
22
mA
mA
Output HIGH current
VOH = 0.8 VDD
VDD = 3.5 V,
VDD = 6.5 V
IOH
-3
-8
-5
-16
-8
-24
mA
mA
Note:
54
Typ.
The pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller:
ATA6020N
4708C–4BMCU–02/04
ATA6020N
AC Characteristics
Operation Cycle Time
VSS = 0 V
Parameters
Test Conditions
System clock cycle
VDD = 2.5 V to 6.5 V
Tamb = -40°C to +85°C
Symbol
Min.
tSYSCL
0.25
Typ.
Max.
Unit
100
µs
Max.
Unit
5
MHz
Supply voltage VDD = 2.5 V to 6.5 V, VSS = 0 V, Tamb = 25°C unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
Typ.
Timer 2 Input Timing Pin T2I
Timer 2 input clock
fT2I
Timer 2 input LOW time
Rise/fall time < 10 ns
tT2IL
100
ns
Timer 2 input HIGH time
Rise/fall time < 10 ns
tT2IH
100
ns
Interrupt request LOW time
Rise/fall time < 10 ns
tIRL
100
ns
Interrupt request HIGH time
Rise/fall time < 10 ns
tIRH
100
ns
EXSCL at OSC1 input
ECM = EN
Rise/fall time < 10 ns
fEXSCL
0.5
8
MHz
EXSCL at OSC1 input
ECM = DI
Rise/fall time < 10 ns
fEXSCL
0.02
8
MHz
Input HIGH time
Rise/fall time < 10 ns
tIH
0.1
Interrupt Request Input Timing
External System Clock
µs
Reset Timing
Power-on reset time
VDD >VPOR
tPOR
1.5
fRcOut1
4
5
ms
RC-oscillator 1
Frequency
Stability
VDD = 3.5V to 5.5 V
Tamb = -40°C to +85°C
Stabilization time
VDD = 3.5 V to 5.5 V
MHz
Df/f
±50
%
tS
1
ms
RC-oscillator 2 – External Resistor
Frequency
Rext = 47 kW
Stability
VDD = 3.5 V to 5.5 V
Tamb = -40°C to +85°C
Stabilization time
VDD = 3.5 V to 5.5 V
External resistor
fRcOut2
1.6
MHz
Df/f
10
%
tS
1
ms
100
kW
Rext
12
47
55
4708C–4BMCU–02/04
Figure 55. Active Supply Current versus Frequency
2.000
1.800
Tamb = 25°C
VDD = 6.5 V
IDDact (mA)
1.600
5V
1.400
1.200
1.000
3V
0.800
0.600
2V
0.400
0.200
0.000
0
500
1000
1500
2000
2500
3000
3500
4000
System Clock (kHz)
Figure 56. Power-down Supply Current versus Frequency
250
VDD = 6.5 V
Tamb = 25°C
IPD (µA)
200
5V
150
4V
100
3V
2V
50
0
200
400
600
800
1000
1200
1400
1600
1800
2000
System Clock (kHz)
Figure 57. Active Supply Current versus VDD
0.600
fSYSCLK = 1 MHz
Tamb = 85°C
IDDact (mA)
0.500
0.400
25°C
0.300
-40°C
0.200
0.100
0.000
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
56
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Figure 58. Power-down Supply Current versus VDD
90.0
80.0
fSYSCL = 500 kHz
70.0
Tamb = 25°C
IPD (µA)
60.0
50.0
40.0
30.0
20.0
10.0
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
5.5
6.0
6.5
VDD (V)
fRC_INT (MHz)
Figure 59. Internal RC Frequency versus VDD
5.60
5.40
5.20
5.00
4.80
4.60
4.40
4.20
4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
Tamb = -40°C
85°C
25°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VDD (V)
Figure 60. External RC Frequency versus VDD
1.730
fRC_EXT (MHz)
1.710
Rext = 43k
Tamb = -40°C
1.690
1.670
1.650
85°C
25°C
1.630
1.610
1.590
1.570
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
57
4708C–4BMCU–02/04
Figure 61. Maximum System Clock versus VDD
fSYSCLK (MHz)
12.00
10.00
8.00
6.00
4.00
2.00
0.00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (V)
fRC_INT (MHz)
Figure 62. Internal RC Frequency versus Tamb
5.60
5.40
5.20
5.00
4.80
4.60
4.40
4.20
4.00
3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
VDD = 6.5 V
2V
3V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
60
70
80
90
Tamb (°C)
Figure 63. External RC Frequency versus Tamb
1.730
Rext = 43k
fRC_EXT (MHz)
1.710
1.690
VDD = 6.5 V
1.670
1.650
3V
1.630
2V
1.610
1.590
1.570
-40
-30
-20
-10
0
10
20
30
40
50
90
Tamb (°C)
58
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Figure 64. External RC Frequency versus Rext
5500
VDD = 5 V
Tamb = 25°C
fRC_EXT (kHz)
4500
3500
2500
max
1500
typ.
min
500
10
20
30
40
50
60
70
80
90
100
110
Rext (kΩ)
Figure 65. Pull-up Resistor versus VDD
1000.0
VIL = VSS
RPU (kΩ)
Tamb = 85°C
25°C
100.0
-40°C
10.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
5.5
6.0
6.5
VDD (V)
Figure 66. Strong Pull-up Resistor versus VDD
100.0
RSPU (kΩ)
VIL = VSS
Tamb = 85°C
25°C
-40°C
10.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
6.5
VDD (V)
59
4708C–4BMCU–02/04
Figure 67. Output High Current versus VDD - Output High Voltage
0.0
VDD = 2.0 V
-5.0
-10.0
3.0 V
IOH (mA)
-15.0
4.0 V
-20.0
-25.0
5.0 V
Tamb = 25°C
-30.0
6.5 V
-35.0
-40.0
0.0
0.5
1.0
1.5 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD - VOH (V)
Figure 68. Pull-down Resistor versus VDD
1000
RPD (kΩ)
VIH = VDD
Tamb = 85°C
25°C
100
-40°C
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
6.0
6.5
VDD (V)
Figure 69. Strong Pull-down Resistor versus VDD
100.0
RSPD (kΩ)
VIH = VDD
Tamb = 85°C
25°C
-40°C
10.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
60
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Figure 70. Output Low Current versus Output Low Voltage
30
VDD = 6.5 V
Tamb = 25°C
IOL (mA)
25
5V
20
4V
15
10
3V
5
2V
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VOL (V)
Figure 71. Output High Current versus Tamb = 25°C, VDD = 6.5 V, VOH = 0.8 ´ VDD
0
-5
min.
IOH (mA)
-10
typ.
-15
max.
-20
-25
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Tamb (°C)
Figure 72. Output Low Current versus Tamb, VDD = 6.5 V, VOL = 0.2 ´ VDD
25
20
max.
IOL (mA)
15
typ.
10
min.
5
0
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Tamb (°C)
61
4708C–4BMCU–02/04
Emulation
The basic function of emulation is to test and evaluate the customer's program and
hardware in real time. This therefore enables the analysis of any timing, hardware or
software problem. For emulation purposes, all MARC4 controllers include a special
emulation mode. In this mode, the internal CPU core is inactive and the I/O buses are
available via Port 0 and Port 1 to allow an external access to the on-chip peripherals.
The MARC4 emulator uses this mode to control the peripherals of any MARC4 controller (target chip) and emulates the lost ports for the application.
The MARC4 emulator can stop and restart a program at specified points during execution, making it possible for the applications engineer to view the memory contents and
those of various registers during program execution. The designer also gains the ability
to analyze the executed instruction sequences and all the I/O activities.
Figure 73. MARC4 Emulation
Emulator target board
MARC4 emulator
MARC4
emulation-CPU
I/O bus
Trace
memory
Port 0
MARC4 target chip
CORE
I/O control
Port 1
Program
memory
CORE
(inactive)
Peripherals
Port 0
Control
logic
Port 1
Emulation control
SYSCL/
TCL,
TE, NRST
Application-specific hardware
Personal computer
62
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Option Settings for Ordering
Please select the option settings from the list below and insert ROM CRC.
Output
Input
Port 2
Output
Input
Port 5
BP20 [ ] CMOS
[ ] Pull-up
BP50 [ ] CMOS
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up static
[ ] Open drain [P]
[ ] Pull-up static
Pull-down static
BP21 [ ] CMOS
[ ] Pull-up
[ ] Pull-down static
BP51 [ ] CMOS
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up static
[ ] Open drain [P]
[ ] Pull-up static
[ ] Pull-down static
Port 4
[ ] Pull-down static
BP52 [ ] CMOS
BP40 [ ] CMOS
[ ] Pull-up
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up static
[ ] Open drain [P]
[ ] Pull-up static
[ ] Pull-down static
BP41 [ ] CMOS
[ ] Pull-down static
BP53 [ ] CMOS
[ ] Pull-up
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up static
[ ] Open drain [P]
[ ] Pull-up static
[ ] Pull-down static
BP42 [ ] CMOS
[ ] Pull-up
[ ] Open drain [N]
[ ] Pull-down
[ ] Open drain [P]
[ ] Pull-up static
[ ] Pull-down static
BP43 [ ] CMOS
[ ] Pull-down static
ECM (External Clock Monitor)
[ ] Pull-up
[ ] Enable
[ ] Disable
Watchdog
[ ] Softlock
[ ] Hardlock
[ ] Open drain [N]
[ ] Pull-down
Used oscillator
[ ] Open drain [P]
[ ] Pull-up static
[ ] Ext. RC
[ ] Pull-down static
[ ] Ext. clock
Please attach this page to the approval form.
Date: ____________
Signature: _________________________ Company: _________________________
63
4708C–4BMCU–02/04
Ordering Information
Extended Type Number(1)
Program Memory
Data-EEPROM
Package
ATA6020x-yyy-TKQ
2 kB ROM
No
SSO20
Taped and reeled
ATA6020x-yyy-TKS
2 kB ROM
No
SSO20
Tubes
Note:
Delivery
1. x = Hardware revision
yyy = Customer specific ROM-version
Package Information
5.7
5.3
Package SSO20
Dimensions in mm
6.75
6.50
4.5
4.3
1.30
0.15
0.05
0.25
0.65
5.85
20
0.15
6.6
6.3
11
technical drawings
according to DIN
specifications
1
64
10
ATA6020N
4708C–4BMCU–02/04
ATA6020N
Revision History
Please note that the referring page numbers in this section are referred to the specific
revision mentioned, not to this document.
Changes from Rev.
4708A - 06/03 to Rev.
4708B - 12/03
1. Put datasheet in a new template.
2. Figure 5 “RAM MAP” on page 4 changed.
3. Table 9 “Peripheral Addresses” on page 19 changed.
4. New heading rows at Table “Absolute Maximum Ratings” on page 53 added.
5. Section “Emulation” on page 56 added.
6. Table “Ordering Information” on page 58 added.
7. Table name on page 57 changed.
Changes from Rev.
4708B - 12/03 to Rev.
4708C - 02/04
1. Figure 4 “ROM MAP” on page 4 changed.
2. Figure 55 to Figure 72 on page 56 to page 61 added.
65
4708C–4BMCU–02/04
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4708C–4BMCU–02/04