Renesas M37540E2FP 8-bit cisc single-chip microcomputer 740 family / 740 sery Datasheet

REJ09B0018-0200Z
7540 Group
8
User's Manual
RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 740 SERIES
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 2.00
Revision date: Jun 21, 2004
www.renesas.com
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7540 Group User’s Manual
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Sep. 17, 2002
–
1.10 May 28, 2003 1-17
First edition issued
[Pull-up control register] PULL; Note added.
Fig.15; Note 2 eliminated.
1-19
Fig.17; (2) Ports P01,P02 revised.
1-34
Fig.29; Port P03 direction register block, Port P01 direction register block and
Port P02 direction register block revised.
1-45
(3) RC oscillation revised.
2-49
Fig.2.4.12; RTI → RTS
2-52
Fig.2.4.16; Prescaler X 1/4 → 1/2, CNTR0 pin output 4 MHz → 4 kHz
2-53
Fig.2.4.17; The second CPUM setting 00000X002 → 11000X002
Prescaler X 0316 → 0116, Note 2 revised.
Fig.2.4.26; The followings are revised.
2-61
The second setting of CNTR0 interrupt enable bit and Timer X interrupt enable bit.
The second setting of timer X mode register.
Fig.3.3.5; NOP added.
3-86
2.00 Jun. 21, 2004 All pages Words standardized: On-chip oscillator, A/D converter
1-9
Fig. 8: “Under development” eliminated.
1-10
Table 2: “Under development” eliminated.
1-11
CPU: Description revised.
1-17
[Pull-up control register] PULL: Note added
1-19
Fig.17 (2) Ports P01, P02 revised.
1-34
Fig. 29 P03/TXOUT, P01/TYOUT, P02/TZOUT revised.
1-42
Note on A/D converter added.
1-45
Fig. 49 revised.
1-51
Note on A/D converter added.
1-52
Notes on clock generating circuit: On-chip oscillator operation added.
Note on Power Source Voltage, and Electrical Characteristic Difference Among
Mask ROM and One Time PROM Version MCUs added.
2-5
Fig.2.1.6: Note 2 eliminated.
2-14
Fig.2.2.3: Note 2 eliminated.
2-35
2.2.7 Notes on timer A, (2): Register name revised.
2-36
Fig.2.3.2: Description revised.
2-66
Fig.2.5.7: Description revised.
2-134
2.8.4 Notes on A/D converter: (3) added.
2-145
2.9.6 Notes on oscillation stop detection circuit, (1): ➁ added.
3-82
3.3.10 Notes on A/D converter: (3) added.
3-83
3.3.11 Notes on oscillation stop detection circuit, (1): ➁ added.
3-91
3.3.19 Note on Power Source Voltage and 3.3.20 Electrical Characteristic Difference Among Mask ROM and One Time PROM Version MCUs added.
(1/2)
7540 Group User’s Manual
REVISION HISTORY
Rev.
Date
2.00
Jun. 21, 2004
Description
Summary
Page
3-100
3-106
3-108
3-120
3-140
Fig.3.5.5: Note 2 eliminated.
Fig.3.5.15: Description revised.
Fig.3.5.19: Description revised.
32P6U-A revised.
Fig.3.11.1: Memory address of 7531 Group revised.
(2/2)
BEFORE USING THIS MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. Chapter 3 also includes necessary information for
systems development. You must refer to that chapter.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
● CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
● CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, such
as the electrical characteristics, the list of registers.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bit attributes
Bits
(Note 1)
Contents immediately after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (CPUM) [Address : 3B 16]
B
Name
0
Processor mode bits
1
Function
At reset
R W
b1 b0
0 0 : Single-chip mode
01:
10:
Not available
11:
0 : 0 page
1 : 1 page
0
0
2
Stack page selection bit
3
0
✕
4
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
0
✕
5
Fix this bit to “0.”
1
6
Main clock (X IN-XOUT) stop bit
7
Internal system clock selection bit
: Bit in which nothing is arranged
0 : Operating
1 : Stopped
0 : XIN -XOUT selected
1 : XCIN -XCOUT selected
0
✽
✽
: Bit that is not used for control of the corresponding function
Note 1:. Contents immediately after reset release
0....... “0” at reset release
1....... “1” at reset release
?....... Undefined at reset release
✽.......Contents determined by option at reset release
Note 2: Bit attributes......... The attributes of control register bits are classified into 3 bytes : read-only, writeonly and read and write. In the figure, these attributes are represented as follows :
R....... Read
...... Read enabled
✕.......Read disabled
W......Write
..... Write enabled
✕...... Write disabled
✽.......“0” write
3. Supplementation
For details of software, refer to the “740 FAMILY SOFTWARE MANUAL.”
For development tools, refer to the “Renesas Technology tool Index for 740 Family.” Homepage (http:/
/www.renesas.com/eng/products/mpumcu/toolhp/mcu/740_e.htm).
Table of contents
7540 Group
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES ...................................................................................................................................... 1-2
APPLICATION ................................................................................................................................ 1-2
PIN CONFIGURATION .................................................................................................................. 1-3
FUNCTIONAL BLOCK .................................................................................................................. 1-5
PIN DESCRIPTION ........................................................................................................................ 1-8
GROUP EXPANSION .................................................................................................................... 1-9
FUNCTIONAL DESCRIPTION .................................................................................................... 1-11
Central Processing Unit (CPU) ............................................................................................ 1-11
Memory .................................................................................................................................... 1-15
I/O Ports .................................................................................................................................. 1-17
Interrupts ................................................................................................................................. 1-21
Key Input Interrupt (Key-On Wake-Up) ............................................................................... 1-23
Timers ...................................................................................................................................... 1-24
Serial I/O ................................................................................................................................. 1-35
A/D Converter ......................................................................................................................... 1-41
Watchdog Timer ..................................................................................................................... 1-42
Reset Circuit ........................................................................................................................... 1-43
Clock Generating Circuit ....................................................................................................... 1-45
NOTES ON PROGRAMMING ..................................................................................................... 1-49
Processor Status Register .................................................................................................... 1-49
Interrupts ................................................................................................................................. 1-49
Decimal Calculations .............................................................................................................. 1-49
Ports ......................................................................................................................................... 1-49
A/D Conversion ....................................................................................................................... 1-49
Instruction Execution Timing ................................................................................................. 1-49
CPU Mode Register ............................................................................................................... 1-49
State Transition ...................................................................................................................... 1-49
NOTES ON HARDWARE ............................................................................................................ 1-49
Handling of Power Source Pin ............................................................................................. 1-49
One Time PROM Version ..................................................................................................... 1-49
NOTES ON PERIPHERAL FUNCTIONS .................................................................................. 1-50
■ Interrupt ............................................................................................................................... 1-50
■ Timers .................................................................................................................................. 1-50
■ Timer A ............................................................................................................................... 1-50
■ Timer X ............................................................................................................................... 1-50
■ Timer Y: Programmable Generation Waveform Mode .................................................. 1-50
■ Timer Z: Programmable Waveform Generation Mode .................................................. 1-50
■ Timer Z: Programmable One-shot Generation Mode ................................................... 1-51
■ Timer Z: Programmable Wait One-shot Generation Mode .......................................... 1-51
■ Serial I/O ............................................................................................................................. 1-51
■ A/D Converter ..................................................................................................................... 1-51
■ Notes on Clock Generating Circuit ................................................................................. 1-52
■ Notes on Power Source Volage ...................................................................................... 1-52
■ Electric Characteristic Differences Among Mask ROM and One Time PROM Version MCUs .... 1-52
DATA REQUIRED FOR MASK ORDERS ................................................................................ 1-53
DATA REQUIRED FOR ROM PROGRAMMING ORDERS .................................................... 1-53
ROM PROGRAMMING METHOD .............................................................................................. 1-53
FUNCTIONAL DESCRIPTION SUPPLEMENT ......................................................................... 1-54
i
Table of contents
7540 Group
CHAPTER 2 APPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Application example of key-on wake up (1) ............................................................... 2-7
2.1.4 Application example of key-on wake up (2) ............................................................... 2-9
2.1.5 Handling of unused pins ............................................................................................. 2-10
2.1.6 Notes on input and output ports ................................................................................ 2-11
2.1.7 Termination of unused pins ........................................................................................ 2-12
2.2 Timer A .................................................................................................................................. 2-13
2.2.1 Memory map ................................................................................................................. 2-13
2.2.2 Relevant registers ........................................................................................................ 2-14
2.2.3 Timer mode ................................................................................................................... 2-19
2.2.4 Period measurement mode ......................................................................................... 2-22
2.2.5 Event counter mode ..................................................................................................... 2-26
2.2.6 Pulse width HL continuously measurement mode ................................................... 2-30
2.2.7 Notes on timer A .......................................................................................................... 2-35
2.3 Timer 1 ................................................................................................................................... 2-36
2.3.1 Memory map ................................................................................................................. 2-36
2.3.2 Relevant registers ........................................................................................................ 2-36
2.3.3 Timer 1 operation description ..................................................................................... 2-39
2.3.4 Notes on timer 1 .......................................................................................................... 2-39
2.4 Timer X .................................................................................................................................. 2-40
2.4.1 Memory map ................................................................................................................. 2-40
2.4.2 Relevant registers ........................................................................................................ 2-41
2.4.3 Timer mode ................................................................................................................... 2-46
2.4.4 Pulse output mode ....................................................................................................... 2-50
2.4.5 Event counter mode ..................................................................................................... 2-54
2.4.6 Pulse width measurement mode ................................................................................ 2-58
2.4.7 Notes on timer X .......................................................................................................... 2-62
2.5 Timer Y and timer Z ........................................................................................................... 2-63
2.5.1 Memory map ................................................................................................................. 2-63
2.5.2 Relevant registers ........................................................................................................ 2-64
2.5.3 Timer mode (timer Y and timer Z) ............................................................................ 2-73
2.5.4 Programmable waveform generation mode (timer Y and timer Z) ....................... 2-77
2.5.5 Programmable one-shot generation mode (timer Z) ............................................... 2-84
2.5.6 Programmable wait one-shot generation mode (timer Z) ....................................... 2-91
2.5.7 Notes on timer Y and timer Z .................................................................................... 2-99
2.6 Serial I/O1 ............................................................................................................................ 2-101
2.6.1 Memory map ............................................................................................................... 2-101
2.6.2 Relevant registers ...................................................................................................... 2-101
2.6.3 Serial I/O1 transfer data format ............................................................................... 2-105
2.6.4 Application example of clock synchronous serial I/O1 ......................................... 2-106
2.6.5 Application example of clock asynchronous serial I/O1 ....................................... 2-112
2.6.6 Notes on Serial I/O1 .................................................................................................. 2-118
2.7 Serial I/O2 ............................................................................................................................ 2-120
2.7.1 Memory map ............................................................................................................... 2-120
2.7.2 Relevant registers ...................................................................................................... 2-120
2.7.3 Application example of serial I/O2 ........................................................................... 2-123
2.7.4 Notes on serial I/O2 .................................................................................................. 2-128
2.8 A/D converter ..................................................................................................................... 2-129
2.8.1 Memory map ............................................................................................................... 2-129
2.8.2 Relevant registers ...................................................................................................... 2-129
2.8.3 A/D converter application examples ........................................................................ 2-132
2.8.4 Notes on A/D converter ............................................................................................ 2-134
ii
Table of contents
7540 Group
2.9 Oscillation control ............................................................................................................. 2-135
2.9.1 Memory map ............................................................................................................... 2-135
2.9.2 Relevant registers ...................................................................................................... 2-135
2.9.3 Application example of on-chip oscillator ............................................................... 2-137
2.9.4 Oscillation stop detection circuit .............................................................................. 2-139
2.9.5 State transition ........................................................................................................... 2-142
2.9.6 Notes on oscillation stop detection circuit .............................................................. 2-145
CHAPTER 3 APPENDIX
3.1 Electrical characteristics ..................................................................................................... 3-2
3.1.1 7540 Group (General purpose) .................................................................................... 3-2
3.1.2 7540Group (Extended operating temperature version) ........................................... 3-13
3.1.3 7540Group (Extended operating temperature 125 °C version) ............................. 3-22
3.2 Typical characteristics ....................................................................................................... 3-31
3.2.1 Mask ROM version ...................................................................................................... 3-31
3.2.2 One Time PROM version ............................................................................................ 3-52
3.3 Notes on use ........................................................................................................................ 3-73
3.3.1 Notes on input and output ports ................................................................................ 3-73
3.3.2 Termination of unused pins ........................................................................................ 3-74
3.3.3 Notes on Timer ............................................................................................................. 3-75
3.3.4 Notes on Timer A ........................................................................................................ 3-75
3.3.5 Notes on timer 1 .......................................................................................................... 3-75
3.3.6 Notes on Timer X ........................................................................................................ 3-76
3.3.7 Notes on timer Y and timer Z .................................................................................... 3-77
3.3.8 Notes on Serial I/O1 .................................................................................................... 3-79
3.3.9 Notes on serial I/O2 .................................................................................................... 3-81
3.3.10 Notes on A/D converter ............................................................................................ 3-82
3.3.11 Notes on oscillation stop detection circuit .............................................................. 3-83
3.3.12 Notes on CPU mode register ................................................................................... 3-85
3.3.13 Notes on interrupts .................................................................................................... 3-86
3.3.14 Notes on RESET pin ................................................................................................. 3-87
3.3.15 Notes on programming .............................................................................................. 3-88
3.3.16 Programming and test of built-in PROM version ................................................... 3-90
3.3.17 Handling of Power Source Pin ................................................................................. 3-90
3.3.18 Notes on built-in PROM version .............................................................................. 3-91
3.3.19 Notes on Power Source Voltage ............................................................................. 3-91
3.3.20 Electric Characteristic Differences Among Mask ROM and One Time PROM Version MCUs .... 3-91
3.4 Countermeasures against noise ...................................................................................... 3-92
3.4.1 Shortest wiring length .................................................................................................. 3-92
3.4.2 Connection of bypass capacitor across V SS line and V CC line ............................... 3-94
3.4.3 Wiring to analog input pins ........................................................................................ 3-95
3.4.4 Oscillator concerns ....................................................................................................... 3-95
3.4.5 Setup for I/O ports ....................................................................................................... 3-96
3.4.6 Providing of watchdog timer function by software .................................................. 3-97
3.5 List of registers ................................................................................................................... 3-98
3.6 Package outline ................................................................................................................. 3-120
3.7 Machine instructions ........................................................................................................ 3-122
3.8 List of instruction code ................................................................................................... 3-133
3.9 SFR memory map .............................................................................................................. 3-134
3.10 Pin configurations ........................................................................................................... 3-135
3.11 Differences between 7540 Group and 7531 Group ................................................. 3-139
iii
List of figures
7540 Group
List of figures
CHAPTER 1 HARDWARE
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1 Pin configuration (32P6U-A type) ..................................................................................... 1-3
2 Pin configuration (36P2R-A type) ..................................................................................... 1-3
3 Pin configuration (32P4B-A type) ..................................................................................... 1-4
4 Pin configuration (42S1M type) ........................................................................................ 1-4
5 Functional block diagram (32P6U package) ................................................................... 1-5
6 Functional block diagram (36P2R package) ................................................................... 1-6
7 Functional block diagram (32P4B package) ................................................................... 1-7
8 Memory expansion plan ..................................................................................................... 1-9
9 740 Family CPU register structure ................................................................................. 1-11
10 Register push and pop at interrupt generation and subroutine call ....................... 1-12
11 Structure of CPU mode register ................................................................................... 1-14
12 Switching method of CPU mode register .................................................................... 1-14
13 Memory map diagram .................................................................................................... 1-15
14 Memory map of special function register (SFR) ........................................................ 1-16
15 Structure of pull-up control register ............................................................................. 1-17
16 Structure of port P1P3 control register ....................................................................... 1-17
17 Block diagram of ports (1) ............................................................................................ 1-19
18 Block diagram of ports (2) ............................................................................................ 1-20
19 Interrupt control ............................................................................................................... 1-22
20 Structure of Interrupt-related registers ........................................................................ 1-22
21 Connection example when using key input interrupt and port P0 block diagram 1-23
22 Structure of timer A mode register .............................................................................. 1-25
23 Structure of timer X mode register .............................................................................. 1-26
24 Timer count source set register ................................................................................... 1-26
25 Structure of timer Y, Z mode register ......................................................................... 1-32
26 Structure of timer Y, Z waveform output control register ......................................... 1-32
27 Structure of one-shot start register .............................................................................. 1-32
28 Block diagram of timer 1 and timer A ......................................................................... 1-33
29 Block diagram of timer X, timer Y and timer Z ......................................................... 1-34
30 Block diagram of clock synchronous serial I/O1 ........................................................ 1-35
31 Operation of clock synchronous serial I/O1 function ................................................ 1-35
32 Block diagram of UART serial I/O1 ............................................................................. 1-36
33 Operation of UART serial I/O1 function ...................................................................... 1-36
34 Structure of serial I/O1-related registers ..................................................................... 1-38
35 Structure of serial I/O2 control registers ..................................................................... 1-39
36 Block diagram of serial I/O2 ......................................................................................... 1-39
37 Serial I/O2 timing (LSB first) ........................................................................................ 1-40
38 Structure of A/D control register .................................................................................. 1-41
39 Structure of A/D conversion register ........................................................................... 1-41
40 Block diagram of A/D converter ................................................................................... 1-41
41 Block diagram of watchdog timer ................................................................................. 1-42
42 Structure of watchdog timer control register .............................................................. 1-42
43 Example of reset circuit ................................................................................................. 1-43
44 Timing diagram at reset ................................................................................................ 1-43
45 Internal status of microcomputer at reset ................................................................... 1-44
46 External circuit of ceramic resonator ........................................................................... 1-45
47 External circuit of RC oscillation .................................................................................. 1-45
48 External clock input circuit ............................................................................................ 1-45
iv
List of figures
7540 Group
Fig.
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49
50
51
52
53
54
55
56
57
58
Processing of X IN and X OUT pins at on-chip oscillator operation .............................. 1-45
Structure of MISRG ........................................................................................................ 1-46
Block diagram of internal clock generating circuit (for ceramic resonator) ........... 1-47
Block diagram of internal clock generating circuit (for RC oscillation) ................... 1-47
State transition ................................................................................................................ 1-48
Programming and testing of One Time PROM version ............................................ 1-53
Timing chart after an interrupt occurs ......................................................................... 1-55
Time up to execution of the interrupt processing routine ........................................ 1-55
A/D conversion equivalent circuit ................................................................................. 1-57
A/D conversion timing chart .......................................................................................... 1-57
CHAPTER 2 APPLICATION
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2.1.1 Memory map of registers relevant to I/O port ......................................................... 2-2
2.1.2 Structure of Port Pi (i = 0, 2, 3) ................................................................................ 2-3
2.1.3 Structure of Port P1 ..................................................................................................... 2-3
2.1.4 Structure of Port Pi direction register (i = 0, 2, 3) ................................................. 2-4
2.1.5 Structure of Port P1 direction register ...................................................................... 2-4
2.1.6 Structure of Pull-up control register .......................................................................... 2-5
2.1.7 Structure of Port P1P3 control register .................................................................... 2-5
2.1.8 Structure of Interrupt edge selection register .......................................................... 2-6
2.1.9 Structure of Interrupt request register 1 ................................................................... 2-6
2.1.10 Structure of Interrupt control register 1 .................................................................. 2-7
2.1.11 Example of application circuit .................................................................................. 2-7
2.1.12 Example of control procedure (1) ............................................................................ 2-8
2.1.13 Example of control procedure (2) ............................................................................ 2-9
2.2.1 Memory map of registers relevant to timer A ........................................................ 2-13
2.2.2 Structure of Port P0 direction register .................................................................... 2-14
2.2.3 Structure of Pull-up control register ........................................................................ 2-14
2.2.4 Structure of Timer A mode register ......................................................................... 2-15
2.2.5 Structure of Timer A register .................................................................................... 2-16
2.2.6 Structure of Interrupt edge selection register ........................................................ 2-16
2.2.7 Structure of Interrupt request register 1 ................................................................. 2-17
2.2.8 Structure of Interrupt request register 2 ................................................................. 2-17
2.2.9 Structure of Interrupt control register 1 .................................................................. 2-18
2.2.10 Structure of Interrupt control register 2 ................................................................ 2-18
2.2.11 Setting method for timer mode .............................................................................. 2-20
2.2.12 Example of control procedure ................................................................................ 2-21
2.2.13 Setting method for period measurement mode (1) ............................................. 2-22
2.2.14 Setting method for period measurement mode (2) ............................................. 2-23
2.2.15 Example of peripheral circuit .................................................................................. 2-24
2.2.16 Example of control procedure ................................................................................ 2-25
2.2.17 Setting method for event counter mode (1) ......................................................... 2-26
2.2.18 Setting method for event counter mode (2) ......................................................... 2-27
2.2.19 Example of measurement method of frequency .................................................. 2-28
2.2.20 Example of control procedure ................................................................................ 2-29
2.2.21 Setting method for pulse width HL continuously measurement mode (1) ....... 2-30
2.2.22 Setting method for pulse width HL continuously measurement mode (2) ....... 2-31
2.2.23 Example of peripheral circuit .................................................................................. 2-32
2.2.24 Operation timing when ringing pulse is input ...................................................... 2-32
2.2.25 Example of control procedure (1) .......................................................................... 2-33
2.2.26 Example of control procedure (2) .......................................................................... 2-34
v
List of figures
7540 Group
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2.3.1 Memory map of registers relevant to timer 1 ........................................................ 2-36
2.3.2 Structure of Prescaler 1 ............................................................................................ 2-36
2.3.3 Structure of Timer 1 .................................................................................................. 2-37
2.3.4 Structure of MISRG ................................................................................................... 2-37
2.3.5 Structure of Interrupt request register 2 ................................................................. 2-38
2.3.6 Structure of Interrupt control register 2 .................................................................. 2-38
2.4.1 Memory map of registers relevant to timer X ........................................................ 2-40
2.4.2 Structure of Port P0 direction register .................................................................... 2-41
2.4.3 Structure of Port P1 direction register .................................................................... 2-41
2.4.4 Structure of Timer X mode register ......................................................................... 2-42
2.4.5 Structure of Prescaler X ............................................................................................ 2-43
2.4.6 Structure of Timer X .................................................................................................. 2-43
2.4.7 Structure of Timer count source set register ......................................................... 2-44
2.4.8 Structure of Interrupt request register 1 ................................................................. 2-45
2.4.9 Structure of Interrupt control register 1 .................................................................. 2-45
2.4.10 Setting method for timer mode .............................................................................. 2-47
2.4.11 Connection of timer and setting of division ratio ................................................ 2-48
2.4.12 Example of control procedure ................................................................................ 2-49
2.4.13 Setting method for pulse output mode (1) ........................................................... 2-50
2.4.14 Setting method for pulse output mode (2) ........................................................... 2-51
2.4.15 Example of peripheral circuit .................................................................................. 2-52
2.4.16 Connection of timer and setting of division ratio ................................................ 2-52
2.4.17 Example of control procedure ................................................................................ 2-53
2.4.18 Setting method for event counter mode (1) ......................................................... 2-54
2.4.19 Setting method for event counter mode (2) ......................................................... 2-55
2.4.20 Example of peripheral circuit .................................................................................. 2-56
2.4.21 Method of measuring water flow rate ................................................................... 2-56
2.4.22 Example of control procedure ................................................................................ 2-57
2.4.23 Setting method for pulse width measurement mode (1) .................................... 2-58
2.4.24 Setting method for pulse width measurement mode (2) .................................... 2-59
2.4.25 Connection of timer and setting of division ratio ................................................ 2-60
2.4.26 Example of control procedure ................................................................................ 2-61
2.5.1 Memory map of registers relevant to timer Y and timer Z .................................. 2-63
2.5.2 Structure of Port P0 direction register .................................................................... 2-64
2.5.3 Structure of Port P3 direction register .................................................................... 2-64
2.5.4 Structure of Pull-up control register ........................................................................ 2-65
2.5.5 Structure of Port P1P3 control register .................................................................. 2-65
2.5.6 Structure of Timer Y, Z mode register .................................................................... 2-66
2.5.7 Structure of Prescaler Y, Prescaler Z ..................................................................... 2-66
2.5.8 Structure of Timer Y secondary, Timer Z secondary ........................................... 2-67
2.5.9 Structure of Timer Y primary, Timer Z primary ..................................................... 2-67
2.5.10 Structure of Timer Y, Z waveform output control register ................................. 2-68
2.5.11 Structure of One-shot start register ....................................................................... 2-68
2.5.12 Structure of Timer count source set register ....................................................... 2-69
2.5.13 Structure of Interrupt edge selection register ...................................................... 2-69
2.5.14 Structure of CPU mode register ............................................................................ 2-70
2.5.15 Structure of Interrupt request register 1 ............................................................... 2-71
2.5.16 Structure of Interrupt request register 2 ............................................................... 2-71
2.5.17 Structure of Interrupt control register 1 ................................................................ 2-72
2.5.18 Structure of Interrupt control register 2 ................................................................ 2-72
2.5.19 Setting method for timer mode .............................................................................. 2-74
2.5.20 Example of peripheral circuit .................................................................................. 2-75
vi
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2.5.21 Method of measuring water flow rate ................................................................... 2-75
2.5.22 Example of control procedure ................................................................................ 2-76
2.5.23 Timing diagram of programmable waveform generation mode ......................... 2-79
2.5.24 Setting method for programmable waveform generation mode (1) .................. 2-80
2.5.25 Setting method for programmable waveform generation mode (2) .................. 2-81
2.5.26 Example of waveform output .................................................................................. 2-82
2.5.27 Example of control procedure ................................................................................ 2-83
2.5.28 Timing diagram of programmable one-shot generation mode ........................... 2-85
2.5.29 Setting method for programmable one-shot generation mode (1) .................... 2-86
2.5.30 Setting method for programmable one-shot generation mode (2) .................... 2-87
2.5.31 Setting method for programmable one-shot generation mode (3) .................... 2-88
2.5.32 Example of peripheral circuit .................................................................................. 2-89
2.5.33 Example of operation timing ................................................................................... 2-89
2.5.34 Example of control procedure ................................................................................ 2-90
2.5.35 Timing diagram of programmable wait one-shot generation mode ................... 2-93
2.5.36 Setting method for programmable wait one-shot generation mode (1) ............ 2-94
2.5.37 Setting method for programmable wait one-shot generation mode (2) ............ 2-95
2.5.38 Setting method for programmable wait one-shot generation mode (3) ............ 2-96
2.5.39 Example of waveform generation and peripheral circuit .................................... 2-97
2.5.40 Example of control procedure ................................................................................ 2-98
2.6.1 Memory map of registers relevant to serial I/O ................................................... 2-101
2.6.2 Structure of Transmit/Receive buffer register ...................................................... 2-101
2.6.3 Structure of Serial I/O1 status register ................................................................. 2-102
2.6.4 Structure of Serial I/O1 control register ................................................................ 2-102
2.6.5 Structure of UART control register ........................................................................ 2-103
2.6.6 Structure of Baud rate generator ........................................................................... 2-103
2.6.7 Structure of Interrupt request register 1 ............................................................... 2-104
2.6.8 Structure of Interrupt control register 1 ................................................................ 2-104
2.6.9 Serial I/O1 transfer data format ............................................................................. 2-105
2.6.10 Setting method for clock synchronous serial I/O1 (1) ...................................... 2-107
2.6.11 Setting method for clock synchronous serial I/O1 (2) ...................................... 2-108
2.6.12 Connection diagram ............................................................................................... 2-109
2.6.13 Timing chart ............................................................................................................ 2-109
2.6.14 Control procedure of transmitter .......................................................................... 2-110
2.6.15 Control procedure of receiver ............................................................................... 2-111
2.6.16 Setting method for UART of serial I/O1 (1) ....................................................... 2-113
2.6.17 Setting method for UART of serial I/O1 (2) ....................................................... 2-114
2.6.18 Connection diagram ............................................................................................... 2-115
2.6.19 Timing chart ............................................................................................................ 2-115
2.6.20 Control procedure of transmitter .......................................................................... 2-116
2.6.21 Control procedure of receiver ............................................................................... 2-117
2.6.22 Sequence of setting serial I/O1 control register again ..................................... 2-119
2.7.1 Memory map of registers relevant to serial I/O2 ................................................ 2-120
2.7.2 Structure of Port P1 direction register .................................................................. 2-120
2.7.3 Structure of Serial I/O2 control register ................................................................ 2-121
2.7.4 Structure of Serial I/O2 register ............................................................................. 2-121
2.7.5 Structure of Interrupt request register 2 ............................................................... 2-122
2.7.6 Structure of Interrupt control register 2 ................................................................ 2-122
2.7.7 Setting method for serial I/O2 ................................................................................ 2-123
2.7.8 Setting method for serial I/O2 ................................................................................ 2-124
2.7.9 Connection diagram ................................................................................................. 2-125
2.7.10 Timing chart ............................................................................................................ 2-125
vii
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2.7.11 Control procedure of transmission side .............................................................. 2-126
2.7.12 Control procedure of reception side .................................................................... 2-127
2.8.1 Memory map of registers relevant to A/D converter ........................................... 2-129
2.8.2 Structure of A/D control register ............................................................................ 2-129
2.8.3 Structure of A/D conversion register (low-order) ................................................. 2-130
2.8.4 Structure of A/D conversion register (high-order) ............................................... 2-130
2.8.5 Structure of Interrupt request register 2 ............................................................... 2-131
2.8.6 Structure of Interrupt control register 2 ................................................................ 2-131
2.8.7 Relevant registers setting ....................................................................................... 2-132
2.8.8 Connection diagram ................................................................................................. 2-133
2.8.9 Control procedure ..................................................................................................... 2-133
2.8.10 Connection diagram ............................................................................................... 2-134
2.9.1 Memory map of registers relevant to oscillation control .................................... 2-135
2.9.2 Structure of MISRG ................................................................................................. 2-135
2.9.3 Structure of Watchdog timer control register ....................................................... 2-136
2.9.4 Structure of CPU mode register ............................................................................ 2-136
2.9.5 Setting method when the on-chip oscillator is used as the operation clock ... 2-137
2.9.6 Control procedure ..................................................................................................... 2-138
2.9.7 Initial setting method for the oscillation stop detection circuit .......................... 2-140
2.9.8 Setting method for the oscillation stop detection circuit in main processing .. 2-141
2.9.9 State transition .......................................................................................................... 2-142
2.9.10 Example of mode transition .................................................................................. 2-143
2.9.11 Control procedure ................................................................................................... 2-144
CHAPTER 3 APPENDIX
Fig.
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3.1.1 Switching characteristics measurement circuit diagram (General purpose) ....... 3-11
3.1.2 Timing chart (General purpose) ............................................................................... 3-12
3.1.3 Switching characteristics measurement circuit diagram (Extended operating temperature)3-20
3.1.4 Timing chart (Extended operating temperature version) ...................................... 3-21
3.1.5 Switching characteristics measurement circuit diagram (Extended operating temperature
125 °C version) ..................................................................................................................... 3-29
Fig. 3.1.6 Timing chart (Extended operating temperature 125 °C version) ......................... 3-30
Fig. 3.2.1 V CC-ICC characteristics (in double-speed mode: Mask ROM version) .................. 3-31
Fig. 3.2.2 V CC-ICC characteristics (in high-speed mode: Mask ROM version) ...................... 3-31
Fig. 3.2.3 V CC-ICC characteristics (in middle-speed mode: Mask ROM version) .................. 3-31
Fig. 3.2.4 V CC-ICC characteristics (at WIT instruction execution: Mask ROM version) ........ 3-32
Fig. 3.2.5 V CC-ICC characteristics (at STP instruction execution: Mask ROM version) ....... 3-32
Fig. 3.2.6 V CC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in
high-speed mode: Mask ROM version) .............................................................................. 3-33
Fig. 3.2.7 V CC -ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in
double-speed mode: Mask ROM version) ......................................................................... 3-33
Fig. 3.2.8VCC-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation
stop: Mask ROM version) .................................................................................................... 3-34
Fig. 3.2.9 VCC-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction
execution, Ceramic oscillation stop: Mask ROM version) ............................................... 3-34
Fig. 3.2.10 f(X IN)-I CC characteristics (in double-speed mode: Mask ROM version) ............. 3-35
Fig. 3.2.11 f(X IN)-I CC characteristics (in high-speed mode: Mask ROM version) ................. 3-35
Fig. 3.2.12 f(X IN)-I CC characteristics (in middle-speed mode: Mask ROM version) ............. 3-35
Fig. 3.2.13 f(X IN)-I CC characteristics (at WIT instruction execution: Mask ROM version) ... 3-36
Fig. 3.2.14 Ta-I CC characteristics (When system is operating by on-chip oscillator, Ceramic
oscillation stop: Mask ROM version) .................................................................................. 3-36
Fig. 3.2.15 Ta-I CC characteristics (When system is operating by on-chip oscillator, at WIT
instruction execution, Ceramic oscillation stop: Mask ROM version) ............................ 3-36
viii
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3.2.16 V CC-V IHL characteristics (I/O port (CMOS): Mask ROM version) ........................ 3-37
3.2.17 V CC-V IHL characteristics (I/O port (TTL): Mask ROM version) ............................ 3-37
3.2.18 V CC-V IHL characteristics (RESET pin: Mask ROM version) ................................. 3-38
3.2.19 V CC-V IHL characteristics (X IN pin: Mask ROM version) ......................................... 3-38
3.2.20 V CC-V IL characteristics (CNV SS pin: Mask ROM version) ..................................... 3-38
3.2.21 V CC-HYS characteristics (RESET pin: Mask ROM version) ................................ 3-39
3.2.22 V CC-HYS characteristics (SIO pin: Mask ROM version) ...................................... 3-39
3.2.23 V CC-HYS characteristics (INT pin: Mask ROM version) ...................................... 3-39
3.2.24 VOH-IOH characteristics of P-channel (VCC = 3.0 V, normal port: Mask ROM version) .. 3-40
3.2.25 VOH-IOH characteristics of P-channel (VCC = 5.0 V, normal port: Mask ROM version) .. 3-40
3.2.26 VOL-IOL characteristics of N-channel (VCC = 3.0 V, normal port: Mask ROM version) ... 3-41
3.2.27 VOL-IOL characteristics of N-channel (VCC = 5.0 V, normal port: Mask ROM version) ... 3-41
3.2.28 VOL-IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: Mask ROM version)
................................................................................................................................................. 3-42
Fig. 3.2.29 VOL-IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: Mask ROM version)
................................................................................................................................................. 3-42
Fig. 3.2.30 V CC-IIL characteristics (Port “L” input current when connecting pull-up transistor:
Mask ROM version) .............................................................................................................. 3-43
Fig. 3.2.31 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8
MHz in high-speed mode: Mask ROM version) ................................................................ 3-44
Fig. 3.2.32 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6
MHz in double-speed mode: Mask ROM version) ............................................................ 3-44
Fig. 3.2.33 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4
MHz in double-speed mode: Mask ROM version) ............................................................ 3-44
Fig. 3.2.34 V CC-ROSC characteristics (on-chip oscillator frequency: Mask ROM version) ... 3-45
Fig. 3.2.35 Ta-R OSC characteristics (on-chip oscillator frequency: Mask ROM version) ..... 3-45
Fig. 3.2.36 R-f(X IN) characteristics (RC oscillation frequency: Mask ROM version) ........... 3-46
Fig. 3.2.37 C-f(X IN) characteristics (RC oscillation frequency: Mask ROM version) ........... 3-46
Fig. 3.2.38 V CC-f(X IN) characteristics (RC oscillation frequency: Mask ROM version) ........ 3-47
Fig. 3.2.39 Ta-f(X IN) characteristics (RC oscillation frequency: Mask ROM version) ......... 3-47
Fig. 3.2.40 Definition of A/D conversion a CCuracy ................................................................... 3-48
Fig. 3.2.41 A/D conversion accuracy typical characteristic example-1 (Mask ROM version) .. 3-49
Fig. 3.2.42 A/D conversion accuracy typical characteristic example-2 (Mask ROM version) .. 3-50
Fig. 3.2.43 A/D conversion aCCuracy typical characteristic example-3 (Mask ROM version) .. 3-51
Fig. 3.2.44 V CC-ICC characteristics (in double-speed mode: One Time PROM version) ..... 3-52
Fig. 3.2.45 V CC-I CC characteristics (in high-speed mode: One Time PROM version) ......... 3-52
Fig. 3.2.46 V CC-ICC characteristics (in middle-speed mode: One Time PROM version) ..... 3-52
Fig. 3.2.47 VCC-ICC characteristics (at WIT instruction execution: One Time PROM version) .. 3-53
Fig. 3.2.48 VCC-ICC characteristics (at STP instruction execution: One Time PROM version) .. 3-53
Fig. 3.2.49 VCC-I CC characteristics (addition when operating A/D conversion, f(X IN) = 8 MHz in
high-speed mode: One Time PROM version) ................................................................... 3-54
Fig. 3.2.50 VCC-I CC characteristics (addition when operating A/D conversion, f(X IN) = 6 MHz in
double-speed mode: One Time PROM version) ............................................................... 3-54
Fig. 3.2.51 V CC-I CC characteristics (When system is operating by on-chip oscillator, Ceramic
oscillation stop: One Time PROM version) ....................................................................... 3-55
Fig. 3.2.52 V CC-I CC characteristics (When system is operating by on-chip oscillator, at WIT
instruction execution, Ceramic oscillation stop: One Time PROM version) ................. 3-55
Fig. 3.2.53 f(X IN)-I CC characteristics (in double-speed mode: One Time PROM version) .. 3-56
Fig. 3.2.54 f(X IN)-I CC characteristics (in high-speed mode: One Time PROM version) ...... 3-56
Fig. 3.2.55 f(X IN)-ICC characteristics (in middle-speed mode: One Time PROM version) .. 3-56
Fig. 3.2.56 f(XIN)-ICC characteristics (at WIT instruction execution: One Time PROM version) ... 3-57
Fig. 3.2.57 Ta-I CC characteristics (When system is operating by on-chip oscillator, Ceramic
oscillation stop: One Time PROM version) ....................................................................... 3-57
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Fig. 3.2.58 Ta-I CC characteristics (When system is operating by on-chip oscillator, at WIT
instruction execution, Ceramic oscillation stop: One Time PROM version) ................. 3-57
Fig. 3.2.59 V CC-V IHL characteristics (I/O port (CMOS): One Time PROM version) ............. 3-58
Fig. 3.2.60 V CC-V IHL characteristics (I/O port (TTL): One Time PROM version) .................. 3-58
Fig. 3.2.61 V CC-V IHL characteristics (RESET pin: One Time PROM version) ....................... 3-59
Fig. 3.2.62 VCC -VIHL characteristics (XIN pin: One Time PROM version) ............................... 3-59
Fig. 3.2.63 V CC-V IL characteristics (CNVSS pin: One Time PROM version) .......................... 3-59
Fig. 3.2.64 V CC-HYS characteristics (RESET pin: One Time PROM version) ..................... 3-60
Fig. 3.2.65 V CC-HYS characteristics (SIO pin: One Time PROM version) ........................... 3-60
Fig. 3.2.66 V CC-HYS characteristics (INT pin: One Time PROM version) ........................... 3-60
Fig. 3.2.67 V OH-I OH characteristics of P-channel (VCC = 3.0 V, normal port: One Time PROM
version) ................................................................................................................................... 3-61
Fig. 3.2.68 V OH-I OH characteristics of P-channel (VCC = 5.0 V, normal port: One Time PROM
version) ................................................................................................................................... 3-61
Fig. 3.2.69 V OL-I OL characteristics of N-channel (V CC = 3.0 V, normal port: One Time PROM
version) ................................................................................................................................... 3-62
Fig. 3.2.70 V OL-I OL characteristics of N-channel (V CC = 5.0 V, normal port: One Time PROM
version) ................................................................................................................................... 3-62
Fig. 3.2.71 VOL-I OL characteristics of N-channel (V CC = 3.0 V, LED drive port: One Time PROM
version) ................................................................................................................................... 3-63
Fig. 3.2.72 VOL-I OL characteristics of N-channel (V CC = 5.0 V, LED drive port: One Time PROM
version) ................................................................................................................................... 3-63
Fig. 3.2.73 V CC-IIL characteristics (Port “L” input current when connecting pull-up transistor:
One Time PROM version) .................................................................................................... 3-64
Fig. 3.2.74 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8
MHz in high-speed mode: One Time PROM version) ..................................................... 3-65
Fig. 3.2.75 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6
MHz in double-speed mode: One Time PROM version) ................................................. 3-65
Fig. 3.2.76 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4
MHz in double-speed mode: One Time PROM version) ................................................. 3-65
Fig. 3.2.77 VCC-ROSC characteristics (on-chip oscillator frequency: One Time PROM version) ..... 3-66
Fig. 3.2.78 Ta-ROSC characteristics (on-chip oscillator frequency: One Time PROM version) ...... 3-66
Fig. 3.2.79 R-f(X IN) characteristics (RC oscillation frequency: One Time PROM version) 3-67
Fig. 3.2.80 C-f(X IN) characteristics (RC oscillation frequency: One Time PROM version) 3-67
Fig. 3.2.81 VCC-f(XIN) characteristics (RC oscillation frequency: One Time PROM version) ... 3-68
Fig. 3.2.82 Ta-f(X IN) characteristics (RC oscillation frequency: One Time PROM version)3-68
Fig. 3.2.83 Definition of A/D conversion accuracy .................................................................. 3-69
Fig. 3.2.84 A/D conversion accuracy typical characteristic example-1 (One Time PROM version) .. 3-70
Fig. 3.2.85 A/D conversion accuracy typical characteristic example-2 (One Time PROM version) .. 3-71
Fig. 3.2.86 A/D conversion accuracy typical characteristic example-3 (One Time PROM version) .. 3-72
Fig. 3.3.1 Sequence of setting serial I/O1 control register again ......................................... 3-80
Fig. 3.3.2 Connection diagram ................................................................................................... 3-82
Fig. 3.3.3 State transition ............................................................................................................ 3-84
Fig. 3.3.4 Switching method of CPU mode register ............................................................... 3-85
Fig. 3.3.5 Sequence of switch the detection edge .................................................................. 3-86
Fig. 3.3.6 Sequence of check of interrupt request bit ............................................................ 3-86
Fig. 3.3.7 Structure of interrupt control register 2 .................................................................. 3-87
Fig. 3.3.8 Initialization of processor status register ................................................................ 3-88
Fig. 3.3.9 Sequence of PLP instruction execution .................................................................. 3-88
Fig. 3.3.10 Stack memory contents after PHP instruction execution ................................... 3-88
Fig. 3.3.11 Status flag at decimal calculations ........................................................................ 3-89
Fig. 3.3.12 Programming and testing of One Time PROM version ...................................... 3-90
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3.4.1 Selection of packages ............................................................................................... 3-92
3.4.2 Wiring for the RESET pin ......................................................................................... 3-92
3.4.3 Wiring for clock I/O pins ........................................................................................... 3-93
3.4.4 Wiring for CNV SS pin ................................................................................................ 3-93
3.4.5 Wiring for the V PP pin of the One Time PROM ..................................................... 3-94
3.4.6 Bypass capacitor across the V SS line and the V CC line ........................................ 3-94
3.4.7 Analog signal line and a resistor and a capacitor ................................................ 3-95
3.4.8 Wiring for a large current signal line ...................................................................... 3-95
3.4.9 Wiring of signal lines where potential levels change frequently ......................... 3-96
3.4.10 V SS pattern on the underside of an oscillator ...................................................... 3-96
3.4.11 Setup for I/O ports ................................................................................................... 3-96
3.4.12 Watchdog timer by software ................................................................................... 3-97
3.5.1 Structure of Port Pi (i = 0, 2, 3) .............................................................................. 3-98
3.5.2 Structure of Port P1 ................................................................................................... 3-98
3.5.3 Structure of Port Pi direction register (i = 0, 2, 3) ............................................... 3-99
3.5.4 Structure of Port P1 direction register .................................................................... 3-99
3.5.5 Structure of Pull-up control register ...................................................................... 3-100
3.5.6 Structure of Port P1P3 control register ................................................................ 3-100
3.5.7 Structure of Transmit/Receive buffer register ...................................................... 3-101
3.5.8 Structure of Serial I/O1 status register ................................................................. 3-101
3.5.9 Structure of Serial I/O1 control register ................................................................ 3-102
3.5.10 Structure of UART control register ...................................................................... 3-102
3.5.11 Structure of Baud rate generator ......................................................................... 3-103
3.5.12 Structure of Timer A mode register .................................................................... 3-104
3.5.13 Structure of Timer A register ............................................................................... 3-105
3.5.14 Structure of Timer Y, Z mode register ............................................................... 3-105
3.5.15 Structure of Prescaler Y, Prescaler Z ................................................................. 3-106
3.5.16 Structure of Timer Y secondary, Timer Z secondary ....................................... 3-106
3.5.17 Structure of Timer Y primary, Timer Z primary ................................................. 3-107
3.5.18 Structure of Timer Y, Z waveform output control register ............................... 3-107
3.5.19 Structure of Prescaler 1 ........................................................................................ 3-108
3.5.20 Structure of Timer 1 .............................................................................................. 3-108
3.5.21 Structure of One-shot start register ..................................................................... 3-109
3.5.22 Structure of Timer X mode register .................................................................... 3-110
3.5.23 Structure of Prescaler X ....................................................................................... 3-111
3.5.24 Structure of Timer X .............................................................................................. 3-111
3.5.25 Structure of Timer count source set register ..................................................... 3-112
3.5.26 Structure of Serial I/O2 control register .............................................................. 3-113
3.5.27 Structure of Serial I/O2 register ........................................................................... 3-113
3.5.28 Structure of A/D control register .......................................................................... 3-114
3.5.29 Structure of A/D conversion register (low-order) ............................................... 3-114
3.5.30 Structure of A/D conversion register (high-order) ............................................. 3-115
3.5.31 Structure of MISRG ............................................................................................... 3-115
3.5.32 Structure of Watchdog timer control register ..................................................... 3-116
3.5.33 Structure of Interrupt edge selection register .................................................... 3-116
3.5.34 Structure of CPU mode register .......................................................................... 3-117
3.5.35 Structure of Interrupt request register 1 ............................................................. 3-118
3.5.36 Structure of Interrupt request register 2 ............................................................. 3-118
3.5.37 Structure of Interrupt control register 1 .............................................................. 3-119
3.5.38 Structure of Interrupt control register 2 .............................................................. 3-119
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List of figures
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Fig.
Fig.
3.10.1
3.10.2
3.10.3
3.10.4
3.11.1
3.11.2
3.11.3
32P6U-A package pin configuration .................................................................... 3-135
36P2R-A package pin configuration .................................................................... 3-136
32P4B package pin configuration ........................................................................ 3-137
42S1M package pin configuration ........................................................................ 3-138
Memory map of 7540 Group and 7531 Group .................................................. 3-140
Memory map of interrupt vector area of 7540 Group and 7531 Group ........ 3-141
Timer function of 7540 Group and 7531 Group ................................................ 3-142
xii
List of tables
7540 Group
List of tables
CHAPTER 1 HARDWARE
Table
Table
Table
Table
Table
Table
Table
Table
Table
1
2
3
4
5
6
7
8
9
Pin description ................................................................................................................. 1-8
List of supported products ........................................................................................... 1-10
Push and pop instructions of accumulator or processor status register ............... 1-12
Set and clear instructions of each bit of processor status register ....................... 1-13
I/O port function table ................................................................................................... 1-18
Interrupt vector address and priority .......................................................................... 1-21
Special programming adapter ...................................................................................... 1-53
Interrupt sources, vector addresses and interrupt priority ....................................... 1-54
Change of A/D conversion register during A/D conversion ..................................... 1-56
CHAPTER 2 APPLICATION
Table
Table
Table
Table
2.1.1
2.2.1
2.4.1
2.6.1
Handling of unused pins ........................................................................................ 2-10
CNTR1 active edge switch bit function ................................................................ 2-15
CNTR0 active edge switch bit function ................................................................ 2-42
Setting example of baud rate generator (BRG) and transfer bit rate values .. 2-112
CHAPTER 3 APPENDIX
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.1 Absolute maximum ratings ....................................................................................... 3-2
3.1.2 Recommended operating conditions (1) ................................................................ 3-3
3.1.3 Recommended operating conditions (2) ................................................................ 3-4
3.1.4 Electrical characteristics (1) ..................................................................................... 3-5
3.1.5 Electrical characteristics (2) ..................................................................................... 3-6
3.1.6 A/D Converter characteristics .................................................................................. 3-7
3.1.7 Timing requirements (1) ........................................................................................... 3-8
3.1.8 Timing requirements (2) ........................................................................................... 3-8
3.1.9 Timing requirements (3) ........................................................................................... 3-9
3.1.10 Switching characteristics (1) ................................................................................ 3-10
3.1.11 Switching characteristics (2) ................................................................................ 3-10
3.1.12 Switching characteristics (3) ................................................................................ 3-11
3.1.13 Absolute maximum ratings ................................................................................... 3-13
3.1.14 Recommended operating conditions (1) ............................................................ 3-14
3.1.15 Recommended operating conditions (2) ............................................................ 3-15
3.1.16 Electrical characteristics (1) ................................................................................ 3-16
3.1.17 Electrical characteristics (2) ................................................................................ 3-17
3.1.18 A/D Converter characteristics .............................................................................. 3-18
3.1.19 Timing requirements (1) ....................................................................................... 3-19
3.1.20 Timing requirements (2) ....................................................................................... 3-19
3.1.21 Switching characteristics (1) ................................................................................ 3-20
3.1.22 Switching characteristics (2) ................................................................................ 3-20
3.1.23 Absolute maximum ratings ................................................................................... 3-22
3.1.24 Recommended operating conditions (1) ............................................................ 3-23
3.1.25 Recommended operating conditions (2) ............................................................ 3-24
3.1.26 Electrical characteristics (1) ................................................................................ 3-25
3.1.27 Electrical characteristics (2) ................................................................................ 3-26
xiii
List of tables
7540 Group
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
3.1.28 A/D Converter characteristics .............................................................................. 3-27
3.1.29 Timing requirements (1) ....................................................................................... 3-28
3.1.30 Timing requirements (2) ....................................................................................... 3-28
3.1.31 Switching characteristics (1) ................................................................................ 3-29
3.1.32 Switching characteristics (2) ................................................................................ 3-29
3.3.1 Programming adapters ........................................................................................... 3-91
3.3.2 PROM programmer address setting ..................................................................... 3-91
3.5.1 CNTR1 active edge switch bit function .............................................................. 3-104
3.5.2 CNTR0 active edge switch bit function .............................................................. 3-110
3.11.1 Differences between 7540 Group and 7531 Group ....................................... 3-139
xiv
CHAPTER 1
HARDWARE
DESCRIPTION
FEATURES
APPLICATION
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USE
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
FUNCTIONAL DESCRIPTION SUPPLEMENT
HARDWARE
7540 Group
DESCRIPTION/FEATURES/APPLICATION
DESCRIPTION
APPLICATION
The 7540 Group is the 8-bit microcomputer based on the 740 family core technology.
The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and
an A/D converter, and is useful for control of home electric appliances and office automation equipment.
Office automation equipment, factory automation equipment,
home electric appliances, consumer electronics, car, etc.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Basic machine-language instructions ...................................... 71
The minimum instruction execution time ......................... 0.34 µs
(at 6 MHz oscillation frequency, double-speed mode for the
shortest instruction)
Memory size ROM ............................................ 8 K to 32 K bytes
RAM ............................................. 384 to 768 bytes
Programmable I/O ports ....................... 29 (25 in 32-pin version)
Interrupts ................................................. 15 sources, 15 vectors
................................. (14 sources, 14 vectors for 32-pin version)
Timers ............................................................................. 8-bit ✕ 4
...................................................................................... 16-bit ✕ 1
Serial I/O1 ................... 8-bit ✕ 1 (UART or Clock-synchronized)
Serial I/O2 (Note 1) ..................... 8-bit ✕ 1 (Clock-synchronized)
A/D converter ............................................... 10-bit ✕ 8 channels
.................................................... (6 channels for 32-pin version)
Clock generating circuit ............................................. Built-in type
(low-power dissipation by an on-chip oscillator enabled)
(connect to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation)
Watchdog timer ............................................................ 16-bit ✕ 1
Power source voltage
XIN oscillation frequency at ceramic oscillation, in double-speed mode
At 6 MHz .................................................................... 4.5 to 5.5 V
XIN oscillation frequency at ceramic oscillation, in high-speed mode
At 8 MHz .................................................................... 4.0 to 5.5 V
At 4 MHz .................................................................... 2.4 to 5.5 V
At 2 MHz .................................................................... 2.2 to 5.5 V
XIN oscillation frequency at RC oscillation in high-speed mode or
middle-speed mode
At 4 MHz .................................................................... 4.0 to 5.5 V
At 2 MHz .................................................................... 2.4 to 5.5 V
At 1 MHz .................................................................... 2.2 to 5.5 V
Power dissipation
Mask ROM version ....................................... 22.5 mW (standard)
One Time PROM version ................................ 30 mW (standard)
Operating temperature range ................................... –20 to 85 °C
(–40 to 85 °C for extended operating temperature version)
(–40 to 125 °C for extended operating temperature 125 °C version (Note 2))
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Notes 1: Serial I/O2 can be used in the following cases;
(1) Serial I/O1 is not used,
(2) Serial I/O1 is used as UART and BRG output divided by 16 is
selected as the synchronized clock.
2: In this version, the operating temperature range and total time
are limited as follows;
55 °C to 85 °C: within total 6000 hours,
85 °C to 125 °C: within total 1000 hours.
1-2
HARDWARE
7540 Group
PIN CONFIGURATION
P07
P10/RXD1
P11/TXD1
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0
P21/AN1
25
26
27
28
29
30
31
18
17
20
19
22
21
23
24
P06
P05
P04
P03/TXOUT
P02/TZOUT
P01/TYOUT
P00/CNTR1
P37/INT0
PIN CONFIGURATION (TOP VIEW)
M37540Mx-XXXGP
M37540MxT-XXXGP
M37540MxV-XXXGP
M37540ExGP
M37540E8T-XXXGP
M37540E8V-XXXGP
16
15
14
13
12
11
10
9
7
8
6
5
4
3
2
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
1
32
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
VSS
XOUT
XIN
Package type: 32P6U-A
Fig. 1 Pin configuration (32P6U-A type)
1
36
2
35
3
34
4
5
6
7
8
9
10
11
12
13
M37540Mx-XXXFP
M37540MxT-XXXFP
M37540MxV-XXXFP
M37540E8FP
M37540E8T-XXXFP
M37540E8V-XXXFP
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
33
32
31
30
29
28
27
26
25
24
14
23
15
22
16
21
17
20
18
19
P11/TXD1
P10/RXD1
P07
P06
P05
P04
P03/TXOUT
P02/TZOUT
P01/TYOUT
P00/CNTR1
P37/INT0
P36(LED6)/INT1
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
Package type: 36P2R-A
Fig. 2 Pin configuration (36P2R-A type)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
1-3
HARDWARE
7540 Group
PIN CONFIGURATION
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
1
32
P11/TXD1
3
30
P10/RXD1
P07
P20/AN0
4
29
P06
P21/AN1
P22/AN2
5
28
P23/AN3
P24/AN4
7
P05
P04
P03/TXOUT
P02/TZOUT
P25/AN5
VREF
9
6
8
M37540Mx-XXXSP
M37540ExSP
2
31
27
26
25
23
P01/TYOUT
P00/CNTR1
22
P37/INT0
21
P34(LED4)
13
20
14
14
19
P33(LED3)
P32(LED2)
XOUT
15
18
P31(LED1)
VSS
16
17
P30(LED0)
10
RESET
CNVSS
VCC
XIN
11
12
24
Package type: 32P4B
Fig. 3 Pin configuration (32P4B-A type)
1
42
2
41
3
40
4
39
5
38
6
37
7
36
8
9
10
11
12
13
14
15
M37540RSS
P14/CNTR0
NC
NC
P20/AN0
P21/AN1
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
NC
NC
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
35
34
33
32
31
30
29
28
16
27
17
26
18
25
19
24
20
23
21
22
P13/SRDY1/SDATA2
P12/SCLK1/SCLK2
P11/TXD1
P10/RXD1
P07
P06
P05
P04
P03/TXOUT
P02/TZOUT
P01/TYOUT
P00/CNTR1
NC
P37/INT0
P36(LED6)/INT1
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
Outline 42S1M
Fig. 4 Pin configuration (42S1M type)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
1-4
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
VREF
Reset
0
PC H
I/O port P2
4 3 2 1 32 31
17 16 15 14 13 12
I/O port P3
P2(6)
INT0
ROM
P3(6)
RAM
A
PS
PC L
S
Y
X
SI/O1(8)
CPU
SI/O2(8)
P1(5)
INT0
I/O port P1
30 29 28 27 26
6
Prescaler Y (8)
P0(8)
TZOUT
I/O port P0
25 24 23 22 21 20 19 18
CNTR1
Timer A (16)
Timer Z (8)
TYOUT
TXOUT
Timer Y (8)
Prescaler Z (8)
Timer X (8)
CNTR0
Timer 1 (8)
Prescaler X (8)
Prescaler 1 (8)
7
CNVSS
7540 Group
5
A/D
converter
(10)
Watchdog timer
Clock generating circuit
8
11
RESET
9
Reset input
VCC
VSS
X IN X OU
T
10
Clock input Clock output
Key-on wakeup
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U)
HARDWARE
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 5 Functional block diagram (32P6U package)
1-5
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
17
VREF
Reset
0
PCH
I/O port P2
11 10 9 8 7 6 5 4
26 25 24 23 22 21 20 19
I/O port P3
P2(8)
INT0 INT1
ROM
P3(8)
RAM
15
18
PS
PCL
S
Y
X
A
SI/O1(8)
CPU
VCC
VSS
SI/O2(8)
P1(5)
INT0
I/O port P1
3 2 1 36 35
13
Reset input
RESET
I/O port P0
34 33 32 31 30 29 28 27
P0(8)
CNTR1
TYOUT
TZOUT
Timer Z (8)
Timer A (16)
Prescaler Z (8)
Timer Y (8)
TXOUT
Prescaler Y (8)
Timer X (8)
CNTR0
Timer 1 (8)
Prescaler X (8)
Prescaler 1 (8)
14
CNVSS
7540 Group
12
A/D
converter
(10)
Watchdog timer
Clock generating circuit
16
Clock input Clock output
X IN X OUT
Key-on wakeup
FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
HARDWARE
FUNCTIONAL BLOCK
Fig. 6 Functional block diagram (36P2R package)
1-6
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
15
Clock output
X OUT
VREF
Reset
0
PCH
I/O port P2
9 8 7 6 5 4
22 21 20 19 18 17
I/O port P3
P2(6)
INT0
ROM
P3(6)
RAM
13
16
PS
PCL
S
Y
X
A
SI/O1(8)
CPU
VCC
VSS
SI/O2(8)
P1(5)
INT0
I/O port P1
3 2 1 32 31
11
Reset input
RESET
I/O port P0
TYOUT
TZOUT
Timer Z (8)
30 29 28 27 26 25 24 23
P0(8)
CNTR1
Timer A (16)
Prescaler Z (8)
Timer Y (8)
TXOUT
Prescaler Y (8)
Timer X (8)
CNTR0
Timer 1 (8)
Prescaler X (8)
Prescaler 1 (8)
12
CNVSS
7540 Group
10
A/D
converter
(10)
Watchdog timer
Clock generating circuit
14
Clock input
X IN
Key-on wakeup
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
HARDWARE
FUNCTIONAL BLOCK
Fig. 7 Functional block diagram (32P4B package)
1-7
HARDWARE
7540 Group
PIN DESCRIPTION
PIN DESCRIPTION
Table 1 Pin description
Pin
Name
Vcc, Vss
Power source
(Note 1)
VREF
Analog reference
voltage
CNVss
CNVss
RESET
Reset input
XIN
Clock input
XOUT
Clock output
P00/CNTR1
P01/TYOUT
P02/TZOUT
P03/TXOUT
P04–P07
I/O port P0
P10/RxD1
I/O port P1
P11/TxD1
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0–P27/AN7 I/O port P2
(Note 2)
P30–P35
I/O port P3
(Note 3)
P36/INT1
P37/INT0
Function
•Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss.
Function expect a port function
•Reference voltage input pin for A/D converter
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
•For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• When the on-chip oscillator is selected as the main clock, connect XIN pin to VSS and leave XOUT open.
• Key-input (key-on wake up
•8-bit I/O port.
interrupt input) pins
•I/O direction register allows each pin to be individually pro• Timer Y, timer Z, timer X and
grammed as either input or output.
timer A function pin
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be determined by program.
•5-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P10, P12 and P13
• Serial I/O1 function pin
• Serial I/O1 function pin
• Serial I/O2 function pin
• Timer X function pin
•8-bit I/O port having almost the same function as P0
• Input pins for A/D converter
•CMOS compatible input level
•CMOS 3-state output structure
•8-bit I/O port
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37).
•CMOS 3-state output structure
•P30 to P36 can output a large current for driving LED.
•Whether a built-in pull-up resistor is to be used or not can be determined by program.
• Interrupt input pins
Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version and the extended operating temperature 125 °C version.
2: P26/AN6 and P27/AN7 do not exist for the 32-pin version, so that Port P2 is a 6-bit I/O port.
3: P35 and P36/INT1 do not exist for the 32-pin version, so that Port P3 is a 6-bit I/O port.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
1-8
HARDWARE
7540 Group
GROUP EXPANSION
GROUP EXPANSION
We plan to expand the 7540 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and
Emulator MCU .
Memory size
ROM/PROM size ................................................. 8 K to 32 K bytes
RAM size .............................................................. 384 to 768 bytes
Package
32P4B .................................................. 32-pin plastic molded SDIP
32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP
36P2R-A ...................... 0.8 mm-pitch 36-pin plastic molded SSOP
42S1M .................................... 42-pin shrink ceramic PIGGY BACK
ROM size
(bytes)
M37540E8V
32K
M37540E8T
M37540E8
M37540M4V
16K
M37540M4T
M37540M4
M37540E2
M37540M2V
8K
M37540M2T
M37540M2
0
384
512
768
RAM size
(bytes)
Fig. 8 Memory expansion plan
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
1-9
HARDWARE
7540 Group
GROUP EXPANSION
Currently supported products are listed below.
Table 2 List of supported products
(P) ROM size (bytes) RAM size
Part Number
(bytes)
ROM size for User ()
384
8192
M37540M2-XXXSP
(8062)
M37540M2-XXXFP
M37540M2T-XXXFP
M37540M2V-XXXFP
M37540M2-XXXGP
M37540M2T-XXXGP
M37540M2V-XXXGP
M37540M4-XXXSP
M37540M4-XXXFP
M37540M4T-XXXFP
M37540M4V-XXXFP
M37540M4-XXXGP
M37540M4T-XXXGP
M37540M4V-XXXGP
M37540E2SP
M37540E2FP
M37540E2GP
M37540E8SP
M37540E8FP
M37540E8T-XXXFP
16384
(16254)
512
8192
(8062)
384
32768
(32638)
768
M37540E8V-XXXFP
M37540E8GP
M37540E8T-XXXGP
M37540E8V-XXXGP
M37540RSS
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
768
Package
Remarks
32P4B Mask ROM version
36P2R-A Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
32P6U-A Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
32P4B Mask ROM version
36P2R-A Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
32P6U-A Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
32P4B One Time PROM version (blank)
36P2R-A One Time PROM version (blank)
32P6U-A One Time PROM version (blank)
32P4B One Time PROM version (blank)
36P2R-A One Time PROM version (blank)
One Time PROM version
(shipped after programming, extended operating temperature version)
One Time PROM version (shipped after programming, extended
operating temperature 125 °C version)
32P6U-A One Time PROM version (blank)
One Time PROM version
(shipped after programming, extended operating temperature version)
One Time PROM version (shipped after programming, extended
operating temperature 125 °C version)
42S1M Emulator MCU
1-10
HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
Stack pointer (S)
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL
for details on each instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used. (This instruction cannot be
used while an on-chip oscillator is operating.)
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real
address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
b7
b7
b0
b7
Index Register X
b0
Y
b7
Index Register Y
b0
S
b7
Stack Pointer
b0
Program Counter
PCL
b7
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Accumulator
X
PCH
Program counter (PC)
b0
A
b15
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are
shown in Fig. 10.
b0
N V T B D I Z C Processor Status Register (PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Fig. 9 740 Family CPU register structure
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
1-11
HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
M (S)
Store Return Address
on Stack
(S)
(PC H)
(S)
(S – 1)
M (S)
(PCL)
(S)
(S – 1)
M (S)
Subroutine
Restore Return
Address
(S + 1)
(PCL)
M (S)
(S)
(S + 1)
(PCH)
M (S)
(S – 1)
(PC L)
(S)
(S – 1)
M (S)
(PS)
(S)
(S – 1)
Interrupt
Service Routine
Execute RTS
(S)
(PC H)
Execute RTI
Note : The condition to enable the interrupt
(S)
(S + 1)
(PS)
M (S)
(S)
(S + 1)
(PC L)
M (S)
(S)
(S + 1)
(PC H)
M (S)
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
I Flag “0” to “1”
Fetch the Jump Vector
Restore Contents of
Processor Status Register
Restore Return
Address
Interrupt enable bit is “1”
Interrupt disable flag is “0”
Fig. 10 Register push and pop at interrupt generation and subroutine call
Table 3 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
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Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
1-12
HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Processor status register (PS)
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)
flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction. Interrupts are disabled when the I flag is
“1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status
register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the
stack with the break flag set to “1”. The saved processor status is
the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed between accumulator and memory, e.g. the results of an operation
between two memory locations is stored in the accumulator. When
the T flag is “1”, direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory
and memory, memory and I/O, and I/O and I/O. In this case, the
result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1.
The address of memory location 1 is specified by index register X,
and the address of memory location 2 is specified by normal addressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
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Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
1-13
HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM: address 003B16, initial value: 8016)
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
1 0
Not available
1 1
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method.
Stack page selection bit
0 : 0 page
1 : 1 page
On-chip oscillator oscillation control bit
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
XIN oscillation control bit
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
Oscillation mode selection bit (Note 1)
0 : Ceramic oscillation
1 : RC oscillation
Clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(XIN)/2 (High-speed mode)
0 1 : f(φ) = f(XIN)/8 (Middle-speed mode)
1 0 : applied from on-chip oscillator
1 1 : f(φ) = f(XIN) (Double-speed mode)(Note 2)
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37540RSS”.)
2: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 11 Structure of CPU mode register
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Wait by on-chip oscillator operation
until establishment of oscillator clock
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Start with an on-chip oscillator
An initial value is set as a ceramic
oscillation mode. When it is switched to an
RC oscillation, its oscillation starts.
When using a ceramic oscillation, wait until
establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not
required basically (time to execute the instruction
to switch from an on-chip oscillator meets the
requirement).
Select 1/1, 1/2, 1/8 or on-chip oscillator.
Main routine
Fig. 12 Switching method of CPU mode register
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function registers (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page
addressing mode.
000016
SFR area
Zero page
004016
RAM
010016
RAM area
RAM capacity
(bytes)
address
XXXX16
384
512
768
01BF16
023F16
033F16
XXXX16
Reserved area
044016
Not used
YYYY16
Reserved ROM area
(128 bytes)
ZZZZ16
ROM
FF0016
ROM area
ROM capacity
(bytes)
address
YYYY16
address
ZZZZ16
8192
16384
32768
E00016
C00016
800016
E08016
C08016
808016
Special page
FFDC16
Interrupt vector area
FFFE16
FFFF16
Reserved ROM area
Fig. 13 Memory map diagram
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Timer Y, Z mode register (TYZM)
000016
Port P0 (P0)
002016
000116
Port P0 direction register (P0D)
002116
Prescaler Y (PREY)
000216
Port P1 (P1)
002216
Timer Y secondary (TYS)
000316
Port P1 direction register (P1D)
002316
Timer Y primary (TYP)
000416
Port P2 (P2)
002416
Timer Y, Z waveform output control register (PUM)
000516
Port P2 direction register (P2D)
002516
Prescaler Z (PREZ)
000616
Port P3 (P3)
002616
Timer Z secondary (TZS)
000716
Port P3 direction register (P3D)
002716
Timer Z primary (TZP)
002816
Prescaler 1 (PRE1)
000916
002916
Timer 1 (T1)
000A16
002A16
One-shot start register (ONS)
000B16
002B16
Timer X mode register (TXM)
000C16
002C16
Prescaler X (PREX)
000D16
002D16
Timer X (TX)
Timer count source set register (TCSS)
000816
000E16
002E16
000F16
002F16
001016
003016
Serial I/O2 control register (SIO2CON)
001116
003116
Serial I/O2 register (SIO2)
001216
003216
001316
003316
001416
003416
A/D control register (ADCON)
001516
003516
A/D conversion register (low-order) (ADL)
A/D conversion register (high-order) (ADH)
001616
Pull-up control register (PULL)
003616
001716
Port P1P3 control register (P1P3C)
003716
001816
Transmit/Receive buffer register (TB/RB)
003816
001916
Serial I/O1 status register (SIO1STS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
MISRG
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
Timer A mode register (TAM)
003D16
Interrupt request register 2 (IREQ2)
001E16
Timer A (low-order) (TAL)
003E16
Interrupt control register 1 (ICON1)
001F16
Timer A (high-order) (TAH)
003F16
Interrupt control register 2 (ICON2)
Note : Do not access to the SFR area including nothing.
Fig. 14 Memory map of special function register (SFR)
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes
an output port. When “0” is set to the bit, the pin becomes an input port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
b7
[Pull-up control register] PULL
By setting the pull-up control register (address 001616), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
Note: P26/AN6, P27/AN7, P35 and P36 do not exist for the 32-pin
version.
Accordingly, the following settings are required;
• Set direction registers of ports P26 and P27 to output.
• Set direction registers of ports P35 and P36 to output.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 0017 16), a
CMOS input level or a TTL input level can be selected for ports
P10, P12, P13, P36, and P37 by program.
b0
Pull-up control register
(PULL: address 001616, initial value: 0016)
P00 pull-up control bit
P01 pull-up control bit
P02, P03 pull-up control bit
P04 – P07 pull-up control bit
P30 – P33 pull-up control bit
P34 pull-up control bit
P35, P36 pull-up control bit
0 : Pull-up Off
1 : Pull-up On
P37 pull-up control bit
Note: Pins set to output ports are disconnected from pull-up control.
Fig. 15 Structure of pull-up control register
b7
b0
Port P1P3 control register
(P1P3C: address 0017 16, initial value: 00 16)
P37/INT 0 input level selection bit
0 : CMOS level
1 : TTL level
P36/INT 1 input level selection bit
0 : CMOS level
1 : TTL level
P10,P1 2,P13 input level selection bit
0 : CMOS level
1 : TTL level
Not used
Note: Keep setting the P3 6/INT 1 input level selection bit
to “0” (initial value) for 32-pin version.
Fig. 16 Structure of port P1P3 control register
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Table 5 I/O port function table
Pin
P00/CNTR1
P01/TYOUT
P02/TZOUT
P03/TXOUT
P04–P07
Name
Input/output
I/O format
I/O port P0 I/O individual •CMOS compatible
bits
input level
•CMOS 3-state output
(Note 1)
Non-port function
Key input interrupt
Timer X function output
Timer Y function output
Timer Z function output
Timer A function input
P10/RxD1
P11/TxD1
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
I/O port P1
Serial I/O1 function
input/output
Serial I/O2 function
input/output
Timer X function input/output
A/D conversion input
I/O port P2
(Note 2)
I/O port P3
(Note 3)
External interrupt input
Diagram No.
Related SFRs
(1)
Pull-up control register
(2)
Timer Y mode register
(3)
Timer Z mode register
(4)
Timer X mode register
Timer Y,Z waveform
output control register
Timer A mode register
(5)
Serial I/O1 control register
(6)
(7)
Serial I/O1 control register
(8)
Serial I/O2 control register
(9)
Timer X mode register
(10)
A/D control register
Interrupt edge selection
register
(11)
(12)
Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level.
2: P26/AN6 and P27/AN7 do not exist for the 32-pin version.
3: P35 and P36/INT1 do not exist for the 32-pin version.
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
(1)Port P00
(2)Ports P01, P02
Pull-up control
Pull-up control
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
**
Programmable waveform generation mode
Timer output
CNTR1 interrupt input
To key input interrupt
generating circuit
P00 key-on wakeup
selection bit
(3)Port P03
To key input interrupt
generating circuit
(4)Ports P04–P07
Pull-up control
Pull-up control
Direction
register
Data bus
Direction
register
Data bus
Port latch
Port latch
Timer output
P03/TXOUT
output valid
To key input interrupt
generating circuit
To key input interrupt
generating circuit
(5)Port P10
(6)Port P11
Serial I/O1 enable bit
Receive enable bit
P11/TxD1 P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Data bus
Direction
register
Port latch
P10, P12, P13
input level
selection bit
Data bus
Port latch
Serial I/O1 input
*
Serial I/O1 output
(7)Port P12
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
SCLK2 pin
selection bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
register
Data bus
Port latch
P10, P12, P13
input level
selection bit
Serial I/O1, serial I/O2 clock output
Serial I/O1, serial I/O2 clock input
*
*
**
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
P02/TZOUT;
Programmable waveform generation mode
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Fig. 17 Block diagram of ports (1)
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
(8) Port P13
(9) Port P14
SDATA2 output in operation signal
SDATA2 pin selection bit
Direction
register
Serial I/O mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Direction
register
Data bus
Data bus
Port
latch
Port latch
Pulse output mode
Timer output
P10, P12, P13
input level
selection bit
CNTR0 interrupt input
Serial I/O1 ready output
Serial I/O2 output
Serial I/O2 input
*
(11) Ports P30–P35
(10) Ports P20–P27
Direction
register
Pull-up control
Direction
register
Data bus
Port latch
Data bus
Port
latch
A/D converter input
Analog input pin
selection bit
(12) Ports P36, P37
Pull-up control
Direction
register
Data bus
Port
latch
P3 input level
selection bit
INT interrupt input
*
*
P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.
When the TTL level is selected, there is no hysteresis characteristics.
Fig. 18 Block diagram of ports (2)
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Interrupts
Interrupts occur by 15 different sources : 5 external sources, 9 internal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by
the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to “1” and the interrupt disable flag is set
to “0”, an interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the
interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status register are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
■ Notes on use
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit).
➂ Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
Table 6 Interrupt vector address and priority
Interrupt source Priority
Vector addresses (Note 1)
High-order
Low-order
Reset (Note 2)
Serial I/O1 receive
Serial I/O1 transmit
1
2
3
FFFD16
FFFB16
FFF916
FFFC16
FFFA16
FFF816
INT0
4
FFF716
FFF616
INT1 (Note 3)
5
FFF516
FFF416
Key-on wake-up
6
FFF316
FFF216
CNTR0
7
FFF116
FFF016
CNTR1
8
FFEF16
FFEE16
Timer X
Timer Y
Timer Z
Timer A
Serial I/O2
A/D conversion
Timer 1
Reserved area
BRK instruction
9
10
11
12
13
14
15
16
17
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Interrupt request generating conditions
Remarks
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At falling of conjunction of input logical level
for port P0 (at input)
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
At timer Y underflow
At timer Z underflow
At timer A underflow
At completion of transmit/receive shift
At completion of A/D conversion
At timer 1 underflow
Not available
At BRK instruction execution
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is
selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: It is an interrupt which can use only for 36 pin version.
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
BRK instruction
Reset
Interrupt request
Fig. 19 Interrupt control
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16, initial value : 0016)
INT0 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT1 interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
P00 key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16, initial value : 0016)
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
INT0 interrupt request bit
INT1 interrupt request bit
Key-on wake up interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Timer X interrupt request bit
b7
b0 Interrupt request register 2
(IREQ2 : address 003D16, initial value : 0016)
Timer Y interrupt request bit
Timer Z interrupt request bit
Timer A interrupt request bit
Serial I/O2 interrupt request bit
A/D conversion interrupt request bit
Timer 1 interrupt request bit
Not used (returns “0” when read)
b7
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b0 Interrupt control register 1
(ICON1 : address 003E16, initial value : 0016)
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
INT0 interrupt enable bit
INT1 interrupt enable bit (Do not write “1” to this bit for 32-pin version)
Key-on wake up interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer X interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
b7
b0 Interrupt control register 2
(ICON2 : address 003F16, initial value : 0016)
Timer Y interrupt enable bit
Timer Z interrupt enable bit
Timer A interrupt enable bit
Serial I/O2 interrupt enable bit
A/D conversion interrupt enable bit
Timer 1 interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 20 Structure of Interrupt-related registers
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L”
level to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes
from “1” to “0”. An example of using a key input interrupt is shown
in Figure 21, where an interrupt request is generated by pressing
one of the keys provided as an active-low key matrix which uses
ports P00 to P03 as input ports.
Port PXx
“L” level output
PULL register
bit 3 = “0”
*
**
P07 output
Port P07
Direction register = “1”
Key input interrupt request
Port P07
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P06 output
Port P06
Direction register = “1”
Port P06
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P05 output
Port P05
Direction register = “1”
Port P05
latch
Falling edge
detection
PULL register
bit 3 = “0”
*
**
P04 output
Port P04
Direction register = “1”
Port P04
latch
PULL register
bit 2 = “1”
*
**
P03 input
Port P03
Direction register = “0”
Port P03
latch
PULL register
bit 2 = “1”
*
**
P02 input
Falling edge
detection
Port P0
Input read circuit
Falling edge
detection
Port P02
Direction register = “0”
Port P02
latch
Falling edge
detection
PULL register
bit 1 = “1”
*
**
P01 input
Port P01
Direction register = “0”
Port P01
latch
Falling edge
detection
PULL register
bit 0 = “1”
*
**
P00 input
Port P00
Direction register = “0”
Port P00
latch
Falling edge
detection
Port P00 key-on wakeup
selection bit
* P-channel transistor for pull-up
** CMOS output buffer
Fig. 21 Connection example when using key input interrupt and port P0 block diagram
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Timers
●Timer A
The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y
and timer Z.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding
timer latch is reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to each timer is set to “1”.
Timer A is a 16-bit timer and counts the signal which is the oscillation frequency divided by 16. When Timer A underflows, the
timer A interrupt request bit is set to “1”.
Timer A consists of the low-order of Timer A (TAL) and the high-order of Timer A (TAH).
Timer A has the timer A latch to retain the reload value. The value
of timer A latch is set to Timer A at the timing shown below.
• When Timer A undeflows.
• When an active edge is input from CNTR 1 pin (valid only when
period measurement mode and pulse width HL continuously measurement mode).
When writing to both the low-order of Timer A (TAL) and the highorder of Timer A (TAH) is executed, the value is written to both the
timer A latch and Timer A.
When reading from the low-order of Timer A (TAL) and the high-order of Timer A (TAH) is executed, the following values are read out
according to the operating mode.
• In timer mode, event counter mode:
The count value of Timer A is read out.
• In period measurement mode, pulse width HL continuously measurement mode:
The measured value is read out.
●Timer 1
Timer 1 is an 8-bit timer and counts the prescaler output.
When Timer 1 underflows, the timer 1 interrupt request bit is set to
“1”.
Prescaler 1 is an 8-bit prescaler and counts the signal which is the
oscillation frequency divided by 16.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows.The value of timer 1 latch is set to Timer 1 when Timer
1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is written to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is executed, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the signal which is the oscillation frequency divided by 16. Each time the count clock is input, the contents of
Prescaler 1 is decremented by 1. When the contents of Prescaler
1 reach “0016”, an underflow occurs at the next count clock, and
the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1
reach “0016”, an underflow occurs at the next count clock, and the
timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer
1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is
1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and
the value of Timer 1 is m.
Timer 1 cannot stop counting by software.
Be sure to write to/read out the low-order of Timer A (TAL) and the
high-order of Timer A (TAH) in the following order;
Read
Read the high-order of Timer A (TAH) first, and the low-order of
Timer A (TAL) next and be sure to read out both TAH and TAL.
Write
Write to the low-order of Timer A (TAL) first, and the high-order of
Timer A (TAH) next and be sure to write to both TAL and TAH.
Timer A can be selected in one of 4 operating modes by setting
the timer A mode register.
(1) Timer mode
Timer A counts the oscillation frequency divided by 16. Each time
the count clock is input, the contents of Timer A is decremented by
1. When the contents of Timer A reach “000016”, an underflow occurs at the next count clock, and the timer A latch is reloaded into
Timer A. The division ratio of Timer A is 1/(n+1) provided that the
value of Timer A is n.
(2) Period measurement mode
In the period measurement mode, the pulse period input from the
P00/CNTR1 pin is measured.
CNTR 1 interrupt request is generated at rising/falling edge of
CNTR1 pin input singal. Simultaneousuly, the value in the timer A
latch is reloaded inTimer A and count continues. The active edge
of CNTR1 pin input signal can be selected from rising or falling by
the CNTR1 active edge switch bit .The count value when trigger
input from CNTR1 pin is accepted is retained until Timer A is read
once.
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
(3) Event counter mode
Timer A counts signals input from the P00/CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR1 pin input signal can be selected from
rising or falling by the CNTR1 active edge switch bit .
(4) Pulse width HL continuously measurement mode
In the pulse width HL continuously measurement mode, the pulse
width (“H” and “L” levels) input to the P00/CNTR1 pin is measured.
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
The count value when trigger input from the CNTR 1 pin is accepted is retained until Timer A is read once.
Timer A can stop counting by setting “1” to the timer A count stop
bit in any mode.
Also, when Timer A underflows, the timer A interrupt request bit is
set to “1”.
Note on Timer A is described below;
■ Note on Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR 1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
b7
b0
Timer A mode register
(TAM : address 001D 16, initial value: 00 16)
Not used (return “0” when read)
Timer A operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR 1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR 1 interrupt
Timer A count stop bit
0 : Count start
1 : Count stop
Fig. 22 Structure of timer A mode register
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REJ09B0018-0200Z
●Timer X
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to “1”.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows.The value of timer X latch is set to Timer X when Timer
X underflows.
When writing to Prescaler X (PREX) is executed, the value is written to both the prescaler X latch and Prescaler X.
When writing to Timer X (TX) is executed, the value is written to
both the timer X latch and Timer X.
When reading from Prescaler X (PREX) and Timer X (TX) is executed, each count value is read out.
Timer X can can be selected in one of 4 operating modes by setting the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach “0016”, an underflow occurs at the next count
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X
reach “0016”, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR0 pin.
The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is “0”,
the output of CNTR0 pin is started at “H” level. When this bit is “1”,
the output is started at “L” level.
Also, the inverted waveform of pulse output from CNTR0 pin can
be output from TXOUT pin by setting “1” to the P03/TXOUT output
valid bit.
When using a timer in this mode, set the port P14 and P03 direction registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P14/CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR0 pin input signal can be selected from
rising or falling by the CNTR0 active edge switch bit .
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(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured.
The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR0 pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR0 pin is “L”. The count
is stopped while the pin is “H”.
FUNCTIONAL DESCRIPTION
b7
b0
Timer X mode register
(TXM : address 002B 16, initial value: 00 16)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR 0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X count stop bit
0 : Count start
1 : Count stop
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
■ Note on Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR 0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
P03/TXOUT output valid bit
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR 0 output)
Not used (return “0” when read)
Fig. 23 Structure of timer X mode register
b7
b0
Timer count source set register
(TCSS : address 002E16, initial value: 0016)
Timer X count source selection bits
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN) (Note 1)
1 1 : Not available
Timer Y count source selection bits
b3 b2
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : On-chip oscillator output (Note 2)
1 1 : Not available
Timer Z count source selection bits
b5 b4
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : Timer Y underflow
1 1 : Not available
Fix this bit to “0”.
Not used (return “0” when read)
Notes 1: f(XIN) can be used as timer X count source when using
a ceramic resonator or on-chip oscillator.
Do not use it at RC oscillation.
2: System operates using an on-chip oscillator as a count
Source by setting the on-chip oscillator to oscillation enabled
by bit 3 of CPUM.
Fig. 24 Timer count source set register
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7540 Group
●Timer Y
Timer Y is an 8-bit timer and counts the prescaler Y output.
When Timer Y underflows, the timer Y interrupt request bit is set to
“1”.
Prescaler Y is an 8-bit prescaler and counts the signal selected by
the timer Y count source selection bit.
Prescaler Y has the prescaler Y latch to retain the reload value.
Timer Y has the timer Y primary latch and timer Y secondary latch
to retain the reload value.
The value of prescaler Y latch is set to Prescaler Y when
Prescaler Y underflows.The value of timer Y primary latch or timer
Y secondary latch are set to Timer Y when Timer Y underflows.
As for the value to transfer to Timer Y, either of timer Y primary or
timer Y secondary is selected depending on the timer Y operating
mode.
When writing to Prescaler Y (PREY), timer Y primary (TYP) or
timer Y secondary (TYS) is executed, writing to “latch only” or
“latch and prescaler (timer)” can be selected by the setting value
of the timer Y write control bit. Be sure to set the timer Y write control bit because there are some notes according to the operating
mode.
When reading from Prescaler Y (PREY) is executed, the count
value of Prescaler Y is read out. When reading from timer Y primary (TYP) is executed, the count value of Timer Y is read out.
The count value of Timer Y can be read out by reading from the
timer Y primary (TYP) even when the value of timer Y primary
latch or timer Y secondary latch is counted. When reading the
timer Y secondary (TYS) is executed, the undefined value is read
out.
FUNCTIONAL DESCRIPTION
(2) Programmable waveform generation mode
In the programmable waveform generation mode, timer counts the
setting value of timer Y primary and the setting value of timer Y
secondary alternately, the waveform inverted each time Timer Y
underflows is output from TYOUT pin.
When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”. Also, set the port P01 direction
registers to output mode.
The active edge of output waveform is set by the timer Y output
level latch (b5) of the timer Y, Z waveform output control register
(PUM). When “0” is set to b5 of PUM, “H” interval by the setting
value of TYP or “L” interval by the setting value of TYS is output
alternately. When “1” is set to b5 of PUM, “L” interval by the setting
value of TYP or “H” interval by the setting value of TYS is output
alternately.
Also, in this mode, the primary interval and the secondary interval
of the output waveform can be extended respectively for 0.5 cycle
of timer count source clock by setting the timer Y primary waveform extension control bit (b2) and the timer Y secondary
waveform extension control bit (b3) of PUM to “1”. As a result, the
waveforms of more accurate resolution can be output.
When b2 and b3 of PUM are used, the frequency and duty of the
output waveform are as follows;
Waveform frequency:
FYOUT=
2✕TMYCL
2✕(TYP+1)+2✕(TYS+1)+(EXPYP+EXPYS)
Duty:
2✕(TYP+1)+EXPYP
(2✕(TYP+1)+EXPYP)+(2✕(TYS+1)+EXPYS)
Timer Y can be selected in one of 2 operating modes by setting
the timer Y operating mode bits of the timer Y, Z mode register.
DYOUT=
(1) Timer mode
Prescaler Y counts the count source selected by the timer Y count
source selection bits. Each time the count clock is input, the contents of Prescaler Y is decremented by 1. When the contents of
Prescaler Y reach “0016”, an underflow occurs at the next count
clock, and the prescaler Y latch is reloaded into Prescaler Y. The
division ratio of Prescaler Y is 1/(n+1) provided that the value of
Prescaler Y is n.
The contents of Timer Y is decremented by 1 each time the underflow signal of Prescaler Y is input. When the contents of Timer Y
reach “0016”, an underflow occurs at the next count clock, and the
timer Y primary latch is reloaded into Timer Y and count continues.
(In the timer mode, the contents of timer Y primary latch is
counted. Timer Y secondary latch is not used in this mode.)
The division ratio of Timer Y is 1/(m+1) provided that the value of
Timer Y is m. Accordingly, the division ratio of Prescaler Y and
Timer Y is 1/((n+1)✕(m+1)) provided that the value of Prescaler Y
is n and the value of Timer Y is m.
In the timer mode, writing to “latch only” or “latches and Prescaler
Y and timer Y primary” can be selected by the setting value of the
timer Y write control bit.
TMYCL: Timer Y count source (frequency)
TYP: Timer Y primary (8bit)
TYS: Timer Y secondary (8bit)
EXPYP: Timer Y primary waveform extension control bit (1bit)
EXPYS: Timer Y secondary waveform extension control bit (1bit)
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REJ09B0018-0200Z
In the programmable waveform generation mode, when values of
the TYP, TYS, EXPYP and EXPYS are changed, the output waveform is changed at the beginning (timer Y primary waveform
interval) of waveform period.
When the count values are changed, set values to the TYS,
EXPYP and EXPYS first. After then, set the value to TYP. The values are set all at once at the beginning of the next waveform
period when the value is set to TYP. (When writing at timer stop is
executed, writing to TYP at last is required.)
Notes on programmable waveform generation mode is described
below;
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7540 Group
FUNCTIONAL DESCRIPTION
■ Notes on programmable generation waveform mode
• Count set value
In the programmable waveform generation mode, values of TYS,
EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when
changing TYP is not required, write the same value again.
• Write timing to TYP
In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by
software in order not to execute the writing to TYP and the timing
of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Y waveform extension control bit can be used only when “0016” is set to Prescaler Y.
When the value other than “0016” is set to Prescaler Y, be sure to
set “0” to EXPYP and EXPYS.
• Timer Y write mode
When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”.
Timer Y can stop counting by setting “1” to the timer Y count stop
bit in any mode.
Also, when Timer Y underflows, the timer Y interrupt request bit is
set to “1”.
Timer Y reloads the value of latch when counting is stopped by the
timer Y count stop bit. (When timer is read out while timer is
stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
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7540 Group
●Timer Z
Timer Z is an 8-bit timer and counts the prescaler Z output.
When Timer Z underflows, the timer Z interrupt request bit is set to
“1”.
Prescaler Z is an 8-bit prescaler and counts the signal selected by
the timer Z count source selection bit.
Prescaler Z has the prescaler Z latch to retain the reload value.
Timer Z has the timer Z primary latch and timer Z secondary latch
to retain the reload value.
The value of prescaler Z latch is set to Prescaler Z when Prescaler
Z underflows.The value of timer Z primary latch or timer Z secondary latch are set to Timer Z when Timer Z underflows.
As for the value to transfer to Timer Z, either of timer Z primary or
timer Z secondary is selected depending on the timer Z operating
mode.
When writing to Prescaler Z (PREZ), timer Z primary (TZP) or
timer Z secondary (TZS) is executed, writing to “latch only” or
“latches and Prescaler Z and Timer Z” can be selected by the setting value of the timer Z write control bit. Be sure to set the write
control bit because there are some notes according to the operating mode.
When reading from Prescaler Z (PREZ) is executed, the count
value of Prescaler Z is read out. When reading from timer Z primary (TZP) is executed, the count value of Timer Z is read out.
The count value of Timer Z can be read out by reading from the
timer Z primary (TZP) even when the value of timer Z primary
latch or timer Z secondary latch is counted. When reading the
timer Z secondary (TZS) is executed, the undefined value is read
out.
FUNCTIONAL DESCRIPTION
(2) Programmable waveform generation mode
In the programmable waveform generation mode, timer counts the
setting value of timer Z primary and the setting value of timer Z
secondary alternately, the waveform inverted each time Timer Z
underflows is output from TZOUT pin.
When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P02 direction
registers to output mode.
The active edge of output waveform is set by the timer Z output
level latch (b4) of the timer Y, Z waveform output control register
(PUM). When “0” is set to b4 of PUM, “H” interval by the setting
value of TZP or “L” interval by the setting value of TZS is output alternately. When “1” is set to b4 of PUM, “L” interval by the setting
value of TZP or “H” interval by the setting value of TZS is output
alternately.
Also, in this mode, the primary interval and the secondary interval
of the output waveform can be extended respectively for 0.5 cycle
of timer count source clock by setting the timer Z primary waveform extension control bit (b0) and the timer Z secondary
waveform extension control bit (b1) of PUM to “1”. As a result, the
waveforms of more accurate resolution can be output.
When b0 and b1 of PUM are used, the frequency and duty of the
output waveform are as follows;
Waveform frequency:
FZOUT=
2✕TMZCL
2✕(TZP+1)+2✕(TZS+1)+(EXPZP+EXPZS)
Duty:
2✕(TZP+1)+EXPZP
(2✕(TZP+1)+EXPZP)+(2✕(TZS+1)+EXPZS
Timer Z can be selected in one of 4 operating modes by setting
the timer Z operating mode bits of the timer Y, Z mode register.
DZOUT=
(1) Timer mode
Prescaler Z counts the count source selected by the timer Z count
source selection bits. Each time the count clock is input, the contents of Prescaler Z is decremented by 1. When the contents of
Prescaler Z reach “0016”, an underflow occurs at the next count
clock, and the prescaler Z latch is reloaded into Prescaler Z. The
division ratio of Prescaler Z is 1/(n+1) provided that the value of
Prescaler Z is n.
The contents of Timer Z is decremented by 1 each time the underflow signal of Prescaler Z is input. When the contents of Timer Z
reach “0016”, an underflow occurs at the next count clock, and the
timer Z primary latch is reloaded into Timer Z and count continues.
(In the timer mode, the contents of timer Z primary latch is
counted. Timer Z secondary latch is not used in this mode.)
The division ratio of Timer Z is 1/(m+1) provided that the value of
Timer Z is m. Accordingly, the division ratio of Prescaler Z and
Timer Z is 1/((n+1)✕(m+1)) provided that the value of Prescaler Z
is n and the value of Timer Z is m.
In the timer mode, writing to “latch only” or “latches and Prescaler
Z and timer Z primary” can be selected by the setting value of the
timer Z write control bit.
TMZCL: Timer Z count source (frequency)
TZP: Timer Z primary (8bit)
TZS: Timer Z secondary (8bit)
EXPZP: Timer Z primary waveform extension control bit (1bit)
EXPZS: Timer Z secondary waveform extension control bit (1bit)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
In the programmable waveform generation mode, when values of
the TZP, TZS, EXPZP and EXPZS are changed, the output waveform is changed at the beginning (timer Z primary waveform
interval) of waveform period.
When the count values are changed, set values to the TZS,
EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once at the beginning of the next waveform
period when the value is set to TZP. (When writing at timer stop is
executed, writing to TZP at last is required.)
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Notes on the programmable waveform generation mode are described below;
■ Notes on programmable waveform generation mode
• Count set value
In the programmable waveform generation mode, values of TZS,
EXPZP, and EXPZS are valid by writing to TZP because the setting to them is executed all at once by writing to TZP. Even when
changing TZP is not required, write the same value again.
• Write timing to TZP
In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by
software in order not to execute the writing to TZP and the timing
of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is
selected as the count source, the waveform extension function
cannot be used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”.
(3) Programmable one-shot generation mode
In the programmable one-shot generation mode, the one-shot
pulse by the setting value of timer Z primary can be output from
TZOUT pin by software or external trigger. When using this mode,
be sure to set “1” to the timer Z write control bit to select “write to
latch only”. Also, set the port P0 2 direction registers to output
mode. In this mode, TZS is not used.
The active edge of output waveform is set by the timer Z output
level latch (b5) of the timer Y, Z waveform output control register
(PUM). When “0” is set to b5 of PUM, “H” pulse during the interval
of the TZP setting value is output. When “1” is set to b5 of PUM,
“L” pulse during the interval of the TZP setting value is output.
Also, in this mode, the interval of the one-shot pulse output can be
extended for 0.5 cycle of timer count source clock by setting the
timer Z primary waveform extension control bit (b2) of PUM to “1”.
As a result, the waveforms of more accurate resolution can be
output.
In the programmable one-shot generation mode, the trigger by
software or the external INT0 pin can be accepted by writing “0” to
the timer Z count stop bit after the count value is set. (At the time
when “0” is written to the timer Z count stop bit, Timer Z stops.)
By writing “1” to the timer Z one-shot start bit, or by inputting the
valid trigger to the INT0 pin after the trigger to the INT 0 pin becomes valid by writing “1” to the INT0 pin one-shot trigger control
bit, Timer Z starts counting, at the same time, the output of TZOUT
pin is inverted. When Timer Z underflows, the output of TZOUT pin
is inverted again and Timer Z stops. When also the trigger of INT0
pin is accepted, the contents of the one-shot start bit is changed to
“1” by hardware.
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REJ09B0018-0200Z
FUNCTIONAL DESCRIPTION
The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin one-shot trigger edge selection bit.
During the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by writing “0” to the timer Z one-shot
start bit.
In the programmable one-shot generation mode, when the count
values are changed, set value to the EXPZP first. After then, set
the value to TZP. The values are set all at once at the beginning of
the next one-shot pulse when the value is set to TZP. (When writing at timer stop is executed, writing to TZP at last is required.)
Notes on the programmable one-shot generation mode are described below;
■ Notes on programmable one-shot generation mode
• Count set value
In the programmable one-shot generation mode, the value of
EXPZP becomes valid by writing to TZP. Even when changing
TZP is not required, write the same value again.
• Write timing to TZP
In the programmable one-shot generation mode, when the setting
value is changed while the waveform is output, set by software in
order not to execute the writing to TZP and the timing of timer underflow simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP. Also, when the timer Y underflow is selected as
the count source, the waveform extension function cannot be
used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”.
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7540 Group
(4) Programmable wait one-shot generation mode
In the programmable wait one-shot generation mode, the one-shot
pulse by the setting value of timer Z secondary can be output from
TZOUT pin by software or external trigger to INT0 pin after the wait
by the setting value of the timer Z primary. When using this mode,
be sure to set “1” to the timer Z write control bit to select “write to
latch only”. Also, set the port P0 2 direction registers to output
mode.
The active edge of output waveform is set by the timer Z output
level latch (b5) of the timer Y, Z waveform output control register
(PUM). When “0” is set to b5 of PUM, after the wait during the interval of the TZP setting value, “H” pulse during the interval of the
TZS setting value is output. When “1” is set to b5 of PUM, after the
wait during the interval of the TZP setting value, “L” pulse during
the interval of the TZS setting value is output.
Also, in this mode, the intervals of the wait and the one-shot pulse
output can be extended for 0.5 cycle of timer count source clock
by setting EXPZP and EXPZS of PUM to “1”. As a result, the
waveforms of more accurate resolution can be output.
In the programmable one-shot generation mode, the trigger by
software or the external INT0 pin can be accepted by writing “0” to
the timer Z count stop bit after the count value is set. (At the time
when “0” is written to the timer Z count stop bit, Timer Z stops.)
By writing “1” to the timer Z one-shot start bit, or by inputting the
valid trigger to the INT0 pin after the trigger to the INT 0 pin becomes valid by writing “1” to the INT0 pin one-shot trigger control
bit, Timer Z starts counting.
While Timer Z counts the TZP, the initial value of the TZOUT pin
output is retained. When Timer Z underflows, the value of TZS is
reloaded, at the same time, the output of TZOUT pin is inverted.
When Timer Z underflows, the output of TZ OUT pin is inverted
again and Timer Z stops. When also the trigger of INT0 pin is accepted, the contents of the one-shot start bit is changed to “1” by
hardware.
The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin one-shot trigger edge selection bit.
During the wait interval and the one-shot pulse output interval, the
one-shot pulse output can be stopped forcibly by writing “0” to the
timer Z one-shot start bit.
In the programmable wait one-shot generation mode, when the
count values are changed, set values to the TZS, EXPZP and
EXPZS first. After then, set the value to TZP. The values are set all
at once at the beginning of the next wait interval when the value is
set to TZP. (When writing at timer stop is executed, writing to TZP
at last is required.)
FUNCTIONAL DESCRIPTION
■ Notes on programmable wait one-shot generation mode
• Count set value
In the programmable wait one-shot generation mode, values of
TZS, EXPZP and EXPZS are valid by writing to TZP. Even when
changing TZP is not required, write the same value again.
• Write timing to TZP
In the programmable wait one-shot generation mode, when the
setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of
timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is
selected as the count source, the waveform extension function
cannot be used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”.
Timer Z can stop counting by setting “1” to the timer Z count stop
bit in any mode.
Also, when Timer Z underflows, the timer Z interrupt request bit is
set to “1”.
Timer Z reloads the value of latch when counting is stopped by the
timer Z count stop bit. (When timer is read out while timer is
stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
Notes on the programmable wait one-shot generation mode are
described below;
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b7
FUNCTIONAL DESCRIPTION
b0
Timer Y, Z mode register
(TYZM : address 0020 16, initial value: 00 16)
Timer Y operating mode bit
0 : Timer mode
1 : Programmable waveform generation mode
Not used (return “0” when read)
Timer Y write control bit
0 : Write to latch and timer simultaneously
1 : Write to only latch
Timer Y count stop bit
0 : Count start
1 : Count stop
Timer Z operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation mode
Timer Z write control bit
0 : Write to latch and timer simultaneously
1 : Write to only latch
Timer Z count stop bit
0 : Count start
1 : Count stop
Fig. 25 Structure of timer Y, Z mode register
b7
b0
Timer Y, Z waveform output control register
(PUM : address 0024 16, initial value: 00 16)
Timer Y primary waveform extension control bit
0 : Waveform not extended
1 : Waveform extended
Timer Y secondary waveform extension control bit
0 : Waveform not extended
1 : Waveform extended
Timer Z primary waveform extension control bit
0 : Waveform not extended
1 : Waveform extended
Timer Z secondary waveform extension control bit
0 : Waveform not extended
1 : Waveform extended
Timer Y output level latch
0 : “L” output
1 : “H” output
Timer Z output level latch
0 : “L” output
1 : “H” output
INT0 pin one-shot trigger control bit
0 : INT 0 pin one-shot trigger invalid
1 : INT 0 pin one-shot trigger valid
INT0 pin one-shot trigger active edge selection bit
0 : Falling edge trigger
1 : Rising edge trigger
Fig. 26 Structure of timer Y, Z waveform output control register
b7
b0
One-shot start register
(ONS : address 002A 16, initial value: 00 16)
Timer Z one-shot start bit
0 : One-shot stop
1 : One-shot start
Not used (return “0” when read)
Fig. 27 Structure of one-shot start register
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FUNCTIONAL DESCRIPTION
Data bus
Timer 1 latch (8)
Prescaler 1 latch (8)
Prescaler 1 (8)
f(XIN)/16
Timer 1 (8)
Timer 1 interrupt
request bit
Pulse width HL
continuously
measurement mode
Rising edge detected
Period measurement mode
Falling edge detected
P00/CNTR1
CNTR1 active
edge switch bit
Data bus
Timer A (low-order) latch (8)
Timer A (low-order) (8)
f(XIN)/16
Timer A operation mode bit
Timer A (high-order) latch (8)
Timer A (high-order) (8)
Timer A interrupt
request bit
Timer A count
stop bit
Fig. 28 Block diagram of timer 1 and timer A
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FUNCTIONAL DESCRIPTION
Data bus
f(XIN)/16
f(XIN)/2
f(XIN)
Timer X count
source selection bits
CNTR0 active
edge switch bit
“0”
P14/CNTR0
Prescaler X latch (8)
Timer X latch (8)
Prescaler X (8)
Timer X (8)
Pulse width
Timer mode
measurement Pulse output
mode
mode
Event
counter
mode
Timer X count stop bit
CNTR0
interrupt
request bit
“1”
CNTR0 active “1”
edge switch bit
Q
Toggle flip-flop T
Q
R
“0”
Port P14
latch
Port P14 direction
register
Timer X
interrupt
request bit
Writing to timer X latch
Pulse output mode
Pulse output mode
P03/
TXOUT
Port P03 latch
Data bus
P03/TXOUT output valid
Port P03
direction
register
Prescaler Y latch (8)
Timer Y primary latch (8) Timer Y secondary latch (8)
Timer Y count
source selection bits
f(XIN)/16
Prescaler Y (8)
Timer Y (8)
f(XIN)/2
Timer Y count
stop bit
On-chip oscillator clock RING
(on-chip oscillator output in
Fig. 51, 52)
Timer Y
interrupt
request bit
Timer Y primary waveform
extension control bit
Q
Toggle flip-flop T
Waveform extension function
Q
P01/TYOUT
Port P01 latch
Port P01
direction
register
Timer Y output level latch
Timer Y secondary
waveform extension
control bit
Programmable waveform
gengeration mode
Data bus
Prescaler Z latch (8)
Timer Z count
source selection bits
f(XIN)/16
f(XIN)/2
Timer Z primary latch (8)
Prescaler Z (8)
Timer Z secondary latch (8)
Timer Z (8)
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Timer Z count
stop bit
Timer Z one-shot start bit
INT0 pin trigger active edge
selection bit
P37/INT0
Timer Z
interrupt
request bit
INT0
interrupt
request bit
One-shot pulse
trigger input
Timer Z primary waveform
extenstion control bit
Q
Toggle flip flop T
Waveform extension function
Q
P02/TZOUT
Port P02 latch
Port P02 direction
register
Timer Z output
level latch
Timer Z secondary waveform
extenstion control bit
Programmable waveform generation mode
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Fig. 29 Block diagram of timer X, timer Y and timer Z
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FUNCTIONAL DESCRIPTION
Serial I/O
●Serial I/O1
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6) to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Data bus
Serial I/O1 control register
Address 0018 16
Receive buffer register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive shift register
P10/RXD1
Address 001A 16
Shift clock
Clock control circuit
P12/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
XIN
Baud rate generator
Address 001C16
1/4
P13/SRDY1
F/F
1/4
Clock control circuit
Falling-edge detector
Shift clock
P11/TXD1
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Transmit buffer register
Address 0018 16
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 0019 16
Data bus
Fig. 30 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 0018 16)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 31 Operation of clock synchronous serial I/O1 function
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FUNCTIONAL DESCRIPTION
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
Data bus
Address 0018 16
P10/RXD1
Serial I/O1 control register Address 001A 16
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
OE
Character length selection bit
ST detector
7 bits
Receive shift register
1/16
8 bits
PE FE
UART control register
Address 001B 16
SP detector
Clock control circuit
Serial I/O1 synchronous clock selection bit
P12/SCLK1
XIN
BRG count source selection bit Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C 16
1/4
ST/SP/PA generator
Transmit shift completion flag (TSC)
1/16
P11/TXD1
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit shift register
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Serial I/O1 status register Address 001916
Data bus
Fig. 32 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
Serial output TXD
TBE=0
TSC=1✽
TBE=1
ST
D0
D1
SP
ST
D0
Receive buffer read
signal
SP
D1
✽
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Generated at 2nd bit in 2-stop-bit mode
RBF=0
RBF=1
Serial input RXD
ST
D0
D1
SP
RBF=1
ST
D0
D1
SP
Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 33 Operation of UART serial I/O1 function
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[Transmit buffer register/receive buffer register (TB/RB)]
001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O1 status register (SIO1STS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O1 control register (SIO1CON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART control register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TXD1 pin.
FUNCTIONAL DESCRIPTION
■ Notes on serial I/O
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled.
The functions of P12 and P1 3 are switched with the setting values
of a serial I/O1 mode selection bit and a serial I/O1 synchronous
clock selection bit as follows.
(1) Serial I/O1 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
(2) Serial I/O1 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
[Baud rate generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
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b7
FUNCTIONAL DESCRIPTION
b0
Serial I/O1 status register
(SIO1STS : address 0019 16, initial value: 00 16)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
b7
b0
UART control register
(UARTCON : address 001B 16, initial value: E0 16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
b7
b0
Serial I/O1 control register
(SIO1CON : address 001A 16, initial value: 00 16)
BRG count source selection bit (CSS)
0: f(X IN)
1: f(X IN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P1 3 pin operates as ordinary I/O pin
1: P1 3 pin operates as S RDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P1 0 to P1 3 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P1 0 to P1 3operate as serial I/O pins)
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P11/TXD1 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 34 Structure of serial I/O1-related registers
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FUNCTIONAL DESCRIPTION
●Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer
is started by a write signal to the serial I/O2 register.
Note: Serial I/O2 can be used in the following cases;
(1) Serial I/O1 is not used,
(2) Serial I/O1 is used as UART and BRG output divided by 16 is
selected as the synchronized clock.
b7
b0
Serial I/O2 control register
(SIO2CON: address 003016, initila value: 0016)
Internal synchronous clock selection bits
000 : f(XIN)/8
001 : f(XIN)/16
010 : f(XIN)/32
011 : f(XIN)/64
110 : f(XIN)/128
111 : f(XIN)/256
SDATA2 pin selection bit (Note)
0 : I/O port / SDATA2 input
1 : SDATA2 output
Not used
(returns “0” when read)
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various serial I/O functions.
• Set “0” to bit 3 to receive.
• At reception, clear bit 7 to “0” by writing a dummy data to the serial I/O2 register after completion of shift.
Transfer direction selection bit
0 : LSB first
1 : MSB first
SCLK2 pin selection bit
0 : External clock (SCLK2 is an input)
1 : Internal clock (SCLK2 is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note : When using it as a SDATA input, set the port P13
direction register to “0”.
Fig. 35 Structure of serial I/O2 control registers
Data bus
1/8
1/16
1/32
Divider
XIN
1/64
1/128
1/256
SCLK2 pin
selection bit
“1”
SCLK
“0”
Internal synchronous
clock selection bits
SCLK2 pin selection bit
“0”
P12/SCLK2
P12 latch
Serial I/O counter 2 (3)
“1”
Serial I/O2
interrupt request
SDATA2 pin selection bit
“0”
P13/SDATA2
P13 latch
“1”
SDATA2 pin selection bit
Serial I/O shift register 2 (8)
Fig. 36 Block diagram of serial I/O2
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FUNCTIONAL DESCRIPTION
Serial I/O2 operation
By writing to the serial I/O2 register (address 003116) the serial I/
O2 counter is set to “7”.
After writing, the SDATA2 pin outputs data every time the transfer
clock shifts from “H” to “L”. And, as the transfer clock shifts from
“L” to “H”, the SDATA2 pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source,
the following operations execute as the transfer clock counts up to
8.
• Serial I/O2 counter is cleared to “0”.
• Transfer clock stops at an “H” level.
• Interrupt request bit is set.
• Shift completion flag is set.
Also, the SDATA2 pin is in a high impedance state after the data
transfer is completed (refer to Fig.37).
When the external clock is selected as the transfer clock source,
the interrupt request bit is set as the transfer clock counts up to 8,
but external control of the clock is required since it does not stop.
Notice that the SDATA2 pin is not in a high impedance state on the
completion of data transfer.
Also, after the receive operation is completed, the transmit/receive
shift completion flag is cleared by reading the serial I/O2 register.
At transmit, the transmit/receive shift completion flag is cleared
and the transmit operation is started by writing to serial I/O2 register.
Synchronous clock
Transfer clock
Serial I/O2 register
write signal
(Note)
SDATA2 at serial I/O2
output transmit
D0
D1
D2
D3
D4
D5
D6
D7
SDATA2 at serial I/O2
input receive
Serial I/O2 interrupt request bit set
Transmit/receive shift completion flag set
Note : When the internal clock is selected as the transfer and the direction register of P1 3/SDATA2 pin is set to the input mode,
the SDATA2 pin is in a high impedance state after the data transfer is completed.
Fig. 37 Serial I/O2 timing (LSB first)
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
A/D Converter
The functional blocks of the A/D converter are described below.
[A/D conversion register] AD
The A/D conversion register is a read-only register that stores the
result of A/D conversion. Do not read out this register during an A/
D conversion.
(2) When VREF voltage is lower than [3.0 V], the accuracy at the
low temperature may become extremely low compared with
that at room temperature When the system would be used at
low temperature, the use at VREF =3.0 V or more is recommended.
b7
b0
A/D control register
(ADCON : address 003416, initial value: 1016)
[A/D control register] ADCON
The A/D control register controls the A/D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion completion bit. The value of this bit remains at “0” during A/D conversion,
and changes to “1” at completion of A/D conversion.
A/D conversion is started by setting this bit to “0”.
Analog input pin selection bits
000 : P20/AN0
001 : P21/AN1
010 : P22/AN2
011 : P23/AN3
100 : P24/AN4
101 : P25/AN5
110 : P26/AN6 (Note)
111 : P27/AN7 (Note)
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 1024, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P27 /AN7 to P2 0/AN0,
and inputs the voltage to the comparator.
Not used (returns “0” when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
Not used (returns “0” when read)
Note: These can be used only for 36 pin version.
Fig. 38 Structure of A/D control register
[Comparator and control circuit]
The comparator and control circuit compares an analog input voltage
with the comparison voltage and stores its result into the A/D conversion register. When A/D conversion is completed, the control circuit
sets the AD conversion completion bit and the AD interrupt request bit
to “1”. Because the comparator is constructed linked to a capacitor,
set f(XIN) to 500 kHz or more during A/D conversion.
Read 8-bit (Read only address 003516)
b7
(Address 003516)
b9 b8
b7
b0
b6
b5
b4
Read 10-bit (read in order address 003616, 003516)
b7
b9
b7
(Address 003516)
b7 b6
b2
b0
(Address 003616)
■ Note on A/D converter
As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when V REF voltage is set up lower than Vcc
voltage, accuracy may become low rather than the case where
VREF voltage and Vcc voltage are set up to the same value.
b3
b8
b0
b5
b4
b3
b2
b1
b0
Note: High-order 6-bit of address 003616 returns “0” when read.
Fig. 39 Structure of A/D conversion register
Data bus
b7
b0
A/D control register
(Address 003416)
3
A/D interrupt request
A/D control circuit
Channel selector
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
Comparator
A/D conversion register (high-order)
(Address 003616)
A/D conversion register (low-order)
(Address 003516)
10
Resistor ladder
VREF
VSS
Fig. 40 Block diagram of A/D converter
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control register (address 003916) is not set after reset. Writing an optional
value to the watchdog timer control register (address 0039 16)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accordingly, it is programmed that the watchdog timer control register
(address 003916) can be set before an underflow occurs.
When the watchdog timer control register (address 0039 16) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction disable bit and watchdog timer H count source selection bit are read.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow signal. The detection time is 131.072 ms at f(XIN)=8 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 512 µs at f(XIN)=8 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can
be disabled by bit 6 of the watchdog timer control register (address 003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an internal reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (address 0039 16), the watchdog timer H is set to “FF 16 ” and the
watchdog timer L is set to “FF16”.
Data bus
Write “FF16” to the
watchdog timer
control register
Watchdog timer L (8)
1/16
XIN
“0”
“1”
Watchdog timer H (8)
Write "FF16" to the
watchdog timer
control register
Watchdog timer H count
source selection bit
STP Instruction disable bit
STP Instruction
Reset
circuit
RESET
Internal reset
Fig. 41 Block diagram of watchdog timer
b7
b0
Watchdog timer control register
(WDTCON: address 0039 16, initial value: 3F 16)
Watchdog timer H (read only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(XIN)/16
Fig. 42 Structure of watchdog timer control register
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Reset Circuit
Poweron
The microcomputer is put into a reset status by holding the RESET pin at the “L” level for 2 µs or more when the power source
voltage is 2.2 to 5.5 V and XIN is in stable oscillation.
After that, this reset status is released by returning the RESET pin
to the “H” level. The program starts from the address having the
contents of address FFFD16 as high-order address and the contents of address FFFC16 as low-order address.
In the case of f(φ) ≤ 6 MHz, the reset input voltage must be 0.9 V
or less when the power source voltage passes 4.5 V.
In the case of f(φ) ≤ 4 MHz, the reset input voltage must be 0.8 V
or less when the power source voltage passes 4.0 V.
In the case of f(φ) ≤ 2 MHz, the reset input voltage must be 0.48 V
or less when the power source voltage passes 2.4 V.
In the case of f(φ) ≤ 1 MHz, the reset input voltage must be 0.44 V
or less when the power source voltage passes 2.2 V.
RESET
VCC
Power source
voltage
0V
Reset input
voltage
0V
(Note)
0.2 VCC
Note : Reset release voltage Vcc = 2.2 V
RESET
VCC
Power source
voltage
detection circuit
Fig. 43 Example of reset circuit
Clock from on-chip
oscillator RING
φ
RESET
RESETOUT
SYNC
?
Address
?
?
Data
8-13 clock cycles
?
?
?
?
FFFC
?
?
?
FFFD
ADL
ADH,ADL
ADH
Reset address from the
vector table
Notes 1 : An on-chip oscillator applies about RING•2 MHz, φ•250 kHz frequency clock at
average of Vcc = 5 V.
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET.
Fig. 44 Timing diagram at reset
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Address
Register contents
0016
(1) Port P0 direction register
000116
(2) Port P1 direction register
000316
(3) Port P2 direction register
000516
0016
(4) Port P3 direction register
000716
0016
(5) Pull-up control register
001616
0016
(6) Port P1P3 control register
001716
0016
(7) Serial I/O1 status register
001916
X
1
X
0
X
0
0
0
0
0
001A16
(9) UART control register
001B16
(10) Timer A mode register
001D16
0016
(11) Timer A (low-order)
001E16
FF16
(12) Timer A (high-order)
001F16
FF16
(13) Timer Y, Z mode register
002016
0016
(14) Prescaler Y
002116
FF16
(15) Timer Y secondary
002216
FF16
(16) Timer Y primary
002316
FF16
(17) Timer Y, Z waveform output control register
002416
0016
(18) Prescaler Z
002516
FF16
(19) Timer Z secondary
002616
FF16
(20) Timer Z primary
002716
FF16
(21) Prescaler 1
002816
FF16
(22) Timer 1
002916
0116
(23) One-shot start register
002A16
0016
(24) Timer X mode register
002B16
0016
(25) Prescaler X
002C16
FF16
(26) Timer X
002D16
FF16
(27) Timer count source set register
002E16
0016
(28) Serial I/O2 control register
003016
0016
(29) Serial I/O2 register
003116
0016
(30) A/D control register
003416
1016
(31) MISRG
003816
0016
(32) Watchdog timer control register
003916
(33) Interrupt edge selection register
003A16
(34) CPU mode register
003B16
1
0
1
0
1
1
0
1
0
1
1
0
0
0
0
(35) Interrupt request register 1
003C16
(36) Interrupt request register 2
003D16
0016
(37) Interrupt control register 1
003E16
0016
(38) Interrupt control register 2
003F16
0016
(40) Program counter
0
0
0
0
0
0
0
1
1
1
0
0
0
1
X
X
0016
0016
(PS)
0
0016
(8) Serial I/O1 control register
(39) Processor status register
0
X
X
X
X
X
(PCH)
Contents of address FFFD16
(PCL)
Contents of address FFFC16
Note X : Undefined
Fig. 45 Internal status of microcomputer at reset
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed
by connecting a resistor and a capacitor.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values.
Note: Externally connect a
M37540
XIN
XOUT
Rd
(1) On-chip oscillator operation
When the MCU operates by the on-chip oscillator for the main
clock, connect XIN pin to VSS and leave XOUT pin open.
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
(2) Ceramic resonator
When the ceramic resonator is used for the main clock, connect
the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT.
(3) RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin and XOUT pin to the external circuit of resistor R and the
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a microcomputer.
So, set the constants within the range of the frequency limits.
COUT
CI N
damping resistor Rd depending on the
oscillation frequency.
(A feedback resistor is
built-in.)
Use the resonator
manufacturer’s recommended value because
constants such as capacitance depend on the
resonator.
Fig. 46 External circuit of ceramic resonator
Note: Connect the external
M37540
XI N
XOUT
circuit of resistor R
and the capacitor C at
the shortest distance.
The frequency is affected by a capacitor,
a resistor and a microR computer.
So, set the constants
C within the range of the
frequency limits.
Fig. 47 External circuit of RC oscillation
(4) External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
Select “ceramic resonance” by setting “0” to the Oscillation mode
selection bit of CPU mode register (address 003B16).
M37540
XIN
XOUT
External oscillation
circuit
Open
VCC
VSS
Fig. 48 External clock input circuit
M37540
XI N
Note: The clock frequency of the
on-chip oscillator depends
on the supply voltage and
the operation temperature
range.
Be careful that variable freXOUT
quencies and obtain the
sufficient margin.
Open
Fig. 49 Processing of XIN and XOUT pins at on-chip oscillator
operation
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HARDWARE
7540 Group
(1) Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at an
“H” level and the XIN oscillator stops. At this time, timer 1 is set to
“0116” and prescaler 1 is set to “FF16” when the oscillation stabilization time set bit after release of the STP instruction is “0”. On the
other hand, timer 1 and prescaler 1 are not set when the above bit is
“1”. Accordingly, set the wait time fit for the oscillation stabilization
time of the oscillator to be used. f(XIN)/16 is forcibly connected to the
input of prescaler 1. When an external interrupt is accepted, oscillation is restarted but the internal clock φ remains at “H” until timer 1
underflows. As soon as timer 1 underflows, the internal clock φ is supplied. This is because when a ceramic oscillator is used, some time is
required until a start of oscillation. In case oscillation is restarted by
reset, no wait time is generated. So apply an “L” level to the RESET
pin while oscillation becomes stable.
Also, the STP instruction cannot be used while CPU is operating
by an on-chip oscillator.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
■ Notes on clock generating circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected
by setting bit 5 of the CPU mode register.
FUNCTIONAL DESCRIPTION
● Oscillation stop detection circuit (Note)
The oscillation stop detection circuit is used for reset occurrence
when a ceramic resonator or an oscillation circuit stops by disconnection. When internal reset occurs, reset because of oscillation
stop can be detected by setting “1” to the oscillation stop detection
status bit.
Also, when using the oscillation stop detection circuit, an on-chip
oscillator is required.
Figure 53 shows the state transition.
Note: The oscillation stop detection circuit is not included in the
emulator MCU “M37540RSS”.
b7
b0
MISRG(address 0038 16, initial value: 00 16)
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “0116” in timer1, and “FF 16”
in prescaler 1 automatically
1: Not set automatically
Ceramic or RC oscillation stop detection
function active bit
0: Detection function inactive
1: Detection function active
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Not used (return “0” when read)
Oscillation stop detection status bit
0: Oscillation stop not detected
1: Oscillation stop detected
Fig. 50 Structure of MISRG
• Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
• CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37540RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
• Clock division ratio, XIN oscillation control, on-chip oscillator control
The state transition shown in Fig. 52 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 52.
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
XI N
XOUT
Rf
Clock division ratio selection bit
Middle-, high-, low-speed mode
1/2
1/2
1/4
Prescaler 1
Timer 1
On-chip oscillator mode
Clock division
ratio selection bit
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
Double-speed mode
RING
1/8
On-chip oscillator
On-chip oscillator mode
S
Q S
WIT
instruction
STP instruction
R
Q
Q
R
S
R
Reset
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Fig. 51 Block diagram of internal clock generating circuit (for ceramic resonator)
XOUT
XI N
Clock division ratio selection bit
Middle-, high-, low-speed mode
1/2
1/2
1/4
Prescaler 1
Timer 1
On-chip
oscillator
mode
Delay
Clock division
ratio selection bit
Middle-speed mode
Timing φ
(Internal clock)
High-speed mode
Double-speed mode
RING
On-chip oscillator
1/8
On-chip oscillator mode
S
Q S
STP instruction
R
WIT
instruction
Q
R
Q
S
RESET
R
STP instruction
Reset
Interrupt disable flag l
Interrupt request
Fig. 52 Block diagram of internal clock generating circuit (for RC oscillation)
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION
Stop mode
Wait mode
Interrupt
WIT
instruction
Interrupt
STP
instruction
State 1
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator stop
CPUM3←02
CPUM3←12
Interrupt
WIT
instruction
State 2
CPUM76←102
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled CPUM76←002
State 3
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enalbed
012
112
(Note 2)
MISRG1←12
MISRG1←02
MISRG1←12
State 2’
CPUM76←102
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled CPUM76←002
MISRG1←02
State 3’
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enalbed
012
112
(Note 2)
Oscillation stop detection circuit valid
Reset released
Reset state
CPUM4←12
CPUM4←02
State 4
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation stop
On-chip oscillator enalbed
Notes on switch of clock
(1) In operation clock source = f(XIN), the following can be
selected for the CPU clock division ratio.
● f(XIN)/2 (high-speed mode)
● f(XIN)/8 (middle-speed mode)
● f(XIN) (double-speed mode, only at a ceramic oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing XIN oscillation.
(3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 → state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
• CPUM76 → 102 (State 2 → state 3)
• NOP instruction
• CPUM4 → 12 (State 3 → state 4)
Double-speed mode at on-chip oscillator: NOP ✕ 3
High-speed mode at on-chip oscillator: NOP ✕ 1
Middle-speed mode at on-chip oscillator: NOP ✕ 0
Fig. 53 State transition
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HARDWARE
7540 Group
NOTES ON PROGRAMMING/NOTES ON HARDWARE
NOTES ON PROGRAMMING
State transition
Processor Status Register
Do not stop the clock selected as the operation clock because of
setting of CM3, 4.
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular,
it is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag
D to “1”, then execute the ADC instruction or SBC instruction. In
this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction
or SBC instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected via a resistor.
Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA instruction, etc.
A/D Conversion
Do not execute the STP instruction during A/D conversion.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles mentioned in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the XIN
in double-speed mode, twice the X IN cycle in high-speed mode
and 8 times the XIN cycle in middle-speed mode.
CPU Mode Register
The oscillation mode selection bit and processor mode bits can be
rewritten only once after releasing reset. However, after rewriting it
is disable to write any value to the bit. (Emulator MCU is excluded.)
When a ceramic oscillation is selected, a double-speed mode of
the clock division ratio selection bits can be used. Do not use it
when an RC oscillation is selected.
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HARDWARE
7540 Group
NOTES ON PERIPHERAL FUNCTIONS
■ Interrupt
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit).
➂ Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
■ Timers
• When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
• When a count source of timer X, timer Y or timer Z is switched,
stop a count of timer X.
■ Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR 1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
■ Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR 0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
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REJ09B0018-0200Z
NOTES ON PERIPHERAL FUNCTIONS
■ Timer Y: Programmable Generation
Waveform Mode
• Count set value
In the programmable waveform generation mode, values of TYS,
EXPYP, and EXPYS are valid by writing to TYP because the setting to them is executed all at once by writing to TYP. Even when
changing TYP is not required, write the same value again.
• Write timing to TYP
In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by
software in order not to execute the writing to TYP and the timing
of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Y waveform extension control bit can be used only when “0016” is set to Prescaler Y.
When the value other than “0016” is set to Prescaler Y, be sure to
set “0” to EXPYP and EXPYS.
• Timer Y write mode
When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”.
Timer Y can stop counting by setting “1” to the timer Y count stop
bit in any mode.
Also, when Timer Y underflows, the timer Y interrupt request bit is
set to “1”.
Timer Y reloads the value of latch when counting is stopped by the
timer Y count stop bit. (When timer is read out while timer is
stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
■ Ti m e r Z : P r o g r a m m a b l e Wa v e f o r m
Generation Mode
• Count set value
In the programmable waveform generation mode, values of TZS,
EXPZP, and EXPZS are valid by writing to TZP because the setting to them is executed all at once by writing to TZP. Even when
changing TZP is not required, write the same value again.
• Write timing to TZP
In the programmable waveform generation mode, when the setting value is changed while the waveform is output, set by
software in order not to execute the writing to TZP and the timing
of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is
selected as the count source, the waveform extension function
cannot be used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”.
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HARDWARE
7540 Group
■ Ti m e r Z : P r o g r a m m a b l e O n e - s h o t
Generation Mode
• Count set value
In the programmable one-shot generation mode, the value of
EXPZP becomes valid by writing to TZP. Even when changing
TZP is not required, write the same value again.
• Write timing to TZP
In the programmable one-shot generation mode, when the setting
value is changed while the waveform is output, set by software in
order not to execute the writing to TZP and the timing of timer underflow simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP. Also, when the timer Y underflow is selected as
the count source, the waveform extension function cannot be
used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”.
■ Timer Z: Programmable Wait One-shot
Generation Mode
• Count set value
In the programmable wait one-shot generation mode, values of
TZS, EXPZP and EXPZS are valid by writing to TZP. Even when
changing TZP is not required, write the same value again.
• Write timing to TZP
In the programmable wait one-shot generation mode, when the
setting value is changed while the waveform is output, set by software in order not to execute the writing to TZP and the timing of
timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform extension control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is
selected as the count source, the waveform extension function
cannot be used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”.
Timer Z can stop counting by setting “1” to the timer Z count stop
bit in any mode.
Also, when Timer Z underflows, the timer Z interrupt request bit is
set to “1”.
Timer Z reloads the value of latch when counting is stopped by the
timer Z count stop bit. (When timer is read out while timer is
stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
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REJ09B0018-0200Z
NOTES ON PERIPHERAL FUNCTIONS
■ Serial I/O
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission enabled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled.
The functions of P12 and P1 3 are switched with the setting values
of a serial I/O1 mode selection bit and a serial I/O1 synchronous
clock selection bit as follows.
(1) Serial I/O1 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
(2) Serial I/O1 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
■ A/D Converter
• The comparator uses internal capacitors whose charge will be
lost if the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A/D conversion.
• As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when V REF voltage is set up lower than Vcc
voltage, accuracy may become low rather than the case where
VREF voltage and Vcc voltage are set up to the same value.
(2) When VREF voltage is lower than [3.0 V], the accuracy at the
low temperature may become extremely low compared with
that at room temperature When the system would be used at
low temperature, the use at VREF =3.0 V or more is recommended.
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HARDWARE
7540 Group
NOTES ON PERIPHERAL FUNCTIONS
■ Notes on clock generating circuit
■ Note on Power Source Voltage
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected
by setting bit 5 of the CPU mode register.
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
• Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
• CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37540RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
• Clock division ratio, XIN oscillation control, on-chip oscillator control
The state transition shown in Fig. 53 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of
CPU mode register. Be careful of notes on use in Fig. 53.
• On-chip oscillator operation
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
■ Electric Characteristic Differences Among
Mask ROM and One TIme PROM Version
MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM and One
Time PROM version MCUs due to the differences in the manufacturing processes.
When manufacturing an application system with One Time PROM
version and then switching to use of the mask ROM version, perform sufficient evaluations for the commercial samples of the
mask ROM version.
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HARDWARE
7540 Group
DATA REQUIRED FOR MASK ORDERS/DATA REQUIRED FOR ROM
PROGRAMMING ORDERS/ ROM PROGRAMMING METHOD
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask ROM production:
1.Mask ROM Order Confirmation Form *
2.Mark Specification Form *
3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
The built-in PROM of the blank One Time PROM version can be
read or programmed with a general-purpose PROM programmer
using a special programming adapter. Set the address of PROM
programmer in the user ROM area.
DATA REQUIRED FOR ROM PROGRAMMING
ORDERS
Table 7 Special programming adapter
Package
32P4B
32P6U-A
36P2R-A
Name of Programming Adapter
PCA7435SPG02
PCA7435GPG03
PCA7435FPG02
The following are necessary when ordering a One Time PROM
production:
1.ROM Programming Order Confirmation Form *
2.Mark Specification Form *
3.Data to be written to ROM, in EPROM form (three identical copies) or one floppy disk.
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in
Figure 54 is recommended to verify programming.
* For the mask ROM confirmation ROM programming order confirmation and the mark specifications,
refer to the “Renesas Technology Corp” Homepage
(http://www.renesas.com/en/rom).
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
Caution: The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 54 Programming and testing of One Time PROM version
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL
SUPPLEMENT
DESCRIPTION
Interrupt
7540 group permits interrupts on the 14 sources
for 42-pin version, 13 sources for 36-pin version
and 12 sources for 32-pin version. It is vector
interrupts with a fixed priority system. Accordingly,
when two or more interrupt requests occur during
the same sampling, the higher-priority interrupt is
accepted first. This priority is determined by
hardware, but variety of priority processing can be
performed by software, using an interrupt enable
bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt
priority, refer to “Table 8.”
Table 8 Interrupt sources, vector addresses and interrupt priority
Interrupt source Priority
Vector addresses (Note 1)
High-order
Low-order
Reset (Note 2)
Serial I/O1 receive
Serial I/O1 transmit
1
2
3
FFFD16
FFFB16
FFF916
FFFC16
FFFA16
FFF816
INT0
4
FFF716
FFF616
INT1 (Note 3)
5
FFF516
FFF416
Key-on wake-up
6
FFF316
FFF216
CNTR0
7
FFF116
FFF016
CNTR1
8
FFEF16
FFEE16
Timer X
Timer Y
Timer Z
Timer A
Serial I/O2
A/D conversion
Timer 1
Reserved area
BRK instruction
9
10
11
12
13
14
15
16
17
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Interrupt request generating conditions
Remarks
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At falling of conjunction of input logical level
for port P0 (at input)
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
At timer Y underflow
At timer Z underflow
At timer A underflow
At completion of transmit/receive shift
At completion of A/D conversion
At timer 1 underflow
Not available
At BRK instruction execution
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is
selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: It is an interrupt which can use only for 36 pin version.
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
instruction that is currently in execution.
Figure 55 shows a timing chart after an interrupt
occurs, and Figure 56 shows the time up to execution
of the interrupt processing routine.
The interrupt processing routine begins with the
machine cycle following the completion of the
φ
SYNC
RD
WR
Address bus
Data bus
PC
S, SPS
Not used
BL
S-1, SPS S-2 , SPS
PCH PCL
PS
BH
AL
AL, AH
AH
SYNC : CPU operation code fetch cycle
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
SPS : “0016” or “01 16”
Fig. 55 Timing chart after an interrupt occurs
Generation of interrupt request
Main routine
0 to 16 cycles
Start of interrupt processing
Waiting time for
post-processing
of pipeline
2 cycles
Stack push and
Vector fetch
Interrupt processing routine
5 cycles
7 to 23 cycles
(At performing 6.0 MHz, in double-speed mode,
1.75 µs to 5.75 µs)
Fig. 56 Time up to execution of the interrupt processing routine
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
A/D Converter
By repeating the above operations up to the lowestorder bit of the A/D conversion register, an analog
value converts into a digital value.
A/D conversion completes at 122 clock cycles (20.34
µs at f(XIN) = 6.0 MHz) after it is started, and the
result of the conversion is stored into the A/D
conversion register.
Concurrently with the completion of A/D conversion,
A/D conversion interrupt request occurs, so that
the AD conversion interrupt request bit is set to
“1.”
A/D conversion is started by setting AD conversion
completion bit to “0.” During A/D conversion, internal
operations are performed as follows.
1. After the start of A/D conversion, A/D conversion
register goes to “00 16.”
2. The highest-order bit of A/D conversion register
is set to “1,” and the comparison voltage Vref is
input to the comparator. Then, Vref is compared
with analog input voltage V IN.
3. As a result of comparison, when Vref < VIN, the
highest-order bit of A/D conversion register becomes “1.” When Vref > VIN, the highest-order
bit becomes “0.”
Relative formula for a reference voltage V REF of A/D converter and Vref
When n = 0
Vref = 0
Vref = VREF ✕ n
1024
n : the value of A/D converter (decimal numeral)
When n = 1 to 1023
Table 9 Change of A/D conversion register during A/D conversion
Change of A/D conversion register
Value of comparison voltage (Vref)
At start of conversion
0
0
0
0
0
0
0
0
0
0
First comparison
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Second comparison
✽
Third comparison
✽
1
1
✽
2
••
•
After completion of
tenth comparison
0
VREF
2
VREF
2
VREF
2
±
VREF
4
VREF
±
4
••
•
1
✽
2
✽
3
✽
4
✽
5
VREF
8
••
•
A result of A/D conversion
✽
±
✽
6
✽
7
✽
8
✽
9
✽
10
VREF
2
±
VREF
4
± •••
±
VREF
1024
✽1–✽10: A result of the first to tenth comparison
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HARDWARE
7540 Group
FUNCTIONAL DESCRIPTION SUPPLEMENT
Figure 56 shows A/D conversion equivalent circuit,
and Figure 57 shows A/D conversion timing chart.
VCC
(Note 1)
C2
1.5 pF(Typical)
R 1.5 kΩ(Typical)
ANi (i=0 to 7: 36-pin version
i=0 to 5: 32-pin version)
SW1
(Note 2)
C1
12 pF(Typical)
(Note 1)
VSS
VSS
Typical voltage
generation circuit
Switch tree,
ladder resistor
Notes 1: This is a parasitic diode.
2: Only the selected analog input pin is turned on.
Chopper Amp.
A/D control circuit
VSS
VREF
Fig. 57 A/D conversion equivalent circuit
XIN
Write signal for A/D control register
122 XIN cycles
AD conversion completion bit
Sampling clock
Fig. 58 A/D conversion timing chart
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1-57
CHAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
I/O port
Timer A
Timer 1
Timer X
Timer Y and timer Z
Serial I/O1
Serial I/O2
A/D converter
Reset
APPLICATION
7540 Group
2.1 I/O port
2.1 I/O port
This paragraph explains the registers setting method and the notes relevant to the I/O ports.
2.1.1 Memory map
000016
Port P0 (P0)
000116
Port P0 direction register (P0D)
000216
Port P1 (P1)
000316
Port P1 direction register (P1D)
000416
Port P2 (P2)
000516
Port P2 direction register (P2D)
000616
Port P3 (P3)
000716
Port P3 direction register (P3D)
001616
Pull-up control register (PULL)
001716
Port P1P3 control register (P1P3C)
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003E16
Interrupt control register 1 (ICON1)
Fig. 2.1.1 Memory map of registers relevant to I/O port
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2-2
APPLICATION
7540 Group
2.1 I/O port
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 2, 3) [Address : 00 16, 04 16, 06 16]
B
Name
0 Port Pi 0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
?
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Note: The 32-pin package versions have nothing to be allocated for the following:
•Bits 6 and 7 of port P2
•Bits 5 and 6 of port P3.
Fig. 2.1.2 Structure of Port Pi (i = 0, 2, 3)
Port P1
b7 b6 b5 b4 b3 b2 b1 b0
Port P1 (P1) [Address : 02 16]
B
Name
0 Port P1 0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port P1 1
2 Port P1 2
At reset
R W
?
?
?
3 Port P1 3
?
4 Port P1 4
?
5 Nothing is allocated for these bits.
?
✕ ✕
6
?
✕ ✕
7
?
✕ ✕
When these bits are read out, the values are undefined.
Fig. 2.1.3 Structure of Port P1
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2-3
APPLICATION
7540 Group
2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 2, 3) [Address : 01
B
1
2
3
4
5
6
7
05 16, 0716]
Function
Name
0 Port Pi direction register
16,
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Note: The 32-pin package versions have nothing to be allocated for the following:
•Bits 6 and 7 of P2D
•Bits 5 and 6 of P3D.
Fig. 2.1.4 Structure of Port Pi direction register (i = 0, 2, 3)
Port P1 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1 direction register (P1D) [Address : 03 16]
B
Function
Name
0 : Port P1 0 input mode
1 : Port P1 0 output mode
0 : Port P1 1 input mode
1 : Port P1 1 output mode
0 : Port P1 2 input mode
1 : Port P1 2 output mode
0 : Port P1 3 input mode
1 : Port P1 3 output mode
0 : Port P1 4 input mode
1 : Port P1 4 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
?
✕ ✕
6
?
✕ ✕
7
?
✕ ✕
0 Port P1 direction register
1
2
3
4
5 Nothing is allocated for these bits.
When these bits are read out, the values are undefined.
Fig. 2.1.5 Structure of Port P1 direction register
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APPLICATION
7540 Group
2.1 I/O port
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register (PULL) [Address : 1616]
Name
B
0 P00 pull-up control bit
1 P01 pull-up control bit
2 P02, P03 pull-up control bit
3 P04 – P07 pull-up control bit
4 P30 – P33 pull-up control bit
5 P34 pull-up control bit
6 P35, P36 pull-up control bit
7 P37 pull-up control bit
Function
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
At reset
R W
0
0
0
0
0
0
0
0
Note: Pins set to output are disconnected from the pull-up control.
Fig. 2.1.6 Structure of Pull-up control register
Port P1P3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1P3 control register (P1P3C) [Address : 17
B
Name
0 P37/INT0 input level selection
bit
1 P36/INT1 input level selection
bit (Note)
2 P10, P12,P1 3 input level
selection bit
16]
Function
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
At reset
R W
0
0
0
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
3 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Note: Keep setting the P3 6/INT1 input level selection bit to “0” (initial value) for the
32-pin package version.
Fig. 2.1.7 Structure of Port P1P3 control register
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APPLICATION
7540 Group
2.1 I/O port
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
Name
Function
0 INT 0 interrupt edge
selection bit
1 INT 1 interrupt edge
selection bit
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
B
16]
At reset
R W
0
0
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 P00 key-on wakeup enable bit 0 : Key-on wakeup enabled
0
1 : Key-on wakeup disabled
Fig. 2.1.8 Structure of Interrupt edge selection register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
0 Serial I/O1 receive
interrupt request bit
1 Serial I/O1 transmit interrupt
request bit
2 INT 0 interrupt request bit
3 INT 1 interrupt request bit
4 Key-on wake up interrupt
request bit
5 CNTR 0 interrupt request bit
6 CNTR 1 interrupt request bit
7 Timer X interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.1.9 Structure of Interrupt request register 1
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APPLICATION
7540 Group
2.1 I/O port
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0 Serial I/O1 receive
interrupt enable bit
1 Serial I/O1 transmit interrupt
enable bit
2 INT 0 interrupt enable bit
3 INT 1 interrupt enable bit
4 Key-on wake up interrupt
enable bit
5 CNTR 0 interrupt enable bit
6 CNTR 1 interrupt enable bit
7 Timer X interrupt enable bit
16]
Function
At reset
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
R W
0
0
0
0
0
0
0
0
Fig. 2.1.10 Structure of Interrupt control register 1
2.1.3 Application example of key-on wake up (1)
Outline: The built-in pull-up resistor is used.
Specifications: System is returned from the wait mode when the key-on wakeup interrupt occurs by input
of the falling edge to port P0i.
Note: Only the falling edge is active for the key-on wakeup interrupt.
Figure 2.1.11 shows an example of application circuit, and Figure 2.1.12 shows an example of control
procedure.
7540 Group
P03
P0i(i:0 to 3)
P02
Key ON
P01
P00
Fig. 2.1.11 Example of application circuit
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7540 Group
2.1 I/O port
RESET
Initialization
X: This bit is not used here. Set it to “0” or “1” arbitrary.
SEI
CLD
CLT
← 10000X002
CPUM (Address 3B16)
Wait until f(XIN) oscillation is stabilized (Note)
← XX000X002
CPUM (Address 3B16)
Note: For the concrete time, ask the oscillator manufacture.
Set pull-up control register
1 1 1
PULL(Address 1616)
P00 pull-up On
P01 pull-up On
P02,P03 pull-up On
CLI
Power-down processing
Set interrupt edge selection register
0
INTEDGE(Address 3A16)
Key-on wakeup enabled
Set “0” to the key-on wakeup interrupt request bit.
Set “1” to the key-on wakeup interrupt enable bit.
(key-on wakeup interrupt enabled)
WIT
Key ON
Processing continued
•
•
Key-on wakeup
interrupt processing
•
•
•
•
RTI
Fig. 2.1.12 Example of control procedure (1)
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2.1 I/O port
2.1.4 Application example of key-on wake up (2)
Outline: The key-on wakeup interrupt is used as the normal external interrupt.
Specifications: The key-on wakeup interrupt occurs by input of the falling edge to port P0i. If necessary,
the built-in pull-up resistor is used.
Note: Only the falling edge is active for the key-on wakeup interrupt.
Figure 2.1.13 shows an example of control procedure.
RESET
X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
CLD
CLT
CPUM(Address 3B16)
← 10000X002
Wait until f(XIN) oscillation is stabilized (Note 1)
CPUM(Address 3B16)
← XX000X002
Set port P0i using key-on wakeup interrupt to input mode.
Set port not using key-on wakeup interrupt to output mode.
Set pull-up control register, if necessary
PULL(Address 1616)
P00 pull-up On/Off
P01 pull-up On/Off
P02,P03 pull-up On/Off
P04–P07 pull-up On/Off
Set interrupt edge selection register (Note 2)
INTEDGE(Address 3A16)
0
Key-on wakeup enabled
Notes 1: For the concrete time, ask the oscillator manufacture.
2: In this case, port P00 is used.
Set “0” to the key-on wakeup interrupt request bit.
Set “1” to the key-on wakeup interrupt enable bit.
(key-on wakeup interrupt enabled)
CLI
Key-on waleup interrupt processing routine
Processing
Processing
RTI
Fig. 2.1.13 Example of control procedure (2)
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2.1 I/O port
2.1.5 Handling of unused pins
Table 2.1.1 Handling of unused pins
Pins/Ports name
P0, P1, P2, P3
Handling
•Set to the input mode and connect each to Vcc or Vss through a resistor of 1 kΩ to
10 kΩ.
VREF
•Set to the output mode and open at “L” or “H” level.
•Connect to Vss (GND).
XIN
•Connect to V SS (GND) when using an on-chip oscillator for main clock.
XOUT
•Open when using an external clock.
•Open when using an on-chip oscillator for main clock.
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7540 Group
2.1 I/O port
2.1.6 Notes on input and output ports
Notes on using input and output ports are described below.
(1) Notes in stand-by state
In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using a built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external.
● Reason
The output transistor becomes the OFF state, which causes the ports to be the high-impedance
state. Note that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined”. This may cause power
source current.
* 1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
* 2 bit managing instructions : SEB, and CLB instructions
(3) Usage for the 32-pin version
➀ Fix the P35, P3 6 pull-up control bit of the pull-up control register to “1”.
➁ Keep the P3 6/INT1 input level selection bit of the port P1P3 control register “0” (initial state).
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2.1 I/O port
2.1.7 Termination of unused pins
(1) Terminate unused pins
➀ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/
O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to V CC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
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7540 Group
2.2 Timer A
2.2 Timer A
This paragraph explains the registers setting method and the notes relevant to the timer A.
2.2.1 Memory map
000116
Port P0 direction register (P0D)
001616
Pull-up control register (PULL)
001D16
Timer A mode register (TAM)
001E16
Timer A (low-order) (TAL)
001F16
Timer A (high-order) (TAH)
003A16
Interrupt edge selection register (INTEDGE)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.2.1 Memory map of registers relevant to timer A
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2.2 Timer A
2.2.2 Relevant registers
Port P0 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 direction register (P0D) [Address : 01 16]
B
Function
Name
0 Port P0 direction register
1
2
3
4
5
6
7
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Fig. 2.2.2 Structure of Port P0 direction register
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register (PULL) [Address : 1616]
Name
B
0 P00 pull-up control bit
1 P01 pull-up control bit
2 P02, P03 pull-up control bit
3 P04 – P07 pull-up control bit
4 P30 – P33 pull-up control bit
5 P34 pull-up control bit
6 P35, P36 pull-up control bit
7 P37 pull-up control bit
Function
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
At reset
R W
0
0
0
0
0
0
0
0
Note: Pins set to output are disconnected from the pull-up control.
Fig. 2.2.3 Structure of Pull-up control register
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7540 Group
2.2 Timer A
Timer A mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A mode register (TAM) [Address : 1D 16]
B
Function
Name
At reset
R W
0
✕
1
0
✕
2
0
✕
3
0
✕
0 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
4 Timer A operating mode bits
5
b5 b4
0
0
1
1
0 : Timer mode
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
0
0
6 CNTR 1 active edge switch bit
The function depends on the
operating mode.
(Refer to Table 2.2.1)
0
7 Timer A count stop bit
0 : Count start
1 : Count stop
0
Fig. 2.2.4 Structure of Timer A mode register
Table 2.2.1 CNTR1 active edge switch bit function
Timer A operating modes
Timer mode
CNTR1 active edge switch bit (bit 6 of address 1D 16) contents
“0” CNTR 1 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR 1 interrupt request occurrence: Rising edge
Period measurement mode
; No influence to timer count
“0” Period measurement: Falling period measurement
CNTR 1 interrupt request occurrence: Falling edge
“1” Period measurement: Rising period measurement
CNTR 1 interrupt request occurrence: Rising edge
Event counter mode
“0” Timer A: Rising edge count
CNTR 1 interrupt request occurrence: Falling edge
“1” Timer A: Falling edge count
CNTR 1 interrupt request occurrence: Rising edge
P u l s e w i d t h H L c o n t i n u o u s l y “0” CNTR1 interrupt request occurrence: Rising edge and Falling edge
measurement mode
“1” CNTR1 interrupt request occurrence: Rising edge and Falling edge
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APPLICATION
7540 Group
2.2 Timer A
Timer A register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E
B
16,
Function
1F 16]
At reset
R W
1
0 •Set a count value of timer A.
•The value set in this register is written to both timer A and timer A
1 latch at the same time.
•When this register is read out, the timer A’s count value is read
2 out.
1
1
3
1
4
1
5
1
6
1
7
1
Notes 1: Be sure to write to/read out both the low-order of timer A (TAL) and the highorder of timer A (TAH).
2: Read the high-order of timer A (TAH) first, and the high-order of timer A (TAL) next.
3: Write to the low-order of timer A (TAL) first, and the high-order of timer A (TAH) next.
4: Do not write to them during read, and do not read out them during write.
Fig. 2.2.5 Structure of Timer A register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
Name
Function
0 INT 0 interrupt edge
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
B
selection bit
1 INT 1 interrupt edge
selection bit
16]
At reset
R W
0
0
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 P00 key-on wakeup enable bit 0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
0
Fig. 2.2.6 Structure of Interrupt edge selection register
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APPLICATION
7540 Group
2.2 Timer A
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
0 Serial I/O1 receive
interrupt request bit
1 Serial I/O1 transmit interrupt
request bit
2 INT 0 interrupt request bit
3 INT 1 interrupt request bit
4 Key-on wake up interrupt
request bit
5 CNTR 0 interrupt request bit
6 CNTR 1 interrupt request bit
7 Timer X interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.2.7 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
Name
0 Timer Y interrupt request bit
1 Timer Z interrupt request bit
2 Timer A interrupt request bit
3 Serial I/O2 interrupt request
bit
4 AD converter interrupt
request bit
5 Timer 1 interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✕
0
✕
6 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.2.8 Structure of Interrupt request register 2
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APPLICATION
7540 Group
2.2 Timer A
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0 Serial I/O1 receive
interrupt enable bit
1 Serial I/O1 transmit interrupt
enable bit
2 INT 0 interrupt enable bit
3 INT 1 interrupt enable bit
4 Key-on wake up interrupt
enable bit
5 CNTR 0 interrupt enable bit
6 CNTR 1 interrupt enable bit
7 Timer X interrupt enable bit
16]
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.2.9 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Name
0 Timer Y interrupt
enable bit
1 Timer Z interrupt enable bit
2 Timer A interrupt enable bit
3 Serial I/O2 interrupt enable bit
4 AD conversion interrupt
enable bit
5 Timer 1 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
0
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
7
Fig. 2.2.10 Structure of Interrupt control register 2
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APPLICATION
7540 Group
2.2 Timer A
2.2.3 Timer mode
(1) Operation description
Timer A counts the oscillation frequency divided by 16. Each time the count clock is input, the
contents of Timer A is decremented by 1. When the contents of Timer A reach “000016”, an underflow
occurs at the next count clock, and the timer A latch is reloaded into Timer A. The division ratio of
Timer A is 1/(n+1) provided that the value of Timer A is n.
Timer A can stop counting by setting “1” to the timer A count stop bit.
Also, when Timer A underflows, the timer A interrupt request bit is set to “1”.
(2) Timer mode setting method
Figure 2.2.11 shows the setting method for timer mode of timer A.
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7540 Group
2.2 Timer A
Process 1: Disable timer A interrupt.
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
0
Timer A interrupt disabled
Process 2: Set timer A mode register.
b7
1
b0
0 0
Timer A mode register (TAM) [Address 1D16]
Timer mode
Timer A count stop
Process 3: Set the count value to Timer A (Note).
• Set the count value to timer A (low-order)
Timer A (low-order) (TAL) (Address 1E16)
Count value
• Set the count value to timer A (high-order)
Timer A (high-order) (TAH) (Address 1F16)
Count value
Note: Write both registers in order of timer X (low-order) and
timer X (high-order) following, certainly.
Process 4: In order not to execute the no requested interrupt processing,
set “0” (no requested) to the timer A interrupt request bit.
b7
b0
Interrupt request register 2 (IREQ2) [Address 3D16]
0
No timer A interrupt request issued
Process 5: When Timer A interrupt is used, set “1” (interrupt enabled)
to the timer A interrupt enable bit.
b7
b0
1
Interrupt control register 2 (ICON2) [Address 3F16]
Timer A interrupt enabled
Process 6: Start counting of Timer A.
b7
0
b0
0 0
Timer A mode register (TAM) [Address 1D16]
Timer A count start
Fig. 2.2.11 Setting method for timer mode
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7540 Group
2.2 Timer A
(3) Application example of timer mode
Outline: The input clock is divided by the timer so that the period processing is executed every
25 ms intervals.
Specifications: •The f(X IN) = 8 MHz is divided by timer A to detect 25 ms.
•The timer A interrupt request is confirmed in the main routine. When 25 ms has
elapsed, the period processing is executed in the timer A interrupt processing
routine.
• Operation clock: f(X IN) = 8 MHz, high-speed mode
Figure 2.2.12 shows an example of control procedure.
RESET
Initialization
SEI
CLD
CLT
CPUM(Address 3B16)
← 10000X002
Wait until f(XIN) oscillation is stabilized (Note 1)
CPUM(Address 3B16)
← 00000X002
X: This bit is not used here. Set it to “0” or “1” arbitrary.
Set “0” to the timer A interrupt enable bit.
(Timer A interrupt disabled)
Set timer A mode register
0 0
1
TAM(Address 1D16)
Timer mode
Timer A count stop
Set value to timer A (Notes 2, 3)
“D316”
Timer A (low-order) (Address 1E16)
“3016”
Timer A (high-order) (Address 1F16 )
Notes 1: For the concrete time, ask the oscillator manufacture.
2: When setting the value to Timer A, set in order of low-order
byte and high-order byte following.
3: 25 ms = 1/8 MHz ✕ 16 ✕ (30D316 + 1)
Timer A
division ratio
(fixed)
Timer A
setting value
Set “0” to the timer A interrupt request bit.
Set “1” to the timer A interrupt enable bit.
(Timer A interrupt enabled)
Set timer A mode register
0
0 0
TAM(Address 1D16)
Timer A count start
CLI
Timer A interrupt processing routine
Processing
Periodic processing
RTI
Fig. 2.2.12 Example of control procedure
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APPLICATION
7540 Group
2.2 Timer A
2.2.4 Period measurement mode
(1) Operation description
In the period measurement mode, the pulse period input from the P0 0/CNTR 1 pin is measured.
CNTR1 interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously,
the value in the timer A latch is reloaded in Timer A and count continues. The active edge of CNTR1
pin input signal can be selected from rising or falling by the CNTR1 active edge switch bit. The count
value when trigger input from CNTR 1 pin is accepted is retained until Timer A is read once.
Timer A can stop counting by setting “1” to the timer A count stop bit.
Also, when Timer A underflows, the timer A interrupt request bit is set to “1”.
(2) Period measurement mode setting method
Figure 2.2.13 and Figure 2.2.14 show the setting method for period measurement mode of timer A.
Process 1: Disable timer A interrupt and CNTR1 interrupt.
b7
b0
0
Interrupt control register 1 (ICON1) [Address 3E16]
CNT R1 interrupt disabled
b7
b0
0
Interrupt control register 2 (ICON2) [Address 3F16]
Timer A interrupt disabled
Process 2: Set the CNTR1 pin to the input mode.
b7
b0
0
Port P0 direction register (P0D) [Address 0116]
Set the P00/CNTR1 pin to the input mode
Process 3: Set pull-up control register.
b7
b0
Pull-up control register (PULL) [Address 1616]
P00/CNTR1 pull-up control bit
0: Pull-up Off
1: Pull-up On
Process 4: Set timer A mode register.
b7
1
b0
0 1
Timer A mode register (TAM) [Address 1D16]
Period measurement mode
CNT R1 active edge selected
0: Falling period measured
Falling edge active for CNTR1 interrupt
1: Rising period measured
Rising edge active for CNT R1 interrupt
Timer A count stop
Fig. 2.2.13 Setting method for period measurement mode (1)
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APPLICATION
7540 Group
2.2 Timer A
Process 5: Set the count value to timer A (Note).
• Set the initial value to timer A (low-order)
Timer A (low-order) (TAL) (Address 1E16)
Initial value
• Set the initial value to timer A (high-order)
Timer A (high-order) (TAH) (Address 1F16)
Initial value
Note: Write both registers in order of timer X (low-order) and timer X (high-order) following, certainly.
Process 6: In order to use the CNTR1 pin function of the P00/CNTR1 pin, disable the P00 key-on wakeup function.
b7
b0
Interrupt edge selection register (INTEDGE) [Address 3A16]
1
Key-on wakeup disabled
Process 7: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the timer A interrupt request bit and CNTR1 interrupt request bit.
b7
b0
Interrupt request register 1 (IREQ1) [Address 3C16]
0
No CNTR1 interrupt request issued
b7
b0
Interrupt request register 2 (IREQ2) [Address 3D16]
0
No timer A interrupt request issued
Process 8: When the interrupt is used, set “1” (interrupt enabled) to the timer A interrupt enable bit
or CNTR1 interrupt enable bit.
b7
b0
1
Interrupt control register 1 (ICON1) [Address 3E16]
CNTR1 interrupt enabled
b7
b0
1
Interrupt control register 2 (ICON2) [Address 3F16]
Timer A interrupt enabled
Process 9: Start counting of timer A.
b7
0
b0
0 1
Timer A mode register (TAM) [Address 1D16]
Timer A count start
Fig. 2.2.14 Setting method for period measurement mode (2)
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APPLICATION
7540 Group
2.2 Timer A
(3) Application example of period measurement mode
Outline: The phase control signal is adjusted by using the period measurement mode.
Specifications: • The phase control signal is output to a load, and that controls the phase of a load.
• The period of the pulse input to the P0 0/CNTR1 pin from the load as a feedback
signal is measured. The correct of the phase control signal to the load is executed
using this result. The input pulse period is set to be less than the period of timer
A. When timer A underflows, the period is recognized as not corrected, and error
processing is executed in the timer A interrupt processing routine.
• Operation clock: f(X IN) = 8 MHz, high-speed mode
Figure 2.2.15 shows an example of a peripheral circuit, and Figure 2.2.16 shows an example of
control procedure.
7540 Group
P00/CNTR 1
Load
Port
VAC
Fig. 2.2.15 Example of peripheral circuit
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APPLICATION
7540 Group
2.2 Timer A
RESET
X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
CLD
CLT
← 10000X002
CPUM (Address 3B16)
Wait until f(XIN) oscillation is stabilized (Note 1)
CPUM (Address 3B16)
← 00000X002
CNTR1 interrupt processing routine
Set “0” to the CNTR1 interrupt enable bit.
(CNTR1 interrupt disabled)
Set “0” to the timer A interrupt enable bit.
(Timer A interrupt disabled)
Set port P00 to the input mode.
Read timer A (Note 3)
RTI
Set pull-up control register
PULL(Address 1616)
P00 pull-up control bit
0: Pull-up Off
1: Pull-up On
Set timer A mode register
1 1 0 1
TAM(Address 1D16)
Period measurement mode
Rising period measured
Rising edge active for CNTR1
interrupt
Timer A count stop
Error processing at incorrect period input
Timer A interrupt processing routine
Error processing
Set value to timer A (Note 2)
RTI
“FF 16”
Timer A (low-order) (Address 1E16)
“FF 16”
Timer A (high-order) (Address 1F16 )
Set interrupt edge selection register
INTEDGE(Address 3A16)
Key-on wakeup disabled
1
Set “0” to the CNTR1 interrupt request bit.
Set “0” to the timer A interrupt request bit.
Set “1” to the CNTR1 interrupt enable bit.
(CNTR1 interrupt enabled)
Set “1” to the timer A interrupt enable bit.
(Timer A interrupt enabled)
Notes 1: For the concrete time, ask the oscillator manufacture.
2: When setting the value to timer A, set in order of low-order byte
and high-order byte following.
3: When reading a value of timer A, read in order of high-order byte
and low-order byte following.
Set timer A mode register
TAM(Address 1D16)
0 1 0 1
Timer A count start
CLI
CNTR1 interrupt processing
Processing
Timer A interrupt processing
Fig. 2.2.16 Example of control procedure
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APPLICATION
7540 Group
2.2 Timer A
2.2.5 Event counter mode
(1) Operation description
Timer A counts signals input from the P0 0/CNTR 1 pin.
Except for this, the operation in event counter mode is the same as in timer mode.
The active edge of CNTR1 pin input signal can be selected from rising or falling by the CNTR1 active
edge switch bit.
Timer A can stop counting by setting “1” to the timer A count stop bit.
Also, when Timer A underflows, the timer A interrupt request bit is set to “1”.
(2) Event counter mode setting method
Figure 2.2.17 and Figure 2.2.18 show the setting method for event counter mode of timer A.
Process 1: Disable timer A interrupt and CNTR1 interrupt.
b7
b0
0
Interrupt control register 1 (ICON1) [Address 3E16]
CNTR1 interrupt disabled
b7
b0
0
Interrupt control register 2 (ICON2) [Address 3F16]
Timer A interrupt disabled
Process 2: Set the CNTR1 pin to the input mode.
b7
b0
0
Port P0 direction register (P0D) [Address 0116]
Set the P00/CNTR1 pin to the input mode
Process 3: Set pull-up control register.
b7
b0
Pull-up control register (PULL) [Address 1616]
P00/CNTR1 pull-up control bit
0: Pull-up Off
1: Pull-up On
Process 4: Set timer A mode register.
b7
1
b0
1 0
Timer A mode register (TAM) [Address 1D16]
Event counter mode
CNTR1 active edge selected
0: Rising period measured
Falling edge active for CNTR1 interrupt
1: Falling period measured
Rising edge active for CNTR1 interrupt
Timer A count stop
Process 5: Set the count value to timer A (Note).
• Set the count value to timer A (low-order)
Timer A (low-order) (TAL) (Address 1E16)
Count value
• Set the count value to timer A (high-order)
Timer A (high-order) (TAH) (Address 1F16)
Count value
Note: Write both registers in order of timer X (low-order) and the timer X (high-order) following, certainly.
Fig. 2.2.17 Setting method for event counter mode (1)
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7540 Group
2.2 Timer A
Process 6: In order to use the CNTR1 pin function of the P00/CNTR1 pin, disable the P00 key-on wakeup function.
b7
b0
1
Interrupt edge selection register (INTEDGE) [Address 3A16]
Key-on wakeup disabled
Process 7: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the timer A interrupt request bit and CNTR1 interrupt request bit.
b7
b0
0
Interrupt request register 1 (IREQ1) [Address 3C16]
No CNTR1 interrupt request issued
b7
b0
0
Interrupt request register 2 (IREQ2) [Address 3D16]
No timer A interrupt request issued
Process 8: When the interrupt is used, set “1” (interrupt enabled) to the timer A
interrupt enable bit or CNTR1 interrupt enable bit.
b7
b0
1
Interrupt control register 1 (ICON1) [Address 3E16]
CNTR1 interrupt enabled
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
1
Timer A interrupt enabled
Process 9: Start counting of timer A.
b7
0
b0
1 0
Timer A mode register (TAM) [Address 1D16]
Timer A count start
Fig. 2.2.18 Setting method for event counter mode (2)
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APPLICATION
7540 Group
2.2 Timer A
(3) Application example of event counter mode
Outline: The frequency of the pulse which is input to the P00/CNTR1 pin (“H” active) is measured by
the number of events in a certain period.
Specifications: The count source of timer A is input from the P00/CNTR1 pin, and the timer A starts
counting the count source. Clock (f(X IN) = 8 MHz) is divided by timer X to detect 1
ms. The frequency of the pulse input to the P0 0/CNTR 1 pin is calculated by the
number of events counted within 1 ms.
Operation clock: f(X IN) = 8 MHz, high-speed mode
Figure 2.2.19 shows an example of measurement method of frequency, and Figure 2.2.20 shows an
example of control procedure.
1ms
Timer X interrupt request bit
P00/CNTR1 pin input
Timer A, Timer X
count start
Counted by Timer A (Note 1)
X times (Note 2)
Notes 1: Counted at falling edge.
2: Frequency of pulse input from P00/CNTR1 pin:
Timer X interrupt processing routine
• Timer A, Timer X count stop
• Timer A read
• Timer A, Timer X set again
• Timer A, Timer X count restart
X times
kHz
1ms
Fig. 2.2.19 Example of measurement method of frequency
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7540 Group
2.2 Timer A
RESET
Initialization
X: This bit is not used here. Set it to “0” or “1” arbitrary.
SEI
CLD
CLT
CPUM(Address 3B16) ←10000X002
f(XIN) until f(XIN) oscillation is stabilized (Note 1)
CPUM(Address 3B16) ←00000X002
Timer X interrupt processing routine (1ms interrupt)
Set timer A mode register
1 1 10
TAM(Address 1D16)
Timer A count stop
Set “0” to the CNTR1 interrupt enable bit.
(CNTR1 interrupt disabled)
Set “0” to the timer A interrupt enable bit.
(Timer A interrupt disabled)
Set “0” to the timer X interrupt enable bit
(Timer X interrupt disabled)
Set port P00 to the input mode.
Set pull-up control register
PULL(Address 1616)
P00 pull-up control bit
0: Pull-up Off
1: Pull-up On
Set timer X mode register
1 0 0 TXM(Address 2B16)
Timer X count stop
(Timer A setting value “FFFF16”) – (Timer A count
value) ← event in1ms
Set value to timer A (Note 2)
“FF 16”
Timer A (low-order) (Address 1E16)
“FF 16”
Timer A (high-order) (Address 1F16 )
Set value to timer X (Note 3)
“0116”
Prescaler X (Address 2C16)
“1816”
Timer X (Address 2D16)
Set timer A mode register
1 1 1 0
TAM(Address 1D16)
Event count mode
Count at falling edge
Timer A count stop
Set value to timer A (Note 2)
“FF 16”
Timer A (low-order) (Address 1E16)
“FF 16”
Timer A (high-order) (Address 1F16 )
Set timer A mode register
0 1 1 0
TAM(Address 1D16)
Timer A count start
Set timer X mode register
0 0 0 TXM(Address 2B16)
Timer X count start
RTI
Set timer X mode register
1 0 0 TXM(Address 2B16)
Timer mode
Timer X count stop
Set timer count source set register
0
0 0 TCSS(Address 2E16)
Timer X count source:
f(XIN)/16 selected
Set value to timer X (Note 3)
“0116”
Prescaler X (Address 2C16)
“F916”
Timer X (Address 2D16)
Notes 1: For the concrete time, ask the oscillator manufacture.
2: When setting the value to timer, set in order of low-order byte and
high-order byte following.
3: 1 ms detection = 1/8 MHz ✕ 16 ✕ (0116 + 1) ✕ (F916 + 1)
Timer X Prescaler X Timer X
division ratio setting value setting value
Set interrupt edge selection register
1
INTEDGE(Address 3A16)
Key-on wakeup disabled
Set timer A mode register
0 1 1 0
TAM(Address 1D16)
Timer A count start
Set “0” to the timer X interrupt request bit.
Set “1” to the timer X interrupt enable bit.
(Timer X interrupt enabled)
Set timer X mode register
0 0 0 TXM(Address 2B16)
Timer X count start
CLI
Processing
Fig. 2.2.20 Example of control procedure
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7540 Group
2.2 Timer A
2.2.6 Pulse width HL continuously measurement mode
(1) Operation description
In the pulse width HL continuously measurement mode, the pulse width (“H” and “L” levels) input to
the P00/CNTR 1 pin is measured.
CNTR 1 interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal.
Except for this, the operation in pulse width HL continuously measurement mode is the same as in
period measurement mode.
The count value when trigger input from the CNTR1 pin is accepted is retained until Timer A is read once.
Timer A can stop counting by setting “1” to the timer A count stop bit.
Also, when Timer A underflows, the timer A interrupt request bit is set to “1”.
(2) Pulse width HL continuously measurement mode setting method
Figure 2.2.21 and Figure 2.2.22 show the setting method for pulse width HL continuously measurement
mode of timer A.
Process 1: Disable timer A interrupt and CNTR1 interrupt.
b7
b0
0
Interrupt control register 1 (ICON1) [Address 3E16]
CNT R1 interrupt disabled
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
0
Timer A interrupt disabled
Process 2: Set the CNTR1 pin to the input mode.
b7
b0
0
Port P0 direction register (P0D) [Address 0116]
Set the P00/CNTR1 pin to the input mode
Process 3: Set the pull-up control register.
b7
b0
Pull-up control register (PULL) [Address 1616]
P00/CNTR1 pull-up control bit
0: Pull-up Off
1: Pull-up On
Process 4: Set timer A mode register.
b7
1
b0
1 1
Timer A mode register (TAM) [Address 1D16]
Pulse width HL continuously measurement mode
Timer A count stop
Process 5: Set the count value to timer A (Note).
• Set the initial value to timer A (low-order)
Timer A (low-order) (TAL) (Address 1E16)
Initial value
• Set the initial value to timer A (high-order)
Timer A (high-order) (TAH) (Address 1F16)
Initial value
Note: Write both registers in order of timer X (low-order) and the timer X (high-order) following, certainly.
Fig. 2.2.21 Setting method for pulse width HL continuously measurement mode (1)
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7540 Group
2.2 Timer A
Process 6: In order to use the CNTR1 pin function of the P00/CNTR1 pin, disable the P00 key-on wakeup function.
b7
b0
Interrupt edge selection register (INTEDGE) [Address 3A16]
1
Key-on wakeup disabled
Process 7: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the timer A interrupt request bit and CNTR1 interrupt request bit (Note).
b7
b0
0
Interrupt request register 1 (IREQ1) [Address 3C16]
No CNTR1 interrupt request issued
b7
b0
0
Interrupt request register 2 (IREQ2) [Address 3D16]
No timer A interrupt request issued
Note: In the pulse width HL continuously measurement mode, the CNTR1 interrupt request occurs
at the rising edge and falling edge of the P00/CNTR1 pin regardless of the value of the
P00/CNTR1 active edge switch bit of the timer A mode register.
Process 8: When the interrupt is used, set “1” (interrupt enabled) to the timer A
interrupt enable bit or CNTR1 interrupt enable bit.
b7
b0
Interrupt control register 1 (ICON1) [Address 3E16]
1
CNTR1 interrupt enabled
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
1
Timer A interrupt enabled
Process 9: Start counting of timer A.
b7
0
b0
1 1
Timer A mode register (TAM) [Address 1D16]
Timer A count start
Fig. 2.2.22 Setting method for pulse width HL continuously measurement mode (2)
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7540 Group
2.2 Timer A
(3) Application example of pulse width HL continuously measurement mode
Outline: A telephone ringing (calling) pulse* is detected by using the pulse width HL continuously
measurement mode.
* Signal which is sent by turning on/off (make/break) the telephone line.
Each country has a different standard. In this case, Japanese domestic standard is adopted as an
example.
Specifications: Whether a telephone call exists or not is judged by measuring a pulse width output
from the ringing signal detection circuit.
f(X IN)/16 (f(XIN) = 6.4 MHz) is used as the count source, and “H” and “L” pulse width
of the ringing pulse are measured by using the pulse width HL continuously measurement
mode. When the following conditions are satisfied, it is recognized as a normal
value. When the following conditions are not satisfied, it is recognized as an unusual
value.
200 ms ≤ “H” pulse width of ringing pulse < 1.2 s
600 ms ≤ “L” pulse width of ringing pulse < 2.2 s
1.0 s ≤ one period (“H” pulse width + “L” pulse width) < 3.0 s
Operation clock: f(X IN) = 6.4 MHz, high-speed mode
Figure 2.2.23 shows an example of a peripheral circuit, and Figure 2.2.24 shows an operation timing
when a ringing pulse is input. Figures 2.2.25 and 2.2.26 show an example of control procedure.
7540 Group
Ringing pulse
detection circuit
P00/CNTR1
Telephone line
Fig. 2.2.23 Example of peripheral circuit
● When a normal-range ringing pulse is input
Ringing duration
(200 ms to 1.2 s)
No ringing
duration
(600 ms to 2.2 s)
(1.0 s to 3.0 s)
Input signal to
P00/CNTR1 pin
Reload
Reload
Timer A value
Timer A
interrupt
request
4 to 23
interrupts
occur
12 to 43
interrupts
occur
1 period
20 to 59
interrupts
occur
C N TR 1
interrupt
request
“H” width measurement end
“L” width measurement end
Fig. 2.2.24 Operation timing when ringing pulse is input
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7540 Group
2.2 Timer A
RESET
Initialization
X: This bit is not used here. Set it to “0” or “1” arbitrary.
SEI
CLD
CLT
← 10000X002
CPUM(Address 3B16)
Wait until f(XIN) oscillation is stabilized (Note 1)
← 00000X002
CPUM(Address 3B16)
Set “0” to the timer A interrupt enable bit.
(Timer A interrupt disabled)
Set “0” to the CNTR1 interrupt enable bit.
(CNTR1 interrupt disabled)
Set port P00 to the input mode.
Set pull-up control register
PULL(Address 1616)
P00 pull-up control bit
0: Pull-up Off
1: Pull-up On
Set timer A mode register
1
1 1
TAM(Address 1D16)
Pulse width HL continuously
measurement mode
Timer A count stop
Set value to timer A (Notes 2, 3)
“1F16”
Timer A (low-order) (Address 1E16)
“4E16”
Timer A (high-order) (Address 1F16 )
Set interrupt edge selection register
INTEDGE(Address 3A16)
Key-on wakeup disabled
1
Set “0” to the CNTR1 interrupt request bit.
Set “0” to the timer A interrupt request bit.
Set “1” to the CNTR1 interrupt enable bit.
(CNTR1 interrupt enabled)
Set “1” to the timer A interrupt enable bit.
(Timer A interrupt enabled)
Notes 1: For the concrete time, ask the oscillator manufacture.
2: When setting the value to timer A, set in order of low-order byte
and high-order byte following.
3: 50 ms = 1/6.4 MHz ✕ 16 ✕ (4E1F16 + 1)
Timer A division
ratio (fixed)
Timer A
setting value
Set timer A mode register
0
11
TAM(Address 1D16)
Timer A count start
CLI
Main processing
CNTR1 interrupt occurs at rising edge and falling
edge of waveform which is input to P00/CNTR1 pin
Timer A interrupt occurs at timer A
underflow (at every 50 ms)
N
CNTR1 interrupt processing
Timer A interrupt processing
A ringing pulse exists ?
(Ringer flag = “1”?)
Y
Processing when a ringing pulse exists
Main processing
Fig. 2.2.25 Example of control procedure (1)
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APPLICATION
7540 Group
2.2 Timer A
CNTR1 interrupt processing routine
L e v e l o f P 0 0 / C N T R 1 is c h e c k e d , a n d w h ic h
d u ra t io n m e a s u rin g is fin is h e d is ju d g e d .
When P00/CNTR1 = “0”,
“H” duration measuring is finished.
N
When P00/CNTR1 = “1”,
“L” duration measuring is finished.
T h e n u m b e r o f u n d e rflo w is w ith in th e ra n g e ?
(“4 ” o r m o re a n d le s s th a n “2 3 ”)
T h e n u m b e r o f u n d e rflo w is w ith in th e ra n g e ?
(“1 2 ” o r m o re a n d le s s t h a n “4 3 ”)
Y
Y
Set “1” to the “H” width decision flag.
T h e n u m b e r o f a p e rio d ’s
u n d e rflo w is w ith in th e ra n g e ?
(“2 0 ” o r m o re a n d le s s t h a n “5 9 ”)
Y
When judging that a ringing pulse exists as
a result of several period measurement, set
“1” to the ringing flag.
* Error processing
N
Set “1” to the “L” width decision flag.
N
* Error processing
Set “0” to the “H” width decision flag and
the “L” width decision flag.
Set “1” to the unusual value detection flag
RTI
Timer A interrupt processing routine
Count the number of underflows
RTI
Fig. 2.2.26 Example of control procedure (2)
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7540 Group
2.2 Timer A
2.2.7 Notes on timer A
Notes on using timer A are described below.
(1) Common to all modes
➀ When reading timer A (high-order) (TAH) and timer A (low-order) (TAL), the contents of timer A
is read out. Read both registers in order of TAH and TAL following, certainly.
TAH and TAL keep the values until they are read out.
Also, do not write to them during read. In this case, unexpected operation may occur.
➁ When writing data to TAL and TAH when timer A is operating or stopped, the data are set to timer
A and timer A latch simultaneously. Write both registers in order of TAL and TAH following,
certainly.
Also, do not read them during write. In this case, unexpected operation may occur.
(2) Period measurement mode, event counter mode, and pulse width HL continuously measurement mode
➀ In order to use CNTR1 pin, set “0” to bit 0 of the port P0 direction register (input mode).
➁ In order to use CNTR 1 pin, set “1” to bit 7 of the interrupt edge selection register to disable the
P00 key-on wakeup function.
➂ CNTR 1 interrupt active edge depends on the CNTR 1 active edge switch bit. When this bit is “0”,
the CNTR1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When
this bit is “1”, the CNTR1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input
signal.
However, in the pulse width HL continuously measurement mode, CNTR 1 interrupt request is
generated at both rising and falling edges of CNTR 1 pin input signal regardless of the setting of
CNTR 1 active edge switch bit.
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7540 Group
2.3 Timer 1
2.3 Timer 1
This paragraph explains the registers setting method and the notes relevant to the timer 1.
2.3.1 Memory map
002816
Prescaler 1 (PRE1)
002916
Timer 1 (T1)
003816
MISRG
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.3.1 Memory map of registers relevant to timer 1
2.3.2 Relevant registers
Prescaler 1
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 1 (PRE1) [Address : 2816]
B
Function
0 •Set a count value of prescaler 1.
•The value set in this register is written to both prescaler 1
and the prescaler 1 latch at the same time.
•When this register is read out, the count value of the prescaler 1
2 is read out.
1
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.3.2 Structure of Prescaler 1
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2.3 Timer 1
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 29 16]
B
Function
At reset
R W
1
0 •Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
1 latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 2.3.3 Structure of Timer 1
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG [Address : 3816]
B
Name
0 Oscillation stabilization time
set bit after release of the
STP instruction
Function
0 : Set “0116” in timer 1, and
“FF16” in prescaler 1
automatically
1 : Not set automatically
1 Ceramic or RC oscillation stop 0 : Detection function inactive
detection function active bit
2 These are reserved bits.
Do not write “1” to these bits.
1 : Detection function active
At reset
R W
0
0
0
✕
0
✕
0
✕
5
0
✕
6
0
✕
(Note)
✕
3
4 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 Oscillation stop detection
status bit
0 : Oscillation stop not detected
1 : Oscillation stop detected
Note: “0” at normal reset
“1” at reset by detecting the oscillation stop
Fig. 2.3.4 Structure of MISRG
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2.3 Timer 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
Name
0 Timer Y interrupt request bit
1 Timer Z interrupt request bit
2 Timer A interrupt request bit
3 Serial I/O2 interrupt request
bit
4 AD converter interrupt
request bit
5 Timer 1 interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✕
0
✕
6 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.3.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Name
0 Timer Y interrupt
enable bit
1 Timer Z interrupt enable bit
2 Timer A interrupt enable bit
3 Serial I/O2 interrupt enable bit
4 AD conversion interrupt
enable bit
5 Timer 1 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
0
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
7
Fig. 2.3.6 Structure of Interrupt control register 2
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2.3 Timer 1
2.3.3 Timer 1 operation description
Timer 1 always operates in the timer mode.
Prescaler 1 counts the selected count source. Each time the count clock is input, the contents of Prescaler
1 is decremented by 1.
When the contents of Prescaler 1 reach “00 16”, an underflow occurs at the next count clock, and the
prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/
(n+1) provided that the value of Prescaler 1 is n.
The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When
the contents of Timer 1 reach “00 16”, an underflow occurs at the next count clock, and the timer 1 latch
is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the
value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is provided as follows that
the value of Prescaler 1 is n and the value of Timer 1 is m.
Division ratio =
1
(n+1) ✕ (m+1)
Timer 1 cannot stop counting by software.
Also, when timer 1 underflows, the timer 1 interrupt request bit is set to “1”.
2.3.4 Notes on timer 1
Note on using timer 1 is described below.
(1) Notes on set of the oscillation stabilizing time
Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The
oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/
“not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction
of MISRG. When “0” is set to this bit, “01 16 ” is set to timer 1 and “FF 16 ” is set to prescaler 1
automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the
wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used,
set values again to timer 1 and prescaler 1 after system is returned from the stop mode.
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2.4 Timer X
2.4 Timer X
This paragraph explains the registers setting method and the notes relevant to the timer X.
2.4.1 Memory map
000116
Port P0 direction register (P0D)
000316
Port P1 direction register (P1D)
002B16
Timer X mode register (TXM)
002C16
Prescaler X (PREX)
002D16
Timer X (TX)
002E16
Timer count source set register (TCSS)
003C16
Interrupt request register 1 (IREQ1)
003E16
Interrupt control register 1 (ICON1)
Fig. 2.4.1 Memory map of registers relevant to timer X
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2.4 Timer X
2.4.2 Relevant registers
Port P0 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 direction register (P0D) [Address : 01 16]
B
Function
Name
0 Port P0 direction register
1
2
3
4
5
6
7
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Fig. 2.4.2 Structure of Port P0 direction register
Port P1 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1 direction register (P1D) [Address : 03 16]
B
Function
Name
0 : Port P1 0 input mode
1 : Port P1 0 output mode
0 : Port P1 1 input mode
1 : Port P1 1 output mode
0 : Port P1 2 input mode
1 : Port P1 2 output mode
0 : Port P1 3 input mode
1 : Port P1 3 output mode
0 : Port P1 4 input mode
1 : Port P1 4 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
?
✕ ✕
6
?
✕ ✕
7
?
✕ ✕
0 Port P1 direction register
1
2
3
4
5 Nothing is allocated for these bits.
When these bits are read out, the values are undefined.
Fig. 2.4.3 Structure of Port P1 direction register
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2.4 Timer X
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TXM) [Address : 2B 16]
B
Function
Name
0 Timer X operating mode bits
1
At reset
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
0
0
2 CNTR 0 active edge switch bit
The function depends on the
operating mode.
(Refer to Table 2.4.1)
0
3 Timer X count stop bit
0 : Count start
1 : Count stop
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR 0
output)
0
4
P03/TXOUT output valid bit
R W
0
0
✕
6
0
✕
7
0
✕
5 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 2.4.4 Structure of Timer X mode register
Table 2.4.1 CNTR 0 active edge switch bit function
Timer X operating modes
Timer mode
CNTR 0 active edge switch bit (bit 2 of address 2B16) contents
“0” CNTR 0 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR 0 interrupt request occurrence: Rising edge
; No influence to timer count
Pulse output mode
“0” Pulse output start: Beginning at “H” level
CNTR 0 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR 0 interrupt request occurrence: Rising edge
Event counter mode
“0” Timer X: Rising edge count
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: Falling edge count
CNTR 0 interrupt request occurrence: Rising edge
Pulse width measurement mode
“0” Timer X: “H” level width measurement
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: “L” level width measurement
CNTR 0 interrupt request occurrence: Rising edge
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2.4 Timer X
Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler X (PREX) [Address : 2C 16]
B
Function
0 •Set a count value of prescaler X.
•The value set in this register is written to both prescaler X
and the prescaler X latch at the same time.
•When this register is read out, the count value of the prescaler X
2 is read out.
1
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.4.5 Structure of Prescaler X
Timer X
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (TX) [Address : 2D 16]
B
Function
0 •Set a count value of timer X.
•The value set in this register is written to both timer X and timer X
1 latch at the same time.
•When this register is read out, the timer X’s count value is read
2 out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 2.4.6 Structure of Timer X
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2.4 Timer X
Timer count source set register
b7 b6 b5 b4 b3 b2 b1 b0
0
Timer count source set register (TCSS) [Address : 2E16]
B
Function
Name
0 Timer X count source
selection bits
1
2 Timer Y count source
selection bits
3
4 Timer Z count source
selection bits
5
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN) (Note 1)
1 1 : Not available
b3 b2
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : On-chip oscillator output
(Note 2)
1 1 : Not available
b5 b4
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : Timer Y underflow
1 1 : Not available
At reset
0
0
0
0
0
0
6 Fix this bit to “0”.
0
7 Nothing is allocated for these bits. These are write disabled bits.
0
When these bits are read out, the values are “0”.
R W
✕
Notes 1: f(XIN) can be used as timer X count source only when using a ceramic oscillator
or on-chip oscillator.
Do not use it at RC oscillation.
2: System operates using an on-chip oscillator as a count source by setting the
on-chip oscillator to oscillation enabled by bit 3 of CPUM.
Fig. 2.4.7 Structure of Timer count source set register
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2.4 Timer X
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
0 Serial I/O1 receive
interrupt request bit
1 Serial I/O1 transmit interrupt
request bit
2 INT 0 interrupt request bit
3 INT 1 interrupt request bit
4 Key-on wake up interrupt
request bit
5 CNTR 0 interrupt request bit
6 CNTR 1 interrupt request bit
7 Timer X interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.4.8 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0 Serial I/O1 receive
interrupt enable bit
1 Serial I/O1 transmit interrupt
enable bit
2 INT 0 interrupt enable bit
3 INT 1 interrupt enable bit
4 Key-on wake up interrupt
enable bit
5 CNTR 0 interrupt enable bit
6 CNTR 1 interrupt enable bit
7 Timer X interrupt enable bit
16]
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.4.9 Structure of Interrupt control register 1
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2.4 Timer X
2.4.3 Timer mode
(1) Operation description
Prescaler X counts the selected count source by the timer X count source selection bits. Each time
the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach “0016”, an underflow occurs at the next count clock, and the prescaler X latch is
reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) provided
that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input.
When the contents of Timer X reach “00 16”, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1)
provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X
is provided as follows that
1 the value of Prescaler X is n and the value of Timer X is m.
Division ratio =
(n+1) ✕ (m+1)
Timer X can stop counting by setting “1” to the timer X count stop bit.
Also, when Timer X underflows, the timer X interrupt request bit is set to “1”.
(2) Timer mode setting method
Figure 2.4.10 shows the setting method for timer mode of timer X.
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2.4 Timer X
Process 1: Disable timer X interrupt.
b7
b0
0
Interrupt control register 1 (ICON1) [Address 3E16]
Timer X interrupt disabled
Process 2: Set timer X mode register.
b7
b0
1
0 0
Timer X mode register (TXM) [Address 2B16]
Timer mode
Timer X count stop
Process 3: Set timer count source set register.
b7
b0
0
Timer count source set register (TCSS) [Address 2E16]
Timer X count source selection bits
b1 b0
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN) (Note)
1 : Not available
Note: f(XIN) can be used only when a ceramic resonator or an on-chip oscillator is used.
Do not use f(XIN) at RC oscillation.
Process 4: Set the count value to timer X.
• Set the count value to prescaler X and timer X
Prescaler X (PREX) (Address 2C16)
Count value
Timer X (TX) (Address 2D16)
Count value
Process 5: In order not to execute the no requested interrupt processing,
set “0” (no requested) to the timer X interrupt request bit.
b7
b0
Interrupt request register 1 (IREQ1) [Address 3C16]
0
No timer X interrupt request issued
Process 6: When timer X interrupt is used, set “1” (interrupt enabled)
to the timer X interrupt enable bit.
b7
b0
1
Interrupt control register 1 (ICON1) [Address 3E16]
Timer X interrupt enabled
Process 7: Start counting of timer X.
b7
b0
0
0 0
Timer X mode register (TXM) [Address 2B16]
Timer X count start
Fig. 2.4.10 Setting method for timer mode
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2.4 Timer X
(3) Application example of timer mode
Outline: The input clock is divided by the timer so that the clock is counted up every 250 ms
intervals.
Specifications: •The f(X IN) = 4.19 MHz (2 22 Hz) is divided by timer X.
•The clock is counted up in the timer X interrupt processing routine (timer X interrupt
occurs every 250 ms).
• Operation clock: f(X IN) = 4.19 MHz, high-speed mode
Figure 2.4.11 shows the connection of timer and setting of division ratio and Figure 2.4.12 shows an
example of control procedure.
Timer X count
source selection
bits
f(XIN) = 4.19 MHz
1/16
Prescaler X
1/256
Timer X
Timer X interrupt Divided by 4 by software
request bit
1/256
0 or 1
250 ms
1/4
1s
0: No interrupt request
1: Interrupt request
Fig. 2.4.11 Connection of timer and setting of division ratio
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2.4 Timer X
RESET
Initialization
X: This bit is not used here. Set it to “0” or “1” arbitrary.
SEI
CLD
CLT
CPUM(Address 3B16)
← 10000X002
Wait until f(XIN) oscillation is stabilized (Note 1)
← 00000X002
CPUM(Address 3B16)
Processing of clock setting
Set “0” to the timer X interrupt enable bit.
(Timer X interrupt disabled)
Clock setting
Set “0” to the timer X interrupt enable bit.
(Timer X interrupt disabled)
Set timer X mode register
Set timer X mode register
1
0
1
0 0
0
TXM(Address 2B16)
Set value to timer X (Note 2)
Set timer count source set register
0 0
0 0
Timer X count stop
Timer mode
Timer X count stop
10
1
TXM(Address 2B16)
TCSS(Address 2E16)
“FF16”
Prescaler X (Address 2C16)
“FF16”
Timer X (Address 2D16)
Timer X count source:
f(XIN)/16 selected
Set “0” to the timer X interrupt request bit.
Set value to timer X (Note 2)
“FF16”
Prescaler X (Address 2C16)
“FF16”
Timer X (Address 2D16)
Set “1” to the timer X interrupt enable bit.
(Timer X interrupt enabled)
Set timer X mode register
1 0 0 0 0 TXM(Address 2B16)
Set “0” to the timer X interrupt request bit.
Timer X count start
Set “1” to the timer X interrupt enable bit.
(Timer X interrupt enabled)
RTS
Set timer X mode register
1 0 0 0 0 TXM(Address 2B16)
Timer X count start
Notes 1: For the concrete time, ask the oscillator manufacture.
2: About 250 ms = 1/4.19 MHz ✕ 16 ✕ (FF16 + 1) ✕ (FF16 + 1)
Timer X Prescaler X Timer X
division ratio setting value setting value
CLI
Timer X interrupt processing routine
Processing
Clock is stopped?
Setting clock is required?
Y
N
N
Y
Clock count up (1/4 s to year)
Processing of setting clock
RTI
Fig. 2.4.12 Example of control procedure
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2.4 Timer X
2.4.4 Pulse output mode
(1) Operation description
In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is
output from the P14/CNTR 0 pin.
The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0
active edge switch bit is “0”, the output of CNTR0 pin is started at “H” level. When this bit is “1”, the
output is started at “L” level.
Also, the inverted waveform of pulse output from CNTR0 pin can be output from TXOUT pin by setting
“1” to the P0 3/TX OUT output valid bit.
When using a timer in this mode, set the port P1 4 and P0 3 direction registers to output mode.
Timer X can stop counting by setting “1” to the timer X count stop bit.
Also, when Timer X underflows, the timer X interrupt request bit is set to “1”.
(2) Pulse output mode setting method
Figure 2.4.13 and Figure 2.4.14 show the setting method for pulse output mode of timer X.
Process 1: Disable timer X interrupt.
b7
b0
Interrupt control register 1 (ICON1) [Address 3E16]
0
Timer X interrupt disabled
Process 2: Set timer X mode register.
b7
b0
1
0 1
Timer X mode register (TXM) [Address 2B16]
Pulse output mode
CNTR0 active edge switch
0: Output is started at “H” level
1: Output is started at “L” level
Timer X count stop
P03/TXOUT output
0: Output invalid (I/O port)
1: Output valid (inverted CNTR0 output)
Process 3: Set the CNTR0 pin to the output mode.
b7
b0
1
Port P1 direction register (P1D) [Address 0316]
Set the P14/CNTR0 pin to the output mode
Process 4: Set the TXOUT pin as the output mode when TXOUT output is valid.
b7
b0
1
Port P0 direction register (P0D) [Address 0116]
Set the P03/TXOUT pin to the output mode
Fig. 2.4.13 Setting method for pulse output mode (1)
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2.4 Timer X
Process 5: Set timer count source set register.
b7
b0
Timer count source set register (TCSS) [Address 2E16]
0
Timer X count source selection bits
b1 b0
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN) (No te)
1 : Not available
Note: f(XIN) can be used only when a ceramic resonator or an on-chip oscillator is used.
Do not use f(XIN) at RC oscillation.
Process 6: Set the count value to timer X.
• Set the count value to prescaler X and timer X
Prescaler X (PREX) (Address 2C16)
Count value
Timer X (TX) (Address 2D16)
Count value
Process 7: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the timer X interrupt request bit.
b7
b0
0
Interrupt request register 1 (IREQ1) [Address 3C16]
No timer X interrupt request issued
Process 8: When the interrupt is used, set “1” (interrupt enabled) to the timer X
interrupt enable bit.
b7
b0
Interrupt control register 1 (ICON1) [Address 3E16]
1
Timer X interrupt enabled
Process 9: Start counting of timer X.
b7
b0
0
0 1
Timer X mode register (TXM) [Address 2B16]
Timer X count start
Fig. 2.4.14 Setting method for pulse output mode (2)
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2.4 Timer X
(3) Application example of pulse output mode
Outline: The pulse output mode of timer X is used for a piezoelectric buzzer output.
Specifications: The rectangular waveform which is clock f(X IN) = 4 MHz divided up to 4 kHZ is
output from the P1 4/CNTR 0 pin.
The level of the P1 4/CNTR0 pin is fixed to “H” while a piezoelectric buzzer output is
stopped.
Operation clock: f(X IN) = 4 MHz, double-speed mode
Figure 2.4.15 shows an example of a peripheral circuit, Figure 2.4.16 shows the connection of timer
and setting of the division ratio, and Figure 2.4.17 shows an example of control procedure.
The “H” level is output while a piezoelectric buzzer output is stopped.
7540 Group
CNTR0 output
P14/CNTR0
PiPiPi.....
125 µs 125 µs
Set division ratio so that the underflow
output period of timer X will become
125 µs.
Fig. 2.4.15 Example of peripheral circuit
Timer X count
source selection
bit
f(XIN) = 4MHz
1/2
Prescaler X
1/2
Timer X
Fixed
1/125
1/2
CNTR0 pin output
4 kHz
Fig. 2.4.16 Connection of timer and setting of division ratio
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2.4 Timer X
RESET
X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
CLD
CLT
← 10000X002
CPUM(Address 3B16)
Wait until f(XIN) oscillation is stabilized (Note 1)
CPUM(Address 3B16)
← 11000X002
Set “0” to the CNTR0 interrupt enable bit.
(CNTR0 interrupt disabled)
Set “0” to the timer X interrupt enable bit.
(Timer X interrupt disabled)
Set port P14 to the output mode.
Set “1” to port P14. (“H” output)
Set timer X mode register
1
0
1 0 0 1
TXM(Address 2B16)
Pulse output mode
Output is started at “H” level
Timer X count stop
Set timer count source set register
1 0
0 1
TCSS(Address 2E16)
Timer X count source:
f(XIN)/2 selected
Set value to timer X (Notes 2, 3)
“0116”
Prescaler X (Address 2C16)
“7C16”
Timer X (Address 2D16)
Notes 1: For the concrete time, ask the oscillator manufacture.
2: 125 µs = 1/4 MHz ✕ 2 ✕ (0116 + 1) ✕ (7C16 + 1)
Timer X
division
ratio
Prescaler X
setting
value
Timer X
setting
value
3: The output level of P14/CNTR0 pin is initialized by writing to timer X.
CLI
Processing
Buzzer output processing
Buzzer output is requested?
N
Y
Timer X count is stopped?
Timer X count is operating?
N
N
Y
Set timer X mode register
Y
1
0
1 0 01
Set timer X mode register
1
0
0 0 0 1
TXM(Address 2B16)
Timer X count start
TXM(Address 2B16)
Timer X count stop
Set value to timer X (Note 3)
“7C16”
Timer X (Address 2D16)
Processing
Fig. 2.4.17 Example of control procedure
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2.4 Timer X
2.4.5 Event counter mode
(1) Operation description
The timer X counts signals input from the P1 4/CNTR 0 pin.
Except for this, the operation in event counter mode is the same as in timer mode.
The active edge of CNTR0 pin input signal can be selected from rising or falling by the CNTR0 active
edge switch bit.
Timer X can stop counting by setting “1” to the timer X count stop bit.
Also, when Timer X underflows, the timer X interrupt request bit is set to “1”.
(2) Event counter mode setting method
Figure 2.4.18 and Figure 2.4.19 show the setting method for event counter mode of timer X.
Process 1: Disable timer X interrupt and CNTR0 interrupt.
b7
b0
0
0
Interrupt control register 1 (ICON1) [Address 3E16]
CNT R0 interrupt disabled
Timer X interrupt disabled
Process 2: Set the CNTR0 pin to the input mode.
b7
b0
Port P1 direction register (P1D) [Address 0316]
0
Set the P14/CNTR0 pin to the input mode
Process 3: Set timer X mode register.
b7
b0
1
1 0
Timer X mode register (TXM) [Address 2B16]
Event counter mode
CNTR0 active edge switch
0: Count at rising edge
CNTR0 interrupt request occurs at falling edge
1: Count at falling edge
CNTR0 interrupt request occurs at rising edge
Timer X count stop
Process 4: Set timer count source set register.
b7
b0
0
Timer count source set register (TCSS) [Address 2E16]
Timer X count source selection bits
b1 b0
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN) (Note)
1 : Not available
Note: f(XIN) can be used only when a ceramic oscillator or an on-chip oscillator is used.
Do not use f(XIN) at RC oscillation.
Fig. 2.4.18 Setting method for event counter mode (1)
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2.4 Timer X
Process 5: Set the count value to timer X.
• Set the count value to prescaler X and timer X
Prescaler X (PREX) (Address 2C16)
Count value
Timer X (TX) (Address 2D16)
Count value
Process 6: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the timer X interrupt request bit and CNTR1 interrupt request bit.
b7
0
b0
Interrupt request register 1 (IREQ1) [Address 3C16]
0
No CNTR0 interrupt request is issued
No timer X interrupt request issued
Process 7: When the interrupt is used, set “1” (interrupt enabled) to the timer X
interrupt enable bit.
b7
1
b0
Interrupt control register 1 (ICON1) [Address 3E16]
1
CNT R0 interrupt enabled
Timer X interrupt enabled
Process 8: Start counting of timer X.
b7
b0
0
1 0
Timer X mode register (TXM) [Address 2B16]
Timer X count start
Fig. 2.4.19 Setting method for event counter mode (2)
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2.4 Timer X
(3) Application example of event counter mode
Outline: Pulses generated corresponding to the water flow rate are counted for a fixed period
(100 ms), and the water flow rate during this period is calculated.
Specifications: Pulses generated corresponding to the water flow rate are input to the P1 4/CNTR0
pin and counted using timer X.
The contents of timer X are read in the timer Y interrupt processing routine generated
after 100 ms from the start of counting pulses, and the water flow rate during 100
ms is calculated.
Operation clock: f(X IN) = 8 MHz, high-speed mode
Figure 2.4.20 shows an example of peripheral circuit, Figure 2.4.21 shows the method of measuring
water flow rate, and Figure 2.4.21 shows an example of control procedure.
7540 Group
Water flow rate sensor
Water
flow
P14/CNTR0
Blades rotate in proportion to
water flow and generate pulses.
The faster the water flow,
the shorter the pulse period.
Fig. 2.4.20 Example of peripheral circuit
100 ms
Timer Y interrupt request bit
CNTR0 pin input
Timer X, timer Y
start counting.
Timer X counting (Note)
Timer Y interrupt processing routine
• Timer X, timer Y stop counting.
• Timer X is read out.
Note: Counting rising edges.
• Flow rate during 100 ms = (FF16–read value of timer X) ✕ flow rate per pulse
Fig. 2.4.21 Method of measuring water flow rate
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2.4 Timer X
Flow rate measuring routine
Set “0” to the CNTR0 interrupt enable bit.
(CNTR0 interrupt disabled)
Set “0” to the timer X interrupt enable bit.
(Timer X interrupt disabled)
Set “0” to the timer Y interrupt enable bit.
(Timer Y interrupt disabled)
Timer Y interrupt processing routine
Set timer X mode register
1
Set port P14 to the input mode.
0
1 1 1 0 TXM(Address 2B16)
Timer X count stop
Set timer X mode register
1
0
11 1 0
TXM(Address 2B16)
Set timer Y, Z mode register
10
Event counter mode
Count at falling edge
Timer X count stop
Set timer Y, Z mode register
1 0
0
TYZM(Address 2016)
Timer mode
Writing to latch and timer
simultaneously
Timer Y count stop
0 TYZM(Address 2016)
Timer Y count stop
(Prescaler X setting value “FF16” Timer X setting
value “FF16”) – (Prescaler X count value, Timer X
count value)
← The numbeer of event within 100 ms
RTI
Set timer count source set register
1 0
TCSS(Address 2E16)
0 0
Timer Y count source:
f(XIN)/16 selected
Set value to timer X
“FF 16”
Prescaler X (Address 2C16)
“FF 16”
Timer X (Address 2D16)
Note : 100 ms = 1/8 MHz ✕ 16 ✕ (C716 + 1) ✕ (F916 + 1)
Timer Y
division
ratio
Prescaler Y
setting
value
Timer Y
primary
setting
value
Set value to timer Y (Note)
“C716”
Prescaler Y (Address 2116)
“F916”
Timer Y primary (Address 2316)
Set “0” to the timer Y interrupt request bit.
Set “1” to the timer Y interrupt enable bit.
(Timer Y interrupt enabled)
Set timer X mode register
1
0
0 11 0
TXM(Address 2B16)
Timer X count start
Set timer Y, Z mode register
0 0
0
TYZM(Address 2016)
Timer Y count start
END
Fig. 2.4.22 Example of control procedure
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2.4 Timer X
2.4.6 Pulse width measurement mode
(1) Operation description
In the pulse width measurement mode, the pulse width of the signal input to P1 4/CNTR 0 pin is
measured.
The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin.
When the CNTR 0 active edge switch bit is “0”, the signal selected by the timer X count source
selection bit is counted while the input signal level of CNTR0 pin is “H”. The count is stopped while
the pin is “L”. Also,
when the CNTR 0 active edge switch bit is “1”, the signal selected by the timer X count source
selection bit is counted while the input signal level of CNTR0 pin is “L”. The count is stopped while
the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop bit.
Also, when Timer X underflows, the timer X interrupt request bit is set to “1”.
(2) Pulse width HL continuously measurement mode setting method
Figure 2.4.23 and Figure 2.4.24 show the setting method for pulse width measurement mode of timer X.
Process 1: Disable timer X interrupt and CNTR0 interrupt.
b7
b0
0
Interrupt control register 1 (ICON1) [Address 3E16]
0
CNTR0 interrupt disabled
Timer X interrupt disabled
Process 2: Set the CNTR0 pin to the input mode.
b7
b0
0
Port P1 direction register (P1D) [Address 0316]
Set the P14/CNTR0 pin to the input mode
Process 3: Set timer X mode register.
b7
b0
1
1 1
Timer X mode register (TXM) [Address 2B16]
Pulse width measurement mode
CNT R0 active edge switch
0: “H” level width measurement
1: “L” level width measurement
Timer X count stop
Process 4: Set timer X count source.
b7
b0
0
Timer count source set register (TCSS) [Address 2E16]
Timer X count source selection bits
b1 b0
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : f(XIN) (Note)
1 : Not available
Note: f(XIN) can be used only when a ceramic resonator or an on-chip oscillator is used.
Do not use f(XIN) at RC oscillation.
Fig. 2.4.23 Setting method for pulse width measurement mode (1)
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2.4 Timer X
Process 5: Set the count value to timer X.
• Set the initial value to prescaler X and timer X
Prescaler X (PREX) (Address 2C16)
Initial value
Timer X (TX) (Address 2D16)
Initial value
Process 6: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the timer X interrupt request bit and CNTR0 interrupt request bit.
b7
0
b0
Interrupt request register 1 (IREQ1) [Address 3C16]
0
No CNTR0 interrupt request is issued
No timer X interrupt request issued
Process 7: When the interrupt is used, set “1” (interrupt enabled) to the timer X
interrupt enable bit.
b7
1
b0
Interrupt control register 1 (ICON1) [Address 3E16]
1
CNTR0 interrupt enabled
Timer X interrupt enabled
Process 8: Start counting of timer X.
b7
b0
0
1 1
Timer X mode register (TXM) [Address 2B16]
Timer X count start
Fig. 2.4.24 Setting method for pulse width measurement mode (2)
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2.4 Timer X
(3) Application example of pulse width measurement mode
Outline: “H” level width of pulse input to P1 4/CNTR 0 pin is counted.
Specifications: The “H” level width of a FG pulse input to the P14/CNTR0 pin is counted. An underflow
is detected by the timer X interrupt. The completion of “H” level of input pulse is
detected by the CNTR 0 interrupt.
Operation clock: f(X IN) = 4.19 MHz, high-speed mode
Example: When f(XIN) = 4.19 MHz, the count source becomes 3.8 µs divided by 16. Measurement
can be made up to 250 ms in the range of “FFFF 16” to “000016”.
Figure 2.4.25 shows a connection of the timer and setting of the division ratio. Figure 2.4.26 shows
an example of control procedure.
Timer X count
source selection bit Prescaler X
f(XIN) = 4.19MHz
1/16
1/256
Timer X
Timer X interrupt
request bit
1/256
0 or 1
250 m s
0: No interrupt request
1: Interrupt request
Fig. 2.4.25 Connection of timer and setting of division ratio
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2.4 Timer X
RESET
Initialization
X: This bit is not used here. Set it to “0” or “1” arbitrary.
SEI
CLD
CLT
← 10000X002
CPUM(Address 3B16)
Wait until f(XIN) oscillation is stabilized (Note 1)
← 00000X002
CPUM(Address 3B16)
CNTR0 interrupt processing routine
Set “0” to the CNTR0 interrupt enable bit.
(CNTR0 interrupt disabled)
Set “0” to the timer X interrupt enable bit.
(Timer X interrupt disabled)
Timer X is read out.
RTI
Set port P14 to the input mode.
Set timer X mode register
1
0
1 01 1
TXM(Address 2B16)
Pulse width measurement mode
Falling edge
Timer X count stop
Error processing at incorrect period input
Timer X interrupt processing routine
Set timer count source set register
1 0
0 0
TCSS(Address 2E16)
Timer Y count source:
f(XIN)/16 selected
Error processing
Set value to timer X (Note 2)
“FF16”
Prescaler X (Address 2C16)
“FF16”
Timer X (Address 2D16)
RTI
Set “0” to the CNTR0 interrupt request bit.
Set “0” to the timer X interrupt request bit.
Set “1” to the CNTR0 interrupt enable bit.
(CNTR0 interrupt enabled)
Set “1” to the timer X interrupt enable bit.
(Timer X interrupt enabled)
Notes 1: For the concrete time, ask the oscillator manufacture.
2: About 250 ms = 1/4.19 MHz ✕ 16 ✕ (FF16+ 1) ✕ (FF16 + 1)
Timer X
division
ratio
Prescaler X
setting
value
Timer X
setting
value
Set timer X mode register
1
0
0
TXM(Address 2B16)
1 1
Timer X count start
CLI
Timer X interrupt processing
Processing
CNTR0 interrupt processing
END
Fig. 2.4.26 Example of control procedure
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2.4 Timer X
2.4.7 Notes on timer X
Notes on using each mode of timer X are described below.
(1) Count source
➀ f(X IN) can be used only when a ceramic oscillator or an on-chip oscillator is used.
Do not use f(X IN) at RC oscillation.
(2) Pulse output mode
➀ In order to use CNTR 0 pin, set “1” to bit 4 of the port P1 direction register (output mode).
➁ In order to use TXOUT pin, set “1” to bit 3 of the port P0 direction register (output mode).
➂ CNTR 0 interrupt active edge depends on the CNTR 0 active edge switch bit. When this bit is “0”,
the CNTR 0 interrupt request bit is set to “1” at the falling edge of CNTR 0 pin input signal. When
this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR 0 pin input
signal.
(3) Pulse width measurement mode
➀ In order to use CNTR 0 pin, set “1” to bit 4 of the port P1 direction register (output mode).
➁ CNTR 0 interrupt active edge depends on the CNTR 0 active edge switch bit. When this bit is “0”,
the CNTR 0 interrupt request bit is set to “1” at the falling edge of CNTR 0 pin input signal. When
this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR0 pin input
signal.
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2.5 Timer Y and timer Z
2.5 Timer Y and timer Z
This paragraph explains the registers setting method and the notes relevant to the timer Y and timer Z.
2.5.1 Memory map
000116
Port P0 direction register (P0D)
000716
Port P3 direction register (P3D)
001616
Pull-up control register (PULL)
001716
Port P1P3 control register (P1P3C)
002016
Timer Y, Z mode register (TYZM)
002116
002216
Prescaler Y (PREY)
002316
Timer Y primary (TYP)
002416
002516
Timer Y, Z waveform output control register (PUM)
002616
Timer Z secondary (TZS)
002716
Timer Z primary (TZP)
002A16
One-shot start register (ONS)
002E16
Timer count source set register (TCSS)
003A16
Interrupt edge selection register (INTEDGE)
003B16
CPU mode register (CPUM)
003C16
Interrupt request register 1 (IREQ1)
003D16
Interrupt request register 2 (IREQ2)
003E16
Interrupt control register 1 (ICON1)
003F16
Interrupt control register 2 (ICON2)
Timer Y secondary (TYS)
Prescaler Z (PREZ)
Fig. 2.5.1 Memory map of registers relevant to timer Y and timer Z
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2.5 Timer Y and timer Z
2.5.2 Relevant registers
Port P0 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P0 direction register (P0D) [Address : 01 16]
B
Function
Name
0 Port P0 direction register
1
2
3
4
5
6
7
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Fig. 2.5.2 Structure of Port P0 direction register
Port P3 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 direction register (P3D) [Address : 07 16]
B
Name
0 Port P3 direction register
1
2
3
4
5
6
7
Function
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Note: The 32-pin package versions have nothing to be allocated for the following:
•Bits 5 and 6 of P3D.
Fig. 2.5.3 Structure of Port P3 direction register
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2.5 Timer Y and timer Z
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register (PULL) [Address : 16 16]
Name
B
P0
0
pull-up
control
bit
0
1 P01 pull-up control bit
2 P02, P03 pull-up control bit
3 P04 – P07 pull-up control bit
4 P30 – P33 pull-up control bit
5 P34 pull-up control bit
6 P35, P36 pull-up control bit
7 P37 pull-up control bit
Function
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
At reset
R W
0
0
0
0
0
0
0
0
Notes 1: Pins set to output are disconnected from the pull-up control.
2: Keep setting the P3 5, P36 pull-up control bit to “1” (initial value: 0)
for the 32-pin package versions.
Fig. 2.5.4 Structure of Pull-up control register
Port P1P3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1P3 control register (P1P3C) [Address : 17
B
Name
0 P37/INT0 input level selection
bit
1 P36/INT1 input level selection
bit (Note)
2 P10, P12,P1 3 input level
selection bit
16]
Function
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
At reset
R W
0
0
0
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
3 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Note: Keep setting the P3 6/INT1 input level selection bit to “0” (initial value) for the
32-pin package version.
Fig. 2.5.5 Structure of Port P1P3 control register
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2.5 Timer Y and timer Z
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y, Z mode register (TYZM) [Address : 20 16)
B
0
Function
Name
Timer Y operating mode bit
0 : Timer mode
1 : Programmable waveform
generation mode
1 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
0 : Write to latch and timer
2 Timer Y write control bit
simultaneously
(Note)
1 : Write to only latch
0 : Count start
3 Timer Y count stop bit
1 : Count stop
4 Timer Z operating mode bits
5
6 Timer Z write control bit
(Note)
7 Timer Z count stop bit
b5 b4
0 0 : Timer mode
0 1 : Programmable waveform
generation mode
1 0 : Programmable one-shot
generation mode
1 1 : Programmable wait one-shot
generation mode
At reset
R W
0
0
✕
0
0
0
0
0 : Write to latch and timer
simultaneously
1 : Write to only latch
0
0 : Count start
1 : Count stop
0
Note: When modes other than the timer mode, set these bits to “1”.
Fig. 2.5.6 Structure of Timer Y, Z mode register
Prescaler Y, Prescaler Z
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler Y (PREY) [Address : 2116]
Prescaler Z (PREZ) [Address : 2516]
B
Function
0 • Set a count value of each prescaler.
1
2
3
4
5
• While the corresponding timer is stopped, the value set in this
register is written to both prescaler
and the corresponding prescaler latch at the same time.
• While the corresponding timer is operating, the value set in this
register is written to as follows;
When the timer write control bit is “0”, the value is written to
prescaler latch and prescaler at the same time.
When the timer write control bit is “1”, the value is written to
prescaler latch only.
• When this register is read out, the count value of the
corresponding prescaler is read out.
At reset
R W
1
1
1
1
1
1
6
1
7
1
Fig. 2.5.7 Structure of Prescaler Y, Prescaler Z
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2.5 Timer Y and timer Z
Timer Y secondary, Timer Z secondary
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y secondary, Timer Z secondary (TYS, TZS) [Address : 22
B
16,
2616]
1
R W
✕
1
✕
1
✕
3
1
✕
4
1
✕
5
1
✕
6
1
✕
7
1
✕
Function
At reset
0 •Set a count value of the corresponding timer.
•The value set in this register is written to the corresponding
1 secondary latch at the same time.
•These are read disabled bits.
2 When these bits are read out, the values are undefined.
Fig. 2.5.8 Structure of Timer Y secondary, Timer Z secondary
Timer Y primary, Timer Z primary
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y primary, Timer Z primary (TYP, TZP) [Address : 23
B
16,
2716]
Function
0 •Set a count value of the corresponding timer.
1
2
3
4
5
•When the corresponding timer is stopped, the value set in this
register is written to both the corresponding primary latch and
the corresponding timer at the same time.
•When the corresponding timer is operating, the value set in this
register is written as follows;
timer write control bit = 0:
the value is written to both the corresponding primary latch and
the corresponding timer at the same time.
timer write control bit = 1:
the value is written to the corresponding primary latch.
•When these bits are read out, the count value of the corresponding timer is read out (Note).
At reset
R W
1
1
1
1
1
1
6
1
7
1
Note: The primary count value is read out at the primary interval, the secondary count
value is read out at the secondary interval.
Fig. 2.5.9 Structure of Timer Y primary, Timer Z primary
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2.5 Timer Y and timer Z
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y, Z waveform output control register (PUM) [Address : 24
B
0
1
2
3
4
5
6
7
16]
Function
Name
0 : Waveform not extended
1 : Waveform extended
0 : Waveform not extended
1 : Waveform extended
0 : Waveform not extended
1 : Waveform extended
0 : Waveform not extended
1 : Waveform extended
0 : “L” output
Timer Y output level latch
1 : “H” output
0
: “L” output
Timer Z output level latch
1 : “H” output
0 : INT 0 pin one-shot trigger invalid
INT0 pin one-shot trigger
1 : INT 0 pin one-shot trigger valid
control bit (Note)
INT0 pin one-shot trigger active 0 : Falling edge trigger
1 : Rising edge trigger
edge selection bit ( Note)
Timer Y primary waveform
extension control bit
Timer Y secondary waveform
extension control bit
Timer Z primary waveform
extension control bit
Timer Z secondary waveform
extension control bit
At reset
R W
0
0
0
0
0
0
0
0
Note: Stop timer Z to change the values of these bits.
Fig. 2.5.10 Structure of Timer Y, Z waveform output control register
One-shot start register
b7 b6 b5 b4 b3 b2 b1 b0
One-shot start register (ONS) [Address : 2A 16]
B
Name
0 Timer Z one-shot start bit
Function
0 : One-shot stop
1 : One-shot start
At reset
R W
0
0
✕
2
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
1 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 2.5.11 Structure of One-shot start register
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2.5 Timer Y and timer Z
Timer count source set register
b7 b6 b5 b4 b3 b2 b1 b0
0
Timer count source set register (TCSS) [Address : 2E16]
B
Name
0 Timer X count source
selection bits
1
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : On-chip oscillator output
(Note 2)
1 1 : Not available
3
selection bits
5
0
b3 b2
selection bits
R W
0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN) (Note 1)
1 1 : Not available
2 Timer Y count source
4 Timer Z count source
At reset
Function
b5 b4
0
0
0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : Timer Y underflow
1 1 : Not available
0
6 Fix this bit to “0”.
0
7 Nothing is allocated for this bit. This is a write disabled bit.
0
When this bit is read out, the value is “0”.
✕
Notes 1: f(XIN) can be used as timer X count source only when using a ceramic oscillator
or on-chip oscillator.
Do not use it at RC oscillation.
2: System operates using an on-chip oscillator as a count source by setting the
on-chip oscillator to oscillation enabled by bit 3 of CPUM.
Fig. 2.5.12 Structure of Timer count source set register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
Name
Function
0 INT 0 interrupt edge
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
B
selection bit
1 INT 1 interrupt edge
selection bit
16]
At reset
R W
0
0
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 P00 key-on wakeup enable bit 0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
0
Fig. 2.5.13 Structure of Interrupt edge selection register
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2.5 Timer Y and timer Z
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16]
B
Name
0 Processor mode bits (Note 1)
1
2
Stack page selection bit
3 On-chip oscillator oscillation
control bit
4 XIN oscillation control bit
5 Oscillation mode selection bit
(Note 1)
6
Clock division ratio selection
bits
7
Function
b1 b0
0
0
1
1
0 : Single-chip mode
1 : Not available
0 : Not available
1 : Not available
0 : 0 page
1 : 1 page
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
0 : Ceramic oscillation
1 : RC oscillation
b7 b6
0 0 : φ = f(XIN)/2
(high-speed mode)
0 1 : φ = f(XIN)/8
(middle-speed mode)
1 0 : Applied from on-chip oscillator
1 1 : φ = f(XIN)
(double-speed mode)
(Note 2)
At reset
R W
0
0
0
0
0
0
0
1
Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is
disable to write any data to the bit. However, by reset the bit is initialized and
can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU “M37540RSS”.)
2: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 2.5.14 Structure of CPU mode register
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Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
0 Serial I/O1 receive
interrupt request bit
1 Serial I/O1 transmit interrupt
request bit
2 INT 0 interrupt request bit
3 INT 1 interrupt request bit
4 Key-on wake up interrupt
request bit
5 CNTR 0 interrupt request bit
6 CNTR 1 interrupt request bit
7 Timer X interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.5.15 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
Name
0 Timer Y interrupt request bit
1 Timer Z interrupt request bit
2 Timer A interrupt request bit
3 Serial I/O2 interrupt request
bit
4 AD converter interrupt
request bit
5 Timer 1 interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✕
0
✕
6 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.5.16 Structure of Interrupt request register 2
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Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
16]
Name
Function
0 Serial I/O1 receive
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
B
interrupt enable bit
1 Serial I/O1 transmit interrupt
enable bit
2 INT 0 interrupt enable bit
3 INT 1 interrupt enable bit
4 Key-on wake up interrupt
enable bit
5 CNTR 0 interrupt enable bit
6 CNTR 1 interrupt enable bit
7 Timer X interrupt enable bit
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.5.17 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Name
0 Timer Y interrupt
enable bit
1 Timer Z interrupt enable bit
2 Timer A interrupt enable bit
3 Serial I/O2 interrupt enable bit
4 AD conversion interrupt
enable bit
5 Timer 1 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
0
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
7
Fig. 2.5.18 Structure of Interrupt control register 2
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2.5 Timer Y and timer Z
2.5.3 Timer mode (timer Y and timer Z)
The basic operation of Timer Y and Timer Z are the same. In this section, Timer Y is explained.
(1) Operation description
Prescaler Y counts the count source selected by the timer Y count source selection bits. Each time
the count clock is input, the contents of Prescaler Y is decremented by 1.
When the contents of Prescaler Y reach “0016”, an underflow occurs at the next count clock, and the
prescaler Y latch is reloaded into Prescaler Y and count continues. The division ratio of Prescaler
Y is 1/(n+1) provided that the value of Prescaler Y is n.
The contents of Timer Y is decremented by 1 each time the underflow signal of Prescaler Y is input.
When the contents of Timer Y reach “00 16”, an underflow occurs at the next count clock, and the
timer Y primary latch is reloaded into Timer Y and count continues.
(In the timer mode, the contents of timer Y primary latch is counted. Timer Y secondary latch is not
used in this mode.)
The division ratio of Timer Y is 1/(m+1) provided that the value of Timer Y is m. Accordingly, the
division ratio of Prescaler Y and Timer Y is provided as follows that the value of Prescaler Y is n
and the value of Timer Y is m.
Division ratio =
1
(n+1) ✕ (m+1)
In the timer mode, writing to “latch only” or “latches and Prescaler Y and timer Y primary” can be
selected by the setting value of the timer Y write control bit.
Timer Y can stop counting by setting “1” to the timer Y count stop bit.
Also, when timer Y underflows, the timer Y interrupt request bit is set to “1”.
Timer Y reloads the value of latch when counting is stopped by the timer count stop bit.
(When timer is read out while timer is stopped, the value of latch is read. The value of timer can be
read out only while timer is operating.)
(2) Timer mode setting method
Figure 2.5.19 shows the setting method for timer mode of Timer Y.
When Timer Z is used, registers are set by the same method.
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Process 1: Disable timer Y interrupt.
b7
b0
0
Interrupt control register 2 (ICON2) [Address 3F16]
Timer Y interrupt disabled
Process 2: Set timer Y, Z mode register.
b7
b0
1
0
Timer Y, Z mode register (TYZM) [Address 2016]
Timer mode
Timer Y write control bit
0: Write to latch and timer simultaneously
1: Write to only latch
Timer Y count stop
Process 3: Set timer Y count source (Note 1)
b7
b0
Timer count source set register (TCSS) [Address 2E16]
0
Timer Y count source selection bits
b3 b2
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : On-chip oscillator output (Note 2)
1 : Not available
Notes 1: For timer Z, f(XIN), f(XIN)/2, or timer Y underflow can be selected.
2: Set the on-chip oscillator oscillation to be enabled by bit 3 (on-chip oscillator
oscillation control bit) of CPU mode register.
Process 4: Set the count value to timer Y.
• Set the count value to prescaler Y and timer Y primary
Prescaler Y (PREY) (Address 2116)
Count value
Timer Y primary (TYP) (Address 2316)
Count value
Note: In the timer mode, the timer Y secondary is not used.
Process 5: In order not to execute the no requested interrupt processing,
set “0” (no requested) to the timer Y interrupt request bit.
b7
b0
0
Interrupt request register 2 (IREQ2) [Address 3D16]
No timer Y interrupt request issued
Process 6: When timer Y interrupt is used, set “1” (interrupt enabled)
to the timer Y interrupt enable bit.
b7
b0
1
Interrupt control register 2 (ICON2) [Address 3F16]
Timer Y interrupt enabled
Process 7: Start counting of timer Y.
b7
b0
0
0
Timer Y, Z mode register (TYZM) [Address 2016]
Timer Y count start
Fig. 2.5.19 Setting method for timer mode
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2.5 Timer Y and timer Z
(3) Application example of timer mode
Outline: Pulses generated corresponding to the water flow rate are counted for a fixed period
(100 ms), and the water flow rate during this period is calculated.
Specifications: Pulses generated corresponding to the water flow rate are input to the P1 4/CNTR1
pin and counted using timer X.
The contents of timer X are read in the timer Y interrupt processing routine generated
after 100 ms from the start of counting pulses, and the water flow rate during 100
ms is calculated.
Operation clock: f(XIN) = 8 MHz, high-speed mode
Figure 2.5.20 shows an example of peripheral circuit, Figure 2.5.21 shows the method of measuring
water flow rate, and Figure 2.5.21 shows an example of control procedure.
7540 Group
Water flow rate sensor
Water
flow
P14/CNTR0
Blades rotate in proportion to
water flow and generate pulses.
The faster the water flow,
the shorter the pulse period.
Fig. 2.5.20 Example of peripheral circuit
100 ms
Timer Y interrupt request bit
CNTR0 pin input
Timer X, timer Y
start counting.
Timer X counting (Note)
Timer Y interrupt processing routine
• Timer X, timer Y stop counting.
• Timer X is read out.
Note: Counting rising edges.
• Flow rate during 100 ms = (FF16–read value of timer Y) ✕ flow rate per pulse
Fig. 2.5.21 Method of measuring water flow rate
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Flow rate measuring routine
Set “0” to the CNTR0 interrupt enable bit.
(CNTR0 interrupt disabled)
Set “0” to the timer X interrupt enable bit.
(Timer X interrupt disabled)
Set “0” to the timer Y interrupt enable bit.
(Timer Y interrupt disabled)
Timer Y interrupt processing routine
Set timer X mode register
Set port P14 to the input mode.
1
0
1 1 1 0 TXM(Address 2B16)
Timer X count stop
Set timer X mode register
1
0
11 1 0
TXM(Address 2B16)
Set timer Y, Z mode register
10
Event counter mode
Count at falling edge
Timer X count stop
Set timer Y, Z mode register
1 0
0 TYZM(Address 2016)
Timer mode
W ritin g to la t c h a n d tim e r s im u lta n e o u s ly
Timer Y count stop
0 TYZM(Address 2016)
Timer Y count stop
(Prescaler X setting value “FF16” timer X setting
value “FF16”) – (Prescaler X count value, timer X
count value)
← The numbeer of event within 100 ms
RTI
Set timer count source set register
1 0
0 0
TCSS(Address 2E16)
Timer Y count source:
f(XIN)/16 selected
Set value to timer X
“FF 16”
Prescaler X (Address 2C16)
“FF 16”
Timer X (Address 2D16)
Set value to timer Y (Note)
“C716”
Prescaler Y (Address 2116)
“F916”
Timer Y primary (Address 2316)
Note : 100 ms = 1/8 MHz ✕ 16 ✕ (C716 + 1) ✕ (F916 + 1)
Timer Y
division
ratio
Set “0” to the timer Y interrupt request bit.
Prescaler Y
setting
value
Timer Y
primary
setting
value
Set “1” to the timer Y interrupt enable bit.
(Timer Y interrupt enabled)
Set timer X mode register
1
0
0 1 1 0 TXM(Address 2B16)
Timer X count start
Set timer Y, Z mode register
0 0
0 TYZM(Address 2016)
Timer Y count start
END
Fig. 2.5.22 Example of control procedure
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2.5 Timer Y and timer Z
2.5.4 Programmable waveform generation mode (timer Y and timer Z)
The basic operation of Timer Y and Timer Z are the same. In this section, Timer Y is explained.
(1) Operation description
In the programmable waveform generation mode, timer counts the setting value of timer Y primary
(TYP) and the setting value of timer Y secondary (TYS) alternately, the waveform whose polarity is
inverted each time Timer Y underflows is output from P0 1/TYOUT pin.
When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch only”.
Also, set the port P0 1 direction registers to output mode.
The active edge of output waveform is set by the timer Y output level latch. When “0” is set to the
timer Y output level latch, “H” interval by the setting value of TYP or “L” interval by the setting value
of TYS is output alternately. When “1” is set to the timer Y output level latch, “L” interval by the
setting value of TYP or “H” interval by the setting value of TYS is output alternately.
Also, in this mode, the primary interval and the secondary interval of the output waveform can be
extended respectively for 0.5 cycle of timer count source clock by setting the timer Y primary waveform
extension control bit (b2) and the timer Y secondary waveform extension control bit (b3) of PUM to
“1”. As a result, the waveforms of more accurate resolution can be output.
When b2 and b3 of PUM are used, the frequency and duty of the output waveform are as follows;
Waveform frequency: FYOUT=
2 ✕ (TMYCL)
(2 ✕ (TYP+1)+EXPYP)+(2 ✕ (TYS+1)+EXPYS))
2 ✕ (TYP+1)+EXPYP
Duty: DYOUT= (2 ✕ (TYP+1)+EXPYP)+(2 ✕ (TYS+1)+EXPYS))
TMYCL: Timer Y count source (frequency)
TYP: Timer Y primary
TYS: Timer Y secondary
EXPYP (1 bit): Timer Y primary waveform extension control bit
EXPYS (1 bit): Timer Y secondary waveform extension control bit
In the programmable waveform generation mode, when values of the TYP, TYS, EXPYP and EXPYS
are changed, the output waveform is changed at the beginning (timer Y primary waveform interval)
of waveform period.
When the count values are changed, set values to the TYS, EXPYP and EXPYS first. After then, set
the value to TYP. The values are set all at once at the beginning of the next waveform period when
the value is set to TYP. (When writing at timer stop is executed, writing to TYP at last is required.)
Timer Y can stop counting by setting “1” to the timer Y count stop bit.
Also, when timer Y underflows, the timer Y interrupt request bit is set to “1”.
Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When
timer is read out while timer is stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
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Notes 1: In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are
valid by writing to TYP because the setting to them is executed all at once by writing to
TYP. Even when changing TYP is not required, write the same value again.
2: In the programmable waveform generation mode, when the setting value is changed while
the waveform is output, set by software in order not to execute the writing to TYP and the
timing of timer underflow during the secondary interval simultaneously.
An example of a measurement is shown below.
ex.) The underflow by the primary and the underflow by secondary are stored by polling
etc. using timer Y interrupt.
Writing is performed in by judging that there is no problem if the underflow by secondary
is completed with reference to primary write operation before.
(Depending on a primary and a secondary setting values, and primary write timing, it
may be impossible.)
3: The waveform extension function by the timer Y waveform extension control bits can be
used only when “00 16” is set to Prescaler Y.
When the value other than “00 16” is set to Prescaler Y, be sure to set “0” to EXPYP and
EXPYS.
The waveform extension function by the timer Z waveform extension control bits can be
used only when “00 16” is set to Prescaler Z. When the value other than “00 16” is set to
Prescaler Z, be sure to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow
is selected as the timer Z count source, the waveform extension function cannot be used.
4: When using this mode, be sure to set “1” to the timer Y write control bit to select “write
to latch only”.
5: When TYS is read out, the undefined value is read out. However, while timer Y counts the
setting value of TYS, the count value during the secondary interval can be obtained by
reading the timer Y primary.
6: In order to use TY OUT pin, set “1” to bit 1 of the port P0 direction register (output mode).
Figure 2.5.23 shows the timing diagram of the programmable waveform generation mode.
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● When “0316” is set to TYP and “0216” is set to TYS.
Timer Y count clock
“0” is written
Timer Y count stop bit
Timer Y
secondary
reload
Count start
0316
Contents of timer Y
Timer Y
primary
reload
0216 0116 0016 0216 0116 0016
Underflow
Timer Y interrupt request bit
0316
Timer Y
secondary
reload
0216 0116 0016 0216 0116
Underflow
Underflow
(Note 2)
(Note 2)
(Note 2)
“0” is written
Timer Y output level latch
Waveform output start
Waveform output inverted
Waveform output inverted
Waveform output inverted
Initialized to “L”
TYOUT pin output
(Note 1)
Secondary waveform extension
Notes 1: In this case, timer Y primary waveform is not extended, timer Y secondary waveform is extended.
2: In this time, “0” is written to the timer Y interrupt request bit or the timer Y interrupt request bit
is cleared to “0” by accepting the timer Y interrupt request.
Fig. 2.5.23 Timing diagram of programmable waveform generation mode
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(2) Programmable waveform generation mode setting method
Figure 2.5.24 and Figure 2.5.25 show the setting method for programmable waveform generation
mode of timer Y.
When timer Z is used, registers are set by the same method.
Process 1: Disable timer Y interrupt.
b7
b0
0
Interrupt control register 2 (ICON2) [Address 3F16]
Timer Y interrupt disabled
Process 2: Set timer Y, Z mode register.
b7
b0
1 1
1
Timer Y, Z mode register (TYZM) [Address 2016]
Programmable waveform generation mode
Write to only latch (Note)
Timer Y count stop
Note: When using this mode, be sure to set “1” to the timer Y write control bit
to select “write to latch only”.
Process 3: Set timer Y, Z waveform output control register.
b7
b0
Timer Y, Z waveform output control register (PUM) [Address 2416]
Timer Y primary waveform extension control bit (No te)
0: Waveform not extended
1: Waveform extended
Timer Y secondary waveform extension control bit (Note)
0: Waveform not extended
1: Waveform extended
Timer Y output level latch
0: Initial state at stop: “L”, “H” interval by TYP setting value,
“L” interval by TYS setting value
1: Initial state at stop: “H”, “L” interval by TYP setting value,
“H” interval by TYS setting value
Note: The waveform extension function by the timer Y waveform extension
control bits can be used only when “0016” is set to prescaler Y.
When the value other than “0016” is set to prescaler Y, be sure to set “0”
to EXPYP and EXPYS.
The waveform extension function by the timer Z waveform extension
control bits can be used only when “0016” is set to prescaler Z.
When the value other than “0016” is set to prescaler Z, be sure to set “0”
to EXPZP and EXPZS.
Also, when the timer Y underflow is selected as the timer Z count source,
the waveform extension function cannot be used.
Process 4: Set TYOUT pin to the output (Note).
b7
b0
1
Port P0 direction register (P0D) [Address 0116]
Set P01/TYOUT pin as the output mode
Note: For timer Z, set TZOUT pin as the output by bit 2 of P0D.
Fig. 2.5.24 Setting method for programmable waveform generation mode (1)
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2.5 Timer Y and timer Z
Process 5: Set timer Y count source (Note 1).
b7
b0
Timer count source set register (TCSS) [Address 2E16]
0
Timer Y count source selection bits
b3 b2
0
0
1
1
0 : f(XIN)/16
1 : f(XIN)/2
0 : On-chip oscillator output (Note 2)
1 : Not available
Notes 1: For Timer Z, f(XIN)/16, f(XIN)/2, or timer Y underflow can be selected.
However, when the timer Z waveform expansion function is used,
do not select the timer Y underflow for the timer Z count source.
2: Set the on-chip oscillator oscillation to be enabled by bit 3 (on-chip oscillator
oscillation control bit) of CPU mode register.
Process 6: Set the count value to timer Y (Note 1).
• Set the count value to prescaler Y, timer Y secondary and timer Y primary
Prescaler Y (PREY) (Address 2116) (Note 2)
Count value
Timer Y secondary (TYS) (Address 2216)
Count value
Timer Y primary (TYP) (Address 2316) (Notes 3, 4)
Count value
Notes 1: In the programmable waveform generation mode, values of TYS,
EXPYP, and EXPYS are valid by writing to TYP. Even when
changing TYP is not required, write the same value again.
2: When the timer Y waveform extension function is used, be sure to set
“0016” to prescaler Y.
3: In the programmable waveform generation mode, when the setting
value is changed while the waveform is output, set by software in
order not to execute the writing to TYP and the timing of timer Y
underflow during the secondary interval simultanesously.
4: Count values of the primary interval and secondary interval can be
checked by reading the TYP (TYS is undefined at read).
Process 7: In order not to execute the no requested interrupt processing,
set “0” (no requested) to the timer Y interrupt request bit.
b7
b0
0
Interrupt request register 2 (IREQ2) [Address 3D16]
No timer Y interrupt request issued
Process 8: When Timer Y interrupt is used, set “1” (interrupt enabled)
to the timer Y interrupt enable bit.
b7
b0
1
Interrupt control register 2 (ICON2) [Address 3F16]
Timer Y interrupt enabled
Process 9: Start counting of timer Y.
b7
b0
0 1
1
Timer Y, Z mode register (TYZM) [Address 2016]
Timer Y count start
Fig. 2.5.25 Setting method for programmable waveform generation mode (2)
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2.5 Timer Y and timer Z
(3) Application example of programmable waveform generation mode
Outline: The waveform extension function is used and the waveform output is executed.
Specifications: The “H” width generated by TYP and the “L” width generated by TYS are output. Set
each waveform extension function to be valid, and set the duty ratio to be 2:1. The
frequency is 40 kHz.
Operation clock: f(X IN) = 8 MHz, high-speed mode
Figure 2.5.26 shows an example of waveform output and Figure 2.5.27 shows an example of control
procedure.
● 40 kHz pulse is output
Duty ratio
2
:
16.7 µs
1
8.3 µs
TYOUT pin output
Waveform extended
Waveform extended
Fig. 2.5.26 Example of waveform output
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2.5 Timer Y and timer Z
RESET
Initialization
X: This bit is not used here. Set it to “0” or “1” arbitrary.
SEI
CLD
CLT
CPUM(Address 3B16)
← 10000X002
Wait until f(XIN) oscillation is stabilized (Note 1)
CPUM(Address 3B16)
← 00000X002
Set “0” to the timer Y interrupt enable bit.
(Timer Y interrupt disabled)
Set timer Y, Z mode register
1 1
1
TYZM(Address 2016)
Programmable waveform
generation mode
Writing to only latch (Note 2)
Timer Y count stop
Set timer Y, Z waveform output control register
0
1 1 PUM(Address 2416)
Timer Y primary waveform
generation extended (Note 3)
Timer Y secondary waveform
generation extended (Note 3)
Initial state: “L”, TYP: “H” interval,
TYS: “L” interval
Set port P01 to the output mode.
Set timer count source set register
1 0
0 1
TCSS(Address 2E16)
Timer Y count source:
f(XIN)/2 selected
Set value to timer Y (Notes 3, 4, 5, 6)
“0016”
Prescaler Y (Address 2116)
“2016”
Timer Y secondary (Address 2216)
“4116”
Timer Y primary (Address 2316)
Set “0” to the timer Y interrupt request bit.
Set “1” to the timer Y interrupt enable bit.
(Timer Y interrupt enabled)
Notes 1: For the concrete time, ask the oscillator manufacture.
2: When using this mode, be sure to select “write to latch
only”.
3: The waveform extension function by the timer Y waveform
extension control bits can be used only when “0016” is set
to prescaler Y.
When the value other than “0016” is set to prescaler Y, be
sure to set “0” to EXPYP and EXPYS.
4: In the programmable waveform generation mode, values of
TYS, EXPYP, and EXPYS are valid by writing to TYP. Even
when changing TYP is not required, write the same value
again.
5: In the programmable waveform generation mode, when the
setting value is changed while the waveform is output, set
by software in order not to execute the writing to TYP and
the timing of timer Y underflow during the secondary
interval simultanesously.
6: Count values of the primary interval and secondary interval
can be checked by reading TYP (TYS is undefined at read).
Set timer Y, Z mode register
0 1
1
TYZM(Address 2016)
Timer Y count start
CLI
Processing
Fig. 2.5.27 Example of control procedure
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2.5 Timer Y and timer Z
2.5.5 Programmable one-shot generation mode (timer Z)
(1) Operation description
In the programmable one-shot generation mode, the one-shot pulse by the setting value of timer Z
primary can be output from P02/TZ OUT pin by software or external trigger to the P37/INT 0 pin. When
using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch only”. Also,
set the port P0 2 direction registers to output mode. In this mode, the timer Z secondary (TZS) is not
used.
The active edge of output waveform is set by the timer Z output level latch. When “0” is set to the
timer Z output level latch, “H” pulse during the interval of the timer Z primary (TZP) setting value is
output. When “1” is set to the timer Z output level latch, “L” pulse during the interval of the TZP
setting value is output.
Also, in this mode, the interval of the one-shot pulse output can be extended for 0.5 cycle of timer
count source clock by setting the timer Z primary waveform extension control bit (EXPZP) to “1”.
As a result, the waveforms of more accurate resolution can be output.
During the one-shot pulse output interval, the one-shot pulse output can be stopped forcibly by
writing “0” to the timer Z one-shot start bit.
In the programmable one-shot generation mode, when the count values are changed, set value to
the EXPZP first. After then, set the value to TZP. The values are set all at once at the beginning of
the next one-shot pulse when the value is set to TZP. (Even when writing at timer stop is executed,
writing to TZP at last is required.)
Timer Z can stop counting by setting “1” to the timer Z count stop bit.
Also, when timer Z underflows, the timer Z interrupt request bit is set to “1”.
Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit.
(When timer is read out while timer is stopped, the value of latch is read. The value of timer can be
read out only while timer is operating.)
Notes 1: In the programmable one-shot generation mode, the value of EXPZP becomes valid by
writing to TZP. Even when changing TZP is not required, write the same value again.
2: In the programmable one-shot generation mode, when the setting value is changed while
the waveform is output, set by software in order not to execute the writing to TZP and the
timing of timer underflow simultaneously.
An example of a measurement is shown below.
ex.) The underflow of timer is stored by polling etc. using timer Z interrupt.
Writing to primary is performed in by judging that there is no problem if the underflow
by secondary is completed with reference to primary write operation before.
(Depending on a primary setting value, primary write timing, software and timing of
external trigger to INT 0 pin, it may be impossible.)
3: The waveform extension function by the timer Z waveform extension control bits can be
used only when “00 16 ” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP. Also,
when the timer Y underflow is selected as the timer Z count source, the waveform extension
function cannot be used.
4: When using this mode, be sure to set “1” to the timer Z write control bit to select “write to
latch only”.
5: In order to use TZOUT pin, set “1” to bit 2 of the port P0 direction register (output mode).
6: Stop Timer Z to change the INT 0 pin one-shot trigger control bit and INT 0 pin one-shot
trigger active edge selection bit.
Figure 2.5.28 shows the timing diagram of the programmable one-shot generation mode.
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2.5 Timer Y and timer Z
● When “0316” is set to TZP
Timer Z count clock
“0” is written
Timer Z count stop bit
“1” is written
One-shot start bit
Set to “1” by
INT0 pin input
trigger
INT0 pin input
(Note 1)
Timer Z
primary
reload
Count start
0316
Contents of timer Z
0216 0116 0016
Timer Z
primary
reload
Count
start
0316
0216 0116 0016 0316
Underflow
Timer Z interrupt request bit
Underflow
(Note 3)
“0” is written
Timer Z output level latch
Waveform output start
TZOUT pin output
(Note 2)
Waveform output end
Waveform output start
Waveform output end
Initialized to “L”
Waveform extension
Waveform extension
Notes 1: In this case, INT0 pin one-shot trigger valid.
2: In this case, timer Z primary waveform is extended.
3: In this time, “0” is written to the timer Z interrupt request bit or the timer Z interrupt request bit
is cleared to “0” by accepting the timer Z interrupt request.
Fig. 2.5.28 Timing diagram of programmable one-shot generation mode
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2.5 Timer Y and timer Z
(2) Event counter mode setting method
Figure 2.5.29 to Figure 2.5.31 show the setting method for programmable one-shot generation mode
of timer Z.
Process 1: Disable the interrupt.
b7
b0
0
Interrupt control register 1 (ICON1) [Address 3E16]
INT0 interrupt disabled
b7
b0
0
Interrupt control register 2 (ICON2) [Address 3F16]
Timer Z interrupt disabled
Process 2: Set timer Y, Z mode register.
b7
b0
1 1 1 0
Timer Y, Z mode register (TYZM) [Address 2016]
Programmable one-shot generation mode
Write to only latch (Note)
Timer Y count stop
Note: When using this mode, be sure to select “write to latch only”.
Process 3: Set timer Y, Z waveform output control register.
b7
b0
Timer Y, Z waveform output control register (PUM) [Address 2416]
Timer Z primary waveform extension control bit (Note 1)
0: Waveform not extended
1: Waveform extended
Timer Z output level latch
0: Initial state at stop: “L”, “H” interval by TZP setting value,
“L” interval by TZ S setting value
1: Initial state at stop: “H”, “L” interval by TZP setting value,
“H” interval by TZS setting value
INT0 pin one-shot trigger control bit (Note 2)
0: INT0 pin one-shot trigger invalid
1: INT0 pin one-shot trigger valid
INT0 pin one-shot trigger active edge selection bit (Note 2)
0: Falling edge trigger
1: Rising edge trigger
Notes 1: The waveform extension function by the timer Z waveform extension control bits can be used
only when “0016” is set to prescaler Z.
When the value other than “0016” is set to prescaler Z, be sure to set “0” to EXPZP.
Also, when the timer Y underflow is selected as the timer Z count source, the waveform
extension function cannot be used.
2: Stop timer Z to change these bits.
Process 4: Set TZOUT pin to the output (Note).
b7
b0
1
Port P0 direction register (P0D) [Address 0116]
Set P02/TZOUT pin as the output mode
Fig. 2.5.29 Setting method for programmable one-shot generation mode (1)
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2.5 Timer Y and timer Z
Process 5: When the trigger by INT0 pin input is selected:
Set port P3 direction register, pull-up control register and port P1P3 control register
b7
b0
Port P3 direction register (P3D) [Address 0716]
0
Set P37/INT0 pin as the input mode
b7
b0
Pull-up control register (PULL) [Address 1616]
P37 pull-up control bit
0: Pull-up Off
1: Pull-up On
b7
b0
Port P1P3 control register (P1P3C) [Address 1716]
P37/INT0 input level selection bit
0: CMOS level
1: TTL level
Process 6: Set the timer Z count source.
b7
b0
Timer count source set register (TCSS) [Address 2E16]
0
Timer Z count source selection bits
b5 b4
00
01
10
11
: f(XIN)/16
: f(XIN)/2
: Timer Y underflow (Note)
: Not available
Note: When the timer Z waveform extension function is used,
do not select the timer Y underflow as the timer Z count source.
Process 7: Set the one-shot pulse width (Note 1).
• Set the count value to prescaler Z and timer Z primary
Prescaler Z (PREZ) [Address 2516] (Note 2)
Count value
Timer Z primary (TZP) [Address 2716] (Note 3)
Count value
Notes 1: In the programmable one-shot generation mode, TZS is not used.
When the count setting value is changed, value of EXPZP is valid by
writing to TZP. Even when changing TZP is not required, write the
same value again.
2: When the timer Z waveform extension function is used, be sure to set
“0016” to prescaler Z.
3: In the programmable one-shot generation mode, when the setting
value is changed while the waveform is output, set by software in
order not to execute the writing to TZP and the timing of timer Z
underflow simultanesously.
Process 8: Set the standby state to accept the one-shot start trigger (Note).
b7
0 1 1 0
b0
Timer Y, Z mode register (TYZM) [Address 2016]
Timer Z count start
Note: When the INT0 pin one-shot trigger control bit of PUM is set to“valid”,
timer Z counting is started by the input of trigger to INT0 pin after this setting.
Fig. 2.5.30 Setting method for programmable one-shot generation mode (2)
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2.5 Timer Y and timer Z
Process 9: In order not to execute the no requested interrupt processing,
set “0” (no requested) to the timer Z interrupt request bit.
b7
b0
0
Interrupt request register 2 (IREQ2) [Address 3D16]
No Timer Z interrupt request issued
● When the INT0 pin one-shot trigger control bit of PUM is set to “valid” and
the INT0 interrupt is used, set the following;
b7
b0
Interrupt edge selection register (INTEDGE) [Address 3A16]
INT0 interrupt edge selection bit
0: Falling edge active
1: Rising edge active
b7
b0
Interrupt request register 1 (IREQ1) [Address 3C16]
0
No INT0 interrupt request issued
Process 10: When the interrupt is used, set “1” (interrupt enabled)
to the corresponding interrupt enable bit.
b7
b0
1
Interrupt control register 1 (ICON1) [Address 3E16]
INT0 interrupt enabled (No te)
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
1
Timer Y interrupt enabled
Note: When the INT0 pin one-shot trigger control bit is set to “valid”,
the INT0 interrupt can be accepted after this setting.
Process 11: Start counting of timer Z.
b7
b0
1
One-shot start register (ONS) [Address 2A16]
Timer Z one-shot start (Note)
● When the INT0 pin one-shot trigger control bit of PUM is set to “valid”,
the timer Z count is started by input of trigger to the INT0 pin.
Note: Pulse is output from TZOUT pin. After output, this bit is initialized to “0”.
Fig. 2.5.31 Setting method for programmable one-shot generation mode (3)
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2.5 Timer Y and timer Z
(3) Application example of programmable one-shot generation mode
Outline: The phase control signal to the load is output by using the programmable one-shot generation
mode of Timer Z.
Specifications: The phase control signal to the load is output from the P0 2/TZ OUT pin using the
programmable one-shot generation mode of timer Z.
• Count source: f(XIN)/16
• Rising edges of the signal input to the P3 7/INT0 pin from the trigger detection circuit
are detected.
• A triac is turned on at the “H” level.
The period of the feedback signal input from the load is measured, analyzed, and
used to adjust the phase control signal.
Operation clock: f(X IN) = 8 MHz, high-speed mode
For the measurement of the period of the feedback signal, refer to the period measurement mode
of the using timer.
Figure 2.5.32 shows an example of peripheral circuit, Figure 2.5.33 shows an example of an operation
timing, and Figure 2.5.34 shows an example of a control procedure.
7540 Group
Feedback signal
Port
Load
Phase control signal
P02/TZOUT
Trigger detection circuit
P37/INT0
VAC
Fig. 2.5.32 Example of peripheral circuit
VAC power source
Contents of timer Z
INT0 pin input
RL
Writing to latch in
INT0 interrupt
processing routine
RL
RL
UF
UF
RL
RL
RL
UF
UF
UF
000016
UF
TZOUT pin output
Fig. 2.5.33 Example of operation timing
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2.5 Timer Y and timer Z
RESET
X: This bit is not used here. Set it to “0” or “1” arbitrary.
Initialization
SEI
CLD
CLT
← 10000X002
CPUM(Address 3B16)
Wait until f(XIN) oscillation is stabilized (Note 1)
CPUM(Address 3B16)
← 00000X002
INT0 interrupt processing routine
Set “0” to the timer Z interrupt enable bit.
(Timer Z interrupt disabled)
Set timer Y, Z mode register
1 11 0
TYZM(Address 2016)
Programmable one-shot
generation mode
Writing to only latch (Note 2)
Timer Z count stop
Change of timer Z
RTI
Set timer Y, Z waveform output control register
1 1 0
1
PUM(Address 2416)
Timer Z primary waveform generation
extended (Note 3)
Initial state: “L”, TZP: “H” interval, TZS:
“L” interval, stop at “L” after underflow
INT0 pin one-shot trigger valid (Note 4)
INT0 pin rising edge trigger (Note 4)
Set port P02 to the output mode.
Set port P37 to the input mode.
Set pull-up control register
Set port P1P3 control register
Set timer count source set register (Note 3)
1 0 0 0
TCSS(Address 2E16)
Timer Z count source:
f(XIN)/16 selected
Set value to timer Z (Notes 3, 5, 6)
Prescaler Z (Address 2516)
Timer Z primary (Address 2716)
Set the standby state to accept one-shot start
trigger
0 1 1 0
TYZM(Address 2016)
Timer Z count start (Note 7)
Set the interrupt edge selection register
1
INTEDGE(Address 3A16)
Notes 1: For the concrete time, ask the oscillator manufacture.
2: When using this mode, be sure to select “write to latch
only”.
3: The waveform extension function by the timer Z waveform
extension control bits can be used only when “0016” is set
to prescaler Z.
When the value other than “0016” is set to prescaler Z, be
sure to set “0” to EXPZP. Also, when the timer Y underflow
is selected as the timer Z count source, the waveform
extension function cannot be used.
4: Stop timer Z to change the INT0 pin one-shot trigger
control bit and INT0 one-shot trigger active edge selection
bit.
5: In the programmable one-shot generation mode, the value
of EXPZP is valid by writing to TZP. Even when changing
TZP is not required, write the same value again.
6: In the programmable one-shot generation mode, when the
setting value is changed while the waveform is output, set
by software in order not to execute the writing to TZP and
the timing of timer Z underflow simultanesously.
7: In this state, timer count is not started.
INT0 rising edge active
Set “0” to the INT0 interrupt request bit.
Set “1” to the INT0 interrupt enable bit.
(INT0 interrupt enabled)
CLI
Phase control processing
● Period measurement of feedback signal
● Analyze of measured value
(determination of timer Z setting value)
Fig. 2.5.34 Example of control procedure
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2.5 Timer Y and timer Z
2.5.6 Programmable wait one-shot generation mode (timer Z)
(1) Operation description
In the programmable wait one-shot generation mode, the one-shot pulse by the setting value of timer
Z secondary (TZS) can be output from P0 2/TZOUT pin by software or external trigger to P37/INT0 pin
after the wait by the setting value of the timer Z primary (TZP). When using this mode, be sure to
set “1” to the timer Z write control bit to select “write to latch only”. Also, set the port P0 2 direction
registers to output mode.
The active edge of output waveform is set by the timer Z output level latch. When “0” is set to the
timer Z output level latch, after the wait during the interval of the TZP setting value, “H” pulse during
the interval of the TZS setting value is output. When “1” is set to the timer Z output level latch, after
the wait during the interval of the TZP setting value, “L” pulse during the interval of the TZS setting
value is output.
Also, in this mode, the intervals of the wait and the one-shot pulse output can be extended for 0.5
cycle of timer count source clock by setting the timer Z primary waveform extension control bit
(EXPZP) and the timer Z secondary waveform extension control bit (EXPZS) to “1”. As a result, the
waveforms of more accurate resolution can be output.
In the programmable wait one-shot generation mode, the trigger by software or the external INT0 pin
can be accepted by writing “0” to the timer Z count stop bit after the count value is set. (At the time
when “0” is written to the timer Z count stop bit, Timer Z stops.)
By writing “1” to the timer Z one-shot start bit, or by inputting the valid trigger to the INT0 pin after
the trigger to the INT 0 pin becomes valid by writing “1” to the INT0 pin one-shot trigger control bit,
Timer Z starts counting.
While Timer Z counts the TZP, the initial value of the TZ OUT pin output is retained. When Timer Z
underflows, the value of TZS is reloaded, at the same time, the output of TZ OUT pin is inverted.
When Timer Z underflows, the output of TZOUT pin is inverted again and Timer Z stops. When also
the trigger of INT 0 pin is accepted, the contents of the one-shot start bit is changed to “1” by
hardware.
The falling or rising can be selected as the edge of the valid trigger of INT0 pin by the INT0 pin oneshot trigger edge selection bit.
During the wait interval and the one-shot pulse output interval, the one-shot pulse output can be
stopped forcibly by writing “0” to the timer Z one-shot start bit.
In the programmable wait one-shot generation mode, when the count values are changed, set values
to the TZS, EXPZP and EXPZS first. After then, set the value to TZP. The values are set all at once
at the beginning of the next wait interval when the value is set to TZP. (When writing at timer stop
is executed, writing to TZP at last is required.)
Timer Z can stop counting by setting “1” to the timer Z count stop bit.
Also, when timer Z underflows, the timer Z interrupt request bit is set to “1”.
Timer Z reloads the value of latch when counting is stopped by the timer Z count stop bit.
(When timer is read out while timer is stopped, the value of latch is read. The value of timer can be
read out only while timer is operating.)
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2.5 Timer Y and timer Z
Notes 1: In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS
are valid by writing to TZP. Even when changing TZP is not required, write the same value
again.
2: In the programmable wait one-shot generation mode, when the setting value is changed
while the waveform is output, set by software in order not to execute the writing to TZP and
the timing of timer underflow during the secondary interval simultaneously.
An example of a measurement is shown below.
ex.) The underflow by the primary and the underflow by secondary are stored by polling etc.
using timer Z interrupt.
Writing to primary is performed in by judging that there is no problem if the underflow
by secondary is completed with reference to primary write operation before.
(Depending on a primary setting value, primary write timing, software and timing of
external trigger to INT 0 pin, it may be impossible.)
3: The waveform extension function by the timer Z waveform extension control bits can be
used only when “00 16” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to set “0” to EXPZP and
EXPZS. Also, when the timer Y underflow is selected as the timer Z count source, the
waveform extension function cannot be used.
4: When using this mode, be sure to set “1” to the timer Z write control bit to select “write to
latch only”.
5: When TZS is read out, the undefined value is read out. However, while Timer Z counts the
setting value of TZS (during one-shot output), the count value during the secondary interval
can be obtained by reading TZP.
6: In order to use TZ OUT pin, set “1” to bit 2 of the port P0 direction register (output mode).
7: Stop Timer Z to change the INT 0 pin one-shot trigger control bit and INT 0 pin one-shot
trigger active edge selection bit.
Figure 2.5.35 shows the timing diagram of the programmable wait one-shot generation mode.
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2.5 Timer Y and timer Z
● When “0316” is set to TZP and “0416” is set to TZS.
Timer Z count clock
“0” is written
Timer Z count stop bit
“1” is written
One-shot start bit
Set to “1” by
INT0 pin input
trigger
INT0 pin input
(Note 1)
0316
Contents of timer Z
Count
start
Timer Z
secondary
reload
Count start
0216 0116 0016
0416
0316 0216 0116 0016
Underflow
Timer Z interrupt request bit
Timer Z
primary
reload
0316
Underflow
(Note 3)
(Note 3)
“0” is written
Timer Z output level latch
Wait start
Waveform output start
Waveform output end
Initialized to “L”
TZOUT pin output
(Note 2)
Waveform extension
Notes 1: In this case, INT0 pin one-shot trigger valid (rising edge trigger selected).
2: In this case, timer Z primary waveform is extended, timer Z secondary waveform is not extended.
3: In this time, “0” is written to the timer Z interrupt request bit or the timer Z interrupt request bit
is cleared to “0” by accepting the timer Z interrupt request.
Fig. 2.5.35 Timing diagram of programmable wait one-shot generation mode
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2.5 Timer Y and timer Z
(2) Programmable wait one-shot generation mode setting method
Figure 2.5.36 to Figure 2.5.38 show the setting method for programmable wait one-shot generation
mode of Timer Z.
Process 1: Disable interrupt.
b7
b0
Interrupt control register 1 (ICON1) [Address 3E16]
0
INT0 interrupt disabled
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
0
Timer Z interrupt disabled
Process 2: Set timer Y, Z mode register.
b7
b0
1 1 1 1
Timer Y, Z mode register (TYZM) [Address 2016]
Programmable wait one-shot generation mode
Write to only latch (Note)
Timer Y count stop
Note: When using this mode, be sure to select “write to latch only”.
Process 3: Set timer Y, Z waveform output control register.
b7
b0
Timer Y, Z waveform output control register (PUM) [Address 2416]
Timer Z primary waveform extension control bit (Note 1)
0: Waveform not extended
1: Waveform extended
Timer Z secondary waveform extension control bit (Note 1)
0: Waveform not extended
1: Waveform extended
Timer Z output level latch
0: “L” level is output at timer stop. When count is started, “L”
level is output during the TZP interval (wait), and them, “H”
level is output during the TZS interval (one-shot) and timer
Z output is stopped at “L” level by underflow.
1: “H” level is output at timer stop. When count is started, “H”
level is output during the TZP interval (wait), and them, “L”
level is output during the TZS interval (one-shot) and timer
Z output is stopped at “H” level by underflow.
INT0 pin one-shot trigger control bit (Note 2)
0: INT0 pin one-shot trigger invalid
1: INT0 pin one-shot trigger valid
INT0 pin one-shot trigger active edge selection bit (Note 2)
0: Falling edge trigger
1: Rising edge trigger
Notes 1: The waveform extension function by the timer Z waveform extension control bits can be used
only when “0016” is set to prescaler Z.
When the value other than “0016” is set to prescaler Z, be sure to set “0” to EXPZP and EXPZS.
Also, when the timer Y underflow is selected as the timer Z count source, the waveform
extension function cannot be used.
2: Stop Timer Z to change these bits.
Process 4: Set TZOUT pin to the output.
b7
b0
1
Port P0 direction register (P0D) [Address 0116]
Set P02/TZOUT pin as the output mode
Fig. 2.5.36 Setting method for programmable wait one-shot generation mode (1)
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2.5 Timer Y and timer Z
Process 5: When the trigger by INT0 pin input is selected:
Set port P3 direction register, pull-up control register and port P1P3 control register
b7
b0
0
Port P3 direction register (P3D) [Address 0716]
Set P37/INT0 pin to the input mode
b7
b0
Pull-up control register (PULL) [Address 1616]
P37/INT0 pull-up control bit
0: Pull-up Off
1: Pull-up On
b7
b0
Port P1P3 control register (P1P3C) [Address 1716]
P37/INT0 input level selection bit
0: CMOS level
1: TTL level
Process 6: Set the timer Z count source.
b7
b0
0
Timer count source set register (TCSS) [Address 2E16]
Timer Z count source selection bits
b5 b4
00
01
10
11
: f(XIN)/16
: f(XIN)/2
: Timer Y underflow (Note)
: Not available
Note: When the timer Z waveform extension function is used,
do not select the timer Y underflow for the timer Z count source.
Process 7: Set the wait interval, one-shot pulse width (Note 1).
• Set the wait interval to the timer Z primary, and one-shot pulse width to the timer Z secondary.
Prescaler Z (PREZ) [Address 2516] (Note 2)
Count value
Timer Z secondary (TZS) [Address 2616]
Count value
Timer Z primary (TZP) [Address 2716]
Count value
Notes 1: In the programmable wait one-shot generation mode, values of TZS,
EXPZP, and EXPZS are valid by writing to TZP. Even when changing
TZP is not required, write the same value again.
2: When the timer Z waveform extension function is used, be sure to set
“0016” to prescaler Z.
3: In the programmable wait one-shot generation mode, when the setting
value is changed while the waveform is output, set by software in
order not to execute the writing to TZP and the timing of timer Z
underflow during the secondary interval simultanesously.
4: Count values of the primary interval (during wait) and secondary
interval (during one-shot output) can be checked by reading TZP (TZS
is undefined at read).
Fig. 2.5.37 Setting method for programmable wait one-shot generation mode (2)
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2.5 Timer Y and timer Z
Process 8: Set the standby state to accept the one-shot start trigger (Note).
b7
b0
Timer Y, Z mode register (TYZM) [Address 2016]
0 1 1 1
Timer Z count start
Note: When the INT0 pin one-shot trigger control bit of PUM is set to “valid”,
timer Z counting is started by the input of trigger to INT0 pin after this setting.
Process 9: In order not to execute the no requested interrupt processing,
set “0” (no requested) to the timer Z interrupt request bit.
b7
b0
Interrupt request register 2 (IREQ2) [Address 3D16]
0
No timer Z interrupt request issued
● When the INT0 pin one-shot trigger control bit is set to “valid” and
the INT0 interrupt is used, set the following;
b7
b0
Interrupt edge selection register (INTEDGE) [Address 3A16]
INT0 interrupt edge selection bit
0: Falling edge active
1: Rising edge active
b7
b0
Interrupt request register 1 (IREQ1) [Address 3C16]
0
No INT0 interrupt request issued
Process 10: When the interrupt is used, set “1” (interrupt enabled)
to the corresponding interrupt enable bit.
b7
b0
Interrupt control register 1 (ICON1) [Address 3E16]
1
INT0 interrupt enabled (Note)
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
1
Timer Z interrupt enabled
Note: When the INT0 pin one-shot trigger control bit is set to “valid”,
the INT0 interrupt can be accepted after this setting.
Process 11: Start counting of timer Z.
b7
b0
1
One-shot start register (ONS) [Address 2A16]
Timer Z one-shot start (Note)
● When the INT0 pin one-shot trigger control bit of PUM is set to “valid”,
the timer Z count is started by input of trigger to the INT0 pin.
Note: Pulse is output from TZOUT pin. After output, this bit is initialized to “0”.
Fig. 2.5.38 Setting method for programmable wait one-shot generation mode (3)
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2.5 Timer Y and timer Z
(3) Application example of programmable wait one-shot generation mode
Outline: The wait one-shot pulse synchronized with the PWM waveform output from the P0 1/TY OUT
pin is generated from Timer Z by using the programmable waveform generation mode of
Timer Y.
Specifications: TYOUT pin is connected to the P37/INT0 pin. The wait one-shot pulse is output by the
INT 0 pin input as trigger.
Operation clock: f(XIN) = 8 MHz, high-speed mode
As for the usage of Timer Y, refer to the above mentioned programmable waveform generation mode.
Figure 2.5.39 shows an example of waveform generation and peripheral circuit. Figure 2.5.40 shows
an example of control procedure.
7540 Group
P01/TYOUT
P37/INT0
P02/TZOUT
Timer Z active
Timer Z active
Timer Z active
Fig. 2.5.39 Example of waveform generation and peripheral circuit
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2.5 Timer Y and timer Z
Wait one-shot generation routine
Set “0” to the timer Z interrupt enable bit.
(Timer Z interrupt disabled)
Timer Z interrupt processing routine
Set timer Y, Z mode register
1 11 1
TYZM(Address 2016)
Programmable wait one-shot
generation mode
Writing to only latch (Note 2)
Timer Z count stop
Change of timer Z
Set timer Y, Z waveform output control register
1 1 1 0 0
PUM(Address 2416)
RTI
Timer Z primary waveform
generation not extended (Note 2)
Timer Z secondary waveform
generation not extended (Note 2)
Initial state: T ZP: “H” interval,
TZS: “L” interval after underflow
Stop at “H” after underflow
INT0 pin one-shot trigger valid (Note 3)
INT0 pin rising edge trigger (Note 3)
Set port P02 to the output mode.
Set port P37 to the input mode.
Set pull-up control register
Set port P1P3 control register
Set timer count source set register (Note 3)
1 0
TCSS(Address 2E16)
Timer Z count source selected
Set value to timer Z (Notes 2, 4, 5, 6)
Prescaler Z (Address 2516)
Timer Z secondary (A ddress 261 6)
Timer Z primary (Address 2716)
Set the standby state to accept
one-shot start trigger
0 1 1 1
TYZM(Address 2016)
Timer Z count start (Note 7)
Set interrupt edge selection register
1
Notes 1: When using this mode, be sure to select “write to latch only”.
2: The waveform extension function by the timer Z waveform
extension control bits can be used only when “0016” is set to
prescaler Z.
When the value other than “0016” is set to prescaler Z, be
sure to set “0” to EXPZP and EXPZS. Also, when the timer Y
underflow is selected as the timer Z count source, the
waveform extension function cannot be used.
3: Stop timer Z to change the INT0 pin one-shot trigger control
bit and INT0 one-shot trigger active edge selection bit.
4: In the programmable wait one-shot generation mode, values
of TZS, EXPZP, and EXPZS are valid by writing to TZP.
Even when changing TZP is not required, write the same
value again.
5: In the programmable wait one-shot generation mode, when
the setting value is changed while the waveform is output, set
by software in order not to execute the writing to TZP and the
timing of timer Z underflow simultanesously.
6: Count values of the primary interval (during wait) and
secondary interval (during one-shot output) can be checked
by reading TZP (TZS is undefined at read).
7: In this state, timer count is not started.
INTEDGE(Address 3A16)
INT0 rising edge active
Set “0” to the imer Z interrupt request bit.
Set “1” to the timer Z interrupt enable bit.
(Timer Z interrupt enabled)
RTS
Fig. 2.5.40 Example of control procedure
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2.5 Timer Y and timer Z
2.5.7 Notes on timer Y and timer Z
Notes on using each mode of Timer Y and Timer Z are described below.
(1) Timer mode (timer Y and timer Z)
➀ In the timer mode, TYP and TYS is not used.
(2) Programmable waveform generation mode (timer Y and timer Z)
➀ In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid
by writing to TYP because the setting to them is executed all at once by writing to TYP. Even
when changing TYP is not required, write the same value again.
➁ In the programmable waveform generation mode, when the setting value is changed while the
waveform is output, set by software in order not to execute the writing to TYP and the timing of
timer underflow during the secondary interval simultaneously.
An example of a measurement is shown below.
ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using
timer Y interrupt.
Writing to primary is performed in by judging that there is no problem if the underflow by
secondary is completed with reference to primary write operation before.
(Depending on a primary and a secondary setting values, and primary write timing, it may
be impossible.)
➂ The waveform extension function by the timer Y waveform extension control bits can be used only
when “00 16” is set to Prescaler Y.
When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS.
The waveform extension function by the timer Z waveform extension control bits can be used only
when “0016” is set to Prescaler Z. When the value other than “00 16” is set to Prescaler Z, be sure
to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z
count source, the waveform extension function cannot be used.
➃ When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch
only”.
➄ When TYS is read out, the undefined value is read out. However, while timer Y counts the setting
value of TYS, the count value during the secondary interval can be obtained by reading the timer
Y primary.
➅ In order to use TY OUT pin, set “1” to bit 1 of the port P0 direction register (output mode).
(3) Programmable one-shot generation mode (timer Z)
➀ In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing
to TZP. Even when changing TZP is not required, write the same value again.
➁ In the programmable one-shot generation mode, when the setting value is changed while the
waveform is output, set by software in order not to execute the writing to TZP and the timing of
timer underflow simultaneously.
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2.5 Timer Y and timer Z
➂ The waveform extension function by the timer Z waveform extension control bits can be used only
when “00 16” is set to Prescaler Z.
When the value other than “0016 ” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when
the timer Y underflow is selected as the timer Z count source, the waveform extension function
cannot be used.
An example of a measurement is shown below.
ex.) The underflow of timer is stored by polling etc. using timer Z interrupt.
Writing to primary is performed in by judging that there is no problem if the underflow by
secondary is completed with reference to primary write operation before.
(Depending on a primary setting value, primary write timing, software and timing of external
trigger to INT 0 pin, it may be impossible.)
➃ When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch
only”.
➄ In order to use TZ OUT pin, set “1” to bit 2 of the port P0 direction register (output mode).
➅ Stop Timer Z to change the INT 0 pin one-shot trigger control bit and INT 0 pin one-shot trigger
active edge selection bit.
(4) Programmable wait one-shot generation mode (timer Z)
➀ In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid
by writing to TZP. Even when changing TZP is not required, write the same value again.
An example of a measurement is shown below.
ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using
timer Z interrupt.
Writing to primary is performed in by judging that there is no problem if the underflow by
secondary is completed with reference to primary write operation before.
(Depending on a primary setting value, primary write timing, software and timing of external
trigger to INT 0 pin, it may be impossible.)
➁ In the programmable wait one-shot generation mode, when the setting value is changed while the
waveform is output, set by software in order not to execute the writing to TZP and the timing of
timer underflow during the secondary interval simultaneously.
➂ The waveform extension function by the timer Z waveform extension control bit can be used only
when “00 16” is set to Prescaler Z.
When the value other than “00 16” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS.
Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension
function cannot be used.
➃ When using this mode, be sure to set “1” to the timer Z write control bits to select “write to latch
only”.
➄ When TZS is read out, the undefined value is read out. However, while Timer Z counts the setting
value of TZS (during one-shot output), the count value during the secondary interval can be
obtained by reading TZP.
➅ In order to use TZ OUT pin, set “1” to bit 2 of the port P0 direction register (output mode).
➆ Stop Timer Z to change the INT 0 pin one-shot trigger control bit and INT 0 pin one-shot trigger
active edge selection bit.
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2.6 Serial I/O1
2.6 Serial I/O1
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.6.1 Memory map
001816
Transmit/Receive buffer register (TB/RB)
001916
Serial I/O1 status register (SIO1STS)
001A16
Serial I/O1 control register (SIO1CON)
001B16
UART control register (UARTCON)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
003E16
Interrupt control register 1 (ICON1)
Fig. 2.6.1 Memory map of registers relevant to serial I/O
2.6.2 Relevant registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 18 16]
B
Function
0 The transmission data is written to or the receive data is read out
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
2
At reset
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 2.6.2 Structure of Transmit/Receive buffer register
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2.6 Serial I/O1
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIO1STS) [Address : 19
B
Function
Name
0 Transmit buffer empty flag
16]
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
At reset
R W
0
✕
0
✕
0
✕
3 Overrun error flag (OE)
0
✕
4
0
✕
0
✕
0
✕
1
✕
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
5
6
7
0 : No error
1 : Overrun error
0 : No error
Parity error flag (PE)
1 : Parity error
0 : No error
Framing error flag (FE)
1 : Framing error
0 : (OE) ∪ (PE) ∪ (FE) = 0
Summing error flag (SE)
1 : (OE) ∪ (PE) ∪ (FE) = 1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
Fig. 2.6.3 Structure of Serial I/O1 status register
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A
B
Function
Name
0 BRG count source
selection bit (CSS)
16]
0 : f(X IN)
1 : f(X IN)/4
1 Serial I/O1 synchronous clock When clock synchronous serial I/O
selection bit (SCS)
2 SRDY1 output enable bit
(SRDY)
Transmit
interrupt
3
source selection bit (TIC)
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O1 mode selection bit
(SIOM)
7 Serial I/O1 enable bit
(SIOE)
At reset
R W
0
0
is selected;
0: BRG output divided by 4
1: External clock input
When UART is selected;
0: BRG output divided by 16
1: External clock input divided by 16
0: P13 pin
1: SRDY1 output pin
0
0 : Interrupt when transmit buffer
has emptied
1 : Interrupt when transmit shift
operation is completed
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0: Clock asynchronous (UART)
serial I/O
1: Clock synchronous serial I/O
0
0: Serial I/O1 disabled
1: Serial I/O1 enabled
0
0
Fig. 2.6.4 Structure of Serial I/O1 control register
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2.6 Serial I/O1
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16]
B
Function
Name
0 Character length
selection bit (CHAS)
1 Parity enable bit
(PARE)
2 Parity selection bit
(PARS)
3 Stop bit length selection
bit (STPS)
4
P11/TxD P-channel
output disable bit
(POFF)
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
5 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
0
0
1
✕
6
1
✕
7
1
✕
When these bits are read out, the values are “1”.
Fig. 2.6.5 Structure of UART control register
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C 16]
B
Function
At reset
0 Set a count value of baud rate generator.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 2.6.6 Structure of Baud rate generator
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2.6 Serial I/O1
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
0 Serial I/O1 receive
interrupt request bit
1 Serial I/O1 transmit interrupt
request bit
2 INT 0 interrupt request bit
3 INT 1 interrupt request bit
4 Key-on wake up interrupt
request bit
5 CNTR 0 interrupt request bit
6 CNTR 1 interrupt request bit
7 Timer X interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.6.7 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
B
Name
0 Serial I/O1 receive
interrupt enable bit
1 Serial I/O1 transmit interrupt
enable bit
2 INT 0 interrupt enable bit
3 INT 1 interrupt enable bit
4 Key-on wake up interrupt
enable bit
5 CNTR 0 interrupt enable bit
6 CNTR 1 interrupt enable bit
7 Timer X interrupt enable bit
16]
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
At reset
R W
0
0
0
0
0
0
0
0
Fig. 2.6.8 Structure of Interrupt control register 1
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2.6 Serial I/O1
2.6.3 Serial I/O1 transfer data format
Figure 2.6.9 shows the serial I/O1 transfer data format.
Clock
synchronous
serial I/O
LSB first
1ST-8DATA-1SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
SP
Serial I/O1
1ST-8DATA-1PAR-1SP
ST
LSB
MSB
PAR
PAR
SP
MSB
2SP
SP
1ST-7DATA-1PAR-1SP
ST
UART
LSB
MSB
1ST-8DATA-2SP
ST
LSB
1ST-7DATA-2SP
ST
LSB
MSB
2SP
1ST-8DATA-1PAR-2SP
ST
LSB
MSB
PAR
PAR
2SP
2SP
1ST-7DATA-1PAR-2SP
ST
LSB
MSB
ST: Start bit
SP: Stop bit
PAR: Parity bit
Fig. 2.6.9 Serial I/O1 transfer data format
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2.6 Serial I/O1
2.6.4 Application example of clock synchronous serial I/O1
For clock synchronous serial I/O1, the transmitter and the receiver use the same clock. Synchronizing with
this clock, the transmit operation of the transmitter and the receive operation of the receiver are executed
at the same time. If an internal clock is used as the operation clock, transfer is started by a write signal
to the TB/RB.
(1) Data transfer rate
The synchronous clock frequency is calculated by the following formula;
● When the internal clock is selected (when baud rate generator is used)
Synchronous clock frequency [Hz] =
f(X IN)
Division ratio * 1 ✕ (BRG setting value * 2 + 1) ✕ 4
Division ratio*1 : “1” or “4” is selected (set by bit 0 of serial I/O1 control register)
BRG setting value* 2 : 0 to 255 (00 16 to FF 16) is set
● When the external clock is selected
Synchronous clock frequency [Hz] = Clock input to SCLK1 pin
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2.6 Serial I/O1
(2) Clock synchronous serial I/O setting method
Figure 2.6.10 and Figure 2.6.11 show the setting method for the clock synchronous serial I/O1.
Process 1: Stop and initialize serial I/O.
b7
b0
Serial I/O1 control register (SIO1CON) [Address 1A16]
0 0
Transmit operation stop and initialized
Receive operation stop and initialized
Process 2: Disable serial I/O1 transmit/receive interrupt.
b7
b0
0 0
Interrupt control register 1 (ICON1) [Address 3E16]
Serial I/O1 receive interrupt disabled
Serial I/O1 transmit interrupt disabled
Process 3: Set serial I/O1 control register.
b7
1 1
b0
Serial I/O1 control register (SIO1CON) [Address 1A16]
BRG count source selected (set in internal clock selected)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selected
0: BRG output/4 (Note 1)
1: External clock input
SRDY1 output enable selected
0: P13 pin operates as normal I/O pin
1: P13 pin operates as SRDY1 output pin (Note 2)
Transmit interrupt source selected
0: When transmit buffer has emptied
1: When transmit shift operation is completed
Transmit enable selected
0: Transmit disabled (at half-duplex communication receive)
1: Transmit enabled (at full-duplex communication) (Note 3)
Receive enable selected
0: Receive disabled (at half-duplex communication transmit)
1: Receive enabled (at full-duplex communication) (Note 3)
Clock synchronous serial I/O
Serial I/O1 enabled
(P10–P13 pins operate as serial I/O1 pins)
Notes 1: Setting of serial I/O1 synchronous selection bit is as follows:
“0”: P12 pin is set to be an output pin of the synchronous clock.
“1”: P12 pin is set to be an input pin of the synchronous clock.
2: When an external clock input is selected as the synchronous clock, and the receiver
performs the SRDY1 output, set “1” to the transmit enable bit in addition to the receive
enable bit and SRDY1 output enable bit.
3: When data transmission is executed at the state that an external clock input is
selected as the synchronous clock, set “1” to the transmit enable bit while the SCLK1
is “H” state.
Process 4: When BRG output/4 is selected as synchronous clock, set value to baud rate generator.
Baud rate generator (BRG) [Address 1C16]
Set baud rate value
Fig. 2.6.10 Setting method for clock synchronous serial I/O1 (1)
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2.6 Serial I/O1
Process 5: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the serial I/O1 transmit/receive interrupt request bit.
b7
b0
0 0
Interrupt request register 1 (IREQ1) [Address 3C16]
No serial I/O1 receive interrupt request issued
No serial I/O1 transmit interrupt request issued
Process 6: When the interrupt is used, set “1” (interrupt enabled) to the serial I/O transmit/receive
interrupt enable bit.
b7
b0
1 1
Interrupt control register 1 (ICON1) [Address 3E16]
Serial I/O1 receive interrupt enabled
Serial I/O1 transmit interrupt enabled
Process 7: Transmit/Receive of serial data (Notes 1, 2).
Transmit/Receive buffer register (TB/RB) [Address 1816]
Set transmit data (in full-duplex communication)
Set dummy data (in half-duplex communication)
Notes 1: When data transmission is executed at the state that an external clock input is
selected as the synchronous clock, set the transmit data while the SCLK is “H” state.
2: When inputting the SRDY1 signal, set used pins to to the input mode before
transmitting data.
Fig. 2.6.11 Setting method for clock synchronous serial I/O1 (2)
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2.6 Serial I/O1
(3) Communication using clock synchronous serial I/O1 (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O1. S RDY1
signal is used for communication control.
Specifications : •The serial I/O1 (clock synchronous serial I/O selected ) is used.
•Synchronous clock frequency : 125 kHz; f(X IN) = 4 MHz divided by 32
•The receiver outputs the S RDY1 signal at 2 ms intervals which the timer generates,
and 2-byte data is transferred from the transmitter to the receiver.
Figure 2.6.12 shows a connection diagram, Figure 2.6.13 shows a timing chart, Figure 2.6.14 shows
the control procedure of transmitter, and Figure 2.6.15 shows an example of control procedure of
receiver.
Transmitter
Receiver
P37/INT0
SRDY1
SCLK1
SCLK1
T XD 1
R XD 1
7540 Group
7540 Group
Fig. 2.6.12 Connection diagram
SRDY1
.....
SCLK1
.....
TXD
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1
.....
2ms
Fig. 2.6.13 Timing chart
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2.6 Serial I/O1
RESET
Initialization
SEI
CLD
CLT
Set serial I/O1 control register
1 1 0 1 0 0 0 0 SIO1CON(Address 1A16)
BRG count source: f(XIN)
Synchronous clock:
BRG output/4
P13 pin (Normal I/O pin)
Transmit interrupt source:
W h e n tra n s m it b u ff e r h a s e m p tie d
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O1 enabled
Set baud rate generator
“0716”
BRG(Address 1C16)
Set INT0 interrupt active edge
0 INTEDGE(Address 3A16)
INT0 falling edge active
N
INT0 falling edge input?
Y
Write the first-byte transmission data to
the transmit/receive buffer register
TB/RB(Address 1816)
Transmit buffer has emptied?
(checked by b0 of SIO1STS
(address 1916))
N
Y
Write the second-byte transmission data to
the transmit/receive buffer register
TB/RB(Address 1816)
Transmit buffer has emptied?
(checked by b0 of SIO1STS
(address 1916))
N
Y
Transmit shift has completed?
(checked by b2 of SIO1STS
(address 1916))
N
Y
Fig. 2.6.14 Control procedure of transmitter
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RESET
Initialization
SEI
CLD
CLT
Set serial I/O1 control register
1 1
1 1 1 1
SIO1CON(Address 1A16)
Synchronous clock:
External clock input
SRDY1 output pin
Transmit enabled
Receive enabled
Clock synchronous serial I/O
Serial I/O enabled
2 ms elapsed ?
(generated by timer)
N
Y
Set dummy data to the transmit/receive buffer
TB/RB(Address 1816)
Receive buffer is full?
(checked by b1 of SIO1STS
(address 1916))
N
Y
Read the first-byte reception data from
the transmit/receive buffer register
TB/RB(Address 1816)
Receive buffer is full?
(checked by b1 of SIO1STS
(address 1916))
N
Y
Read the second-byte reception data from
the transmit/receive buffer register
TB/RB(Address 1816)
Fig. 2.6.15 Control procedure of receiver
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2.6 Serial I/O1
2.6.5 Application example of clock asynchronous serial I/O1
For clock asynchronous serial I/O1 (UART), the transfer formats used by a transmitter and receiver must
be identical.
In the 7540 Group, eight serial data transfer formats can be selected.
(1) Data transfer rate
The transfer bit rate is calculated by the following formula;
● When the internal clock is selected (when baud rate generator is used)
Transfer bit rate [bps] =
Division ratio
*1
f(X IN)
✕ (BRG setting value
*2
+ 1) ✕ 16
Division ratio*1 : “1” or “4” is selected (set by bit 0 of serial I/O1 control register)
BRG setting value* 2 : 0 to 255 (00 16 to FF 16) is set
● When the external clock is selected
Transfer bit rate [bps] = Clock input to SCLK1 pin/16
Table 2.6.1 shows the setting example of baud rate generator and transfer bit rate values.
Table 2.6.1 Setting example of baud rate generator (BRG) and transfer bit rate values
BRG count source
BRG set value
f(X IN ) / 4
255 (FF16)
300
488.28125
f(X IN ) / 4
127 (7F16)
600
976.5625
f(X IN ) / 4
63 (3F 16)
1200
1953.125
f(X IN ) / 4
f(X IN ) / 4
31 (1F 16)
15 (0F 16)
2400
4800
3906.25
7812.5
f(X IN ) / 4
7 (07 16)
9600
15625
f(X IN ) / 4
3 (03 16)
19200
31250
f(X IN ) / 4
1 (01 16)
38400
62500
f(X IN)
3 (03 16)
76800
125000
f(X IN)
f(X IN)
1 (01 16)
0 (00 16)
153600
250000
307200
500000
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Transfer bit rate (bps)
At f(X IN) = 4.9152 MHz
At f(X IN) = 8 MHz
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2.6 Serial I/O1
(2) UART setting method
Figure 2.6.16 and Figure 2.6.17 show the setting method for UART of serial I/O1.
Process 1: Stop and initialize serial I/O.
b7
b0
0 0
Serial I/O1 control register (SIO1CON) [Address 1A16]
Transmit operation stop and initialization
Receive operation stop and initialization
Process 2: Disable serial I/O1 transmit/receive interrupt.
b7
b0
0 0
Interrupt control register 1 (ICON1) [Address 3E16]
Serial I/O1 receive interrupt disabled
Serial I/O1 transmit interrupt disabled
Process 3: Set serial I/O1 control register.
b7
1 0
b0
Serial I/O1 control register (SIO1CON) [Address 1A16]
BRG count source selected (set in internal clock selected)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selected (Note 1)
0: BRG output/16
1: External clock input/16
Transmit interrupt source selected
0: When transmit buffer has emptied
1: When transmit shift operation is completed
Transmit enable selected
0: Transmit disabled (at half-duplex communication receive)
1: Transmit enabled (at full-duplex communication) (Note 2)
Receive enable selected
0: Receive disabled (at half-duplex communication transmit)
1: Receive enabled (at full-duplex communication) (Note 2)
Clock asynchronous serial I/O
Serial I/O1 enabled (P10–P12 pins operate as serial I/O1 pins)(Note 3)
Note 1: Setting of serial I/O1 synchronous clock selection bit is as follows;
“0”: P12 pin can be used as a normal I/O pin
“1”: P12 pin is used as an input pin for an external clock.
2: When data transmission is executed at the state that an external clock input is selected
as the synchronous clock, set “1” to the transmit enable bit while the SCLK1 is “H” state.
3: When clock asynchronous (UART) serial I/O is selected, P13 pin can be used as a
normal I/O pin.
Fig. 2.6.16 Setting method for UART of serial I/O1 (1)
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Process 4: Set UART control register.
b7
b0
UART control register (UARTCON) [Address 1B16]
Select character length
0: 8 bits
1: 7 bits
Select parity enable
0: Parity disabled
1: Parity enabled
Select parity (valid only when parity is enabled)
0: Even parity
1: Odd parity
Select stop bit length
0: 1 stop bit
1: 2 stop bits
Select P11/TxD P-channel output disable (in output mode)
0: CMOS output
1: N-channel open-drain output
Process 5: When BRG output/16 is selected as synchronous clock, set value to baud rate generator.
Baud rate generator (BRG) [Address 1C16]
Set baud rate value
Process 6: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the serial I/O1 transmit/receive interrupt request bit.
b7
b0
0 0
Interrupt request register 1 (IREQ1) [Address 3C16]
No serial I/O1 receive interrupt request issued
No serial I/O1 transmit interrupt request issued
Process 7: When the interrupt is used, set “1” (interrupt enabled) to the serial I/O1
transmit/receive interrupt enable bit.
b7
b0
1 1
Interrupt control register 1 (ICON1) [Address 3E16]
Serial I/O1 receive interrupt enabled
Serial I/O1 transmit interrupt enabled
Process 8: When transmitting, start serial data transmission (Note).
Transmit/Receive buffer register (TB/RB) [Address 1816]
Set transmit data
Note: When data transmission is executed at the state that an external clock input is
selected as the synchronous clock, set the transmit data while the SCLK1 is “H” state.
Fig. 2.6.17 Setting method for UART of serial I/O1 (2)
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2.6 Serial I/O1
(3) Communication using UART of serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using UART. Port P00 is used for communication
control.
Specifications : •The Serial I/O1 (UART selected ) is used.
•Transfer bit rate : 9600 bps (f(X IN) = 4.9152 MHz divided by 512)
•Communication control using port P0 0 (output level of port P0 0 is controlled by
software)
2-byte data is transferred from the transmitter to the receiver at 10 ms intervals
which the timer generates.
Figure 2.6.18 shows a connection diagram, Figure 2.6.19 shows a timing chart, Figure 2.6.20 shows
the control procedure of transmitter, and Figure 2.6.21 shows an example of control procedure of
receiver.
Transmitter
Receiver
P00
P00
TxD
RXD
7540 Group
7540 Group
Fig. 2.6.18 Connection diagram
.....
P00
T XD
ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2) ST D0 D1 D2 D3 D4 D5 D6 D7 SP(2)
ST D0
.....
10 ms
Fig. 2.6.19 Timing chart
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2.6 Serial I/O1
RESET
Initialization
SEI
CLD
CLT
Set serial I/O1 control register
1 0 0 1 0
0 1
SIO1CON(Address 1A16)
BRG count source: f(XIN)/4
Synchronous clock:
BRG output/16
Transmit interrupt source:
W h e n tra n s m it b u ff e r h a s e m p tie d
Transmit enabled
Receive disabled
UART
Serial I/O1 enabled
Set UART control register
0 1
0 0 UARTCON(Address 1B16)
Character length: 8 bits
Parity disabled
Stop bit length: 2 bits
TXD: CMOS output
Set baud rate generator
BRG(Address 1C16)
“0716”
Set the communication control port P00 to the
output mode.
10 ms elapsed ?
(generated by timer)
N
Y
Set “1” to the communication control port P00.
Write the first-byte transmission data to
the transmit/receive buffer register
TB/RB(Address 1816)
Transmit buffer has emptied?
(checked by b0 of SIO1STS
(address 1916))
N
Y
Write the second-byte transmission data to
the transmit/receive buffer register
TB/RB(Address 1816)
Transmit buffer has emptied?
(checked by b0 of SIO1STS
(address 1916))
N
Y
Transmit shift has completed?
(checked by b2 of SIO1STS
(address 1916))
N
Y
Set “0” to the communication control port P00.
Fig. 2.6.20 Control procedure of transmitter
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Initialization
SEI
CLD
CLT
Set serial I/O1 control register
1 0 1 0
0 1
SIO1CON(Address 1A16)
BRG count source: f(XIN)/4
Synchronous clock:
BRG output/16
Transmit disabled
Receive enabled
UART
Serial I/O1 enabled
Set UART control register
1
0 0 UAR TCON(Address 1B16)
Character length: 8 bits
Parity disabled
Stop bit length: 2 bits
Set baud rate generator
“0716”
BRG(Address 1C16)
Set the communication control port P00 to the
input mode.
Receive buffer is full?
(checked by b1 of SIO1STS
(address 1916))
N
Y
Read the first-byte transmission data from
the transmit/receive buffer register
TB/RB(Address 1816)
Error occurs?
(checked by b6 of SIO1STS
(address 1916))
Y
N
Receive buffer is full?
(checked by b1 of SIO1STS
(address 1916))
N
Y
Read the second-byte transmission data from
the transmit/receive buffer register
TB/RB(Address 1816)
Error occurs?
(checked by b6 of SIO1STS
(address 1916))
N
Y
Error processing
N
Communication control port P00 = “0” ?
Y
Fig. 2.6.21 Control procedure of receiver
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2.6 Serial I/O1
2.6.6 Notes on Serial I/O1
Notes on using serial I/O1 are described below.
(1) Notes when selecting clock synchronous serial I/O
➀ When the clock synchronous serial I/O1 is used, serial I/O2 cannot be used.
➁ When the transmit operation is stopped, clear the serial I/O1 enable bit and the transmit enable
bit to “0” (serial I/O1 and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD 1, RxD 1, SCLK1, and SRDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD1 pin and an operation failure occurs.
➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled), or
clear the serial I/O1 enable bit to “0” (serial I/O1 disabled).
➃ When the transmit/receive operation is stopped, clear both the transmit enable bit and receive
enable bit to “0” (transmit and receive disabled) simultaneously. (any one of data transmission and
reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit cannot be initialized even if the serial I/O1 enable bit is
cleared to “0” (serial I/O1 disabled) (same as ➁).
➄ When signals are output from the SRDY1 pin on the reception side by using an external clock, set
all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to “1”.
➅ When the SRDY1 signal input is used, set the using pin to the input mode before data is written to
the transmit/receive buffer register.
➆ Setup of a
selected;
“0” : P12
“1” : P12
Setup of a
“0” : P1 3
“1” : P1 3
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serial I/O1 synchronous clock selection bit when a clock synchronous serial I/O is
pin turns into an output pin of a synchronous clock.
pin turns into an input pin of a synchronous clock.
S RDY1 output enable bit (S RDY1) when a clock synchronous serial I/O1 is selected;
pin can be used as a normal I/O pin.
pin turns into a S RDY1 output pin.
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(2) Notes when selecting UART
➀ When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG
output divided by 16 is selected as the synchronous clock.
➁ When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Same as (1) ➁.
➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled).
➃ When the transmit/receive operation is stopped, clear the transmit enable bit to “0” (transmit
disabled) and receive enable bit to “0” (receive disabled).
➄ Setup of a serial I/O1 synchronous clock selection bit when a clock asynchronous (UART) serial
I/O is selected;
“0”: P1 2 pin can be used as a normal I/O pin.
“1”: P1 2 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin.
(3) Notes common to clock synchronous serial I/O and UART
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
→
➁ The transmit shift completion flag changes
from “1” to “0” with a delay of 0.5 to 1.5
shift clocks. When data transmission is
controlled with referring to the flag after
writing the data to the transmit buffer register,
note the delay.
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
→
➀ Set the serial I/O control register again after
the transmission and the reception circuits
are reset by clearing both the transmit enable
bit and the receive enable bit to “0.”
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or one
of them to “1”
Can be set
with the LDM
instruction at
the same time
Fig. 2.6.22 Sequence of setting serial I/O1 control
register again
➂ When data transmission is executed at the state that an external clock input is selected as the
synchronous clock, set “1” to the transmit enable bit while the SCLK1 is “H” state. Also, write to the
transmit buffer register while the S CLK1 is “H” state.
➃ When the transmit interrupt is used, set as the following sequence.
❶ Serial I/O1 transmit interrupt enable bit is set to “0” (disabled).
❷ Serial I/O1 transmit enable bit is set to “1”.
❸ Serial I/O1 transmit interrupt request bit is set to “0”.
❹ Serial I/O1 transmit interrupt enable bit is set to “1” (enabled).
● Reason
When the transmit enable bit is set to “1”, the transmit buffer empty flag and transmit shift
completion flag are set to “1”.
Accordingly, even if the timing when any of the above flags is set to “1” is selected for the transmit
interrupt source, interrupt request occurs and the transmit interrupt request bit is set.
➄ Write to the baud rate generator (BRG) while the transmit/receive operation is stopped.
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2.7 Serial I/O2
2.7 Serial I/O2
This paragraph explains the registers setting method and the notes relevant to the serial I/O.
2.7.1 Memory map
000316
Port P1 direction register (P1D)
003016
Serial I/O2 control register (SIO2CON)
003116
Serial I/O2 register (SIO2)
003D16
Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.7.1 Memory map of registers relevant to serial I/O2
2.7.2 Relevant registers
Port P1 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1 direction register (P1D) [Address : 03 16]
B
Function
Name
0 : Port P1 0 input mode
1 : Port P1 0 output mode
0 : Port P1 1 input mode
1 : Port P1 1 output mode
0 : Port P1 2 input mode
1 : Port P1 2 output mode
0 : Port P1 3 input mode
1 : Port P1 3 output mode
0 : Port P1 4 input mode
1 : Port P1 4 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
?
✕ ✕
6
?
✕ ✕
7
?
✕ ✕
0 Port P1 direction register
1
2
3
4
5 Nothing is allocated for these bits.
When these bits are read out, the values are undefined.
Fig. 2.7.2 Structure of Port P1 direction register
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Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 3016]
B
Function
Name
0 Internal synchronous
b2 b1 b0
0 0 0 : f(XIN)/8
0 0 1 : f(XIN)/16
0 1 0 : f(XIN)/32
0 1 1 : f(XIN)/64
1 1 0 : f(XIN)/128
1 1 1 : f(XIN)/256
SDATA2 pin selection bit
0 : I/O port / SDATA2 input
(Note)
1 : SDATA2 output
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
Transfer direction selection bit 0 : LSB first
1 : MSB first
0
: External clock (SCLK2 is input)
SCLK2 pin selection bit
1 : Internal clock (SCLK2 is output)
Transmit / receive shift
0 : shift in progress
completion flag
1 : shift completed
At reset
R W
0
clock selection bits
1
2
3
4
5
6
7
0
0
0
0
✕
0
0
0
✕
Note: When using it as a SDATA input, set the port P13 direction register bit to “0”.
Fig. 2.7.3 Structure of Serial I/O2 control register
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 31 16]
B
Function
0 A shift register for serial transmission and reception.
1
• At transmitting : Set a transmission data.
• At receiving : A reception data is stored.
At reset
R W
?
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 2.7.4 Structure of Serial I/O2 register
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Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
Name
0 Timer Y interrupt request bit
1 Timer Z interrupt request bit
2 Timer A interrupt request bit
3 Serial I/O2 interrupt request
bit
4 AD converter interrupt
request bit
5 Timer 1 interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✕
0
✕
6 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.7.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Name
0 Timer Y interrupt
enable bit
1 Timer Z interrupt enable bit
2 Timer A interrupt enable bit
3 Serial I/O2 interrupt enable bit
4 AD conversion interrupt
enable bit
5 Timer 1 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
0
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
7
Fig. 2.7.6 Structure of Interrupt control register 2
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2.7 Serial I/O2
2.7.3 Application example of serial I/O2
(1) Serial I/O2 setting method
Figure 2.7.7 and Figure 2.7.8 show the setting method for the serial I/O2.
Process 1: Disable serial I/O2 transmit/receive interrupt.
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
0
Serial I/O2 interrupt disabled
Process 2: Set port P1 according to the usage condition.
b7
b0
Port P1 direction register (P1D) [Address 0316]
P12/SCLK2 pin (Note 1)
P13/SDATA2 pin (Notes 2, 3)
Notes 1: When an external clock input is selected, set P12/SCLK2 pin to the input mode.
2: When P13/SDATA2 pin is used as the P13 pin, set this bit to “0”.
3: When this bit is set to “0” at transmit and the internal clock is selected for SCLK2,
the SDATA2 pin is in a high impedance state after the data transfer is completed.
Process 3: Set serial I/O2 control register.
b7
b0
Serial I/O2 control register (SIO2CON) [Address 3016]
Internal synchronous clock selected (set in internal clock selected)
b2b1b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
SDATA2 pin selected
0: I/O port/SDATA2 input (at receive)
1: SDATA2 output (at transmit)
Transfer direction selected
0: LSB first
1: MSB first
SCLK2 pin selected
0: External clock (SCLK2 is input)
1: Internal clock (SCLK2 is outpu)
Process 4: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the serial I/O2 interrupt request bit.
b7
b0
0
Interrupt request register 2 (IREQ2) [Address 3D16]
No serial I/O2 interrupt request issued
Fig. 2.7.7 Setting method for serial I/O2
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2.7 Serial I/O2
Process 5: When the interrupt is used, set “1” (interrupt enabled) to the serial I/O2 interrupt.
enable bit.
b7
b0
1
Interrupt control register 2 (ICON2) [Address 3F16]
Serial I/O2 interrupt enabled
Process 6: When transmitting, start serial data transmission.
Serial I/O2 register (SIO2) [Address 3116]
Set transmit data
Fig. 2.7.8 Setting method for serial I/O2
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2.7 Serial I/O2
(2) Communication using serial I/O2 (transmit/receive)
Outline: 2-byte data is transmitted and received, using the serial I/O2. Port P00 is used for communication
control and outputs the quasi-SRDY signal.
Specifications: • The serial I/O2, clock synchronous serial I/O, is used.
• Synchronous clock frequency : 125 kHz; f(X IN) = 8 MHz divided by 64
• Transfer direction : LSB first
• The receiver outputs the quasi-SRDY signal at 2 ms intervals which the timer generates,
and 2-byte data is transferred from the transmitter to the receiver.
Figure 2.7.9 shows a connection diagram, Figure 2.7.10 shows a timing chart, Figure 2.7.11 shows
the control procedure of transmitter, and Figure 2.7.12 shows an example of control procedure of
receiver.
Receiver
Transmitter
P37/INT0
P00
SCLK
SCLK
SDATA
SDATA
7540 Group
7540 Group
Fig. 2.7.9 Connection diagram
Quasi-SRDY
.....
SCLK
.....
SDATA
D 0 D1 D2 D 3 D 4 D5 D 6 D 7
D0 D 1 D 2 D 3 D 4 D 5 D 6 D 7
D0 D1
.....
2 ms
Fig. 2.7.10 Timing chart
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2.7 Serial I/O2
RESET
Initialization
SEI
CLD
CLT
Set port P12 to the output mode.
Set port P13 to the output mode. (Note)
Set serial I/O2 control register
1 0
1 0 1 1
SIO2CON(Address 3016)
Synchronous clock: f(XIN)/64
SDATA2 pin: SDATA2 output
LSB first
SCLK2 pin: Internal clock
Set INT0 interrupt active edge
0
INTEDGE(Address 3A16)
INT0 falling edge active
N
INT0 falling edge input?
Y
Set “0” to the serial I/O2 interrupt request bit.
Write the first-byte transmission data to
the serial I/O2 register
SIO2(Address 3116)
Transmit shift has completed?
(checked by serial I/O2 interrupt
request bit)
Y
N
Set “0” to the serial I/O2 interrupt request bit.
Write the second-byte transmission data to
the serial I/O2 register
SIO2(Address 3116)
Transmit shift has completed?
(checked by serial I/O2 interrupt
request bit)
Y
N
Note: When direction register of P13/SDATA2 pin is set to the input mode and
the internal clock is selected, the SDATA2 pin is in a high impedance
state after the data transfer is completed.
Fig. 2.7.11 Control procedure of transmission side
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2.7 Serial I/O2
RESET
Initialization
SEI
CLD
CLT
Set quasi-SRDY signal port P00 to the output mode.
Output “1” from quasi-SRDY signal port P00.
Set port P12 to the input mode.
Set port P13 to the input mode.
Set serial I/O2 control register
0 0
0 0 1 1
SIO2CON(Address 3016)
Synchronous clock: f(XIN)/64
SDATA2 pin: SDATA2 input
LSB first
SCLK2 pin: External clock
2 ms elapsed ?
(generated by timer)
N
Y
Output “0” from quasi-SRDY signal port P00.
Output “1” from quasi-SRDY signal port P00.
Set dummy data to the serial I/O2 register
(Note 1)
SIO2(Address 3116)
Receive has completed?
(checked by b7 of SIO2CON
(address 3016))
N
Y
Wait for half cycle of clock (Note 2)
Read receive data from serial I/O2 register
SIO2(Address 3116)
Set dummy data to serial I/O2 register
(Note 1)
SIO2(Address 3116)
Receive has completed?
(checked by b7 of SIO2CON
(address 3016))
N
Y
Wait for half cycle of clock (Note 2)
Read receive data from serial I/O2 register
SIO2(Address 3116)
Notes 1: The transmit/receive shift completion flag of the serial I/O2 control register is “1” after
transmit/receive shift is completed. In order to set “0” to this flag, set data (dummy data at
receive) to the serial I/O2 register by program.
2: Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier
than the completion of the actual shift operation for a half cycle of shift clock. Accordingly,
when the shift completion is checked by using this bit, read/write the serial I/O2 register after
a half or more cycle of clock from the setting “1” to this bit is checked.
Fig. 2.7.12 Control procedure of reception side
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2.7 Serial I/O2
2.7.4 Notes on serial I/O2
Notes on using serial I/O2 are described below.
(1) Note on serial I/O1
Serial I/O2 can be used only when serial I/O1 is not used or serial I/O1 is used as UART and the
BRG output divided by 16 is selected as the synchronous clock.
(2) Note on S CLK2 pin
When an external clock is selected, set “0” to bit 2 of the port P1 direction register (input mode).
(3) Note on SDATA2 pin
When P13/S RDY1/SDATA2 pin is used as the SDATA input, set “0” to bit 3 of the port P1 direction register
(input mode).
When the internal clock is selected as the transfer and P1 3/S DATA2 pin is set to the input mode, the
SDATA2 pin is in a high-impedance state after the data transfer is completed.
(4) Notes on serial I/O2 transmit/receive shift completion flag
➀ The transmit/receive shift completion flag of the serial I/O2 control register is “1” after transmit/
receive shift is completed. In order to set “0” to this flag, set data (dummy data at receive) to the
serial I/O2 register by program.
➁ Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier than
the completion of the actual shift operation for a half cycle of shift clock. Accordingly, when the
shift completion is checked by using this bit, read/write the serial I/O2 register after a half or more
cycle of clock from the setting “1” to this bit is checked.
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2.8 A/D converter
2.8 A/D converter
This paragraph explains the registers setting method and the notes relevant to the A/D converter.
2.8.1 Memory map
003416
A/D control register (ADCON)
003516
A/D conversion register (low-order) (ADL)
003616
A/D conversion register (high-order) (ADH)
003D16 Interrupt request register 2 (IREQ2)
003F16
Interrupt control register 2 (ICON2)
Fig. 2.8.1 Memory map of registers relevant to A/D converter
2.8.2 Relevant registers
A/D control register
b7 b6 b5 b4 b3 b2 b1 b0
A/D control register (ADCON) [Address : 3416]
B
Name
0
Analog input pin selection bits
Function
1
2
0
0
1
1
0
0
1
1
0 : P20/AN0
1 : P21/AN1
0 : P22/AN2
1 : P23/AN3
0 : P24/AN4
1 : P25/AN5
0 : P26/AN6
1 : P27/AN7
R W
0
b2 b1 b0
0
0
0
0
1
1
1
1
At reset
0
(Note)
(Note)
0
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
0
✕
1
✽
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
0
✕
6
0
✕
7
0
✕
3
4
5
Note: These can be used only for the 36-pin package versions.
✽: This bit can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.8.2 Structure of A/D control register
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2.8 A/D converter
A/D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A/D conversion register (low-order) (ADL) [Address : 3516]
B
Function
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
< 10-bit read>
?
✕
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
stored.
1
2
b7
3
4
b7
5
< 8-bit read>
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 2.8.3 Structure of A/D conversion register (low-order)
A/D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A/D conversion register (high-order) (ADH) [Address : 3616]
B
Function
At reset
R W
?
✕
?
✕
?
✕
3
?
✕
4
?
✕
5
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
stored.
1
b7
< 10-bit read>
b0
b9 b8
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 2.8.4 Structure of A/D conversion register (high-order)
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2.8 A/D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
Name
0 Timer Y interrupt request bit
1 Timer Z interrupt request bit
2 Timer A interrupt request bit
3 Serial I/O2 interrupt request
bit
4 AD converter interrupt
request bit
5 Timer 1 interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✕
0
✕
6 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 2.8.5 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Name
0 Timer Y interrupt
enable bit
1 Timer Z interrupt enable bit
2 Timer A interrupt enable bit
3 Serial I/O2 interrupt enable bit
4 AD conversion interrupt
enable bit
5 Timer 1 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
0
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
7
Fig. 2.8.6 Structure of Interrupt control register 2
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2.8 A/D converter
2.8.3 A/D converter application examples
(1) Setting of A/D converter
Figure 2.8.7 shows the relevant registers setting.
Process 1: Disable A/D conversion interrupt.
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
0
A/D conversion interrupt disabled
Process 2: Set A/D control register.
b7
b0
A/D control register (ADCON) [Address 3416]
Analog input pins selected
b2b1b 0
00
00
01
01
10
10
11
11
0: P20/AN0
1: P21/AN1
0: P22/AN2
1: P23/AN3
0: P24/AN4
1: P25/AN5
0: P26/AN6 (Note)
1: P27/AN7 (Note)
Note: These can be used only for 36-pin version.
Process 3: In order not to execute the no requested interrupt processing, set “0” (no requested)
to the A/D conversion interrupt request bit.
b7
b0
0
Interrupt request register 2 (IREQ2) [Address 3D16]
No A/D conversion interrupt request issued
Process 4: When the interrupt is used, set “1” (interrupt enabled) to
the A/D conversion interrupt enable bit.
b7
b0
Interrupt control register 2 (ICON2) [Address 3F16]
1
A/D conversion interrupt enabled
Process 5: Start A/D conversion.
b7
b0
0
A/D control register (ADCON) [Address 3416]
Start A/D conversion
Fig. 2.8.7 Relevant registers setting
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2.8 A/D converter
(2) Control procedure
Outline : The analog input voltage input from a sensor is converted to digital values.
Specifications : •The analog input voltage input from a sensor is converted to digital values.
•P2 0/AN 0 pin is used as an analog input pin.
Figure 2.8.8 shows a connection diagram, and Figure 2.8.9 shows an example of control procedure.
Sensor
P20/AN0
7540 Group
Fig. 2.8.8 Connection diagram
A/D conversion processing
Set “0” to the A/D conversion interrupt enable bit.
(A/D conversion interrupt disabled)
Set analog input pins
1
0 0 0 ADCON(Address 3416)
Analog input pins: P20/AN0
Set “0” to the A/D conversion interrupt request bit.
Set “1” to the A/D conversion interrupt enable bit.
(A/D conversion interrupt enabled) (Note 1)
Start A/D conversion
0
0 0 0 ADCON(Address 3416)
Start A/D conversion
N
A/D conversion completed ? (Note 2)
Y
Read ADH (address 3616) (Note 3)
Read ADL (address 3516) (Note 4)
RTS
Notes 1: In this case, the A/D conversion interrupt is used.
2: The completion of the A/D conversion is checked by the following;
• The A/D conversion completion bit of the A/D control register is “1”.
• The A/D conversion interrupt request bit of the interrupt request register 2 is “1”.
• Branch to the A/D conversion interrupt processing routine is executed. (In this time,
the A/D conversion interrupt is enabled.)
3: At 10-bit read: the conversion result of the high-order 2 bits (b9, b8) can be read.
At 8-bit read: Not used.
4: At 10-bit read: the conversion result of the low-order 8 bits (b7 to b0) can be read.
At 8-bit read: the conversion result of b7 to b0 can be read.
Fig. 2.8.9 Control procedure
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2.8 A/D converter
2.8.4 Notes on A/D converter
Notes on A/D converter are described below.
(1) Analog input pin
Figure 2.8.10 shows the internal equivalent circuit of an analog input. In order to execute the A/D
conversion correctly, to complete the charge to an internal capacitor within the specified time is
required. The maximum output impedance of the analog input source required to complete the
charge to a capacitor within the specified time is as follows;
About 35 kΩ (at f(X IN) = 8 MHz)
When the maximum output impedance exceeds the above value, equip an analog input pin with an
external capacitor of 0.01µF to 1µF between an analog input pin and V SS.
Further, be sure to verify the operation of application products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion/comparison precision to be worse.
VCC
(Note 1)
C2
1.5 pF(Typical)
R 1.5 kΩ(Typical)
ANi (i=0 to 7: 36-pin version
i=0 to 5: 32-pin version)
SW1
(Note 2)
C1
12 pF(Typical)
(Note 1)
VSS
VSS
Typical voltage
generation circuit
Switch tree,
ladder resistor
Notes 1: This is a parasitic diode.
2: Only the selected analog input pin is turned on.
Chopper Amp.
A/D control circuit
VSS
VREF
Fig. 2.8.10 Connection diagram
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(X IN) is 500 kHz or more
• Do not execute the STP instruction
(3) Note on A/D converter
As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage
is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF
voltage and Vcc voltage are set up to the same value.
(2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become
extremely low compared with that at room temperature When the system would be used at low
temperature, the use at VREF=3.0 V or more is recommended.
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2.9 Reset
2.9 Oscillation control
This paragraph explains the registers setting method and the notes relevant to the oscillation control.
2.9.1 Memory map
003816
MISRG
003916
Watchdog timer control register (WDTCON)
003B16
CPU mode register (CPUM)
Fig. 2.9.1 Memory map of registers relevant to oscillation control
2.9.2 Relevant registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG [Address : 3816]
B
Name
0 Oscillation stabilization time
set bit after release of the
STP instruction
Function
0 : Set “0116” in timer 1, and
“FF16” in prescaler 1
automatically
1 : Not set automatically
1 Ceramic or RC oscillation stop 0 : Detection function inactive
detection function active bit
2 These are reserved bits.
Do not write “1” to these bits.
1 : Detection function active
At reset
R W
0
0
0
✕
0
✕
0
✕
5
0
✕
6
0
✕
(Note)
✕
3
4 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 Oscillation stop detection
status bit
0 : Oscillation stop not detected
1 : Oscillation stop detected
Note: “0” at normal reset
“1” at reset by detecting the oscillation stop
Fig. 2.9.2 Structure of MISRG
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2.9 Reset
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 39
B
Name
16]
Function
At reset
R W
1
✕
1
1
✕
2
1
✕
3
1
✕
4
1
✕
5
1
✕
0 Watchdog timer H
(The high-order 6 bits are read-only bits.)
0 : STP instruction enabled
1 : STP instruction disabled
0 : Watchdog timer L underflow
1 : f(X IN)/16
6 STP instruction disable bit
7 Watchdog timer H count
source selection bit
0
0
Fig. 2.9.3 Structure of Watchdog timer control register
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16]
B
Name
0 Processor mode bits (Note 1)
1
2
Stack page selection bit
3 On-chip oscillator oscillation
control bit
4 XIN oscillation control bit
5 Oscillation mode selection bit
(Note 1)
6
Clock division ratio selection
bits
7
Function
b1 b0
0
0
1
1
0 : Single-chip mode
1 : Not available
0 : Not available
1 : Not available
At reset
0
0
0 : 0 page
1 : 1 page
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
0
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
0 : Ceramic oscillation
1 : RC oscillation
0
b7 b6
0 0 : φ = f(XIN)/2
(high-speed mode)
0 1 : φ = f(XIN)/8
(middle-speed mode)
1 0 : Applied from on-chip oscillator
1 1 : φ = f(XIN)
(double-speed mode)
(Note 2)
R W
0
0
0
1
Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is
disable to write any data to the bit. However, by reset the bit is initialized and
can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU “M37540RSS”.)
2: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 2.9.4 Structure of CPU mode register
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2.9 Reset
2.9.3 Application example of on-chip oscillator
The on-chip oscillator is the oscillation circuit which is equipped with the 7540 Group. External circuits can
be eliminated by using this oscillator as the operation clock or by using this oscillator with a ceramic or
RC oscillation circuit. When this oscillator is used as the operation clock, all peripheral functions can be
used. In this section, the setting method and application example are explained.
Note: The 7540 Group starts operation by the on-chip oscillator.
(1) Setting method
Figure 2.9.5 shows the setting method when the on-chip oscillator is used as the operation clock.
Process 1: Enable on-chip oscillator oscillation.
b7
b0
0
0 0
CPU mode register (CPUM) [Address 3B16]
on-chip oscillatior oscillation enabled
Process 2: Set the operation clock to on-chip oscillator.
b7
1 0
b0
0
0 0
CPU mode register (CPUM) [Address 3B16]
Applied from on-chip oscillator
Process 3: When f(XIN) is not used, stop f(XIN).
b7
1 0
b0
1 0
0 0
CPU mode register (CPUM) [Address 3B16]
Ceramic or RC oscillation stop
Fig. 2.9.5 Setting method when the on-chip oscillator is used as the operation clock
(2) Example of control procedure
Outline: The frequency of the on-chip oscillator is measured, and an error by the power source
voltage or temperature is confirmed.
Specifications: • The f(X IN ) = 4 MHz is divided by timer Z and 10 ms is detected. The on-chip
oscillator is divided by timer Y.
• The count value of timer Y is read out in the timer Z interrupt processing routine
which occurs every 10 ms, and an error from f(XIN) is confirmed.
Figure 2.9.6 shows an example of control procedure.
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2.9 Reset
RESET
Initialization
SEI
CLD
CLT
Set CPU mode register
1 0 0 0 0 0 0 CPU M(Address 3B16)
Single-chip mode
O n -ch ip oscilla tor oscillation enab le d
f(XIN) oscillation (ceramic/RC)
enabled
Ceramic oscillation
Applied from on-chip oscillator
Wait until f(XIN) oscillation is stabilized (Note 1)
Set CPU mode register
0 0 0 0 0 CPU M(Address 3B16)
00 : φ=f(XIN)/2 (High-speed mode)
01 : φ=f(XIN)/8 (Middle-speed mode)
10 : Applied from on-chip oscillator
(Note 2)
11 : φ=f(XIN) (Double-speed mode)
Set “0” to the timer Y interrupt enable bit.
(Timer Y interrupt disabled)
Set “0” to the timer Z interrupt enable bit.
(Timer Z interrupt disabled)
Set timer Y, Z mode register
1
0 0 1
0 0 TYZM(Address 2016)
Timer Y: Timer mode selected
Timer Y count stop
Timer Z: Timer mode selected
Timer Z count stop
Set timer count source set register
0 0 0 1 1 0
TCSS(Address 2E16)
Timer Y count source:
On-chip oscillator selected
Timer Z: f(XIN)/2 selected
Set value to prescaler Y, timer Y
“FF 16”
Prescaler Y (Address 2116)
“FF 16”
Timer Y (Address 2316)
Set value to prescaler Z, timer Z (Note 3)
“F916”
Prescaler Z (Address 2516)
“4F16”
Timer Z primary (Address 2716 )
Set “0” to the timer Y interrupt request bit.
Set “0” to the timer Z interrupt request bit.
Set “1” to the timer Z interrupt enable bit.
(Timer Z interrupt enabled)
Set timer Y, Z mode register
0
0 0 0
0 0 TYZM(Address 2016)
Timer Y count start
Timer Z count start
Notes 1: For the concrete time, ask the oscillator manufacture.
2: In this example, this setting cannot be selected.
3: 10 ms = 1/4 MHz ✕ 2 ✕ (F916 + 1) ✕ (4F16 + 1)
Timer Z
division
ratio
Prescaler Z
Timer Z
primary
CLI
Timer Z interrupt processing routine
Read prescaler Y and timer Y and
compare their complement with the setting
values of prescaler Z and timer Z
Processing
Processing
RTI
Fig. 2.9.6 Control procedure
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2.9.4 Oscillation stop detection circuit
The oscillation stop detection circuit can be used to detect the stop by some failure or disconnection of
an external ceramic oscillation circuit.
In this section, the setting method and application example.
(1) Operation description
When the stop of an external oscillation circuit is detected by the oscillation stop detection circuit,
the oscillation stop detection status bit of MISRG is set to “1” and the internal reset occurs.
The 7540 Group starts operation by the on-chip oscillator after system is released from reset.
Accordingly, error of the external oscillation circuit can be detected by checking the oscillation stop
detection status bit after system starts operation.
Notes 1: When the stop mode is used, set the oscillation stop detection function to “invalid”.
2: When f(XIN) oscillation is stopped, set the oscillation stop detection function to “invalid”.
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(2) Setting method
Figure 2.9.7 shows the initial setting method oscillation stop detection circuit.
Figure 2.9.8 shows the setting method for the oscillation stop detection circuit in the main processing.
* Execute the following set at the beginning of program after system is released from reset.
Process 1: Check that reset by oscillation stop detection is executed
by referring the oscillation stop detection status bit.
b7
b0
0 0 0 0 0
MISRG (MISRG) [Address 3816]
Oscillation stop detection status bit
0: Oscillation stop not detected
1: Oscillation stop detected
• Oscillation stop is detected
Some error occus in the oscillation circuit.
Do not switch the operation clock and execute the processing when some error occurs.
• Oscillation stop is not detected
Execute the Process 2.
Process 2: Select oscillation mode.
b7
b0
1 0
0 0
0 0
CPU mode register (CPUM) [Address 3B16]
Oscillation mode selection bit (Note)
0: Ceramic oscillation
1: RC oscillation
Note: The bit can be rewritten only once after releasing reset. After rewriting it is disable to write
any data to the bit. However, by reset the bit is initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU “M37540RSS”).
Process 3: Wait oscillation stabilizing (Note).
Note: This process can be eliminated when the RC oscillation is selected.
For the oscillation stabilizing time, ask the oscillator manufacture.
Process 4: Set the ceramic or RC oscillation stop detection function active bit.
b7
b0
MISRG (MISRG) [Address 3816]
0 0 0 0 0 1
Detection function active (Note)
Note: When some error occurs in the oscillation circuit, system is released from reset
after setting of Process 4 is executed.
Process 5: Select clock division ratio.
b7
b0
0 0
CPU mode register (CPUM) [Address 3B16]
Clock division ratio selection bits
b7b6
0 0: f(φ) = f(XIN)/2 (high-speed mode)
0 1: f(φ)= f(XIN)/8 (middle-speed mode)
1 0: Applied from on-chip oscillator
1 1: f(φ)=f(XIN) (double-speed mode) (Note)
Note: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 2.9.7 Initial setting method for the oscillation stop detection circuit
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Process: Start on-chip oscillation when it is stopped.
b7
b0
0 0
0 0
CPU mode register (CPUM) [Address 3B16]
On-chip oscillatior oscillation enabled
Process 2: Set ceramic or RC oscillation stop detection function active bit.
b7
b0
0 0 0 0 0 1
MISRG (MISRG) [Address 3816]
Detection function active (Note)
Note: When some error occurs in the oscillation circuit, system is released from reset
after setting of Process 2 is executed.
Fig. 2.9.8 Setting method for the oscillation stop detection circuit in main processing
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2.9.5 State transition
In the 7540 Group, the operation clock is selected from the following 4 types.
• f(X IN)/2 (high-speed mode)
• f(X IN)/8 (middle-speed mode)
• On-chip oscillator
• f(X IN) (double-speed mode) (Note 1)
Note 1: f(X IN) can be used only at the ceramic oscillation. Do not use f(X IN) at RC oscillation.
Also, in the 7540 Group, the function to stop CPU operation by software and to keep CPU wait in the
following 2-type low power dissipation.
● Stop mode with the STP instruction (Notes 2, 3, 4, 5, 6, 7)
● Wait mode with the WIT instruction (Note 8)
Notes 2: When the stop mode is used, set the oscillation stop detection function to “invalid”.
3: When the stop mode is used, set “0” (STP instruction enabled) the STP instruction disable bit
of the watchdog timer control register.
4: Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The
oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/
“not set automaticallzy” by the oscillation stabilizing time set bit after release of the STP instruction
of MISRG. When “0” is set to this bit, “01 16” is set to timer 1 and “FF 16” is set to prescaler 1
automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set
the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is
used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode.
5: The STP instruction cannot be used during CPU is operating by the on-chip oscillator.
6: When the stop mode is used, stop the on-chip oscillator oscillation.
7: Do not execute the STP instruction during the A/D conversion.
8: When the wait mode is used, stop the clock except the operation clock source.
Figure 2.9.9 shows the state transition.
Stop mode
Wait mode
Interrupt
WIT
instruction
Interrupt
STP
instruction
State 1
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator stop
CPUM3←02
CPUM3←12
Interrupt
WIT
instruction
State 2
CPUM76←102
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled CPUM76←002
State 3
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enalbed
012
112
(Note 2)
MISRG1←12
MISRG1←02
MISRG1←12
State 2’
CPUM76←102
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled CPUM76←002
MISRG1←02
State 3’
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enalbed
012
112
(Note 2)
Oscillation stop detection circuit valid
Reset released
Reset state
CPUM4←12
CPUM4←02
State 4
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation stop
On-chip oscillator enalbed
Notes on switch of clock
(1) In operation clock source = f(XIN), the following can be
selected for the CPU clock division ratio.
● f(XIN)/2 (high-speed mode)
● f(XIN)/8 (middle-speed mode)
● f(XIN) (double-speed mode, only at a ceramic oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing XIN oscillation.
(3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 → state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
• CPUM76 → 102 (State 2 → state 3)
• NOP instruction
• CPUM4 → 12 (State 3 → state 4)
Double-speed mode at on-chip oscillator: NOP ✕ 3
High-speed mode at on-chip oscillator: NOP ✕ 1
Middle-speed mode at on-chip oscillator: NOP ✕ 0
Fig. 2.9.9 State transition
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(1) Example of control procedure
Outline: The on-chip oscillator is used, and the intermittent operation for the low-power dissipation
can be realized.
Specifications: A mode is selected from the following modes 1 to 4 according to the usage condition.
The return from mode 1 is executed by the timer A interrupt request which occurs
every 0.5 s.
Mode 1: Wait mode by the on-chip oscillator oscillation
Operation clock source: On-chip oscillator
CPU stop, ceramic oscillation stop, on-chip oscillator oscillation
Mode 2: Middle-speed mode by the on-chip oscillator oscillation
Operation clock source: On-chip oscillator
CPU operation, ceramic oscillation stop, on-chip oscillator oscillation
Mode 3: Middle-speed mode by the ceramic oscillation
Operation clock source: Ceramic oscillation
CPU operation, ceramic oscillation, on-chip oscillator oscillation
Mode 4: Double-speed mode by the ceramic oscillation
Operation clock source: Ceramic oscillation
CPU operation, ceramic oscillation, on-chip oscillator oscillation
Figure 2.9.10 shows an example of mode transition and Figure 2.9.11 shows an example of control
procedure.
Mode 4
Power dissipation
Ceramic oscillation
Double-speed mode (1/1)
Ceramic oscillation start
Middle-speed mode (1/8)
Wait m ode by
on-chip oscillation
• CPU stop
• TImer operating
CPU operation is started
by interrupt of timer
underflow
Mode 2
Mode 1
Mode 3
Mode 2
Mode 1
Mode 2
Mode 1
Mode 2
Mode 1
Time
Fig. 2.9.10 Example of mode transition
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2.9 Reset
RESET
Initialization
SEI
CLD
CLT
Operation mode by ceramic oscillation
Mode 3
Set CPU mode register
1 0 0 1 0
0 0
Set CPU mode register
1 0 0 0 0
0 0 CPUM(Address 3B16)
CPUM(Address 3B16)
f(XIN) oscillation (ceramic) enabled
Single-chip mode
O n -ch ip oscilla tor oscillation enab le d
f(XIN) oscillation (ceramic) stop
Ceramic oscillation
Ap plied from on-chip oscillator (N o te 1)
Wait until f(XIN) oscillation is stabilized (Note 4)
Set CPU mode register
0 1 0 0 0
Mode 2
00
CPUM(Address 3B16)
Middle-speed mode
Set “0” to the timer A interrupt enable bit.
(Timer A interrupt disabled)
Processing
Set timer A mode register
1
0 0
Switch to double-speed
mode is required?
TAM(Address 1D16)
Timer mode selected
Count stop
N
Y
Mode 4
Set values to timer A (Notes 2, 3)
Set CPU mode register
1 1 0 0 0
0 0 CPUM(Address 3B16)
“2316”
T im er A (low -order) [A ddress 1 E1 6]
“F416”
T im er A (high-o rder) [A ddress 1F 1 6]
Double-speed mode
Set “0” to the timer A interrupt request bit
Processing
Set “0” to the timer A interrupt enable bit.
(Timer A interrupt disabled)
Set “0” to other interrupt enable bits.
(Other interrups disabled)
Modes 3, 4 (common)
Set CPU mode register
1 0 0 1 0
0 0 CPUM(Address 3B16)
O n -ch ip oscilla tor oscillation enab le d
XIN oscillation (ceramic) stop
Applied from on-chip oscillator
CLI
Set timer A mode register
TAM(Address 1D16)
0
0 0
RTS
Count start
WIT instruction executed
Mode 1
Wait mode
Mode 2
Timer A interrupt processing routine
Processing
RTI
Mode 2
Set timer A mode register
1
0 0
TAM(Address 1D16)
Count stop
Notes 1: At VCC = 5 V, the timer A count source when an on-chip oscillator
is selected as the operation clock is as follows;
About 2 MHz / 16 = about 125 kHz
Processing
Timer A division ratio (fixed)
Switch to ceramic
oscillation is required?
Y
Modes 3, 4
Operation mode by ceramic oscillation
N
2: When setting the value to timer, set in order of low-order byte
and high-order byte following.
3: 0.5 s = 1/125 kHz ✕ (F42316 + 1)
Timer A setting value
4: For the concrete time, ask the oscillator manufacture.
Fig. 2.9.11 Control procedure
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2.9.6 Notes on oscillation stop detection circuit
Notes on using oscillation stop detection circuit are described below.
(1) Note on on-chip oscillator
➀ The 7540 Group starts operation by the on-chip oscillator.
➁ On-chip oscillator operation
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation
temperature range.
Be careful that variable frequencies when designing application products.
(2) Notes on oscillation circuit stop detection circuit
➀ When the stop mode is used, set the oscillation stop detection function to “invalid”.
➁ When f(X IN) oscillation is stopped, set the oscillation stop detection function to “invalid”.
➂ The oscillation stop detection circuit is not included in the emulator MCU “M37540RSS”.
(3) Notes on stop mode
➀ When the stop mode is used, set the oscillation stop detection function to “invalid”.
➁ When the stop mode is used, set “0” (STP instruction enabled) to the STP instruction disable bit
of the watchdog timer control register.
➂ Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The
oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/
“not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction
of MISRG. When “0” is set to this bit, “01 16 ” is set to timer 1 and “FF 16” is set to prescaler 1
automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set
the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is
used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode.
➃ The STP instruction cannot be used during CPU is operating by the on-chip oscillator.
➄ When the stop mode is used, stop the on-chip oscillator oscillation.
➅ Do not execute the STP instruction during the A/D conversion.
(4) Note on wait mode
➀ When the wait mode is used, stop the clock except the operation clock source.
(5) Notes on state transition
➀ When the operation clock source is f(XIN), the CPU clock division ratio can be selected from the
following;
• f(X IN)/2 (high-speed mode)
• f(X IN)/8 (middle-speed mode)
• f(X IN) (double-speed mode)
The double-speed mode can be used only at ceramic oscillation.
Do not use the mode at RC oscillation.
➁ Stabilize the f(XIN) oscillation to change the operation clock source from the on-chip oscillator to f(XIN).
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➂ When the on-chip oscillation is used as the operation clock, the CPU clock division ratio is the
middle-speed mode.
➃ When the state transition state 2→state 3→state 4 is performed, execute the NOP instruction as
shown below according to the division ratio of CPU clock.
• CPUM 76→10 2 (State 2→state 3)
• NOP instruction
• CPUM 4→1 2 (State 3→state 4)
Double-speed mode at on-chip oscillator: NOP✕3
High-speed mode at on-chip oscillator: NOP✕1
Middle-speed mode at on-chip oscillator: NOP✕0
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CHAPTER 3
APPENDIX
3.1
3.2
3.3
3.4
Electrical characteristics
Typical characteristics
Notes on use
Countermeasures against
noise
3.5 List of registers
3.6 Package outline
3.7 List of instruction code
3.8 Machine instructions
3.9 SFR memory map
3.10 Pin configurations
3.11 Differences between 7540
Group and 7531 Group
APPENDIX
7540 Group
3.1 Electrical characteristics
3.1 Electrical characteristics
3.1.1 7540 Group (General purpose)
Applied to: M37540M2-XXXFP/SP/GP, M37540M4-XXXFP/SP/GP, M37540E2FP/SP/GP, M37540E8FP/SP/GP
(1) Absolute Maximum Ratings (General purpose)
Table 3.1.1
Symbol
VCC
VI
VI
VI
VO
Pd
Topr
Tstg
Absolute maximum ratings
Parameter
Power source voltage
Input voltage
P00–P07, P10–P14, P20–P27, P30–P37, VREF
Input voltage RESET, XIN
Input voltage CNVSS (Note 2)
Output voltage
P00–P07, P10–P14, P20–P27, P30–P37, XOUT
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Ratings
–0.3 to 6.5 (Note 1)
–0.3 to VCC + 0.3
Unit
V
V
–0.3 to VCC + 0.3
–0.3 to 13
–0.3 to VCC + 0.3
V
V
V
300 (Note 3)
–20 to 85
–40 to 125
mW
°C
°C
Notes 1: This is the rating value for the Mask ROM version.
The rating value for the One Time PROM version is –0.3 to 7.0 V.
2: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version.
3: 200 mW for the 32P6U package product.
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APPENDIX
7540 Group
3.1 Electrical characteristics
(2) Recommended Operating Conditions (General purpose)
Table 3.1.2
Recommended operating conditions (1)
(V CC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
Parameter
Power source voltage (ceramic)
Power source voltage (RC)
VSS
VREF
VIH
VIH
VIH
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
f(XIN) = 8 MHz (High-, Middle-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 2 MHz (High-, Middle-speed mode)
f(XIN) = 6 MHz (Double-speed mode)
f(XIN) = 4 MHz (Double-speed mode)
f(XIN) = 2 MHz (Double-speed mode)
f(XIN) = 1 MHz (Double-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 2 MHz (High-, Middle-speed mode)
f(XIN) = 1 MHz (High-, Middle-speed mode)
Power source voltage
Analog reference voltage
“H” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“H” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“H” input voltage
RESET, XIN
“L” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“L” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total peak output current (Note 2)
P30–P36
“H” total average output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total average output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total average output current (Note 2)
P30–P36
Limits
Min.
4.0
2.4
2.2
4.5
4.0
2.4
2.2
4.0
2.4
2.2
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Unit
2.0
0.8VCC
VCC
VCC
V
V
V
V
V
V
V
V
V
V
V
V
V
2.0
VCC
V
0.8VCC
VCC
V
0
0.3VCC
V
0
0.8
V
0
0.2VCC
V
0
0.16VCC
V
–80
mA
80
mA
60
mA
–40
mA
40
mA
30
mA
Note 1: Vcc = 4.0 to 5.5V
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
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APPENDIX
7540 Group
Table 3.1.3
3.1 Electrical characteristics
Recommended operating conditions (2)
(V CC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
Parameter
Limits
Min.
“H” peak output current (Note 1)
P00–P07, P10–P14, P20–P27, P30–P37
“L” peak output current (Note 1)
P00–P07, P10–P14, P20–P27, P37
“L” peak output current (Note 1)
P30–P36
“H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37
“L” average output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” average output current (Note 2)
P30–P36
Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Typ.
Unit
Max.
–10
10
30
–5
5
15
6
mA
mA
mA
mA
mA
mA
MHz
4
MHz
2
MHz
1
MHz
8
MHz
4
MHz
2
MHz
4
MHz
2
MHz
1
MHz
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
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APPENDIX
7540 Group
3.1 Electrical characteristics
(3) Electrical Characteristics (General purpose)
Table 3.1.4
Electrical characteristics (1)
VCC = 2.2 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
ROSC
DOSC
Parameter
“H” output voltage
P00–P07, P10–P14, P20–P27, P30–P37 (Note 1)
“L” output voltage
P00–P07, P10–P14, P20–P27, P37
“L” output voltage
P30–P36
Hysteresis
CNTR0, CNTR1, INT0, INT1(Note 2)
P00–P07 (Note 3)
Hysteresis
RXD, SCLK1, SCLK2, SDATA2 (Note 2)
Hysteresis
RESET
“H” input current
P00–P07, P10–P14, P20–P27, P30–P37
“H” input current
RESET
“H” input current
XIN
“L” input current
P00–P07, P10–P14, P20–P27, P30–P37
“L” input current
RESET, CNVSS
“L” input current
XIN
“L” input current
P00–P07, P30–P37
RAM hold voltage
On-chip oscillator oscillation frequency
Oscillation stop detection circuit detection frequency
Test conditions
IOH = –5 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 2.2 to 5.5 V
IOL = 5 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
VCC = 2.2 to 5.5 V
IOL = 15 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 10 mA
VCC = 2.2 to 5.5 V
Min.
Typ.
Max.
Unit
VCC–1.5
V
VCC–1.0
V
V
0.3
V
1.0
V
2.0
V
0.3
V
1.0
V
0.4
V
0.5
V
0.5
V
VI = VCC
(Pin floating. Pull up
transistors “off”)
VI = VCC
VI = VCC
1.5
5.0
µA
5.0
µA
µA
4.0
VI = VSS
(Pin floating. Pull up
transistors “off”)
VI = VSS
–5.0
µA
–5.0
µA
µA
VI = VSS
–4.0
VI = VSS
(Pull up transistors “on”)
When clock stopped
VCC = 5.0 V, Ta = 25 °C
VCC = 5.0 V, Ta = 25 °C
–0.2
–0.5
mA
2000
125
5.5
3000
187.5
V
kHz
kHz
2.0
1000
62.5
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-5
APPENDIX
7540 Group
Table 3.1.5
3.1 Electrical characteristics
Electrical characteristics (2)
(V CC = 2.2 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
ICC
Parameter
Power source
current
Test conditions
One Time PROM
version
Mask ROM version
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V
Output transistors “off”
Double-speed mode, f(XIN) = 6 MHz
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz
Output transistors “off”
On-chip oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5V
Output transistors “off”
Increment when A/D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
Ta = 25 °C
(in STP state)
Ta = 85 °C
Output transistors “off”
High-speed mode, f(X IN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V
Output transistors “off”
Double-speed mode, f(XIN) = 6 MHz
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz
Output transistors “off”
On-chip oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5V
Output transistors “off”
Increment when A/D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
Ta = 25 °C
All oscillation stopped
(in STP state)
Ta = 85 °C
Output transistors “off”
Min.
Unit
Typ.
Max.
5.0
8.0
mA
0.5
1.5
mA
6.0
10.0
mA
2.0
5.0
mA
350
1000
µA
1.6
3.2
mA
0.2
150
mA
450
0.5
µA
mA
0.1
1.0
10
µA
µA
3.5
6.5
mA
0.4
1.2
mA
4.5
8.0
mA
2.0
5.0
mA
300
900
µA
1.6
3.2
mA
0.2
150
mA
450
0.5
0.1
µA
mA
1.0
10
µA
µA
3-6
APPENDIX
7540 Group
3.1 Electrical characteristics
(4) A/D Converter Characteristics (General purpose)
Table 3.1.6
A/D Converter characteristics
(V CC = 2.7 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
One Time
PROM version
Parameter
—
—
Resolution
Linearity error
—
Differential nonlinear error
VOT
Zero transition voltage
VFST
Full scale transition voltage
tCONV
Conversion time
RLADDER Ladder resistor
IVREF
Reference power source input current
Mask ROM version
II(AD)
—
—
A/D port input current
Resolution
Linearity error
—
Differential nonlinear error
VOT
Zero transition voltage
VFST
Full scale transition voltage
tCONV
Conversion time
RLADDER Ladder resistor
IVREF
Reference power source
input current
II(AD)
A/D port input current
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Test conditions
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
Limits
Min.
Typ.
0
0
5105
3060
5
3
5115
3069
50
50
55
150
70
0
0
5105
3060
15
9
5125
3075
50
50
55
150
70
Max.
Unit
10
±3
Bits
LSB
±0.9
LSB
20
15
5125
3075
122
mV
mV
mV
mV
tc(XIN)
kΩ
µA
200
120
5.0
10
±3
µA
Bits
LSB
±1.5
LSB
35
21
5150
3090
122
mV
mV
mV
mV
tc(XIN)
kΩ
µA
200
120
5.0
µA
3-7
APPENDIX
7540 Group
3.1 Electrical characteristics
(5) Timing Requirements (General purpose)
Table 3.1.7
Timing requirements (1)
(V CC = 4.0 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Limits
Parameter
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Min.
2
125
50
50
200
80
80
2000
800
800
800
370
370
220
100
1000
400
400
200
200
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Table 3.1.8
Timing requirements (2)
(V CC = 2.4 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
Limits
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Min.
2
250
100
100
500
230
230
4000
1600
1600
2000
950
950
400
200
2000
950
950
400
400
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-8
APPENDIX
7540 Group
Table 3.1.9
3.1 Electrical characteristics
Timing requirements (3)
(VCC = 2.2 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
Limits
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Min.
2
500
200
200
1000
460
460
8000
3200
3200
4000
1900
1900
800
400
4000
1900
1900
800
800
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-9
APPENDIX
7540 Group
3.1 Electrical characteristics
(6) Switching Characteristics (General purpose)
Table 3.1.10 Switching characteristics (1)
(V CC = 4.0 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Limits
Min.
Typ.
Max.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
140
–30
30
30
tC(SCLK2)/2–30
tC(SCLK2)/2–30
140
0
10
10
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Pin XOUT is excluded.
Table 3.1.11 Switching characteristics (2)
(V CC = 2.4 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Limits
Min.
Typ.
Max.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
350
–30
50
50
tC(SCLK2)/2–50
tC(SCLK2)/2–50
350
0
20
20
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Pin XOUT is excluded.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-10
APPENDIX
7540 Group
3.1 Electrical characteristics
Table 3.1.12 Switching characteristics (3)
(V CC = 2.2 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Limits
Min.
Typ.
Max.
tC(SCLK1)/2–70
tC(SCLK1)/2–70
450
–30
70
70
tC(SCLK2)/2–70
tC(SCLK2)/2–70
450
0
25
25
70
70
70
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Pin XOUT is excluded.
Measured
output pin
100 pF
///
CMOS output
Fig. 3.1.1
Switching characteristics measurement
circuit diagram (General purpose)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-11
APPENDIX
7540 Group
3.1 Electrical characteristics
tC(CNTR0)
tWL(CNTR0)
tWH(CNTR0)
CNTR0
0.8VCC
0.2VCC
tC(CNTR1)
tWL(CNTR1)
tWH(CNTR1)
0.8VCC
CNTR1
0.2VCC
tWL(CNTR0)
tWH(CNTR0)
INT0, INT1
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
tC(SCLK1)
tr
tf
SCLK1
0.2VCC
tWL(SCLK1)
tWH(SCLK1 )
0.8VCC
0.2VCC
tsu(RxD1-SCLK1)
th(SCLK1 -RxD1)
0.8VCC
0.2VCC
RXD1 (at receive)
td(SCLK1 -TxD1)
tv(SCLK1-TxD1)
TXD1 (at transmit)
tC(SCLK2)
tr
tf
SCLK2
tWL(SCLK2)
tWH(SCLK2 )
0.8VCC
0.2VCC
tsu(SDATA2 -SCLK2)
th(SCLK2 -SDATA2 )
0.8VCC
0.2VCC
SDATA2 (at receive)
td(SCLK2 -SDATA2 )
tv(SCLK2-SDATA2 )
SDATA2 (at transmit)
Fig. 3.1.2
Timing chart (General purpose)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-12
APPENDIX
7540 Group
3.1 Electrical characteristics
3.1.2 7540Group (Extended operating temperature version)
Applied to: M37540M2T-XXXFP/GP, M37540M4T-XXXFP/GP, M37540E8T-XXXFP/GP
(2) Absolute Maximum Ratings (Extended operating temperature version)
Table 3.1.13 Absolute maximum ratings
Symbol
VCC
VI
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage
P00–P07, P10–P14, P20–P27, P30–P37, VREF
Input voltage RESET, XIN, CNVSS
Output voltage
P00–P07, P10–P14, P20–P27, P30–P37, XOUT
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Ratings
–0.3 to 6.5 (Note 1)
–0.3 to VCC + 0.3
Unit
V
V
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
V
V
300 (Note 2)
–40 to 85
–65 to 150
mW
°C
°C
Notes 1: This is the rating value for the Mask ROM version.
The rating value for the One Time PROM version is –0.3 to 7.0 V.
2: 200 mW for the 32P6U package product.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-13
APPENDIX
7540 Group
3.1 Electrical characteristics
(2) Recommended Operating Conditions (Extended operating temperature version)
Table 3.1.14 Recommended operating conditions (1)
(V CC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
VCC
Parameter
Power source voltage (ceramic)
Power source voltage (RC)
VSS
VREF
VIH
VIH
VIH
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
f(XIN) = 8 MHz (High-, Middle-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 6 MHz (Double-speed mode)
f(XIN) = 4 MHz (Double-speed mode)
f(XIN) = 2 MHz (Double-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 2 MHz (High-, Middle-speed mode)
Power source voltage
Analog reference voltage
“H” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“H” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“H” input voltage
RESET, XIN
“L” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“L” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total peak output current (Note 2)
P30–P36
“H” total average output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total average output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total average output current (Note 2)
P30–P36
Limits
Min.
4.0
2.4
4.5
4.0
2.4
4.0
2.4
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Unit
2.0
0.8VCC
VCC
VCC
V
V
V
V
V
V
V
V
V
V
2.0
VCC
V
0.8VCC
VCC
V
0
0.3VCC
V
0
0.8
V
0
0.2VCC
V
0
0.16VCC
V
–80
mA
80
mA
60
mA
–40
mA
40
mA
30
mA
Note 1: Vcc = 4.0 to 5.5V
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-14
APPENDIX
7540 Group
3.1 Electrical characteristics
Table 3.1.15 Recommended operating conditions (2)
(V CC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
“H” peak output current (Note 1)
P00–P07, P10–P14, P20–P27, P30–P37
“L”
peak
output
current
(Note
1)
P0
0–P07, P10–P14, P20–P27, P37
IOL(peak)
“L”
peak
output
current
(Note
1)
P3
0–P36
IOL(peak)
“H”
average
output
current
(Note
2)
P0
0–P07, P10–P14, P20–P27, P30–P37
IOH(avg)
“L”
average
output
current
(Note
2)
P0
0–P07, P10–P14, P20–P27, P37
IOL(avg)
“L”
average
output
current
(Note
2)
P3
0–P36
IOL(avg)
Internal
clock
oscillation
frequency
(Note
3) VCC = 4.5 to 5.5 V
f(XIN)
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
IOH(peak)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Typ.
Unit
Max.
–10
10
30
–5
5
15
6
mA
mA
mA
mA
mA
mA
MHz
4
MHz
2
MHz
8
MHz
4
MHz
4
MHz
2
MHz
3-15
APPENDIX
7540 Group
3.1 Electrical characteristics
(3) Electrical Characteristics (Extended operating temperature version)
Table 3.1.16 Electrical characteristics (1)
(V CC = 2.4 to 5.5 V, V SS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
ROSC
DOSC
Parameter
“H” output voltage
P00–P07, P10–P14, P20–P27, P30–P37 (Note 1)
“L” output voltage
P00–P07, P10–P14, P20–P27, P37
“L” output voltage
P30–P36
Hysteresis
CNTR0, CNTR1, INT0, INT1(Note 2)
P00–P07 (Note 3)
Hysteresis
RXD, SCLK1, SCLK2, SDATA2 (Note 2)
Hysteresis
RESET
“H” input current
P00–P07, P10–P14, P20–P27, P30–P37
“H” input current
RESET
“H” input current
XIN
“L” input current
P00–P07, P10–P14, P20–P27, P30–P37
“L” input current
RESET, CNVSS
“L” input current
XIN
“L” input current
P00–P07, P30–P37
RAM hold voltage
On-chip oscillator oscillation frequency
Oscillation stop detection circuit detection frequency
Test conditions
IOH = –5 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 2.4 to 5.5 V
IOL = 5 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
VCC = 2.4 to 5.5 V
IOL = 15 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 10 mA
VCC = 2.4 to 5.5 V
Min.
Typ.
Max.
Unit
VCC–1.5
V
VCC–1.0
V
V
0.3
V
1.0
V
2.0
V
0.3
V
1.0
V
0.4
V
0.5
V
0.5
V
VI = VCC
(Pin floating. Pull up
transistors “off”)
VI = VCC
VI = VCC
1.5
5.0
µA
5.0
µA
µA
4.0
VI = VSS
(Pin floating. Pull up
transistors “off”)
VI = VSS
–5.0
µA
–5.0
µA
µA
VI = VSS
–4.0
VI = VSS
(Pull up transistors “on”)
When clock stopped
VCC = 5.0 V, Ta = 25 °C
VCC = 5.0 V, Ta = 25 °C
–0.2
–0.5
mA
2000
125
5.5
3000
187.5
V
kHz
kHz
2.0
1000
62.5
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-16
APPENDIX
7540 Group
3.1 Electrical characteristics
Table 3.1.17 Electrical characteristics (2)
(VCC = 2.4 to 5.5 V, V SS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Test conditions
Symbol
ICC
One Time PROM version High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V
Output transistors “off”
Double-speed mode, f(XIN) = 6 MHz,
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5V (in WIT state),
functions except timer 1 disabled, Output transistors “off”
Increment when A/D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
Ta = 25 °C
(in STP state)
Ta = 85 °C
Output transistors “off”
High-speed mode, f(XIN) = 8 MHz
Mask ROM version
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V
Output transistors “off”
Double-speed mode, f(XIN) = 6 MHz
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz
Output transistors “off”
On-chip oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5V (in WIT state),
functions except timer 1 disabled, Output transistors “off”
Increment when A/D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
Ta = 25 °C
(in STP state)
Ta = 85 °C
Output transistors “off”
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Min.
Unit
Typ.
Max.
5.0
8.0
mA
0.5
1.5
mA
6.0
10.0
mA
2.0
5.0
mA
350
1000
µA
1.6
3.2
mA
0.2
150
mA
450
0.5
µA
mA
0.1
1.0
10
µA
µA
3.5
6.5
mA
0.4
1.2
mA
4.5
8.0
mA
2.0
5.0
mA
300
900
µA
1.6
3.2
mA
0.2
150
mA
450
0.5
0.1
µA
mA
1.0
10
µA
µA
3-17
APPENDIX
7540 Group
3.1 Electrical characteristics
(4) A/D Converter Characteristics (Extended operating temperature version)
Table 3.1.18 A/D Converter characteristics
(V CC = 2.7 to 5.5 V, V SS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
One Time
PROM version
Parameter
—
—
Resolution
Linearity error
—
Differential nonlinear error
VOT
Zero transition voltage
VFST
Full scale transition voltage
tCONV
Conversion time
RLADDER Ladder resistor
IVREF
Reference power source input current
Mask ROM version
II(AD)
—
—
A/D port input current
Resolution
Linearity error
—
Differential nonlinear error
VOT
Zero transition voltage
VFST
Full scale transition voltage
tCONV
Conversion time
RLADDER Ladder resistor
IVREF
Reference power source
input current
II(AD)
A/D port input current
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Test conditions
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
Limits
Min.
Typ.
0
0
5105
3060
5
3
5115
3069
50
50
55
150
70
0
0
5105
3060
15
9
5125
3075
50
30
55
150
70
Max.
Unit
10
±3
Bits
LSB
±0.9
LSB
20
15
5125
3075
122
mV
mV
mV
mV
tc(XIN)
kΩ
µA
200
120
5.0
10
±3
µA
Bits
LSB
±1.5
LSB
35
21
5150
3090
122
mV
mV
mV
mV
tc(XIN)
200
120
5.0
kΩ
µA
µA
3-18
APPENDIX
7540 Group
3.1 Electrical characteristics
(5) Timing Requirements (Extended operating temperature version)
Table 3.1.19 Timing requirements (1)
(VCC = 4.0 to 5.5 V, V SS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
Limits
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Min.
2
125
50
50
200
80
80
2000
800
800
800
370
370
220
100
1000
400
400
200
200
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Table 3.1.20 Timing requirements (2)
(VCC = 2.4 to 5.5 V, V SS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
Limits
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Min.
2
250
100
100
500
230
230
4000
1600
1600
2000
950
950
400
200
2000
950
950
400
400
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-19
APPENDIX
7540 Group
3.1 Electrical characteristics
(6) Switching Characteristics (Extended operating temperature version)
Table 3.1.21 Switching characteristics (1)
(V CC = 4.0 to 5.5 V, V SS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Limits
Min.
Typ.
Max.
tC(SCLK1)/2–30
tC(SCLK1)/2–30
140
–30
30
30
tC(SCLK2)/2–30
tC(SCLK2)/2–30
140
0
30
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
10
10
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Pin XOUT is excluded.
Table 3.1.22 Switching characteristics (2)
(V CC = 2.4 to 5.5 V, V SS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Symbol
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Limits
Min.
Typ.
Max.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
350
–30
50
50
tC(SCLK2)/2–50
tC(SCLK2)/2–50
350
0
20
20
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Pin XOUT is excluded.
Measured
output pin
100 pF
///
CMOS output
Fig. 3.1.3
Switching characteristics measurement
circuit diagram (Extended operating
temperature)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-20
APPENDIX
7540 Group
3.1 Electrical characteristics
tC(CNTR0)
tWL(CNTR0)
tWH(CNTR0)
CNTR0
0.8VCC
0.2VCC
tC(CNTR1)
tWL(CNTR1)
tWH(CNTR1)
0.8VCC
CNTR1
0.2VCC
tWL(CNTR0)
tWH(CNTR0)
INT0, INT1
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
tC(SCLK1)
tr
tf
SCLK1
0.2VCC
tWL(SCLK1)
tWH(SCLK1 )
0.8VCC
0.2VCC
tsu(RxD1-SCLK1)
th(SCLK1 -RxD1)
0.8VCC
0.2VCC
RXD1 (at receive)
td(SCLK1 -TxD1)
tv(SCLK1-TxD1)
TXD1 (at transmit)
tC(SCLK2)
tr
tf
SCLK2
tWL(SCLK2)
tWH(SCLK2 )
0.8VCC
0.2VCC
tsu(SDATA2 -SCLK2)
th(SCLK2 -SDATA2 )
0.8VCC
0.2VCC
SDATA2 (at receive)
td(SCLK2 -SDATA2 )
tv(SCLK2-SDATA2 )
SDATA2 (at transmit)
Fig. 3.1.4
Timing chart (Extended operating temperature version)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-21
APPENDIX
7540 Group
3.1 Electrical characteristics
3.1.3 7540Group (Extended operating temperature 125 °C version)
Applied to: M37540M2V-XXXFP/GP, M37540M4V-XXXFP/GP, M37540E8V-XXXFP/GP
(1) Absolute Maximum Ratings (Extended operating temperature 125 °C version)
Table 3.1.23 Absolute maximum ratings
Symbol
VCC
VI
VI
VO
Pd
Topr
Tstg
Parameter
Power source voltage
Input voltage
P00–P07, P10–P14, P20–P27, P30–P37, VREF
Input voltage RESET, XIN, CNVSS
Output voltage
P00–P07, P10–P14, P20–P27, P30–P37, XOUT
Power dissipation
Operating temperature
Storage temperature
Conditions
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Ratings
–0.3 to 6.5 (Note 1)
–0.3 to VCC + 0.3
Unit
V
V
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
V
V
300 (Note 2)
–40 to 125 (Note 3)
–65 to 150
mW
°C
°C
Notes 1: This is the rating value for the Mask ROM version.
The rating value for the One Time PROM version is –0.3 to 7.0 V.
2: 200 mW for the 32P6U package product.
3: In this version, the operating temperature range and total time are limited as follows;
55 °C to 85 °C: within total 6000 hours,
85 °C to 125 °C: within total 1000 hours.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-22
APPENDIX
7540 Group
3.1 Electrical characteristics
(2) Recommended Operating Conditions (Extended operating temperature 125 °C version)
Table 3.1.24 Recommended operating conditions (1)
(V CC = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted)
Symbol
VCC
Parameter
Power source voltage (ceramic)
Power source voltage (RC)
VSS
VREF
VIH
VIH
VIH
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
f(XIN) = 8 MHz (High-, Middle-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 4 MHz (Double-speed mode)
f(XIN) = 2 MHz (Double-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 2 MHz (High-, Middle-speed mode)
Power source voltage
Analog reference voltage
“H” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“H” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“H” input voltage
RESET, XIN
“L” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“L” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total peak output current (Note 2)
P30–P36
“H” total average output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total average output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total average output current (Note 2)
P30–P36
Limits
Min.
4.0
2.4
4.0
2.4
4.0
2.4
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
Unit
2.0
0.8VCC
VCC
VCC
V
V
V
V
V
V
V
V
V
2.0
VCC
V
0.8VCC
VCC
V
0
0.3VCC
V
0
0.8
V
0
0.2VCC
V
0
0.16VCC
V
–80
mA
80
mA
60
mA
–40
mA
40
mA
30
mA
Note 1: Vcc = 4.0 to 5.5V
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-23
APPENDIX
7540 Group
3.1 Electrical characteristics
Table 3.1.25 Recommended operating conditions (2)
(V CC = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted)
Symbol
Parameter
Limits
Min.
“H” peak output current (Note 1)
P00–P07, P10–P14, P20–P27, P30–P37
“L” peak output current (Note 1)
P00–P07, P10–P14, P20–P27, P37
“L” peak output current (Note 1)
P30–P36
“H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37
“L” average output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” average output current (Note 2)
P30–P36
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at RC oscillation
High-, Middle-speed mode
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Typ.
Unit
Max.
–10
10
30
–5
5
15
4
mA
mA
mA
mA
mA
mA
MHz
2
MHz
8
MHz
4
MHz
4
MHz
2
MHz
3-24
APPENDIX
7540 Group
3.1 Electrical characteristics
(3) Electrical Characteristics (Extended operating temperature 125 °C version)
Table 3.1.26 Electrical characteristics (1)
(VCC = 2.4 to 5.5 V, V SS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Limits
Symbol
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
ROSC
DOSC
Parameter
“H” output voltage
P00–P07, P10–P14, P20–P27, P30–P37 (Note 1)
“L” output voltage
P00–P07, P10–P14, P20–P27, P37
“L” output voltage
P30–P36
Hysteresis
CNTR0, CNTR1, INT0, INT1(Note 2)
P00–P07 (Note 3)
Hysteresis
RXD, SCLK1, SCLK2, SDATA2 (Note 2)
Hysteresis
RESET
“H” input current
P00–P07, P10–P14, P20–P27, P30–P37
“H” input current
RESET
“H” input current
XIN
“L” input current
P00–P07, P10–P14, P20–P27, P30–P37
“L” input current
RESET, CNVSS
“L” input current
XIN
“L” input current
P00–P07, P30–P37
RAM hold voltage
On-chip oscillator oscillation frequency
Oscillation stop detection circuit detection frequency
Test conditions
IOH = –5 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 2.4 to 5.5 V
IOL = 5 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
VCC = 2.4 to 5.5 V
IOL = 15 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 10 mA
VCC = 2.4 to 5.5 V
Min.
Typ.
Max.
Unit
VCC–1.5
V
VCC–1.0
V
V
0.3
V
1.0
V
2.0
V
0.3
V
1.0
V
0.4
V
0.5
V
0.5
V
VI = VCC
(Pin floating. Pull up
transistors “off”)
VI = VCC
VI = VCC
1.5
5.0
µA
5.0
µA
µA
4.0
VI = VSS
(Pin floating. Pull up
transistors “off”)
VI = VSS
–5.0
µA
–5.0
µA
µA
VI = VSS
–4.0
VI = VSS
(Pull up transistors “on”)
When clock stopped
VCC = 5.0 V, Ta = 25 °C
VCC = 5.0 V, Ta = 25 °C
–0.2
–0.5
mA
2000
125
5.5
3000
187.5
V
kHz
kHz
2.0
1000
62.5
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-25
APPENDIX
7540 Group
3.1 Electrical characteristics
Table 3.1.27 Electrical characteristics (2)
(V CC = 2.4 to 5.5 V, V SS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Limits
Symbol
ICC
Test conditions
One Time PROM version High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5V (in WIT state),
functions except timer 1 disabled, Output transistors “off”
Increment when A/D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
Ta = 25 °C
All oscillation stopped
(in STP state)
Ta = 125 °C
Output transistors “off”
Mask ROM version
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
On-chip oscillator operation mode, VCC = 5V (in WIT state),
functions except timer 1 disabled, Output transistors “off”
Increment when A/D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
Ta = 25 °C
(in STP state)
Ta = 125 °C
Output transistors “off”
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Min.
Unit
Typ.
Max.
5.0
8.0
mA
0.5
1.5
mA
2.0
5.0
mA
350
1000
µA
1.6
3.2
mA
0.2
150
mA
450
0.5
µA
mA
0.1
1.0
50
µA
µA
3.5
6.5
mA
0.4
1.2
mA
2.0
5.0
mA
300
900
µA
1.6
3.2
mA
0.2
150
mA
450
0.5
0.1
µA
mA
1.0
50
µA
µA
3-26
APPENDIX
7540 Group
3.1 Electrical characteristics
(4) A/D Converter Characteristics (Extended operating temperature 125 °C version)
Table 3.1.28 A/D Converter characteristics
(VCC = 2.7 to 5.5 V, V SS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Symbol
One Time
PROM version
Parameter
—
—
Resolution
Linearity error
—
Differential nonlinear error
VOT
Zero transition voltage
VFST
Full scale transition voltage
tCONV
Conversion time
RLADDER Ladder resistor
IVREF
Reference power source input current
Mask ROM version
II(AD)
—
—
A/D port input current
Resolution
Linearity error
—
Differential nonlinear error
VOT
Zero transition voltage
VFST
Full scale transition voltage
tCONV
Conversion time
RLADDER Ladder resistor
IVREF
Reference power source
input current
II(AD)
A/D port input current
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Test conditions
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
Limits
Min.
Typ.
0
0
5105
3060
5
3
5115
3069
50
30
55
150
70
0
0
5105
3060
15
9
5125
3075
50
30
55
150
70
Max.
Unit
10
±3
Bits
LSB
±0.9
LSB
20
15
5125
3075
122
mV
mV
mV
mV
tc(XIN)
kΩ
µA
200
120
7.0
10
±3
µA
Bits
LSB
±1.5
LSB
35
21
5150
3090
122
mV
mV
mV
mV
tc(XIN)
kΩ
µA
200
120
7.0
µA
3-27
APPENDIX
7540 Group
3.1 Electrical characteristics
(5) Timing Requirements (Extended operating temperature 125 °C version)
Table 3.1.29 Timing requirements (1)
(V CC = 4.0 to 5.5 V, V SS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
Limits
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Min.
2
125
50
50
200
80
80
2000
800
800
800
370
370
220
100
1000
400
400
200
200
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Table 3.1.30 Timing requirements (2)
(V CC = 2.4 to 5.5 V, V SS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Symbol
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
Limits
Parameter
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
Min.
2
250
100
100
500
230
230
4000
1600
1600
2000
950
950
400
200
2000
950
950
400
400
Typ.
Unit
Max.
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-28
APPENDIX
7540 Group
3.1 Electrical characteristics
(6) Switching Characteristics (Extended operating temperature 125 °C version)
Table 3.1.30 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, V SS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Symbol
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Limits
Min.
Typ.
Max.
tC(SCLK1)/2–50
tC(SCLK1)/2–50
140
–30
30
30
tC(SCLK2)/2–50
tC(SCLK2)/2–50
140
0
10
10
30
30
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Pin XOUT is excluded.
Table 3.1.31 Switching characteristics (2)
(VCC = 2.4 to 5.5 V, V SS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Symbol
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Parameter
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Limits
Min.
Typ.
Max.
tC(SCLK1)/2–80
tC(SCLK1)/2–80
350
–30
50
50
tC(SCLK2)/2–80
tC(SCLK2)/2–80
350
0
20
20
50
50
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1: Pin XOUT is excluded.
Measured
output pin
100 pF
///
CMOS output
Fig. 3.1.5
Switching characteristics measurement
circuit diagram (Extended operating
temperature 125 °C version)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-29
APPENDIX
7540 Group
3.1 Electrical characteristics
tC(CNTR0)
tWL(CNTR0)
tWH(CNTR0)
CNTR0
0.8VCC
0.2VCC
tC(CNTR1)
tWL(CNTR1)
tWH(CNTR1)
0.8VCC
CNTR1
0.2VCC
tWL(CNTR0)
tWH(CNTR0)
INT0, INT1
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
tC(SCLK1)
tr
tf
SCLK1
0.2VCC
tWL(SCLK1)
tWH(SCLK1 )
0.8VCC
0.2VCC
tsu(RxD1-SCLK1)
th(SCLK1 -RxD1)
0.8VCC
0.2VCC
RXD1 (at receive)
td(SCLK1 -TxD1)
tv(SCLK1-TxD1)
TXD1 (at transmit)
tC(SCLK2)
tr
tf
SCLK2
tWL(SCLK2)
tWH(SCLK2 )
0.8VCC
0.2VCC
tsu(SDATA2 -SCLK2)
th(SCLK2 -SDATA2 )
0.8VCC
0.2VCC
SDATA2 (at receive)
td(SCLK2 -SDATA2 )
tv(SCLK2-SDATA2 )
SDATA2 (at transmit)
Fig. 3.1.6
Timing chart (Extended operating temperature 125 °C version)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-30
APPENDIX
7540 Group
3.2 Typical characteristics
3.2 Typical characteristics
Standard characteristics described below are just examples of the 7540 Group’s characteristics and are not
guaranteed. For rated values, refer to “3.1 Electrical characteristics”.
Power source current Icc [mA]
3.2.1 Mask ROM version
(1) Power source current characteristic example (V CC-ICC characteristics)
Measuring condition: When system is operating in double-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
f(X IN) = 6 MHz
6
f(X IN) = 4 MHz
4
f(X IN) = 2 MHz
f(X IN) = 1 MHz
2
0
2
Power source current Icc [mA]
Fig. 3.2.1 V CC-ICC
3
4
5
6
Power source voltage Vcc [V]
characteristics (in double-speed mode: Mask ROM version)
Measuring condition: When system is operating in high-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
5
f(X IN) = 8 MHz
4
f(X IN) = 4 MHz
3
f(X IN) = 2 MHz
2
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Power source current Icc [mA]
Fig. 3.2.2 V CC-ICC characteristics (in high-speed mode: Mask ROM version)
Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
3
f(X IN) = 8 MHz
f(X IN) = 4 MHz
2
f(X IN) = 2 MHz
1
0
2
Fig. 3.2.3 V CC-ICC
3
4
5
6
Power source voltage Vcc [V]
characteristics (in middle-speed mode: Mask ROM version)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-31
APPENDIX
7540 Group
3.2 Typical characteristics
Power source current Icc [mA]
Measuring condition: At WIT instruction execution (at wait), Ta = 25 °C, Ceramic oscillation
3
f(X IN) = 8 MHz
2
f(X IN) = 6 MHz
f(X IN) = 4 MHz
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.4 V CC-ICC characteristics (at WIT instruction execution: Mask ROM version)
Power source current Icc [nA]
Measuring condition: At STP instruction execution (at stop), Ta = 25 °C, On-chip oscillator stop
1.5
1.0
0.5
0.0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.5 V CC-ICC characteristics (at STP instruction execution: Mask ROM version)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-32
APPENDIX
7540 Group
3.2 Typical characteristics
Power source current Icc [mA]
Measuring condition: A/D conversion executed/not executed (f(XIN) = 8 MHz in high-speed mode),
Ta = 25 °C, Ceramic oscillation
8
6
During A/D conversion
4
During not A/D conversion
2
0
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.6 V CC-I CC characteristics (addition when operating A/D conversion, f(X IN) = 8 MHz in highspeed mode: Mask ROM version)
Power source current Icc [mA]
Measuring condition: A/D conversion executed/not executed (f(XIN) = 6 MHz in double-speed mode),
Ta = 25 °C, Ceramic oscillation
8
During A/D conversion
6
4
During not A/D conversion
2
0
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.7 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in doublespeed mode: Mask ROM version)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-33
APPENDIX
7540 Group
3.2 Typical characteristics
Power source current Icc [µA]
Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed),
Ceramic oscillation stop
600
Ta = –45 °C
Ta = –25 °C
400
Ta = 25 °C
Ta = 90 °C
Ta = 130 °C
200
0
2
3
4
5
6
Power source voltage Vcc [V]
Power source current Icc [µA]
Fig. 3.2.8 VCC-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation
stop: Mask ROM version)
Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution
Ceramic oscillation stop
300
Ta = –45 °C
Ta = –25 °C
Ta = 25 °C
Ta = 90 °C
200
Ta = 130 °C
100
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.9 V CC-I CC characteristics (When system is operating by on-chip oscillator, at WIT instruction
execution, Ceramic oscillation stop: Mask ROM version)
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3.2 Typical characteristics
Power source current Icc [mA]
(2) Power source current characteristic example (f(X IN)-ICC characteristics)
Measuring condition: When system is operating in double-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
5
V CC = 5.0 V
4
3
2
V CC = 3.0 V
1
0
1
2
3
4
5
6
Oscillation frequency f(XIN) [MHz]
Power source current Icc [mA]
Fig. 3.2.10 f(XIN)-ICC characteristics (in double-speed mode: Mask ROM version)
Measuring condition: When system is operating in high-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
4
V CC = 5.0 V
3
2
V CC = 3.0 V
1
0
2
3
4
5
6
7
8
Oscillation frequency f(XIN) [MHz]
Power source current Icc [mA]
Fig. 3.2.11 f(XIN)-ICC characteristics (in high-speed mode: Mask ROM version)
Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
2.5
V CC = 5.0 V
2.0
1.5
1.0
V CC = 3.0 V
0.5
0.0
2
3
4
5
6
7
8
Oscillation frequency f(XIN) [MHz]
Fig. 3.2.12 f(XIN)-ICC characteristics (in middle-speed mode: Mask ROM version)
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3.2 Typical characteristics
Power source current Icc [mA]
Measuring condition: At WIT instruction execution, Ta = 25 °C, Ceramic oscillation
2.0
V CC = 5.0 V
1.5
1.0
0.5
V CC = 3.0 V
0.0
1
2
3
4
5
6
7
8
Oscillation frequency f(XIN) [MHz]
Fig. 3.2.13 f(X IN)-I CC characteristics (at WIT instruction execution: Mask ROM version)
Power source current Icc [µA]
(3) Power source current characteristic example (Ta-I CC characteristics)
Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed),
Ceramic oscillation stop
400
300
V CC = 5.0 V
200
100
V CC = 3.0 V
0
-50
-25
0
25
50
75
100
125
150
Operating temperature range [°C]
Fig. 3.2.14 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation
stop: Mask ROM version)
Power source current Icc [µA]
Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution,
Ceramic oscillation stop
200
150
V CC = 5.0 V
100
50
V CC = 3.0 V
0
-50
-25
0
25
50
75
100
125
150
Operating temperature range Ta [°C]
Fig. 3.2.15 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction
execution, Ceramic oscillation stop: Mask ROM version)
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3.2 Typical characteristics
(4) Port typical characteristic example (VCC-VIHL characteristics)
Measuring condition: VCC–V IHL characteristics of I/O port (CMOS), V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: P0 1–P0 7, P1 1, P2 0–P27, P3 0–P3 5)
Input voltage V IHL [V]
5
4
3
2
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.16 VCC-V IHL characteristics (I/O port (CMOS): Mask ROM version)
Measuring condition: V CC–V IHL characteristics of I/O port (TTL), V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: P1 0, P1 2, P13, P36, P3 7)
5
Input voltage V IHL [V]
4
3
2
1
0
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.17 VCC-V IHL characteristics (I/O port (TTL): Mask ROM version)
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3.2 Typical characteristics
Measuring condition: V CC–V IHL characteristics of RESET pin, V CC = 5.0 V, Ta = 25 °C
Input voltage V IHL [V]
5
4
“H” input voltage (V IH)
3
2
“L” input voltage (VIL)
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.18 V CC-VIHL characteristics (RESET pin: Mask ROM version)
Measuring condition: V CC–V IHL characteristics of X IN pin, V CC = 5.0 V, Ta = 25 °C
Input voltage V IHL [V]
5
4
3
2
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.19 VCC-V IHL characteristics (XIN pin: Mask ROM version)
Measuring condition: V CC –VIL characteristics of CNV SS pin, V CC = 5.0 V, Ta = 25 °C
Input voltage V IL [V]
5
4
3
2
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.20 VCC-V IL characteristics (CNVSS pin: Mask ROM version)
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3.2 Typical characteristics
Measuring condition: VCC–HYS characteristics of RESET pin, V CC = 5.0 V, Ta = 25 °C
1.0
Hysteresis HYS [V]
0.8
0.6
0.4
0.2
0.0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.21 V CC-HYS characteristics (RESET pin: Mask ROM version)
Measuring condition: V CC–HYS characteristics of SIO pin, V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: RxD1, SCLK1, SCLK2, S DATA2)
Hysteresis HYS [V]
1.0
0.8
0.6
0.4
0.2
0.0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.22 VCC-HYS characteristics (SIO pin: Mask ROM version)
Hysteresis HYS [V]
Measuring condition: V CC–HYS characteristics of INT pin, V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: CNTR 0, CNTR 1, INT 0, INT 1, P0 0–P07)
1.0
0.8
0.6
0.4
0.2
0.0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.23 VCC-HYS characteristics (INT pin: Mask ROM version)
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3.2 Typical characteristics
(5) Port typical characteristic example (VOH-I OH characteristics)
Measuring condition: V OH–I OH characteristics of P-channel (normal port), V CC = 3.0 V
(same characteristics pins: P0 0–P0 7, P1 0–P1 4, P20–P2 7, P30–P3 7)
“H” output current I OH [mA]
-15
Ta = –40 °C
-10
Ta = 25 °C
Ta = 125 °C
-5
0
0
1
2
3
“H” output voltage VOH [V]
Fig. 3.2.24 V OH-IOH characteristics of P-channel (V CC = 3.0 V, normal port: Mask ROM version)
“H” output current I OH [mA]
Measuring condition: V OH–I OH characteristics of P-channel (normal port), V CC = 5.0 V
(same characteristics pins: P0 0–P0 7, P1 0–P1 4, P20–P2 7, P30–P3 7)
-40
Ta = –40 °C
-30
Ta = 25 °C
Ta = 125 °C
-20
-10
0
0
1
2
3
4
5
“H” output voltage VOH [V]
Fig. 3.2.25 V OH-IOH characteristics of P-channel (V CC = 5.0 V, normal port: Mask ROM version)
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3.2 Typical characteristics
(6) Port typical characteristic example (VOL-I OL characteristics)
Measuring condition: VOL–I OL characteristics of N-channel (normal port), VCC = 3.0 V
(same characteristics pins: P0 0–P0 7, P10–P14, P2 0–P2 7, P3 7)
“L” output current IOL [mA]
25
Ta = –40 °C
20
Ta = 25 °C
15
Ta = 125 °C
10
5
0
0
1
2
3
“L” output voltage V OL [V]
Fig. 3.2.26 V OL-IOL characteristics of N-channel (VCC = 3.0 V, normal port: Mask ROM version)
Measuring condition: VOL–I OL characteristics of N-channel (normal port), VCC = 5.0 V
(same characteristics pins: P0 0–P0 7, P10–P14, P2 0–P2 7, P3 7)
60
“L” output current IOL [mA]
Ta = –40 °C
Ta = 25 °C
45
Ta = 125 °C
30
15
0
0
1
2
3
4
5
“L” output voltage VOL [V]
Fig. 3.2.27 V OL-IOL characteristics of N-channel (VCC = 5.0 V, normal port: Mask ROM version)
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3.2 Typical characteristics
Measuring condition: VOL–I OL characteristics of N-channel (LED drive port), VCC = 3.0 V
(same characteristics pins: P3 0–P3 6)
“L” output current IOL [mA]
50
Ta = –40 °C
40
Ta = 25 °C
30
Ta = 125 °C
20
10
0
0
1
2
3
“L” output voltage VOL [V]
Fig. 3.2.28 V OL-IOL characteristics of N-channel (VCC = 3.0 V, LED drive port: Mask ROM version)
Measuring condition: VOL–I OL characteristics of N-channel (LED drive port), VCC = 5.0 V
(same characteristics pins: P3 0–P3 6)
100
“L” output current IOL [mA]
Ta = –40 °C
Ta = 25 °C
80
Ta = 125 °C
60
40
20
0
0
1
2
3
4
5
“L” output voltage VOL [V]
Fig. 3.2.29 V OL-IOL characteristics of N-channel (VCC = 5.0 V, LED drive port: Mask ROM version)
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3.2 Typical characteristics
(7) Port typical characteristic example (V CC-IIL characteristics)
Measuring condition: Port “L” input current when connecting pull-up transistor
(same characteristics pins: P0 0–P0 7, P3 0–P3 7)
“L” output current IIL [mA]
-0.4
Ta = –45 °C
Ta = –25 °C
-0.3
Ta = 25 °C
Ta = 90 °C
-0.2
Ta = 130 °C
-0.1
0
2
3
4
5
6
Power source voltage V CC [V]
Fig. 3.2.30 V CC-IIL characteristics (Port “L” input current when connecting pull-up transistor: Mask
ROM version)
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3.2 Typical characteristics
(8) Port typical characteristic example (V IN-II(AD) characteristics)
Input current II(AD) [µA]
Measuring condition: f(XIN) = 8 MHz in high-speed mode, V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: P2 0–P2 7)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
1
2
3
4
5
Input voltage V IN [V]
Fig. 3.2.31 V IN -II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 8 MHz
in high-speed mode: Mask ROM version)
Input current II(AD) [µA]
Measuring condition: f(X IN) = 6 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 °C
(same characteristics pins: P2 0–P2 7)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
1
2
3
4
5
Input voltage V IN [V]
Fig. 3.2.32 V IN -II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 6 MHz
in double-speed mode: Mask ROM version)
Input current II(AD) [µA]
Measuring condition: f(X IN) = 4 MHz in double-speed mode, VCC = 5.0 V, Ta = 25 °C
(same characteristics pins: P2 0–P2 7)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
1
2
3
4
5
Input voltage V IN [V]
Fig. 3.2.33 V IN -II(AD) characteristics (A/D port input current during A/D conversion, f(XIN) = 4 MHz
in double-speed mode: Mask ROM version)
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3.2 Typical characteristics
(9) On-chip oscillator frequency typical characteristic example
Measuring parameter: On-chip oscillator frequency
On-chip oscillator frequency R OSC
[MHz]
4
Ta = –45 °C
3
Ta = –25 °C
Ta = 25 °C
2
Ta = 90 °C
Ta = 130 °C
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.34 V CC-ROSC characteristics (on-chip oscillator frequency: Mask ROM version)
On-chip oscillator frequency R OSC [MHz]
Measuring parameter: On-chip oscillator frequency
3
2
V CC = 5.0 V
1
V CC = 3.0 V
0
-60
-40
-20
0
20
40
60
80
100
120
140
Operating temperature range Ta [°C]
Fig. 3.2.35 Ta-R OSC characteristics (on-chip oscillator frequency: Mask ROM version)
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3.2 Typical characteristics
(10) RC oscillation frequency typical characteristic example
Measuring parameter: RC oscillation frequency
Measuring condition: V CC = 5.0 V, Ta = 25 °C, C = 33 pF
RC oscillation frequency f(XIN) [MHz]
6
5
4
3
2
1
0
0
10
20
30
40
50
External resistor R [kΩ]
Fig. 3.2.36 R-f(XIN) characteristics (RC oscillation frequency: Mask ROM version)
RC oscillation frequency f(XIN) [MHz]
Measuring parameter: RC oscillation frequency
Measuring condition: V CC = 5.0 V, Ta = 25 °C, R = 6.8 kΩ (fixed)
5
4
3
2
1
0
0
10
20
30
40
50
60
External capacitor C [pF]
Fig. 3.2.37 C-f(X IN) characteristics (RC oscillation frequency: Mask ROM version)
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APPENDIX
7540 Group
3.2 Typical characteristics
Measuring parameter: RC oscillation frequency
Measuring condition: Ta = 25 °C, f(XIN ) ≅ 4 MHz (R = 5.1 kΩ, C = 20 pF)
RC oscillation frequency f(XIN) [MHz]
5
4
3
2
1
0
2
3
4
5
6
Power source voltage VCC [V]
Fig. 3.2.38 V CC-f(X IN) characteristics (RC oscillation frequency: Mask ROM version)
Measuring parameter: RC oscillation frequency
Measuring condition: f(X IN) ≅ 4 MHz (R = 5.1 kΩ, C = 20 pF)
RC oscillation frequency f(XIN) [MHz]
5.0
V CC = 5.0 V
4.5
4.0
V CC = 3.0 V
3.5
3.0
-60
-40
-20
0
20
40
60
80
100
120
140
Operating temperature range Ta [°C]
Fig. 3.2.39 Ta-f(XIN) characteristics (RC oscillation frequency: Mask ROM version)
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3.2 Typical characteristics
(11) A/D conversion typical characteristics example
➀ Definition of A/D conversion accuracy
The A/D conversion accuracy is defined below (refer to Fig. 3.2.40).
●Relative accuracy
• Zero transition voltage (VOT)
This means an analog input voltage when the actual A/D conversion output data changes from
“0” to “1.”
• Full-scale transition voltage (V FST)
This means an analog input voltage when the actual A/D conversion output data changes from
“1023” to “1022.”
• Non-linearity error
This means a deviation from the line between VOT and VFST of a converted value between VOT and
VFST.
• Differential non-linearity error
This means a deviation from the input potential difference required to change a converted value
between V OT and VFST by 1 LSB of the 1 LSB at the relative accuracy.
●Absolute accuracy
This means a deviation from the ideal characteristics between 0 to VREF of actual A/D conversion
characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error=
c
Non-linearity error=
a [LSB]
b-a
a [LSB]
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB at relative accuracy
b: Vn+1-Vn
c: Difference between
the ideal Vn and actual Vn
Ideal line of A/D
conversion between
V0 to V1022
1
0
V0
V1
Vn
Zero transition voltage (V0T)
Vn+1
V1022
Analog voltage VREF
Fig. 3.2.40 Definition of A/D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
V FST – V OT
1022
VREF
• 1 LSB at absolute accuracy →
1024
• 1 LSB at relative accuracy →
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APPENDIX
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3.2 Typical characteristics
➁ A/D conversion accuracy typical characteristics-1
M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT
•V CC = 5.12 [V]
•V REF = 5.12 [V]
•X IN = 4 [MHz]
•Temp. = 25 [°C]
•CPU mode = double-speed mode
•Zero transition voltage: 13.75 mV
•Full-scale transition voltage: 5120.94 mV
•Differential non-linearity error: –1.72 mV (–0.34 LSB)
•Non-linearity error: –5.09 mV (–1.02 LSB)
ERROR/1LSB WIDTH [mV]
15
10
Reference(ERROR(ABSOLUTE))
5
1LSB WIDTH
0
0
32
64
128
160
192
224
256
0
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
-5
96
ERROR (LINEARITY)
-10
-15
ERROR/1LSB WIDTH [mV]
15
10
5
-5
-10
-15
ERROR/1LSB WIDTH [mV]
15
10
5
0
512
-5
-10
-15
ERROR/1LSB WIDTH [mV]
15
10
5
0
768
992
1024
-5
-10
-15
Fig. 3.2.41 A/D conversion accuracy typical characteristic example-1 (Mask ROM version)
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3.2 Typical characteristics
➂ A/D conversion accuracy typical characteristics-2
M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT
•VCC = 5.12 [V]
•VREF = 5.12 [V]
•XIN = 6 [MHz]
•Temp. = 25 [°C]
•CPU mode = double-speed mode
•Zero transition voltage: 14.38 mV
•Full-scale transition voltage: 5121.88 mV
•Differential non-linearity error: 1.41 mV (0.28 LSB)
•Non-linearity error: –4.23 mV (–0.85 LSB)
ERROR/1LSB WIDTH [mV]
15
Reference(ERROR(ABSOLUTE))
10
5
1LSB WIDTH
0
0
32
64
128
160
192
224
256
0
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
-5
96
ERROR (LINEARITY)
-10
-15
ERROR/1LSB WIDTH [mV]
15
10
5
-5
-10
-15
ERROR/1LSB WIDTH [mV]
15
10
5
0
512
-5
-10
-15
ERROR/1LSB WIDTH [mV]
15
10
5
0
768
992
1024
-5
-10
-15
Fig. 3.2.42 A/D conversion accuracy typical characteristic example-2 (Mask ROM version)
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3.2 Typical characteristics
➃ A/D conversion accuracy typical characteristics-3
M37540M4-XXXFP A/D CONVERTER STEP WIDTH MEASUREMENT
•V CC = 5.12 [V]
•V REF = 5.12 [V]
•X IN = 8 [MHz]
•Temp. = 25 [°C]
•CPU mode = high-speed mode
•Zero transition voltage: 30.31 mV
•Full-scale transition voltage: 5143.33 mV
•Differential non-linearity error: 1.72 mV (0.34 LSB)
•Non-linearity error: –7.64 mV (–1.53 LSB)
ERROR/1LSB WIDTH [mV]
30
25
Reference(ERROR(ABSOLUTE))
20
15
10
1LSB WIDTH
5
0
0
32
-5
64
96
128
160
192
224
256
ERROR (LINEARITY)
-10
ERROR/1LSB WIDTH [mV]
30
25
20
15
10
5
0
256
-5
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
-10
ERROR/1LSB WIDTH [mV]
30
25
20
15
10
5
0
512
-5
-10
ERROR/1LSB WIDTH [mV]
30
25
20
15
10
5
0
768
-5
992
1024
-10
Fig. 3.2.43 A/D conversion accuracy typical characteristic example-3 (Mask ROM version)
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3.2 Typical characteristics
Power source current Icc [mA]
3.2.2 One Time PROM version
(1) Power source current characteristic example (V CC-I CC characteristics)
Measuring condition: When system is operating in double-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
10
f(X IN) = 6 MHz
8
f(X IN) = 4 MHz
6
f(X IN) = 2 MHz
4
f(X IN) = 1 MHz
2
0
2
3
4
5
6
Power source voltage Vcc [V]
Power source current Icc [mA]
Fig. 3.2.44 VCC-ICC characteristics (in double-speed mode: One Time PROM version)
Measuring condition: When system is operating in high-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
8
f(X IN) = 8 MHz
6
f(X IN) = 4 MHz
4
f(X IN) = 2 MHz
2
0
2
3
4
5
6
Power source voltage Vcc [V]
Power source current Icc [mA]
Fig. 3.2.45 VCC-ICC characteristics (in high-speed mode: One Time PROM version)
Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
4
f(X IN) = 8 MHz
3
f(X IN) = 4 MHz
2
f(X IN) = 2 MHz
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.46 V CC-ICC characteristics (in middle-speed mode: One Time PROM version)
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3.2 Typical characteristics
Power source current Icc [mA]
Measuring condition: At WIT instruction execution (at wait), Ta = 25 °C, Ceramic oscillation
3
f(X IN) = 8 MHz
2
f(X IN) = 6 MHz
1
f(X IN) = 4 MHz
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.47 V CC-I CC characteristics (at WIT instruction execution: One Time PROM version)
Power source current Icc [nA]
Measuring condition: At STP instruction execution (at stop), Ta = 25 °C, On-chip oscillator stop
3
2
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.48 V CC-ICC characteristics (at STP instruction execution: One Time PROM version)
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3.2 Typical characteristics
Power source current Icc [mA]
Measuring condition: A/D conversion executed/not executed (f(XIN) = 8 MHz in high-speed mode),
Ta = 25 °C, Ceramic oscillation
8
During A/D conversion
6
During not A/D conversion
4
2
0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power source voltage Vcc [V]
Fig. 3.2.49 V CC-I CC characteristics (addition when operating A/D conversion, f(XIN) = 8 MHz in highspeed mode: One Time PROM version)
Power source current Icc [mA]
Measuring condition: A/D conversion executed/not executed (f(XIN) = 6 MHz in double-speed mode),
Ta = 25 °C, Ceramic oscillation
10
During A/D conversion
8
6
4
During not A/D conversion
2
0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
Power source voltage Vcc [V]
Fig. 3.2.50 VCC-ICC characteristics (addition when operating A/D conversion, f(XIN) = 6 MHz in doublespeed mode: One Time PROM version)
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7540 Group
3.2 Typical characteristics
Power source current Icc [µA]
Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed),
Ceramic oscillation stop
800
Ta = –45 °C
Ta = –25 °C
600
Ta = 25 °C
Ta = 90 °C
400
Ta = 130 °C
200
0
2
3
4
5
6
Power source voltage Vcc [V]
Power source current Icc [µA]
Fig. 3.2.51 VCC-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation
stop: One Time PROM version)
Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution
Ceramic oscillation stop
300
Ta = –45 °C
Ta = –25 °C
Ta = 25 °C
200
Ta = 90 °C
Ta = 130 °C
100
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.52 VCC-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction
execution, Ceramic oscillation stop: One Time PROM version)
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7540 Group
3.2 Typical characteristics
Power source current Icc [mA]
(2) Power source current characteristic example (f(X IN)-ICC characteristics)
Measuring condition: When system is operating in double-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
8
V CC = 5.0 V
6
4
2
V CC = 3.0 V
0
1
2
3
4
5
6
Oscillation frequency f(XIN) [MHz]
Power source current Icc [mA]
Fig. 3.2.53 f(X IN)-I CC characteristics (in double-speed mode: One Time PROM version)
Measuring condition: When system is operating in high-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
6
V CC = 5.0 V
4
2
V CC = 3.0 V
0
2
3
4
5
6
7
8
Oscillation frequency f(XIN) [MHz]
Power source current Icc [mA]
Fig. 3.2.54 f(X IN)-I CC characteristics (in high-speed mode: One Time PROM version)
Measuring condition: When system is operating in middle-speed mode (A/D conversion not executed),
Ta = 25 °C, Ceramic oscillation
3
V CC = 5.0 V
2
1
V CC = 3.0 V
0
2
3
4
5
6
7
8
Oscillation frequency f(XIN) [MHz]
Fig. 3.2.55 f(X IN)-I CC characteristics (in middle-speed mode: One Time PROM version)
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3.2 Typical characteristics
Power source current Icc [mA]
Measuring condition: At WIT instruction execution, Ta = 25 °C, Ceramic oscillation
2.0
1.5
V CC = 5.0 V
1.0
0.5
V CC = 3.0 V
0.0
1
2
3
4
5
6
7
8
Oscillation frequency f(XIN) [MHz]
Fig. 3.2.56 f(XIN)-ICC characteristics (at WIT instruction execution: One Time PROM version)
Power source current Icc [µA]
(3) Power source current characteristic example (Ta-I CC characteristics)
Measuring condition: When system is operating by on-chip oscillator (A/D conversion not executed),
Ceramic oscillation stop
500
400
V CC = 5.0 V
300
200
100
V CC = 3.0 V
0
-50
-25
0
25
50
75
100
125
150
Operating temperature range [°C]
Fig. 3.2.57 Ta-ICC characteristics (When system is operating by on-chip oscillator, Ceramic oscillation
stop: One Time PROM version)
Power source current Icc [µA]
Measuring condition: When system is operating by on-chip oscillator, at WIT instruction execution,
Ceramic oscillation stop
200
150
V CC = 5.0 V
100
50
V CC = 3.0 V
0
-50
-25
0
25
50
75
100
125
150
Operating temperature range Ta [°C]
Fig. 3.2.58 Ta-ICC characteristics (When system is operating by on-chip oscillator, at WIT instruction
execution, Ceramic oscillation stop: One Time PROM version)
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3.2 Typical characteristics
(4) Port typical characteristic example (VCC-V IHL characteristics)
Measuring condition: VCC –VIHL characteristics of I/O port (CMOS), VCC = 5.0 V, Ta = 25 °C
(same characteristics pins: P0 1–P0 7, P1 1, P2 0–P2 7, P3 0–P3 5)
Input voltage V IHL [V]
5
4
3
2
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.59 VCC-V IHL characteristics (I/O port (CMOS): One Time PROM version)
Measuring condition: V CC–V IHL characteristics of I/O port (TTL), V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: P1 0, P12, P13, P3 6, P3 7)
5
Input voltage V IHL [V]
4
3
2
1
0
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.60 VCC-V IHL characteristics (I/O port (TTL): One Time PROM version)
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3.2 Typical characteristics
Measuring condition: V CC–V IHL characteristics of RESET pin, V CC = 5.0 V, Ta = 25 °C
Input voltage V IHL [V]
5
4
“H” input voltage (V IH)
3
2
“L” input voltage (VIL)
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.61 VCC-VIHL characteristics (RESET pin: One Time PROM version)
Measuring condition: V CC–V IHL characteristics of X IN pin, V CC = 5.0 V, Ta = 25 °C
Input voltage V IHL [V]
5
4
3
2
1
0
2
3
4
Power source voltage
Vcc [V]
5
6
Fig. 3.2.62 VCC-V IHL characteristics (XIN pin: One Time PROM version)
Measuring condition: V CC–V IL characteristics of CNV SS pin, V CC = 5.0 V, Ta = 25 °C
Input voltage V IL [V]
5
4
3
2
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.63 VCC-V IL characteristics (CNVSS pin: One Time PROM version)
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3.2 Typical characteristics
Measuring condition: VCC –HYS characteristics of RESET pin, VCC = 5.0 V, Ta = 25 °C
1.0
Hysteresis HYS [V]
0.8
0.6
0.4
0.2
0.0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.64 V CC-HYS characteristics (RESET pin: One Time PROM version)
Measuring condition: V CC–HYS characteristics of SIO pin, V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: RxD 1, S CLK1, S CLK2, SDATA2)
Hysteresis HYS [V]
1.0
0.8
0.6
0.4
0.2
0.0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.65 VCC-HYS characteristics (SIO pin: One Time PROM version)
Measuring condition: V CC–HYS characteristics of INT pin, V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: CNTR 0, CNTR1, INT 0, INT 1, P00–P0 7)
Hysteresis HYS [V]
1.0
0.8
0.6
0.4
0.2
0.0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.66 VCC-HYS characteristics (INT pin: One Time PROM version)
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3.2 Typical characteristics
(5) Port typical characteristic example (VOH-I OH characteristics)
Measuring condition: VOH–I OH characteristics of P-channel (normal port), V CC = 3.0 V
(same characteristics pins: P00–P0 7, P10–P1 4, P2 0–P2 7, P3 0–P3 7)
“H” output current I OH [mA]
-15
Ta = 25 °C
-10
Ta = 125 °C
-5
0
0
1
2
3
“H” output voltage V OH [V]
Fig. 3.2.67 V OH-IOH characteristics of P-channel (V CC = 3.0 V, normal port: One Time PROM version)
“H” output current I OH [mA]
Measuring condition: VOH–I OH characteristics of P-channel (normal port), V CC = 5.0 V
(same characteristics pins: P00–P0 7, P10–P1 4, P2 0–P2 7, P3 0–P3 7)
-50
Ta = –40 °C
-40
Ta = 25 °C
-30
Ta = 125 °C
-20
-10
0
0
1
2
3
4
5
“H” output voltage VOH [V]
Fig. 3.2.68 V OH-IOH characteristics of P-channel (V CC = 5.0 V, normal port: One Time PROM version)
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3.2 Typical characteristics
(6) Port typical characteristic example (VOL-I OL characteristics)
Measuring condition: V OL–I OL characteristics of N-channel (normal port), VCC = 3.0 V
(same characteristics pins: P0 0–P0 7, P10–P1 4, P2 0–P2 7, P3 7)
“L” output current IOL [mA]
25
20
Ta = 25 °C
15
Ta = 125 °C
10
5
0
0
1
2
3
“L” output voltage VOL [V]
Fig. 3.2.69 V OL-IOL characteristics of N-channel (VCC = 3.0 V, normal port: One Time PROM version)
Measuring condition: V OL–I OL characteristics of N-channel (normal port), VCC = 5.0 V
(same characteristics pins: P0 0–P0 7, P10–P1 4, P2 0–P2 7, P3 7)
“L” output current IOL [mA]
60
Ta = –40 °C
45
Ta = 25 °C
Ta = 125 °C
30
15
0
0
1
2
3
4
5
“L” output voltage VOL [V]
Fig. 3.2.70 V OL-IOL characteristics of N-channel (VCC = 5.0 V, normal port: One Time PROM version)
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7540 Group
3.2 Typical characteristics
Measuring condition: VOL–I OL characteristics of N-channel (LED drive port), VCC = 3.0 V
(same characteristics pins: P3 0–P3 6)
“L” output current IOL [mA]
40
Ta = 25 °C
30
Ta = 125 °C
20
10
0
0
1
2
3
“L” output voltage V OL [V]
Fig. 3.2.71 VOL-IOL characteristics of N-channel (V CC = 3.0 V, LED drive port: One Time PROM version)
Measuring condition: VOL–I OL characteristics of N-channel (LED drive port), VCC = 5.0 V
(same characteristics pins: P3 0–P3 6)
“L” output current IOL [mA]
100
Ta = –40 °C
80
Ta = 25 °C
60
Ta = 125 °C
40
20
0
0
1
2
3
4
5
“L” output voltage VOL [V]
Fig. 3.2.72 VOL-IOL characteristics of N-channel (V CC = 5.0 V, LED drive port: One Time PROM version)
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7540 Group
3.2 Typical characteristics
(7) Port typical characteristic example (V CC-IIL characteristics)
“L” output current IIL [mA]
Measuring condition: Port “L” input current when connecting pull-up transistor
(same characteristics pins: P0 0–P07, P30–P37)
-0.5
Ta = –45 °C
Ta = –25 °C
-0.4
Ta = 25 °C
-0.3
Ta = 90 °C
-0.2
Ta = 130 °C
-0.1
0
2
3
4
5
6
Power source voltage VCC [V]
Fig. 3.2.73 V CC-IIL characteristics (Port “L” input current when connecting pull-up transistor: One
Time PROM version)
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7540 Group
3.2 Typical characteristics
(8) Port typical characteristic example (V IN-II(AD) characteristics)
Input current II(AD) [µA]
Measuring condition: f(XIN) = 8 MHz in high-speed mode, VCC = 5.0 V, Ta = 25 °C
(same characteristics pins: P2 0–P2 7)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
1
2
3
4
5
Input voltage V IN [V]
Fig. 3.2.74 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(X IN) = 8 MHz
in high-speed mode: One Time PROM version)
Input current II(AD) [µA]
Measuring condition: f(X IN) = 6 MHz in double-speed mode, V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: P2 0–P2 7)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
1
2
3
4
5
Input voltage V IN [V]
Fig. 3.2.75 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(X IN) = 6 MHz
in double-speed mode: One Time PROM version)
Input current II(AD) [µA]
Measuring condition: f(X IN) = 4 MHz in double-speed mode, V CC = 5.0 V, Ta = 25 °C
(same characteristics pins: P2 0–P2 7)
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
1
2
3
4
5
Input voltage V IN [V]
Fig. 3.2.76 V IN-II(AD) characteristics (A/D port input current during A/D conversion, f(X IN) = 4 MHz
in double-speed mode: One Time PROM version)
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7540 Group
3.2 Typical characteristics
(9) On-chip oscillator frequency typical characteristic example
On-chip oscillator frequency R OSC [MHz]
Measuring parameter: On-chip oscillator frequency
4
Ta = –45 °C
3
Ta = –25 °C
Ta = 25 °C
Ta = 90 °C
2
Ta = 130 °C
1
0
2
3
4
5
6
Power source voltage Vcc [V]
Fig. 3.2.77 VCC-ROSC characteristics (on-chip oscillator frequency: One Time PROM version)
On-chip oscillator frequency R OSC [MHz]
Measuring parameter: On-chip oscillator frequency
4
3
V CC = 5.0 V
2
1
V CC = 3.0 V
0
-60
-40
-20
0
20
40
60
80
100
120
140
Operating temperature range Ta [°C]
Fig. 3.2.78 Ta-R OSC characteristics (on-chip oscillator frequency: One Time PROM version)
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3.2 Typical characteristics
(10) RC oscillation frequency typical characteristic example
RC oscillation frequency f(XIN) [MHz]
Measuring parameter: RC oscillation frequency
Measuring condition: V CC = 5.0 V, Ta = 25 °C
6
C = 20 pF
C = 33 pF
4
C = 47 pF
2
0
0
10
20
30
40
50
External resistor R [kΩ]
Fig. 3.2.79 R-f(X IN) characteristics (RC oscillation frequency: One Time PROM version)
RC oscillation frequency f(XIN) [MHz]
Measuring parameter: RC oscillation frequency
Measuring condition: V CC = 5.0 V, Ta = 25 °C
8
R = 5.1 kΩ
6
R = 10 kΩ
4
R = 15 kΩ
2
0
0
10
20
30
40
50
60
External capacitor C [pF]
Fig. 3.2.80 C-f(X IN) characteristics (RC oscillation frequency: One Time PROM version)
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7540 Group
3.2 Typical characteristics
RC oscillation frequency f(XIN) [MHz]
Measuring parameter: RC oscillation frequency
Measuring condition: Ta = 25 °C, R = 5.1 kΩ/C = 33 pF
5.0
4.0
3.0
2.0
1.0
0.0
2
3
4
5
6
Power source voltage V CC [V]
Fig. 3.2.81 VCC-f(XIN) characteristics (RC oscillation frequency: One Time PROM version)
RC oscillation frequency f(XIN) [MHz]
Measuring parameter: RC oscillation frequency
Measuring condition: R = 5.1 kΩ, C = 33 pF
5.0
4.8
V CC = 5.0 V
4.6
V CC = 3.0 V
4.4
4.2
4.0
-60
-30
0
30
60
90
120
150
Operating temperature range Ta [°C]
Fig. 3.2.82 Ta-f(X IN) characteristics (RC oscillation frequency: One Time PROM version)
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3.2 Typical characteristics
(11) A/D conversion typical characteristics example
➀ Definition of A/D conversion accuracy
The A/D conversion accuracy is defined below (refer to Fig. 3.2.83).
●Relative accuracy
• Zero transition voltage (VOT)
This means an analog input voltage when the actual A/D conversion output data changes from
“0” to “1.”
• Full-scale transition voltage (VFST)
This means an analog input voltage when the actual A/D conversion output data changes from
“1023” to “1022.”
• Non-linearity error
This means a deviation from the line between VOT and VFST of a converted value between VOT and
VFST.
• Differential non-linearity error
This means a deviation from the input potential difference required to change a converted value
between V OT and VFST by 1 LSB of the 1 LSB at the relative accuracy.
●Absolute accuracy
This means a deviation from the ideal characteristics between 0 to VREF of actual A/D conversion
characteristics.
Output data
Full-scale transition voltage (VFST)
1023
1022
Differential non-linearity error=
c
Non-linearity error=
a [LSB]
b-a
a [LSB]
b
a
n+1
n
Actual A/D conversion
characteristics
c
a: 1LSB at relative accuracy
b: Vn+1-Vn
c: Difference between
the ideal Vn and actual Vn
Ideal line of A/D
conversion between
V0 to V1022
1
0
V0
Vn
V1
Zero transition voltage (V0T)
Vn+1
V1022
Analog voltage VREF
Fig. 3.2.83 Definition of A/D conversion accuracy
Vn: Analog input voltage when the output data changes from “n” to “n + 1” (n = 0 to 1022)
V FST – V OT
1022
VREF
• 1 LSB at absolute accuracy →
1024
• 1 LSB at relative accuracy →
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APPENDIX
7540 Group
3.2 Typical characteristics
➁ A/D conversion accuracy typical characteristics-1
M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT
•VCC = 5.12 [V]
•VREF = 5.12 [V]
•XIN = 4 [MHz]
•Temp. = 25 [°C]
•CPU mode = double-speed mode
•Zero transition voltage: 6.88 mV
•Full-scale transition voltage: 5115.63 mV
•Differential non-linearity error: –2.34 mV (–0.47 LSB)
•Non-linearity error: –5.66 mV (–1.13 LSB)
ERROR/1LSB WIDTH [mV]
10
1LSB WIDTH
5
Reference(ERROR(ABSOLUTE))
0
0
32
64
96
128
160
192
224
256
ERROR (LINEARITY)
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
0
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
992
1024
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
0
512
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
0
768
960
-5
-10
Fig. 3.2.84 A/D conversion accuracy typical characteristic example-1 (One Time PROM version)
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APPENDIX
7540 Group
3.2 Typical characteristics
➂ A/D conversion accuracy typical characteristics-2
M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT
•V CC = 5.12 [V]
•V REF = 5.12 [V]
•X IN = 6 [MHz]
•Temp. = 25 [°C]
•CPU mode = double-speed mode
•Zero transition voltage: 5.94 mV
•Full-scale transition voltage: 5113.44 mV
•Differential non-linearity error: 3.28 mV (0.66 LSB)
•Non-linearity error: –4.91 mV (–0.98 LSB)
ERROR/1LSB WIDTH [mV]
10
1LSB WIDTH
5
Reference(ERROR(ABSOLUTE))
0
0
32
64
0
256
288
320
544
800
96
ERROR (LINEARITY)
128
160
192
224
256
352
384
416
448
480
512
576
608
640
672
704
736
768
832
864
896
928
992
1024
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
0
512
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
0
768
960
-5
-10
Fig. 3.2.85 A/D conversion accuracy typical characteristic example-2 (One Time PROM version)
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7540 Group
3.2 Typical characteristics
➃ A/D conversion accuracy typical characteristics-3
M37540E8FP A/D CONVERTER STEP WIDTH MEASUREMENT
•VCC = 5.12 [V]
•VREF = 5.12 [V]
•XIN = 8 [MHz]
•Temp. = 25 [°C]
•CPU mode = high-speed mode
•Zero transition voltage: 5.63 mV
•Full-scale transition voltage: 5115.31 mV
•Differential non-linearity error: –2.66 mV (–0.53 LSB)
•Non-linearity error: –5.99 mV (–1.20 LSB)
ERROR/1LSB WIDTH [mV]
10
1LSB WIDTH
5
Reference(ERROR(ABSOLUTE))
0
0
32
64
96
128
160
192
224
256
ERROR (LINEARITY)
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
0
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
992
1024
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
0
512
-5
-10
ERROR/1LSB WIDTH [mV]
10
5
0
768
960
-5
-10
Fig. 3.2.86 A/D conversion accuracy typical characteristic example-3 (One Time PROM version)
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7540 Group
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on input and output ports
Notes on using input and output ports are described below.
(1) Notes in stand-by state
In stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an I/O
port “undefined”.
Pull-up (connect the port to V CC ) or pull-down (connect the port to V SS ) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using a built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to external.
● Reason
The output transistor becomes the OFF state, which causes the ports to be the high-impedance
state. Note that the level becomes “undefined” depending on external circuits.
Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the
state that input levels of a input port and an I/O port are “undefined”. This may cause power
source current.
* 1 stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
(2) Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction* 2, the value of the
unspecified bit may be changed.
● Reason
The bit managing instructions are read-modify-write form instructions for reading and writing data
by a byte unit. Accordingly, when these instructions are executed on a bit of the port latch of an
I/O port, the following is executed to all bits of the port latch.
• As for a bit which is set for an input port :
The pin state is read in the CPU, and is written to this bit after bit managing.
• As for a bit which is set for an output port :
The bit value of the port latch is read in the CPU, and is written to this bit after bit managing.
Note the following :
• Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
• As for a bit of the port latch which is set for an input port, its value may be changed even when
not specified with a bit managing instruction in case where the pin state differs from its port latch
contents.
* 2 bit managing instructions : SEB, and CLB instructions
(3) Usage for the 32-pin version
➀ Fix the P35, P3 6 pull-up control bit of the pull-up control register to “1”.
➁ Keep the P3 6/INT1 input level selection bit of the port P1P3 control register “0” (initial state).
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3.3 Notes on use
3.3.2 Termination of unused pins
(1) Terminate unused pins
➀ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the I/
O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a program runaway or noise, set
direction registers by program periodically to increase the reliability of program.
(2) Termination remarks
➀ Input ports and I/O ports :
Do not open in the input mode.
● Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➁ and
➂ shown on the above.
➁ I/O ports :
When setting for the input mode, do not connect to VCC or V SS directly.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between a port and V CC (or V SS ).
➂ I/O ports :
When setting for the input mode, do not connect multiple ports in a lump to VCC or V SS through
a resistor.
● Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
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3.3 Notes on use
3.3.3 Notes on Timer
• When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
• When a count source of timer X, timer Y or timer Z is switched, stop a count of timer X.
3.3.4 Notes on Timer A
Notes on using timer A are described below.
(1) Common to all modes
➀ When reading timer A (high-order) (TAH) and timer A (low-order) (TAL), the contents of timer A
is read out. Read both registers in order of TAH and TAL following, certainly.
TAH and TAL keep the values until they are read out.
Also, do not write to them during read. In this case, unexpected operation may occur.
➁ When writing data to TAL and TAH even when timer A is operating or stopped, the data are set
to timer A and timer A latch simultaneously. Write both registers in order of TAL and TAH following,
certainly.
Also, do not read them during write. In this case, unexpected operation may occur.
(2) Period measurement mode, event counter mode, and pulse width HL continuously measurement mode
➀ In order to use CNTR1 pin, set “0” to bit 0 of the port P0 direction register (input mode).
➁ In order to use CNTR1 pin, set “1” to bit 7 of the interrupt control register to disable the P0 0 keyon wakeup function.
➂ CNTR 1 interrupt active edge depends on the CNTR 1 active edge switch bit. When this bit is “0”,
the CNTR1 interrupt request bit is set to “1” at the falling edge of the CNTR1 pin input signal. When
this bit is “1”, the CNTR1 interrupt request bit is set to “1” at the rising edge of the CNTR1 pin input
signal.
However, in the pulse width HL continuously measurement mode, CNTR1 interrupt request is
generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
3.3.5 Notes on timer 1
Note on timer 1 is described below.
(1) Notes on set of the oscillation stabilizing time
Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The
oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/
“not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction
of MISRG. When “0” is set to this bit, “01 16” is set to timer 1 and “FF 16 ” is set to prescaler 1
automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set the
wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used,
set values again to timer 1 and prescaler 1 after system is returned from the stop mode.
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3.3.6 Notes on Timer X
Notes on using each mode of timer X are described below.
(1) Count source
➀ f(XIN) can be used only when a ceramic oscillator or an on-chip oscillator is used.
Do not use f(X IN) at RC oscillation.
(2) Pulse output mode
➀ In order to use CNTR 0 pin, set “1” to bit 4 of the port P1 direction register (output mode).
➁ In order to use TXOUT pin, set “1” to bit 3 of the port P0 direction register (output mode).
➂ CNTR 0 interrupt active edge depends on the CNTR 0 active edge switch bit. When this bit is “0”,
the CNTR0 interrupt request bit is set to “1” at the falling edge of CNTR 0 pin input signal. When
this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR 0 pin input
signal.
(3) Pulse width measurement mode
➀ In order to use CNTR 0 pin, set “1” to bit 4 of the port P1 direction register (output mode).
➁ CNTR 0 interrupt active edge depends on the CNTR 0 active edge switch bit. When this bit is “0”,
the CNTR0 interrupt request bit is set to “1” at the falling edge of CNTR 0 pin input signal. When
this bit is “1”, the CNTR 0 interrupt request bit is set to “1” at the rising edge of CNTR 0 pin input
signal.
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3.3 Notes on use
3.3.7 Notes on timer Y and timer Z
Notes on using each mode of Timer Y and Timer Z are described below.
(1) Timer mode (timer Y and timer Z)
➀ In the timer mode, TYP and TYS is not used.
(2) Programmable waveform generation mode (timer Y and timer Z)
➀ In the programmable waveform generation mode, values of TYS, EXPYP, and EXPYS are valid
by writing to TYP because the setting to them is executed all at once by writing to TYP. Even
when changing TYP is not required, write the same value again.
➁ In the programmable waveform generation mode, when the setting value is changed while the
waveform is output, set by software in order not to execute the writing to TYP and the timing of
timer underflow during the secondary interval simultaneously.
An example of a measurement is shown below.
ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using
timer Y interrupt.
Writing to primary is performed in by judging that there is no problem if the underflow by
secondary is completed with reference to primary write operation before.
(Depending on a primary and a secondary setting values, and primary write timing, it may
be impossible.)
➂ The waveform extension function by the timer Y waveform extension control bits can be used only
when “00 16” is set to Prescaler Y.
When the value other than “0016” is set to Prescaler Y, be sure to set “0” to EXPYP and EXPYS.
The waveform extension function by the timer Z waveform extension control bits can be used only
when “0016” is set to Prescaler Z. When the value other than “00 16” is set to Prescaler Z, be sure
to set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is selected as the timer Z
count source, the waveform extension function cannot be used.
➃ When using this mode, be sure to set “1” to the timer Y write control bit to select “write to latch
only”.
➄ When TYS is read out, the undefined value is read out. However, while timer Y counts the setting
value of TYS, the count value during the secondary interval can be obtained by reading the timer
Y primary.
➅ In order to use TY OUT pin, set “1” to bit 1 of the port P0 direction register (output mode).
(3) Programmable one-shot generation mode (timer Z)
➀ In the programmable one-shot generation mode, the value of EXPZP becomes valid by writing
to TZP. Even when changing TZP is not required, write the same value again.
➁ In the programmable one-shot generation mode, when the setting value is changed while the
waveform is output, set by software in order not to execute the writing to TZP and the timing of
timer underflow simultaneously.
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3.3 Notes on use
➂ The waveform extension function by the timer Z waveform extension control bits can be used only
when “00 16” is set to Prescaler Z.
When the value other than “00 16” is set to Prescaler Z, be sure to set “0” to EXPZP. Also, when
the timer Y underflow is selected as the timer Z count source, the waveform extension function
cannot be used.
An example of a measurement is shown below.
ex.) The underflow of timer is stored by polling etc. using timer Z interrupt.
Writing to primary is performed in by judging that there is no problem if the underflow by
secondary is completed with reference to primary write operation before.
(Depending on a primary setting value, primary write timing, software and timing of external
trigger to INT0 pin, it may be impossible.)
➃ When using this mode, be sure to set “1” to the timer Z write control bit to select “write to latch
only”.
➄ In order to use TZ OUT pin, set “1” to bit 2 of the port P0 direction register (output mode).
➅ Stop Timer Z to change the INT 0 pin one-shot trigger control bit and INT 0 pin one-shot trigger
active edge selection bit.
(4) Programmable wait one-shot generation mode (timer Z)
➀ In the programmable wait one-shot generation mode, values of TZS, EXPZP and EXPZS are valid
by writing to TZP. Even when changing TZP is not required, write the same value again.
An example of a measurement is shown below.
ex.) The underflow by the primary and the underflow by secondary are stored by polling etc. using
timer Z interrupt.
Writing is performed in by judging that there is no problem if the underflow by secondary is
completed with reference to primary write operation before.
(Depending on a primary setting value, primary write timing, software and timing of external
trigger to INT0 pin, it may be impossible.)
➁ In the programmable wait one-shot generation mode, when the setting value is changed while the
waveform is output, set by software in order not to execute the writing to TZP and the timing of
timer underflow during the secondary interval simultaneously.
➂ The waveform extension function by the timer Z waveform extension control bit can be used only
when “00 16” is set to Prescaler Z.
When the value other than “00 16” is set to Prescaler Z, be sure to set “0” to EXPZP and EXPZS.
Also, when the timer Y underflow is selected as the timer Z count source, the waveform extension
function cannot be used.
➃ When using this mode, be sure to set “1” to the timer Z write control bits to select “write to latch
only”.
➄ When TZS is read out, the undefined value is read out. However, while Timer Z counts the setting
value of TZS (during one-shot output), the count value during the secondary interval can be
obtained by reading TZP.
➅ In order to use TZ OUT pin, set “1” to bit 2 of the port P0 direction register (output mode).
➆ Stop Timer Z to change the INT 0 pin one-shot trigger control bit and INT 0 pin one-shot trigger
active edge selection bit.
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3.3 Notes on use
(5) Common to all modes (timer Y and timer Z)
Timer Y can stop counting by setting “1” to the timer Y count stop bit in any mode.
Also, when Timer Y underflows, the timer Y interrupt request bit is set to “1”.
Timer Y reloads the value of latch when counting is stopped by the timer Y count stop bit. (When
timer is read out while timer is stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
3.3.8 Notes on Serial I/O1
Notes on using serial I/O1 are described below.
(1) Notes when selecting clock synchronous serial I/O
➀ When the clock synchronous serial I/O1 is used, serial I/O2 cannot be used.
➁ When the transmit operation is stopped, clear the serial I/O1 enable bit and the transmit enable
bit to “0” (serial I/O1 and transmit disabled).
● Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/O1 enable bit is cleared to “0” (serial I/O1 disabled), the internal transmission is running
(in this case, since pins TxD1, RxD1, SCLK1, and S RDY1 function as I/O ports, the transmission data
is not output). When data is written to the transmit buffer register in this state, data starts to be
shifted to the transmit shift register. When the serial I/O1 enable bit is set to “1” at this time, the
data during internally shifting is output to the TxD1 pin and an operation failure occurs.
➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled), or
clear the serial I/O1 enable bit to “0” (serial I/O1 disabled).
➃ When the transmit/receive operation is stopped, clear both the transmit enable bit and receive
enable bit to “0” (transmit and receive disabled) simultaneously. (any one of data transmission and
reception cannot be stopped.)
● Reason
In the clock synchronous serial I/O mode, the same clock is used for transmission and reception.
If any one of transmission and reception is disabled, a bit error occurs because transmission and
reception cannot be synchronized.
In this mode, the clock circuit of the transmission circuit also operates for data reception. Accordingly,
the transmission circuit does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Also, the transmission circuit cannot be initialized even if the serial I/O1 enable bit is
cleared to “0” (serial I/O1 disabled) (same as ➁).
➄ When signals are output from the SRDY1 pin on the reception side by using an external clock, set
all of the receive enable bit, the SRDY1 output enable bit, and the transmit enable bit to “1”.
➅ When the S RDY1 signal input is used, set the using pin to the input mode before data is written to
the transmit/receive buffer register.
➆ Setup of a serial I/O1 synchronous clock selection bit when a clock synchronous serial I/O is selected;
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P1 2 pin turns into an input pin of a synchronous clock.
Setup of a S RDY1 output enable bit (SRDY1) when a clock synchronous serial I/O1 is selected;
“0” : P1 3 pin can be used as a normal I/O pin.
“1” : P1 3 pin turns into a SRDY1 output pin.
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(2) Notes when selecting UART
➀ When the clock asynchronous serial I/O1 (UART) is used, serial I/O2 can be used only when BRG
output divided by 16 is selected as the synchronous clock.
➁ When the transmit operation is stopped, clear the transmit enable bit to “0” (transmit disabled).
● Reason
Same as (1) ➁.
➂ When the receive operation is stopped, clear the receive enable bit to “0” (receive disabled).
➃ When the transmit/receive operation is stopped, clear the transmit enable bit to “0” (transmit
disabled) and receive enable bit to “0” (receive disabled).
➄ Setup of a serial I/O1 synchronous clock selection bit when a clock asynchronous (UART) serial
I/O is selected;
“0”: P1 2 pin can be used as a normal I/O pin.
“1”: P1 2 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin.
(3) Notes common to clock synchronous serial I/O and UART
Set the bits 0 to 3 and bit 6 of the
serial I/O1 control register
→
➁ The transmit shift completion flag changes
from “1” to “0” with a delay of 0.5 to 1.5
shift clocks. When data transmission is
controlled with referring to the flag after
writing the data to the transmit buffer register,
note the delay.
Clear both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
→
➀ Set the serial I/O control register again after
the transmission and the reception circuits
are reset by clearing both the transmit enable
bit and the receive enable bit to “0.”
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or one
of them to “1”
Can be set
with the LDM
instruction at
the same time
Fig. 3.3.1 Sequence of setting serial I/O1 control
register again
➂ When data transmission is executed at the state that an external clock input is selected as the
synchronous clock, set “1” to the transmit enable bit while the SCLK1 is “H” state. Also, write to the
transmit buffer register while the SCLK1 is “H” state.
➃ When the transmit interrupt is used, set as the following sequence.
❶ Serial I/O1 transmit interrupt enable bit is set to “0” (disabled).
❷ Serial I/O1 transmit enable bit is set to “1”.
❸ Serial I/O1 transmit interrupt request bit is set to “0”.
❹ Serial I/O1 transmit interrupt enable bit is set to “1” (enabled).
● Reason
When the transmit enable bit is set to “1”, the transmit buffer empty flag and transmit shift
completion flag are set to “1”.
Accordingly, even if the timing when any of the above flags is set to “1” is selected for the transmit
interrupt source, interrupt request occurs and the transmit interrupt request bit is set.
➄ Write to the baud rate generator (BRG) while the transmit/receive operation is stopped.
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3.3 Notes on use
3.3.9 Notes on serial I/O2
Notes on using serial I/O2 are described below.
(1) Note on serial I/O1
Serial I/O2 can be used only when serial I/O1 is not used or serial I/O1 is used as UART and the
BRG output divided by 16 is selected as the synchronous clock.
(2) Note on S CLK2 pin
When an external clock is selected, set “0” to bit 2 of the port P1 direction register (input mode).
(3) Note on S DATA2 pin
When P13/SRDY1/SDATA2 pin is used as the SDATA input, set “0” to bit 3 of the port P1 direction register
(input mode).
When the internal clock is selected as the transfer and P1 3/S DATA2 pin is set to the input mode, the
SDATA2 pin is in a high-impedance state after the data transfer is completed.
(4) Notes on serial I/O2 transmit/receive shift completion flag
➀ The transmit/receive shift completion flag of the serial I/O2 control register is “1” after transmit/
receive shift is completed. In order to set “0” to this flag, set data (dummy data at receive) to the
serial I/O2 register by program.
➁ Bit 7 (transmit/receive shift completion flag) of the serial I/O2 control register is set earlier than
the completion of the actual shift operation for a half cycle of shift clock. Accordingly, when the
shift completion is checked by using this bit, read/write the serial I/O2 register after a half or more
cycle of clock from the setting “1” to this bit is checked.
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3.3 Notes on use
3.3.10 Notes on A/D converter
Notes on A/D converter are described below.
(1) Analog input pin
Figure 3.3.2 shows the internal equivalent circuit of an analog input. In order to execute the A/D
conversion correctly, to complete the charge to an internal capacitor within the specified time is
required. The maximum output impedance of the analog input source required to complete the
charge to a capacitor within the specified time is as follows;
About 35 kΩ (at f(X IN) = 8 MHz)
When the maximum output impedance exceeds the above value, equip an analog input pin with an
external capacitor of 0.01µF to 1µF between an analog input pin and V SS.
Further, be sure to verify the operation of application products on the user side.
● Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion/comparison precision to be worse.
VCC
(Note 1)
C2
1.5 pF(Typical)
R 1.5 kΩ(Typical)
ANi (i=0 to 7: 36-pin version
i=0 to 5: 32-pin version)
SW1
(Note 2)
C1
12 pF(Typical)
(Note 1)
VSS
VSS
Typical voltage
generation circuit
Switch tree,
ladder resistor
Notes 1: This is a parasitic diode.
2: Only the selected analog input pin is turned on.
Chopper Amp.
A/D control circuit
VSS
VREF
Fig. 3.3.2 Connection diagram
(2) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(X IN) is 500 kHz or more
• Do not execute the STP instruction
(3) Note on A/D converter
As for AD translation accuracy, on the following operating conditions, accuracy may become low.
(1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage
is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF
voltage and Vcc voltage are set up to the same value.
(2) When VREF voltage is lower than [3.0 V], the accuracy at the low temperature may become
extremely low compared with that at room temperature When the system would be used at low
temperature, the use at VREF=3.0 V or more is recommended.
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3.3.11 Notes on oscillation stop detection circuit
Notes on using oscillation stop detection circuit are described below.
(1) Note on on-chip oscillator
➀ The 7540 Group starts operation by the on-chip oscillator.
➁ On-chip oscillator operation
The clock frequency of the on-chip oscillator depends on the supply voltage and the operation
temperature range.
Be careful that variable frequencies when designing application products.
(2) Notes on oscillation circuit stop detection circuit
➀ When the stop mode is used, set the oscillation stop detection function to “invalid”.
➁ When f(XIN) oscillation is stopped, set the oscillation stop detection function to “invalid”.
➂ The oscillation stop detection circuit is not included in the emulator MCU “M37540RSS”.
(3) Notes on stop mode
➀ When the stop mode is used, set the oscillation stop detection function to “invalid”.
➁ When the stop mode is used, set “0” (STP instruction enabled) to the STP instruction disable bit
of the watchdog timer control register.
➂ Timer 1 can be used to set the oscillation stabilizing time after release of the STP instruction. The
oscillation stabilizing time after release of STP instruction can be selected from “set automatically”/
“not set automatically” by the oscillation stabilizing time set bit after release of the STP instruction
of MISRG. When “0” is set to this bit, “01 16” is set to timer 1 and “FF 16” is set to prescaler 1
automatically. When “1” is set to this bit, nothing is set to timer 1 and prescaler 1. Therefore, set
the wait time according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is
used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode.
➃ The STP instruction cannot be used during CPU is operating by the on-chip oscillator.
➄ When the stop mode is used, stop the on-chip oscillator oscillation.
➅ Do not execute the STP instruction during the A/D conversion.
(4) Note on wait mode
➀ When the wait mode is used, stop the clock except the operation clock source.
(5) Notes on state transition
➀ When the operation clock source is f(XIN), the CPU clock division ratio can be selected from the
following;
• f(X IN)/2 (high-speed mode)
• f(X IN)/8 (middle-speed mode)
• f(X IN) (double-speed mode)
The double-speed mode can be used only at ceramic oscillation.
Do not use the mode at RC oscillation.
➁ Stabilize the f(XIN) oscillation to change the operation clock source from the on-chip oscillator to f(XIN).
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3.3 Notes on use
➂ When the on-chip oscillation is used as the operation clock, the CPU clock division ratio is the
middle-speed mode.
➃ When the state transition state 2→state 3→state 4 is performed, execute the NOP instruction as
shown below according to the division ratio of CPU clock.
• CPUM 76→10 2 (State 2→state 3)
• NOP instruction
• CPUM 4→1 2 (State 3→state 4)
Double-speed mode at on-chip oscillator: NOP✕3
High-speed mode at on-chip oscillator: NOP✕1
Middle-speed mode at on-chip oscillator: NOP✕0
(6) Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation
or an RC oscillation is selected by setting bit 5 of the CPU mode register.
(7) Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an
RC oscillation is selected.
(8) Clock division ratio, XIN oscillation control, on-chip oscillator control
The state transition shown in Figure 3.3.3 can be performed by setting the clock division ratio
selection bits (bits 7 and 6), X IN oscillation control bit (bit 4), on-chip oscillator oscillation control bit
(bit 3) of CPU mode register. Be careful of notes on use in Figure 3.3.3.
Stop mode
Wait mode
Interrupt
WIT
instruction
Interrupt
STP
instruction
State 1
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator stop
CPUM3←02
CPUM3←12
Interrupt
WIT
instruction
State 2
CPUM76←102
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled CPUM76←002
State 3
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enalbed
012
112
(Note 2)
MISRG1←12
MISRG1←02
MISRG1←12
State 2’
CPUM76←102
Operation clock source:
f(XIN) (Note 1)
f(XIN) oscillation enabled
On-chip oscillator enabled CPUM76←002
MISRG1←02
State 3’
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation enabled
On-chip oscillator enalbed
012
112
(Note 2)
Oscillation stop detection circuit valid
Reset released
Reset state
CPUM4←12
CPUM4←02
State 4
Operation clock source:
On-chip oscillator (Note 3)
f(XIN) oscillation stop
On-chip oscillator enalbed
Notes on switch of clock
(1) In operation clock source = f(XIN), the following can be
selected for the CPU clock division ratio.
● f(XIN)/2 (high-speed mode)
● f(XIN)/8 (middle-speed mode)
● f(XIN) (double-speed mode, only at a ceramic oscillation)
(2) Execute the state transition state 3 to state 2 or
state 3’ to state 2’ after stabilizing XIN oscillation.
(3) In operation clock source = on-chip oscillator, the middlespeed mode is selected for the CPU clock division ratio.
(4) When the state transition state 2 → state 3 → state 4
is performed, execute the NOP instruction as shown below
according to the division ratio of CPU clock.
• CPUM76 → 102 (State 2 → state 3)
• NOP instruction
• CPUM4 → 12 (State 3 → state 4)
Double-speed mode at on-chip oscillator: NOP ✕ 3
High-speed mode at on-chip oscillator: NOP ✕ 1
Middle-speed mode at on-chip oscillator: NOP ✕ 0
Fig. 3.3.3 State transition
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3.3 Notes on use
3.3.12 Notes on CPU mode register
(1) Switching method of CPU mode register after releasing reset
Switch the CPU mode register (CPUM) at the head of program after releasing reset in the following
method.
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Wait by on-chip oscillator operation
until establishment of oscillator clock
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Start with an on-chip oscillator (Note)
An initial value is set as a ceramic
oscillation mode. When it is switched to an
RC oscillation, its oscillation starts.
When using a ceramic oscillation, wait until
establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not
required basically (time to execute the instruction to
switch from an on-chip oscillator meets the
requirement).
Select 1/1, 1/2, 1/8 or on-chip oscillator.
Main routine
Note. After releasing reset the operation starts by starting an on-chip oscillator automatically.
Do not use an on-chip oscillator at ordinary operation.
Fig. 3.3.4 Switching method of CPU mode register
(2) CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation
modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program runaway), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write
any data to the bit. (The emulator MCU “M37540RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits
5, 1 and 0 are locked.
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3.3 Notes on use
3.3.13 Notes on interrupts
(1) Switching external interrupt detection edge
For the products able to switch the external interrupt detection edge, switch it as the following sequence.
Clear an interrupt enable bit to “0” (interrupt disabled)
↓
Switch the detection edge
↓
NOP (one or more instructions)
↓
Clear an interrupt request bit to “0”
(no interrupt request issued)
↓
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 3.3.5 Sequence of switch the detection edge
● Reason
The interrupt circuit recognizes the switching of the detection edge as the change of external input
signals. This may cause an unnecessary interrupt.
(2) Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request register
immediately after this bit is set to “0” by using a data transfer instruction, execute one or more
instructions before executing the BBC or BBS instruction.
● Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Data transfer instruction:
LDM, LDA, STA, STX, and STY instructions
Fig. 3.3.6 Sequence of check of interrupt request bit
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3.3 Notes on use
(3) Structure of interrupt control register 2
Fix the bit 7 of the interrupt control register 1 to “0”. Figure 3.3.7 shows the structure of the interrupt
control register 2.
b7
0
b0
Interrupt control register 2 (address: 003F 16)
Interrupt enable bit
Not used (fix this bit to “0”)
Fig. 3.3.7 Structure of interrupt control register 2
(4) Interrupt
When setting the followings, the interrupt request bit may be set to “1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address 003A16)
Timer X mode register (address 002B 16)
Timer A mode register (address 001D 16)
When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit).
➂ Set the corresponding interrupt request bit to “0” after 1 or more instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
3.3.14 Notes on RESET pin
(1) Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
● Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
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3.3 Notes on use
3.3.15 Notes on programming
(1) Processor status register
➀ Initializing of processor status register
Flags which affect program execution must be initialized after a reset.
In particular, it is essential to initialize the T and D flags because they have an important effect
on calculations.
● Reason
After a reset, the contents of the processor status register (PS) are undefined except for the I
flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.8 Initialization of processor status register
➁ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
↓
NOP
Fig. 3.3.9 Sequence of PLP instruction execution
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(S)+1
Stored PS
Fig. 3.3.10 Stack memory contents after PHP
instruction execution
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3.3 Notes on use
(2) Decimal calculations
➀ Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1” with the SED instruction. After executing the ADC or SBC instruction,
execute another instruction before executing the SEC, CLC, or CLD instruction.
➁ Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in the status register (the N, V,
and Z flags) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a borrow is generated. To determine whether a calculation has generated a carry, the C
flag must be initialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.11 Status flag at decimal calculations
(3) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
(4) Interrupts
The contents of the interrupt request bit do not change even if the BBC or BBS instruction is
executed immediately after they are changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed contents, execute one instruction
before executing the BBC or BBS instruction.
(5) Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is
“1”, addressing mode using direction register values as qualifiers, and bit test instructions such as
BBC and BBS.
It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write
instructions of direction registers for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA instruction, etc.
(6) A/D Conversion
Do not execute the STP instruction during A/D conversion.
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3.3 Notes on use
(7) Instruction Execution Timing
The instruction execution time can be obtained by multiplying the frequency of the internal clock f by
the number of cycles mentioned in the machine-language instruction table.
The frequency of the internal clock f is the same as that of the X IN in double-speed mode, twice the
X IN cycle in high-speed mode and 8 times the X IN cycle in middle-speed mode.
(8) CPU Mode Register
The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing
reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.)
When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits
can be used. Do not use it when an RC oscillation is selected.
3.3.16 Programming and test of built-in PROM version
As for in the One Time PROM version (shipped in blank), its built-in PROM can be read or programmed
with a general-purpose PROM programmer using a special programming adapter.
The programming test and screening for PROM of the One Time PROM version (shipped in blank) are not
performed in the assembly process and the following processes. To ensure reliability after programming,
performing programming and test according to the Figure 3.3.12 before actual use are recommended.
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
Caution: The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 3.3.12 Programming and testing of One Time PROM version
(1) One Time PROM Version
The CNVss pin is connected to the internal memory circuit block by a low-ohmic resistance, since
it has the multiplexed function to be a programmable power source pin (V PP pin) as well.
To improve the noise reduction, connect a track between CNVss pin and Vss pin with 1 to 10 kΩ
resistance.
The mask ROM version track of CNVss pin has no operational interference even if it is connected
via a resistor.
3.3.17 Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass
capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to
as close as possible. For bypass capacitor which should not be located too far from the pins to be
connected, a ceramic capacitor of 0.01 µF to 0.1 µF is recommended.
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3.3 Notes on use
3.3.18 Notes on built-in PROM version
(1) Programming adapter
Use a special programming adapter shown in Table 3.3.1 and a general-purpose PROM programmer
when reading from or programming to the built-in PROM in the built-in PROM version.
Table 3.3.1 Programming adapters
Part Number
Programming adapter
M37540E8GP (One Time PROM version shipped in blank)
PCA7435GPG03
M37540E8SP (One Time PROM version shipped in blank)
PCA7435SPG02
M37540E8FP (One Time PROM version shipped in blank)
PCA7435FPG02
(2) Programming/reading
In PROM mode, operation is the same as that of the M5M27C101AK, but programming conditions
of PROM programmer are not set automatically because there are no internal device ID codes.
Accurately set the following conditions for data programming /reading. Take care not to apply 21 V
to V PP pin (is also used as the CNV SS pin), or the product may be permanently damaged.
• Programming voltage: 12.5 V
• Setting of PROM programmer switch: refer to Table 3.3.2.
Table 3.3.2 PROM programmer address setting
PROM programmer
Part Number
start address
PROM programmer
end address
M37540E8GP
M37540E8SP
Address 08080 16 (Note)
Address 0FFFD16 (Note)
M37540E8FP
Note: Addersses 8080 16 to FFFD16 in the built-in PROM corresponds to addresses 0808016 to 0FFFD16 in
the PROM programmer.
3.3.19 Note on Power Source Voltage
When the power source voltage value of a microcomputer is less than the value which is indicated as the
recommended operating conditions, the microcomputer does not operate normally and may perform unstable
operation.
In a system where the power source voltage drops slowly when the power source voltage drops or the
power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended
operating conditions and design a system not to cause errors to the system by this unstable operation.
3.3.20 Electric Characteristic Differences Among Mask ROM and One TIme PROM Version MCUs
There are differences in electric characteristics, operation margin, noise immunity, and noise radiation
among mask ROM and One Time PROM version MCUs due to the differences in the manufacturing
processes.
When manufacturing an application system with One Time PROM version and then switching to use of the
mask ROM version, perform sufficient evaluations for the commercial samples of the mask ROM version.
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3.4 Countermeasures against noise
3.4 Countermeasures against noise
3.4.1 Shortest wiring length
(1) Package
Select the smallest possible package to make the total wiring length short.
● Reason
The wiring length depends on a microcomputer package. Use of a small package, for example
QFP and not DIP, makes the total wiring length short to reduce influence of noise.
DIP
SDIP
SOP
QFP
Fig. 3.4.1 Selection of packages
(2) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by the timing necessary conditions.
If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is completely initialized. This may cause
a program runaway.
Noise
Reset
circuit
RESET
VSS
VSS
N.G.
Reset
circuit
VSS
RESET
VSS
O.K.
Fig. 3.4.2 Wiring for the RESET pin
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3.4 Countermeasures against noise
(3) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected
to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the V SS pattern only for oscillation from other V SS patterns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the V SS
level of a microcomputer and the V SS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
XIN
XOUT
VSS
XIN
XOUT
VSS
O.K.
N.G.
Fig. 3.4.3 Wiring for clock I/O pins
(4) Wiring to CNV SS pin
Connect the CNV SS pin to the V SS pin with the shortest possible wiring.
● Reason
The processor mode of a microcomputer is influenced by a potential at the CNV SS pin. If a
potential difference is caused by the noise between pins CNVSS and VSS, the processor mode may
become unstable. This may cause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
VSS
VSS
N.G.
O.K.
Fig. 3.4.4 Wiring for CNV SS pin
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3.4 Countermeasures against noise
(5) Wiring to VPP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the
VSS pin. When not connecting the resistor, make the length of wiring between the VPP pin and the
VSS pin the shortest possible.
Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM
version, the microcomputer operates correctly.
● Reason
The VPP pin of the One Time PROM is the power source input pin for the built-in PROM. When
programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current
for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin,
abnormal instruction codes or data are read from the built-in PROM, which may cause a program
runaway.
Approximately
5kΩ
CNVSS/VPP
VSS
In the shortest
distance
Fig. 3.4.5 Wiring for the V PP pin of the One Time PROM
3.4.2 Connection of bypass capacitor across V SS line and VCC line
Connect an approximately 0.1 µF bypass capacitor across the V SS line and the V CC line as follows:
• Connect a bypass capacitor across the V SS pin and the V CC pin at equal length.
• Connect a bypass capacitor across the V SS pin and the V CC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for V SS line and V CC line.
• Connect the power source wiring via a bypass capacitor to the V SS pin and the V CC pin.
AA
AA
AA
AA
AA
VCC
VSS
N.G.
AA
AA
AA
AA
AA
VCC
VSS
O.K.
Fig. 3.4.6 Bypass capacitor across the V SS line and the VCC line
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3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the V SS pin at equal length.
● Reason
Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far from
the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily.
This long wiring functions as an antenna which feeds noise into the microcomputer, which causes
noise to an analog input pin.
Noise
(Note)
Microcomputer
Analog
input pin
Thermistor
N.G.
O.K.
VSS
Note : The resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.7 Analog signal line and a resistor and a capacitor
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
● Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
XIN
XOUT
VSS
Large
current
GND
Fig. 3.4.8 Wiring for a large current signal line
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3.4 Countermeasures against noise
(2) Installing oscillator away from signal lines where potential levels change frequently
Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential
levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines
which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect
other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms
may be deformed, which causes a microcomputer failure or a program runaway.
3) Oscillator protection using V SS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the V SS pattern to the microcomputer V SS pin with the shortest possible wiring. Besides,
separate this V SS pattern from other V SS patterns.
N.G.
Do not cross
An example of VSS patterns on the
underside of a printed circuit board
A
AAA
A
AAA
A
A
AAA
A
A
AA
AA
CNTR
XIN
XOUT
VSS
Fig. 3.4.9 Wiring of signal lines where potential
levels change frequently
Oscillator wiring
pattern example
XIN
XOUT
VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.4.10 VSS pattern on the underside of an oscillator
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as
follows:
O.K.
Noise
Data bus
<Hardware>
• Connect a resistor of 100 Ω or more to an
I/O port in series.
Noise
Direction register
N.G.
Port latch
<Software>
• As for an input port, read data several times
by a program for checking whether input
levels are equal or not.
• As for an output port, since the output data
may reverse because of noise, rewrite data
to its port latch at fixed periods.
• Rewrite data to direction registers and pullup control registers at fixed periods.
I/O port
pins
Fig. 3.4.11 Setup for I/O ports
Note: When a direction register is set for input port
again at fixed periods, a several-nanosecond
short pulse may be output from this port. If this
is undesirable, connect a capacitor to this port
to remove the noise pulse.
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3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥≥ (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comparing the SWDT contents with
counts of interrupt processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and determines to branch to the program
initialization routine for recovery processing in the following case:
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt processing.
• Determines that the main routine operates normally when the SWDT contents are reset to the
initial value N at almost fixed cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to branch to the program initialization
routine for recovery processing in the following case:
If the SWDT contents are not initialized to the initial value N but continued to decrement and if
they reach 0 or less.
≠N
Main routine
Interrupt processing routine
(SWDT)← N
(SWDT) ← (SWDT)—1
CLI
Interrupt processing
Main processing
(SWDT)
≤0?
(SWDT)
=N?
N
Interrupt processing
routine errors
>0
RTI
≤0
Return
Main routine
errors
Fig. 3.4.12 Watchdog timer by software
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3.5 List of registers
3.5 List of registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (Pi) (i = 0, 2, 3) [Address : 00 16, 04 16, 06 16]
B
Name
0 Port Pi 0
Function
●
In output mode
Write
Port latch
Read
●
In input mode
Write : Port latch
Read : Value of pins
1 Port Pi1
2 Port Pi2
At reset
R W
?
?
?
3 Port Pi3
?
4 Port Pi4
?
5 Port Pi5
?
6 Port Pi6
?
7 Port Pi7
?
Note: The 32-pin package versions have nothing to be allocated for the following:
•Bits 6 and 7 of port P2
•Bits 5 and 6 of port P3.
Fig. 3.5.1 Structure of Port Pi (i = 0, 2, 3)
Port P1
b7 b6 b5 b4 b3 b2 b1 b0
Port P1 (P1) [Address : 02 16]
B
Name
0 Port P1 0
Function
●
1 Port P1 1
●
2 Port P1 2
In output mode
Write
Port latch
Read
In input mode
Write : Port latch
Read : Value of pins
At reset
R W
?
?
?
3 Port P1 3
?
4 Port P1 4
?
5 Nothing is allocated for these bits.
?
✕ ✕
6
?
✕ ✕
7
?
✕ ✕
When these bits are read out, the values are undefined.
Fig. 3.5.2 Structure of Port P1
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3.5 List of registers
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (PiD) (i = 0, 2, 3) [Address : 01
B
1
2
3
4
5
6
7
05 16, 0716]
Function
Name
0 Port Pi direction register
16,
0 : Port Pi 0 input mode
1 : Port Pi 0 output mode
0 : Port Pi 1 input mode
1 : Port Pi 1 output mode
0 : Port Pi 2 input mode
1 : Port Pi 2 output mode
0 : Port Pi 3 input mode
1 : Port Pi 3 output mode
0 : Port Pi 4 input mode
1 : Port Pi 4 output mode
0 : Port Pi 5 input mode
1 : Port Pi 5 output mode
0 : Port Pi 6 input mode
1 : Port Pi 6 output mode
0 : Port Pi 7 input mode
1 : Port Pi 7 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
0
✕
Note: The 32-pin package versions have nothing to be allocated for the following:
•Bits 6 and 7 of P2D
•Bits 5 and 6 of P3D.
Fig. 3.5.3 Structure of Port Pi direction register (i = 0, 2, 3)
Port P1 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1 direction register (P1D) [Address : 03 16]
B
Function
Name
0 : Port P1 0 input mode
1 : Port P1 0 output mode
0 : Port P1 1 input mode
1 : Port P1 1 output mode
0 : Port P1 2 input mode
1 : Port P1 2 output mode
0 : Port P1 3 input mode
1 : Port P1 3 output mode
0 : Port P1 4 input mode
1 : Port P1 4 output mode
At reset
R W
0
✕
0
✕
0
✕
0
✕
0
✕
?
✕ ✕
6
?
✕ ✕
7
?
✕ ✕
0 Port P1 direction register
1
2
3
4
5 Nothing is allocated for these bits.
When these bits are read out, the values are undefined.
Fig. 3.5.4 Structure of Port P1 direction register
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APPENDIX
7540 Group
3.5 List of registers
Pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Pull-up control register (PULL) [Address : 1616]
Name
B
P
0
0
p
u
l
l
u
p
c
ontrol bit
0
1 P01 pull-up control bit
2 P02, P03 pull-up control bit
3 P04 – P07 pull-up control bit
4 P30 – P33 pull-up control bit
5 P34 pull-up control bit
6 P35, P36 pull-up control bit
7 P37 pull-up control bit
Function
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
0 : Pull-up Off
1 : Pull-up On
At reset
R W
0
0
0
0
0
0
0
0
Note: Pins set to output are disconnected from the pull-up control.
Fig. 3.5.5 Structure of Pull-up control register
Port P1P3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P1P3 control register (P1P3C) [Address : 17
B
Name
0 P37/INT0 input level selection
bit
1 P36/INT1 input level selection
bit (Note)
2 P10, P12,P1 3 input level
selection bit
16]
Function
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
0 : CMOS level
1 : TTL level
At reset
R W
0
0
0
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
3 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Note: Keep setting the P3 6/INT1 input level selection bit to “0” (initial value) for the
32-pin package version.
Fig. 3.5.6 Structure of Port P1P3 control register
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APPENDIX
7540 Group
3.5 List of registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register (TB/RB) [Address : 18 16]
B
Function
At reset
0 The transmission data is written to or the receive data is read out
from this buffer register.
1 • At writing: A data is written to the transmit buffer register.
• At reading: The contents of the receive buffer register are read
out.
2
R W
?
?
?
3
?
4
?
5
?
6
?
7
?
Note: The contents of transmit buffer register cannot be read out.
The data cannot be written to the receive buffer register.
Fig. 3.5.7 Structure of Transmit/Receive buffer register
Serial I/O1 status register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIO1STS) [Address : 19
B
Name
0 Transmit buffer empty flag
16]
Function
0 : Buffer full
1 : Buffer empty
0 : Buffer empty
1 : Buffer full
0 : Transmit shift in progress
1 : Transmit shift completed
At reset
R W
0
✕
0
✕
0
✕
3 Overrun error flag (OE)
0
✕
4
0
✕
0
✕
0
✕
1
✕
(TBE)
1 Receive buffer full flag (RBF)
2 Transmit shift register shift
completion flag (TSC)
5
6
7
0 : No error
1 : Overrun error
0 : No error
Parity error flag (PE)
1 : Parity error
0 : No error
Framing error flag (FE)
1 : Framing error
0 : (OE) ∪ (PE) ∪ (FE) = 0
Summing error flag (SE)
1 : (OE) ∪ (PE) ∪ (FE) = 1
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “1”.
Fig. 3.5.8 Structure of Serial I/O1 status register
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APPENDIX
7540 Group
3.5 List of registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register (SIO1CON) [Address : 1A
B
Function
Name
0 BRG count source
selection bit (CSS)
16]
0 : f(X IN)
1 : f(X IN)/4
2 SRDY1 output enable bit
(SRDY)
3 Transmit interrupt
source selection bit (TIC)
4 Transmit enable bit (TE)
5 Receive enable bit (RE)
6 Serial I/O1 mode selection bit
(SIOM)
7 Serial I/O1 enable bit
(SIOE)
R W
0
1 Serial I/O1 synchronous clock When clock synchronous serial I/O
selection bit (SCS)
At reset
0
is selected;
0: BRG output divided by 4
1: External clock input
When UART is selected;
0: BRG output divided by 16
1: External clock input divided by 16
0: P13 pin
1: SRDY1 output pin
0
0 : Interrupt when transmit buffer
has emptied
1 : Interrupt when transmit shift
operation is completed
0
0 : Transmit disabled
1 : Transmit enabled
0 : Receive disabled
1 : Receive enabled
0
0: Clock asynchronous (UART)
serial I/O
1: Clock synchronous serial I/O
0
0: Serial I/O1 disabled
1: Serial I/O1 enabled
0
0
Fig. 3.5.9 Structure of Serial I/O1 control register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
UART control register (UARTCON) [Address : 1B16]
B
0
1
2
3
4
Name
Character length
selection bit (CHAS)
Parity enable bit
(PARE)
Parity selection bit
(PARS)
Stop bit length selection
bit (STPS)
P11/TxD P-channel
output disable bit
(POFF)
Function
0 : 8 bits
1 : 7 bits
0 : Parity checking disabled
1 : Parity checking enabled
0 : Even parity
1 : Odd parity
0 : 1 stop bit
1 : 2 stop bits
In output mode
0 : CMOS output
1 : N-channel open-drain
output
5 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
0
0
1
✕
6
1
✕
7
1
✕
When these bits are read out, the values are “1”.
Fig. 3.5.10 Structure of UART control register
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APPENDIX
7540 Group
3.5 List of registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator (BRG) [Address : 1C 16]
B
Function
At reset
0 Set a count value of baud rate generator.
?
1
?
2
?
3
?
4
?
5
?
6
?
7
?
R W
Fig. 3.5.11 Structure of Baud rate generator
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APPENDIX
7540 Group
3.5 List of registers
Timer A mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer A mode register (TAM) [Address : 1D 16]
B
Function
Name
At reset
R W
0
✕
1
0
✕
2
0
✕
3
0
✕
0 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
4 Timer A operating mode bits
5
b5 b4
0
0
1
1
0 : Timer mode
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
0
0
6 CNTR 1 active edge switch bit
The function depends on the
operating mode.
(Refer to Table 3.5.1)
0
7 Timer A count stop bit
0 : Count start
1 : Count stop
0
Fig. 3.5.12 Structure of Timer A mode register
Table 3.5.1 CNTR 1 active edge switch bit function
Timer A operating modes
Timer mode
CNTR1 active edge switch bit
“0” CNTR 1 interrupt request occurrence: Falling edge
; No influence to timer A count
“1” CNTR 1 interrupt request occurrence: Rising edge
; No influence to timer A count
Period measurement mode
“0” Pulse output start: Falling edge period measurement
CNTR 1 interrupt request occurrence: Falling edge
“1” Pulse output start: Rising edge period measurement
CNTR 1 interrupt request occurrence: Rising edge
Event counter mode
“0” Timer A: Rising edge count
CNTR 1 interrupt request occurrence: Falling edge
“1” Timer A: Falling edge count
CNTR 1 interrupt request occurrence: Rising edge
Pulse width HL continuously
measurement mode
“0” CNTR 1 interrupt request occurrence: Falling edge and rising edge
; No influence to timer A count
“1” CNTR 1 interrupt request occurrence: Rising edge and falling edge
; No influence to timer A count
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APPENDIX
7540 Group
3.5 List of registers
Timer A register (low-order, high-order)
b7 b6 b5 b4 b3 b2 b1 b0
Timer A register (low-order, high-order) (TAL, TAH) [Address : 1E
B
16,
Function
1F 16]
At reset
R W
1
0 •Set a count value of timer A.
•The value set in this register is written to both timer A and timer A
latch at the same time.
•When this register is read out, the timer A’s count value is read
2 out.
1
1
1
3
1
4
1
5
1
6
1
7
1
Notes 1: Be sure to write to/read out both the low-order of timer A (TAL) and the highorder of timer A (TAH).
2: Read the high-order of timer A (TAH) first, and the high-order of timer A (TAL) next.
3: Write to the low-order of timer A (TAL) first, and the high-order of timer A (TAH) next.
4: Do not write to them during read, and do not read out them during write.
Fig. 3.5.13 Structure of Timer A register
Timer Y, Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y, Z mode register (TYZM) [Address : 20 16)
B
0
Function
Name
Timer Y operating mode bit
0 : Timer mode
1 : Programmable waveform
generation mode
1 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
0 : Write to latch and timer
2 Timer Y write control bit
simultaneously
(Note)
1 : Write to only latch
0 : Count start
3 Timer Y count stop bit
1 : Count stop
4 Timer Z operating mode bits
5
6 Timer Z write control bit
(Note)
7 Timer Z count stop bit
b5 b4
0 0 : Timer mode
0 1 : Programmable waveform
generation mode
1 0 : Programmable one-shot
generation mode
1 1 : Programmable wait one-shot
generation mode
At reset
R W
0
0
✕
0
0
0
0
0 : Write to latch and timer
simultaneously
1 : Write to only latch
0
0 : Count start
1 : Count stop
0
Note: When modes other than the timer mode, set these bits to “1”.
Fig. 3.5.14 Structure of Timer Y, Z mode register
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APPENDIX
7540 Group
3.5 List of registers
Prescaler Y, Prescaler Z
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler Y (PREY) [Address : 2116]
Prescaler Z (PREZ) [Address : 2516]
B
Function
At reset
0 •Set a count value of each prescaler.
1
2
3
4
5
R W
1
•While the corresponding timer is stopped, the value set in this
register is written to both prescaler
and the corresponding prescaler latch at the same time.
•While the corresponding timer is operating, the value set in this
register is written to as follows;
When the timer write control bit is “0”, the value is written to
prescaler latch and prescaler at the same time.
When the timer write control bit is “1”, the value is written to
prescaler latch only.
•When this register is read out, the count value of the
corresponding prescaler is read out.
1
1
1
1
1
6
1
7
1
Fig. 3.5.15 Structure of Prescaler Y, Prescaler Z
Timer Y secondary, Timer Z secondary
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y secondary, Timer Z secondary (TYS, TZS) [Address : 22
B
16,
2616]
1
R W
✕
1
✕
1
✕
3
1
✕
4
1
✕
5
1
✕
6
1
✕
7
1
✕
Function
0 •Set a count value of the corresponding timer.
•The value set in this register is written to the corresponding
1 secondary latch at the same time.
•These are read disabled bits.
2 When these bits are read out, the values are undefined.
At reset
Fig. 3.5.16 Structure of Timer Y secondary, Timer Z secondary
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APPENDIX
7540 Group
3.5 List of registers
Timer Y primary, Timer Z primary
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y primary, Timer Z primary (TYP, TZP) [Address : 23
B
16,
2716]
Function
At reset
1
2
3
4
5
R W
1
0 •Set a count value of the corresponding timer.
•When the corresponding timer is stopped, the value set in this
register is written to both the corresponding primary latch and
the corresponding timer at the same time.
•When the corresponding timer is operating, the value set in this
register is written as follows;
timer write control bit = 0:
the value is written to both the corresponding primary latch and
the corresponding timer at the same time.
timer write control bit = 1:
the value is written to the corresponding primary latch.
•When these bits are read out, the count value of the corresponding timer is read out (Note).
1
1
1
1
1
6
1
7
1
Note: The primary count value is read out at the primary interval, the secondary count
value is read out at the secondary interval.
Fig. 3.5.17 Structure of Timer Y primary, Timer Z primary
Timer Y, Z waveform output control register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y, Z waveform output control register (PUM) [Address : 24
B
0
1
2
3
4
5
6
7
Name
16]
Function
0 : Waveform not extended
1 : Waveform extended
0 : Waveform not extended
1 : Waveform extended
0 : Waveform not extended
1 : Waveform extended
0 : Waveform not extended
1 : Waveform extended
0 : “L” output
Timer Y output level latch
1 : “H” output
0 : “L” output
Timer Z output level latch
1 : “H” output
0 : INT 0 pin one-shot trigger invalid
INT0 pin one-shot trigger
1 : INT 0 pin one-shot trigger valid
control bit (Note)
INT0 pin one-shot trigger active 0 : Falling edge trigger
1 : Rising edge trigger
edge selection bit ( Note)
Timer Y primary waveform
extension control bit
Timer Y secondary waveform
extension control bit
Timer Z primary waveform
extension control bit
Timer Z secondary waveform
extension control bit
At reset
R W
0
0
0
0
0
0
0
0
Note: Stop timer Z to change the values of these bits.
Fig. 3.5.18 Structure of Timer Y, Z waveform output control register
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APPENDIX
7540 Group
3.5 List of registers
Prescaler 1
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 1 (PRE1) [Address : 2816]
B
Function
0 •Set a count value of prescaler 1.
•The value set in this register is written to both prescaler 1
1 and the prescaler 1 latch at the same time.
•When this register is read out, the count value of the prescaler 1
2 is read out.
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.19 Structure of Prescaler 1
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1 (T1) [Address : 2916]
B
Function
0 •Set a count value of timer 1.
•The value set in this register is written to both timer 1 and timer 1
1 latch at the same time.
•When this register is read out, the timer 1’s count value is read
2 out.
At reset
R W
1
0
0
3
0
4
0
5
0
6
0
7
0
Fig. 3.5.20 Structure of Timer 1
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APPENDIX
7540 Group
3.5 List of registers
One-shot start register
b7 b6 b5 b4 b3 b2 b1 b0
One-shot start register (ONS) [Address : 2A 16]
B
Name
0 Timer Z one-shot start bit
Function
0 : One-shot stop
1 : One-shot start
At reset
R W
0
0
✕
2
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
7
0
✕
1 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 3.5.21 Structure of One-shot start register
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APPENDIX
7540 Group
3.5 List of registers
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer X mode register (TXM) [Address : 2B 16]
B
0
Function
Name
Timer X operating mode bits
b1 b0
0
0
1
1
1
At reset
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement
mode
0
0
2 CNTR 0 active edge switch bit
The function depends on the
operating mode.
(Refer to Table 3.5.2)
0
3 Timer X count stop bit
0 : Count start
1 : Count stop
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR 0
output)
0
4
P03/TXOUT output valid bit
R W
0
0
✕
6
0
✕
7
0
✕
5 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 3.5.22 Structure of Timer X mode register
Table 3.5.2 CNTR 0 active edge switch bit function
Timer X operating modes
Timer mode
CNTR 0 active edge switch bit (bit 2 of address 2B16) contents
“0” CNTR 0 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR 0 interrupt request occurrence: Rising edge
; No influence to timer count
Pulse output mode
“0” Pulse output start: Beginning at “H” level
CNTR 0 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR 0 interrupt request occurrence: Rising edge
Event counter mode
“0” Timer X: Rising edge count
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: Falling edge count
CNTR 0 interrupt request occurrence: Rising edge
Pulse width measurement mode
“0” Timer X: “H” level width measurement
CNTR 0 interrupt request occurrence: Falling edge
“1” Timer X: “L” level width measurement
CNTR 0 interrupt request occurrence: Rising edge
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APPENDIX
7540 Group
3.5 List of registers
Prescaler X
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler X (PREX) [Address : 2C 16]
B
Function
0 •Set a count value of prescaler X.
•The value set in this register is written to both prescaler X
and the prescaler X latch at the same time.
•When this register is read out, the count value of the prescaler X
2 is read out.
1
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.23 Structure of Prescaler X
Timer X
b7 b6 b5 b4 b3 b2 b1 b0
Timer X (TX) [Address : 2D 16]
B
Function
0 •Set a count value of timer X.
•The value set in this register is written to both timer X and timer X
latch at the same time.
•When this register is read out, the timer X’s count value is read
2 out.
1
At reset
R W
1
1
1
3
1
4
1
5
1
6
1
7
1
Fig. 3.5.24 Structure of Timer X
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APPENDIX
7540 Group
3.5 List of registers
Timer count source set register
b7 b6 b5 b4 b3 b2 b1 b0
0
Timer count source set register (TCSS) [Address : 2E16]
B
Function
Name
0 Timer X count source
selection bits
1
2 Timer Y count source
selection bits
3
4 Timer Z count source
selection bits
5
b1 b0
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : f(XIN) (Note 1)
1 1 : Not available
b3 b2
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : On-chip oscillator output
(Note 2)
1 1 : Not available
b5 b4
0 0 : f(XIN)/16
0 1 : f(XIN)/2
1 0 : Timer Y underflow
1 1 : Not available
At reset
0
0
0
0
0
0
6 Fix this bit to “0”.
0
7 Nothing is allocated for this bit. This is a write disabled bit.
0
When this bit is read out, the value is “0”.
R W
✕
Notes 1: f(XIN) can be used as timer X count source only when using a ceramic
oscillator or on-chip oscillator.
Do not use it at RC oscillation.
2: System operates using an on-chip oscillator as a count source by setting the
on-chip oscillator to oscillation enabled by bit 3 of CPUM.
Fig. 3.5.25 Structure of Timer count source set register
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APPENDIX
7540 Group
3.5 List of registers
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register (SIO2CON) [Address : 3016]
B
Function
Name
0 Internal synchronous
b2 b1 b0
0 0 0 : f(XIN)/8
0 0 1 : f(XIN)/16
0 1 0 : f(XIN)/32
0 1 1 : f(XIN)/64
1 1 0 : f(XIN)/128
1 1 1 : f(XIN)/256
SDATA2 pin selection bit
0 : I/O port / SDATA2 input
(Note)
1 : SDATA2 output
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
Transfer direction selection bit 0 : LSB first
1 : MSB first
0 : External clock (SCLK2 is input)
SCLK2 pin selection bit
1 : Internal clock (SCLK2 is output)
Transmit / receive shift
0 : shift in progress
completion flag
1 : shift completed
At reset
R W
0
clock selection bits
1
2
3
4
5
6
7
0
0
0
0
✕
0
0
0
✕
Note: When using it as a SDATA input, set the port P13 direction register bit to “0”.
Fig. 3.5.26 Structure of Serial I/O2 control register
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register (SIO2) [Address : 31 16]
B
Function
0 A shift register for serial transmission and reception.
At reset
R W
?
• At transmitting : Set a transmission data.
1 • At receiving : A reception data is stored.
?
2
?
3
?
4
?
5
?
6
?
7
?
Fig. 3.5.27 Structure of Serial I/O2 register
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APPENDIX
7540 Group
3.5 List of registers
A/D control register
b7 b6 b5 b4 b3 b2 b1 b0
A/D control register (ADCON) [Address : 3416]
B
Name
0
Analog input pin selection bits
Function
1
2
0
0
1
1
0
0
1
1
0 : P20/AN0
1 : P21/AN1
0 : P22/AN2
1 : P23/AN3
0 : P24/AN4
1 : P25/AN5
0 : P26/AN6
1 : P27/AN7
R W
0
b2 b1 b0
0
0
0
0
1
1
1
1
At reset
0
(Note)
(Note)
0
Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is “0”.
AD conversion completion bit 0 : Conversion in progress
1 : Conversion completed
0
✕
1
✽
Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
0
✕
6
0
✕
7
0
✕
3
4
5
Note: These can be used only for the 36-pin package versions.
✽: This bit can be cleared to “0” by program, but cannot be set to “1”.
Fig. 3.5.28 Structure of A/D control register
A/D conversion register (low-order)
b7 b6 b5 b4 b3 b2 b1 b0
A/D conversion register (low-order) (ADL) [Address : 3516]
B
Function
At reset
R W
?
✕
?
✕
b0
?
✕
b9 b8 b7 b6 b5 b4 b3 b2
?
✕
< 10-bit read>
?
✕
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
stored.
1
2
3
b7
4
b7
5
< 8-bit read>
b0
b7 b6 b5 b4 b3 b2 b1 b0
Fig. 3.5.29 Structure of A/D conversion register (low-order)
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-114
APPENDIX
7540 Group
3.5 List of registers
A/D conversion register (high-order)
b7 b6 b5 b4 b3 b2 b1 b0
A/D conversion register (high-order) (ADH) [Address : 3616]
B
Function
At reset
R W
?
✕
?
✕
?
✕
3
?
✕
4
?
✕
5
?
✕
6
?
✕
7
?
✕
0 The read-only register in which the A/D conversion’s results are
stored.
b7
1
< 10-bit read>
b0
b9 b8
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
Fig. 3.5.30 Structure of A/D conversion register (high-order)
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG [Address : 3816]
B
Name
0 Oscillation stabilization time
set bit after release of the
STP instruction
Function
0 : Set “0116” in timer 1, and
“FF16” in prescaler 1
automatically
1 : Not set automatically
1 Ceramic or RC oscillation stop 0 : Detection function inactive
detection function active bit
2 These are reserved bits.
Do not write “1” to these bits.
1 : Detection function active
At reset
R W
0
0
0
✕
0
✕
0
✕
5
0
✕
6
0
✕
(Note)
✕
3
4 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 Oscillation stop detection
status bit
0 : Oscillation stop not detected
1 : Oscillation stop detected
Note: “0” at normal reset
“1” at reset by detecting the oscillation stop
Fig. 3.5.31 Structure of MISRG
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-115
APPENDIX
7540 Group
3.5 List of registers
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog timer control register (WDTCON) [Address : 39
B
Name
16]
Function
At reset
R W
1
✕
1
1
✕
2
1
✕
3
1
✕
4
1
✕
5
1
✕
0 Watchdog timer H
(The high-order 6 bits are read-only bits.)
6 STP instruction disable bit
7 Watchdog timer H count
source selection bit
0 : STP instruction enabled
1 : STP instruction disabled
0 : Watchdog timer L underflow
1 : f(X IN)/16
0
0
Fig. 3.5.32 Structure of Watchdog timer control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register (INTEDGE) [Address : 3A
Name
Function
0 INT 0 interrupt edge
0 : Falling edge active
1 : Rising edge active
0 : Falling edge active
1 : Rising edge active
B
selection bit
1 INT 1 interrupt edge
selection bit
16]
At reset
R W
0
0
0
✕
3
0
✕
4
0
✕
5
0
✕
6
0
✕
2 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7 P00 key-on wakeup enable bit 0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
0
Fig. 3.5.33 Structure of Interrupt edge selection register
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-116
APPENDIX
7540 Group
3.5 List of registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register (CPUM) [Address : 3B16]
B
Name
0 Processor mode bits (Note 1)
1
2
Stack page selection bit
3 On-chip oscillator oscillation
control bit
X
4 IN oscillation control bit
5 Oscillation mode selection bit
(Note 1)
6
Clock division ratio selection
bits
7
Function
b1 b0
0
0
1
1
0 : Single-chip mode
1 : Not available
0 : Not available
1 : Not available
0 : 0 page
1 : 1 page
0 : On-chip oscillator oscillation enabled
1 : On-chip oscillator oscillation stop
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
0 : Ceramic oscillation
1 : RC oscillation
b7 b6
0 0 : φ = f(XIN)/2
(high-speed mode)
0 1 : φ = f(XIN)/8
(middle-speed mode)
1 0 : Applied from on-chip oscillator
1 1 : φ = f(XIN)
(double-speed mode)
(Note 2)
At reset
R W
0
0
0
0
0
0
0
1
Notes 1: The bit can be rewritten only once after releasing reset. After rewriting it is
disable to write any data to the bit. However, by reset the bit is initialized and
can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU “M37540RSS”.)
2: These bits are used only when a ceramic oscillation is selected.
Do not use these when an RC oscillation is selected.
Fig. 3.5.34 Structure of CPU mode register
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-117
APPENDIX
7540 Group
3.5 List of registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address : 3C
B
Name
0 Serial I/O1 receive
interrupt request bit
1 Serial I/O1 transmit interrupt
request bit
2 INT 0 interrupt request bit
3 INT 1 interrupt request bit
4 Key-on wake up interrupt
request bit
5 CNTR 0 interrupt request bit
6 CNTR 1 interrupt request bit
7 Timer X interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 3.5.35 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2 (IREQ2) [Address : 3D
B
Name
0 Timer Y interrupt request bit
1 Timer Z interrupt request bit
2 Timer A interrupt request bit
3 Serial I/O2 interrupt request
bit
4 AD converter interrupt
request bit
5 Timer 1 interrupt request bit
16]
Function
At reset
R W
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✽
0
✽
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
✽
0
✽
0
✕
0
✕
6 Nothing is allocated for these bits. These are write disabled bits.
When these bits are read out, the values are “0”.
7
✽: These bits can be cleared to “0” by program, but cannot be set to “1”.
Fig. 3.5.36 Structure of Interrupt request register 2
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-118
APPENDIX
7540 Group
3.5 List of registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address : 3E
16]
Name
Function
0 Serial I/O1 receive
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
B
interrupt enable bit
1 Serial I/O1 transmit interrupt
enable bit
2 INT 0 interrupt enable bit
3 INT 1 interrupt enable bit
4 Key-on wake up interrupt
enable bit
5 CNTR 0 interrupt enable bit
6 CNTR 1 interrupt enable bit
7 Timer X interrupt enable bit
At reset
R W
0
0
0
0
0
0
0
0
Fig. 3.5.37 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address : 3F 16]
B
Name
0 Timer Y interrupt
enable bit
1 Timer Z interrupt enable bit
2 Timer A interrupt enable bit
3 Serial I/O2 interrupt enable bit
4 AD conversion interrupt
enable bit
5 Timer 1 interrupt enable bit
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
6 Nothing is allocated for these bits. These are write disabled bits.
At reset
R W
0
0
0
0
0
0
0
✕
0
✕
When these bits are read out, the values are “0”.
7
Fig. 3.5.38 Structure of Interrupt control register 2
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-119
APPENDIX
7540 Group
3.6 Package outline
3.6 Package outline
Recommended
32P4B
EIAJ Package Code
SDIP32-P-400-1.78
Plastic 32pin 400mil SDIP
Weight(g)
2.2
Lead Material
Alloy 42/Cu Alloy
17
1
16
E
32
e1
c
JEDEC Code
–
D
L
A1
A
A2
Symbol
e
b1
b
b2
SEATING PLANE
32P6U-A
Recommended
Plastic 32pin 7✕7mm body LQFP
Weight(g)
JEDEC Code
–
Lead Material
Cu Alloy
MD
b2
HD
D
32
ME
e
EIAJ Package Code
LQFP32-P-0707-0.80
A
A1
A2
b
b1
b2
c
D
E
e
e1
L
Dimension in Millimeters
Min
Nom
Max
–
–
5.08
0.51
–
–
–
3.8
–
0.35
0.45
0.55
0.9
1.0
1.3
0.63
0.73
1.03
0.22
0.27
0.34
27.8
28.0
28.2
8.75
8.9
9.05
–
1.778
–
–
10.16
–
3.0
–
–
0°
–
15°
25
I2
24
Recommended Mount Pad
Symbol
E
HE
1
8
17
9
16
A
b
y
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
x
M
L
Lp
Detail F
c
A2
A1
F
A3
L1
e
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
A3
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.7
0.1
0.2
0
–
–
1.4
0.32
0.37
0.45
0.105
0.125
0.175
6.9
7.0
7.1
6.9
7.0
7.1
0.8
–
–
8.8
9.0
9.2
8.8
9.0
9.2
0.3
0.5
0.7
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.2
0.1
–
–
0°
10°
–
0.5
–
–
1.0
–
–
7.4
–
–
–
–
7.4
3-120
APPENDIX
7540 Group
3.6 Package outline
Recommended
36P2R-A
EIAJ Package Code
SSOP36-P-450-0.80
JEDEC Code
–
Plastic 36pin 450mil SSOP
Weight(g)
0.53
e
b2
19
E
HE
e1
I2
36
Lead Material
Alloy 42
Recommended Mount Pad
F
Symbol
1
18
A
D
G
A2
e
b
L
L1
y
A1
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
c
z
Z1
Detail G
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Detail F
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
2.4
–
–
–
–
0.05
–
2.0
–
0.5
0.4
0.35
0.2
0.15
0.13
15.2
15.0
14.8
8.6
8.4
8.2
–
0.8
–
12.23
11.93
11.63
0.7
0.5
0.3
–
1.765
–
–
0.7
–
–
–
0.85
0.15
–
–
0°
–
10°
–
0.5
–
–
11.43
–
–
1.27
–
3-121
APPENDIX
7540 Group
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
ADC
(Note 1)
(Note 5)
When T = 0
A←A+M+C
When T = 1
M(X) ← M(X) + M + C
AND
(Note 1)
When TV= 0
A←A M
When T = 1 V
M(X) ← M(X) M
7
ASL
C←
0
←0
IMM
# OP n
A
# OP n
BIT,A,AR
BIT,
# OP n
ZP
# OP n
BIT,ZP,
ZPR
BIT,
# OP n
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory
where is indicated by X.
69 2
2
65 3
2
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the contents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
M(X) represents the contents of memory
where is indicated by X.
29 2
2
25 3
2
06 5
2
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A 2
1
#
BBC
(Note 4)
Ai or Mi = 0?
This instruction tests the designated bit i of M
or A and takes a branch if the bit is 0. The
branch address is specified by a relative address. If the bit is 1, next instruction is
executed.
13 4
+
20i
2
17 5
+
20i
3
BBS
(Note 4)
Ai or Mi = 1?
This instruction tests the designated bit i of the
M or A and takes a branch if the bit is 1. The
branch address is specified by a relative address. If the bit is 0, next instruction is
executed.
03 4
+
20i
2
07 5
+
20i
3
BCC
(Note 4)
C = 0?
This instruction takes a branch to the appointed address if C is 0. The branch address
is specified by a relative address. If C is 1, the
next instruction is executed.
BCS
(Note 4)
C = 1?
This instruction takes a branch to the appointed address if C is 1. The branch address
is specified by a relative address. If C is 0, the
next instruction is executed.
BEQ
(Note 4)
Z = 1?
This instruction takes a branch to the appointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
BIT
A
BMI
(Note 4)
N = 1?
This instruction takes a branch to the appointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
BNE
(Note 4)
Z = 0?
This instruction takes a branch to the appointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
V
M
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
24 3
2
3-122
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
75 4
ABS
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
2
6D 4
3 7D 5
3 79 5
35 4
2
2D 4
3 3D 5
3 39 5
16 6
2
0E 6
3 1E 7
3
2C 4
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
# OP n
# OP n
# OP n
3
61 6
2 71 6
2
N
V
•
•
•
•
Z
C
3
21 6
2 31 6
2
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90 2
2
•
•
•
•
•
•
•
•
B0 2
2
•
•
•
•
•
•
•
•
F0 2
2
•
•
•
•
•
•
•
•
M7 M6 •
•
•
•
Z
•
3
30 2
2
•
•
•
•
•
•
•
•
D0 2
2
•
•
•
•
•
•
•
•
3-123
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
IMM
OP n
# OP n
00 7
1
BPL
(Note 4)
N = 0?
This instruction takes a branch to the appointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
BRA
PC ← PC ± offset
This instruction branches to the appointed address. The branch address is specified by a
relative address.
BRK
B←1
(PC) ← (PC) + 2
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
M(S) ← PS
S←S–1
I← 1
PCL ← ADL
PCH ← ADH
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
BVC
(Note 4)
V = 0?
This instruction takes a branch to the appointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
BVS
(Note 4)
V = 1?
This instruction takes a branch to the appointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is executed.
CLB
Ai or Mi ← 0
This instruction clears the designated bit i of A
or M.
CLC
C←0
This instruction clears C.
18 2
1
CLD
D←0
This instruction clears D.
D8 2
1
CLI
I←0
This instruction clears I.
58 2
1
CLT
T←0
This instruction clears T.
12 2
1
CLV
V←0
This instruction clears V.
B8 2
1
CMP
(Note 3)
When T = 0
A–M
When T = 1
M(X) – M
When T = 0, this instruction subtracts the contents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
COM
M←M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
CPX
X–M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
E0 2
CPY
Y–M
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
C0 2
DEC
A ← A – 1 or
M←M–1
This instruction subtracts 1 from the contents
of A or M.
__
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
A
# OP n
BIT, A
# OP n
1B 2
+
20i
C9 2
ZP
# OP n
BIT, ZP
# OP n
#
1F 5
+
20i
2
1
C5 3
2
44 5
2
2
E4 3
2
2
C4 3
2
C6 5
2
2
1A 2
1
3-124
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
ZP, X
OP n
D5 4
D6 6
ZP, Y
# OP n
2
2
ABS
# OP n
CD 4
ABS, X
# OP n
3 DD 5
ABS, Y
# OP n
3 D9 5
IND
# OP n
3
Processor status register
ZP, IND
# OP n
IND, X
# OP n
C1 6
IND, Y
# OP n
2 D1 6
REL
# OP n
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
10 2
2
•
•
•
•
•
•
•
•
80 4
2
•
•
•
•
•
•
•
•
•
•
•
1
•
1
•
•
50 2
2
•
•
•
•
•
•
•
•
70 2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
•
N
•
•
•
•
•
Z
C
N
•
•
•
•
•
Z
•
EC 4
3
N
•
•
•
•
•
Z
C
CC 4
3
N
•
•
•
•
•
Z
C
CE 6
3 DE 7
N
•
•
•
•
•
Z
•
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3
3-125
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
IMM
# OP n
DEX
X←X–1
This instruction subtracts one from the current CA 2
contents of X.
1
DEY
Y←Y–1
This instruction subtracts one from the current
contents of Y.
88 2
1
DIV
A ← (M(zz + X + 1),
M(zz + X )) / A
M(S) ← one's complement of Remainder
S←S–1
This instruction divides the 16-bit data in
M(zz+(X)) (low-order byte) and M(zz+(X)+1)
(high-order byte) by the contents of A. The
quotient is stored in A and the one's complement of the remainder is pushed onto the stack.
EOR
(Note 1)
When T = 0
–M
A←AV
When T = 0, this instruction transfers the contents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bitwise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
When T = 1
–M
M(X) ← M(X) V
49 2
A
# OP n
BIT, A
# OP n
2
ZP
# OP n
BIT, ZP
# OP n
45 3
2
E6 5
2
A5 3
2
3C 4
3
INC
A ← A + 1 or
M←M+1
This instruction adds one to the contents of A
or M.
INX
X←X+1
This instruction adds one to the contents of X.
E8 2
1
INY
Y←Y+1
This instruction adds one to the contents of Y.
C8 2
1
JMP
If addressing mode is ABS
PCL ← ADL
PCH ← ADH
If addressing mode is IND
PCL ← M (ADH, ADL)
PCH ← M (ADH, ADL + 1)
If addressing mode is ZP, IND
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction jumps to the address designated by the following three addressing
modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
JSR
M(S) ← PCH
S←S–1
M(S) ← PCL
S←S–1
After executing the above,
if addressing mode is ABS,
PCL ← ADL
PCH ← ADH
if addressing mode is SP,
PCL ← ADL
PCH ← FF
If addressing mode is ZP, IND,
PCL ← M(00, ADL)
PCH ← M(00, ADL + 1)
This instruction stores the contents of the PC
in the stack, then jumps to the address designated by the following addressing modes:
Absolute
Special Page
Zero Page Indirect Absolute
LDA
(Note 2)
When T = 0
A←M
When T = 1
M(X) ← M
When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
LDM
M ← nn
This instruction loads the immediate value in
M.
LDX
X←M
This instruction loads the contents of M in X.
A2 2
2
A6 3
2
LDY
Y←M
This instruction loads the contents of M in Y.
A0 2
2
A4 3
2
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3A 2
A9 2
2
1
#
3-126
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
ZP, X
OP n
ZP, Y
# OP n
ABS
# OP n
ABS, X
# OP n
ABS, Y
# OP n
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
REL
# OP n
SP
# OP n
#
E2 16 2
55 4
2
4D 4
3 5D 5
3 59 5
F6 6
2
EE 6
3 FE 7
3
B5 4
2
B6 4
B4 4
2
4C 3
3
20 6
3
AD 4
3 BD 5
2 AE 4
AC 4
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
41 6
6C 5
3 B9 5
3
3 BC 5
3
BE 5
3
3
3
3 B2 4
2
02 7
2
2 51 6
2
22 5
A1 6
2 B1 6
2
2
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
3-127
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
LSR
7
0→
0
→C
This instruction multiply Accumulator with the
memory specified by the Zero Page X address
mode and stores the high-order byte of the result on the Stack and the low-order byte in A.
NOP
PC ← PC + 1
This instruction adds one to the PC but does EA 2
no otheroperation.
ORA
(Note 1)
When T = 0
A←AVM
When T = 0, this instruction transfers the contents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the contents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
PHP
PLA
PLP
ROL
# OP n
1
ZP
# OP n
BIT, ZP
# OP n
46 5
2
05 3
2
09 2
2
48 3
1
M(S) ← PS
S←S–1
This instruction pushes the contents of PS to
the memory location designated by S and decrements the contents of S by one.
08 3
1
S←S+1
A ← M(S)
This instruction increments S by one and
stores the contents of the memory designated
by S in A.
68 4
1
S←S+1
PS ← M(S)
This instruction increments S by one and
stores the contents of the memory location
designated by S in PS.
28 4
1
7
←
This instruction shifts either A or M one bit left
through C. C is stored in bit 0 and bit 7 is
stored in C.
2A 2
1
26 5
2
This instruction shifts either A or M one bit
right through C. C is stored in bit 7 and bit 0 is
stored in C.
6A 2
1
66 5
2
82 8
2
0
←C ←
RRF
7
→
0
→
0
→
This instruction rotates 4 bits of the M content
to the right.
S←S+1
PS ← M(S)
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
This instruction increments S by one, and
stores the contents of the memory location
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PC L . S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
S←S+1
PCL ← M(S)
S←S+1
PCH ← M(S)
(PC) ← (PC) + 1
This instruction increments S by one and
stores the contents of the memory location
d e s i g n a t e d b y S i n P C L. S i s a g a i n
incremented by one and the contents of the
memory location is stored in PC H . PC is
incremented by 1.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
#
1
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
7
C→
RTS
BIT, A
M(S) ← A
S←S–1
ROR
RTI
# OP n
4A 2
M(S) • A ← A ✽ M(zz + X)
S←S–1
PHA
# OP n
A
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
MUL
When T = 1
M(X) ← M(X) V M
IMM
40 6
1
60 6
1
3-128
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
56 6
2
ABS
ABS, X
ABS, Y
# OP n
# OP n
# OP n
4E 6
3 5E 7
3
IND
# OP n
Processor status register
ZP, IND
# OP n
IND, X
# OP n
IND, Y
# OP n
# OP n
62 15 2
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
REL
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
0
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
•
•
•
•
•
Z
C
76 6
2
6E 6
3 7E 7
3
N
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
(Value saved in stack)
•
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
•
•
•
•
•
•
•
3-129
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
OP n
SBC
(Note 1)
(Note 5)
When T = 0 _
A←A–M–C
When T = 1
_
M(X) ← M(X) – M – C
IMM
# OP n
E9 2
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
SEB
Ai or Mi ← 1
This instruction sets the designated bit i of A
or M.
SEC
C←1
This instruction sets C.
38 2
1
SED
D←1
This instruction set D.
F8 2
1
SEI
I←1
This instruction set I.
78 2
1
SET
T←1
This instruction set T.
32 2
1
STA
M←A
This instruction stores the contents of A in M.
The contents of A does not change.
This instruction resets the oscillation control F/
F and the oscillation stops. Reset or interrupt
input is needed to wake up from this mode.
STP
A
# OP n
BIT, A
# OP n
# OP n
2
E5 3
0B 2
+
20i
42 2
ZP
BIT, ZP
# OP n
2
1
0F 5
+
20i
85 4
2
M←X
This instruction stores the contents of X in M.
The contents of X does not change.
86 4
2
STY
M←Y
This instruction stores the contents of Y in M.
The contents of Y does not change.
84 4
2
TAX
X←A
This instruction stores the contents of A in X. AA 2
The contents of A does not change.
1
TAY
Y←A
This instruction stores the contents of A in Y.
The contents of A does not change.
1
TST
M = 0?
This instruction tests whether the contents of
M are “0” or not and modifies the N and Z.
64 3
2
TSX
X←S
This instruction transfers the contents of S in BA 2
X.
1
TXA
A←X
This instruction stores the contents of X in A.
8A 2
1
TXS
S←X
This instruction stores the contents of X in S.
9A 2
1
TYA
A←Y
This instruction stores the contents of Y in A.
98 2
1
The WIT instruction stops the internal clock
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All registers or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
C2 2
1
WIT
Notes 1
2
3
4
5
:
:
:
:
:
2
1
STX
A8 2
#
The number of cycles “n” is increased by 3 when T is 1.
The number of cycles “n” is increased by 2 when T is 1.
The number of cycles “n” is increased by 1 when T is 1.
The number of cycles “n” is increased by 2 when branching has occurred.
N, V, and Z flags are invalid in decimal operation mode.
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-130
APPENDIX
7540 Group
3.7 Machine instructions
Addressing mode
ZP, X
ZP, Y
OP n
# OP n
F5 4
2
95 5
2
2
ABS, X
ABS, Y
IND
# OP n
# OP n
# OP n
# OP n
ED 4
3 FD 5
3 F9 5
3
8D 5
96 5
94 5
ABS
3 9D 6
3 99 6
3
Processor status register
ZP, IND
# OP n
IND, X
IND, Y
REL
# OP n
# OP n
# OP n
E1 6
2 F1 6
2
81 7
2 91 7
2
SP
# OP n
#
7
6
5
4
3
2
1
0
N
V
T
B
D
I
Z
C
N
V
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
1
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2 8E 5
3
•
•
•
•
•
•
•
•
8C 5
3
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
N
•
•
•
•
•
Z
•
•
•
•
•
•
•
•
•
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-131
APPENDIX
7540 Group
3.7 Machine instructions
Symbol
Contents
IMP
IMM
A
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
ABS, X
ABS, Y
IND
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Z
I
D
B
T
V
N
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
Negative flag
Symbol
+
–
✽
/
V
V
–
V
–
←
X
Y
S
PC
PS
PCH
PCL
ADH
ADL
FF
nn
zz
M
M(X)
M(S)
M(ADH, ADL)
M(00, ADL)
Ai
Mi
OP
n
#
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
Contents
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
Stack pointer
Program counter
Processor status register
8 high-order bits of program counter
8 low-order bits of program counter
8 high-order bits of address
8 low-order bits of address
FF in Hexadecimal notation
Immediate value
Zero page address
Memory specified by address designation of any addressing mode
Memory of address indicated by contents of index
register X
Memory of address indicated by contents of stack
pointer
Contents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits.
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
Number of bytes
3-132
APPENDIX
7540 Group
3.8 List of instruction code
3.8 List of instruction code
D7 – D4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
BBS
ORA
JSR
IND, X ZP, IND 0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
ROL
CLB
LDM
AND
ZP ABS, X ABS, X 1, ZP
0100
4
RTI
EOR
IND, X
STP
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
ADC
IND, X
MUL
ZP, X
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
BBC
LDA
IND, Y ZP, IND 5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
SBC
IND, X
DIV
ZP, X
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
—
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
ASL
CLB
ORA
ABS, X ABS, X 0, ZP
AND
ABS
EOR
ABS
ROL
ABS
LSR
ABS
SEB
1, ZP
SEB
2, ZP
LSR
CLB
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
ROR
CLB
ADC
ABS, X ABS, X 3, ZP
LDX
CLB
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
DEC
CLB
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
INC
CLB
SBC
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
Rev.2.00 Jun 21, 2004
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APPENDIX
7540 Group
3.9 SFR memory map
3.9 SFR memory map
000016
Port P0 (P0)
002016
Timer Y, Z mode register (TYZM)
000116
Port P0 direction register (P0D)
002116
Prescaler Y (PREY)
000216
Port P1 (P1)
002216
Timer Y secondary (TYS)
000316
Port P1 direction register (P1D)
002316
Timer Y primary (TYP)
000416
Port P2 (P2)
002416
Timer Y, Z waveform output control register (PUM)
000516
Port P2 direction register (P2D)
002516
Prescaler Z (PREZ)
000616
Port P3 (P3)
002616
Timer Z secondary (TZS)
000716
Port P3 direction register (P3D)
002716
Timer Z primary (TZP)
000816
002816
Prescaler 1 (PRE1)
000916
002916
Timer 1 (T1)
000A16
002A16
One-shot start register (ONS)
000B16
002B16
Timer X mode register (TXM)
000C16
002C16
Prescaler X (PREX)
000D16
002D16
Timer X (TX)
000E16
002E16
Timer count source set register (TCSS)
000F16
002F16
001016
003016
Serial I/O2 control register (SIO2CON)
001116
003116
Serial I/O2 register (SIO2)
001216
003216
001316
003316
001416
003416
A/D control register (ADCON)
003516
A/D conversion register (low-order) (ADL)
001616
Pull-up control register (PULL)
003616
A/D conversion register (high-order) (ADH)
001716
Port P1P3 control register (P1P3C)
003716
001816
Transmit/Receive buffer register (TB/RB)
003816
MISRG
001916
Serial I/O1 status register (SIO1STS)
003916
Watchdog timer control register (WDTCON)
001A16
Serial I/O1 control register (SIO1CON)
003A16
Interrupt edge selection register (INTEDGE)
001B16
UART control register (UARTCON)
003B16
CPU mode register (CPUM)
001C16
Baud rate generator (BRG)
003C16
Interrupt request register 1 (IREQ1)
001D16
Timer A mode register (TAM)
003D16
Interrupt request register 2 (IREQ2)
001E16
Timer A (low-order) (TAL)
003E16
Interrupt control register 1 (ICON1)
001F16
Timer A (high-order) (TAH)
003F16
Interrupt control register 2 (ICON2)
001516
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-134
APPENDIX
7540 Group
3.10 Pin configurations
3.10 Pin configurations
25
26
27
28
29
30
31
17
18
19
20
21
22
M37540Mx-XXXGP
M37540MxT-XXXGP
M37540MxV-XXXGP
M37540ExGP
M37540E8T-XXXGP
M37540E8V-XXXGP
16
15
14
13
12
11
10
9
8
7
6
5
4
3
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
VSS
XOUT
XIN
P22/AN2
P23/AN3
P24/AN4
P25/AN5
VREF
RESET
CNVSS
VCC
2
32
1
P07
P10/RXD1
P11/TXD1
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0
P21/AN1
23
24
P06
P05
P04
P03/TXOUT
P02/TZOUT
P01/TYOUT
P00/CNTR1
P37/INT0
(Top view)
Package type: 32P6U-A
Fig. 3.10.1 32P6U-A package pin configuration
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-135
APPENDIX
7540 Group
3.10 Pin configurations
(Top view)
1
36
2
35
3
34
4
33
5
6
7
8
9
10
11
12
13
M37540Mx-XXXFP
M37540MxT-XXXFP
M37540MxV-XXXFP
M37540E8FP
M37540E8T-XXXFP
M37540E8V-XXXFP
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0
P21/AN1
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
32
31
30
29
28
27
26
25
24
14
23
15
22
16
21
17
20
18
19
P11/TXD1
P10/RXD1
P07
P06
P05
P04
P03/TXOUT
P02/TZOUT
P01/TYOUT
P00/CNTR1
P37/INT0
P36(LED6)/INT1
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
Package type: 36P2R-A
Fig. 3.10.2 36P2R-A package pin configuration
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-136
APPENDIX
7540 Group
3.10 Pin configurations
(Top view)
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
32
P11/TXD1
2
31
3
30
P10/RXD1
P07
P20/AN0
4
29
P06
P21/AN1
P22/AN2
5
28
P23/AN3
P24/AN4
7
P05
P04
P03/TXOUT
P02/TZOUT
P25/AN5
VREF
9
6
8
M37540Mx-XXXSP
M37540ExSP
1
27
26
25
23
P01/TYOUT
P00/CNTR1
22
P37/INT0
21
P34(LED4)
13
20
14
14
19
P33(LED3)
P32(LED2)
XOUT
15
18
P31(LED1)
VSS
16
17
P30(LED0)
RESET
CNVSS
VCC
XIN
10
11
12
24
Package type: 32P4B
Fig. 3.10.3 32P4B package pin configuration
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-137
APPENDIX
7540 Group
3.10 Pin configurations
(Top view)
1
42
2
41
3
40
4
39
5
38
6
37
7
36
M37540RSS
P14/CNTR0
NC
NC
P20/AN0
P21/AN1
NC
P22/AN2
P23/AN3
P24/AN4
P25/AN5
P26/AN6
P27/AN7
NC
NC
VREF
RESET
CNVSS
Vcc
XIN
XOUT
VSS
8
9
10
11
12
13
14
15
35
34
33
32
31
30
29
28
16
27
17
26
18
25
19
24
20
23
21
22
P13/SRDY1/SDATA2
P12/SCLK1/SCLK2
P11/TXD1
P10/RXD1
P07
P06
P05
P04
P03/TXOUT
P02/TZOUT
P01/TYOUT
P00/CNTR1
NC
P37/INT0
P36(LED6)/INT1
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
P31(LED1)
P30(LED0)
Outline 42S1M
Fig. 3.10.4 42S1M package pin configuration
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
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APPENDIX
7540 Group
3.11 Differences between 7540 Group and 7531 Group
3.11 Differences between 7540 Group and 7531 Group
Table 3.11.1 shows the differences between 7540 Group and 7531 Group.
Table 3.11.1 Differences between 7540 Group and 7531 Group
(Performance overview)
Parameter
Number of basic instructions
Memory sizes ROM
7531 Group
69
RAM
16 to 32 K bytes
512 to 768 bytes
8 to 16 K bytes
256 to 384 bytes
Initial value: 0016
Initial value: FF16
32-pin version
(Ports P0 and P3 pull-up Off)
14 sources, 14 vector
(Ports P0 and P3 pull-up On)
11 sources, 8 vector
(4 for external)
(3 for external)
15 sources, 15 vector
(5 for external)
12 sources, 8 vector
(4 for external)
Input/Output
ports
Interrupt
7540 Group
71 (DIV, MUL instruction added)
sources
36-pin version
16-bit timer
8-bit timer
1 (Timer A)
Serial I/O1
3 (Timer 1, X, Y, Z)
Clock synchronous/UART
3 (Timer 1, 2, X)
UART only
Clock generation circuit
Cecamic oscillator/
Cecamic oscillator/
Quartz-crystal oscillator/
RC oscillation/
Quartz-crystal oscillator/
RC oscillation
On-chip oscillator oscillation
Oscillation stop detection circuit
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
1
3-139
APPENDIX
7540 Group
3.11 Differences between 7540 Group and 7531 Group
Figure 3.11.1 shows the memory map of 7540 Group and 7531 Group.
7531 Group
000016
004016
7540 Group
000016
004016
SFR area
SFR area
Zero page
RAM
(256/384 bytes)
00FF16
010016
RAM
(512/768 bytes)
00FF16
010016
XXXX16
PPPP16
Reserved area
Reserved area
044016
044016
Not used
YYYY16
Not used
QQQQ16
Reserved ROM area
Reserved ROM area
(Common ROM area
128 bytes)
(Common ROM area
128 bytes)
ZZZZ16
RRRR16
ROM
ROM
FF0016
FF0016
FFEC16
FFDC16
Interrupt vector area
FFFE16
FFFF16 Reserved ROM area
FFFE16
FFFF16
RAM area
Interrupt vector area
Special
page
Reserved ROM area
RAM area
RAM capacity
(bytes)
Address
XXXX16
RAM capacity
(bytes)
256
013F16
512
023F16
384
01BF16
768
033F16
ROM area
Address
PPPP16
ROM area
ROM capacity
(bytes)
Address
YYYY16
Address
ZZZZ16
ROM capacity
(bytes)
Address
QQQQ16
Address
RRRR16
8192
E00016
E08016
16384
C00016
C08016
16384
C00016
C08016
32768
800016
808016
Fig. 3.11.1 Memory map of 7540 Group and 7531 Group
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-140
APPENDIX
7540 Group
3.11 Differences between 7540 Group and 7531 Group
Figure 3.11.2 shows the memory map of interrupt vector area of 7540 Group and 7531 Group.
FFEC16
FFED16
FFEE16
FFEF16
FFF016
FFF116
FFF216
FFF316
FFF416
FFF516
FFF616
FFF716
FFF816
FFF916
FFFA16
FFFB16
FFFC16
FFFD16
BRK instruction interrupt
CNTR0/A/D conversion interrupt
Timer 2/Serial I/O2 interrupt
Timer 1 interrupt
Timer X/Key-on wakeup interrupt
INT0 interrupt
Serial I/O1 transmit/
INT1 (Note) interrupt
Serial I/O1 receive interrupt
Reset
7531 Group
FFDC16
FFDD16
FFDE16
FFDF16
FFE016
FFE116
FFE216
FFE316
FFE416
FFE516
FFE616
FFE716
FFE816
FFE916
FFEA16
FFEB16
FFEC16
FFED16
FFEE16
FFEF16
FFF016
FFF116
FFF216
FFF316
FFF416
FFF516
FFF616
FFF716
FFF816
FFF916
FFFA16
FFFB16
FFFC16
FFFD16
BRK instruction interrupt
Reserved area
Timer 1 interrupt
A/D conversion interrupt
Serial I/O2 interrupt
Timer A interrupt
Timer Z interrupt
Timer Y interrupt
Timer X interrupt
CNTR1 interrupt
CNTR0 interrupt
Key-on wakeup interrupt
INT1 interrupt (Note)
INT0 interrupt
Serial I/O1 transmit interrupt
Serial I/O1 receive interrupt
Reset
7540 Group
: Interrupts added in 7540 Group
Note: The interrupt can be used only for the 36-pin version.
Fig. 3.11.2 Memory map of interrupt vector area of 7540 Group and 7531 Group
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-141
APPENDIX
7540 Group
3.11 Differences between 7540 Group and 7531 Group
Figure 3.11.3 shows the timer function of 7540 Group and 7531 Group.
7531 Group
7540 Group
● Timer 1 (8-bit timer)
● Timer 1 (8-bit timer)
• Timer mode
• Timer mode
● Timer X (8-bit timer)
● Timer 2 (8-bit timer)
• Timer mode
● Timer X (8-bit timer)
• Timer mode
The number of
timer increased
Function
expanded
• Timer mode
• Pulse output mode (inverted output port added)
• Event counter mode
• Pulse width measurement mode
• Pulse output mode
• Event counter mode
• Pulse width measurement mode
● Timer Y (8-bit timer)
• Timer mode
• Programmable waveform generation mode
Timer Y can be
used for the
timer Z count
source.
● Timer Z (8-bit timer)
• Timer mode
• Programmable waveform generation mode
• Programmable one-shot generation mode
• Programmable wait one-shot generation mode
● Timer A (16-bit timer)
• Timer mode
• Period measurement mode
• Event counter mode
• Pulse width HL continuously measurement mode
Fig. 3.11.3 Timer function of 7540 Group and 7531 Group
Rev.2.00 Jun 21, 2004
REJ09B0018-0200Z
3-142
RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
USER’S MANUAL
7540 Group
Publication Data :
Published by :
Rev.1.00 Jan 01, 2002
Rev.2.00 Jun 21, 2004
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
7540 Group
User's Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan