AD AD654 Low cost monolithic voltage-to-frequency converter Datasheet

a
FEATURES
Low Cost
Single or Dual Supply, 5 V to 36 V, ⴞ5 V to ⴞ18 V
Full-Scale Frequency Up to 500 kHz
Minimum Number of External Components Needed
Versatile Input Amplifier
Positive or Negative Voltage Modes
Negative Current Mode
High Input Impedance, Low Drift
Low Power: 2.0 mA Quiescent Current
Low Offset: 1 mV
PRODUCT DESCRIPTION
The AD654 is a monolithic V/F converter consisting of an input
amplifier, a precision oscillator system, and a high current output
stage. A single RC network is all that is required to set up any
full scale (FS) frequency up to 500 kHz and any FS input voltage
up to ± 30 V. Linearity error is only 0.03% for a 250 kHz FS,
and operation is guaranteed over an 80 dB dynamic range. The
overall temperature coefficient (excluding the effects of external
components) is typically ± 50 ppm/°C. The AD654 operates from
a single supply of 5 V to 36 V and consumes only 2.0 mA quiescent current.
The low drift (4 µV/°C typ) input amplifier allows operation
directly from small signals such as thermocouples or strain gauges
while offering a high (250 MΩ) input resistance. Unlike most
V/F converters, the AD654 provides a square-wave output, and
can drive up to 12 TTL loads, optocouplers, long cables, or
similar loads.
PRODUCT HIGHLIGHTS
1. Packaged in both an 8-lead mini-DIP and an 8-lead SOIC
package, the AD654 is a complete V/F converter requiring
only an RC timing network to set the desired full-scale frequency and a selectable pull-up resistor for the open-collector
output stage. Any full scale input voltage range from 100 mV
to 10 volts (or greater, depending on +VS ) can be accommodated by proper selection of the timing resistor. The fullscale frequency is then set by the timing capacitor from the
simple relationship, f = V/10 RC.
Low Cost Monolithic
Voltage-to-Frequency Converter
AD654
FUNCTIONAL BLOCK DIAGRAM
+VS
CT
CT
–VS
8
7
6
5
DRIVER
OSC
AD654
1
2
3
4
FOUT
LOGIC
COMMON
RT
+VIN
2. A minimum number of low cost external components are
necessary. A single RC network is all that is required to set
up any full scale frequency up to 500 kHz and any full-scale
input voltage up to ± 30 V.
3. Plastic packaging allows low cost implementation of the
standard VFC applications: A/D conversion, isolated signal
transmission, F/V conversion, phase-locked loops, and tuning
switched-capacitor filters.
4. Power supply requirements are minimal; only 2.0 mA of
quiescent current is drawn from the single positive supply
from 4.5 volts to 36 volts. In this mode, positive inputs can
vary from 0 volts (ground) to (+VS –4) volts. Negative inputs
can easily be connected for below ground operation.
5. The versatile open-collector output stage can sink more than
10 mA with a saturation voltage less than 0.4 volts. The Logic
Common terminal can be connected to any level between
ground (or –VS) and 4 volts below +V S. This allows easy
direct interface to any logic family with either positive or
negative logic levels.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD654–SPECIFICATIONS
Model
CURRENT-TO-FREQUENCY CONVERTER
Frequency Range
Nonlinearity1
fMAX = 250 kHz
fMAX = 500 kHz
Full-Scale Calibration Error
C = 390 pF, IIN = 1.000 mA
vs. Supply (fMAX ≤ 250 kHz)
VS = +4.75 V to +5.25 V
VS = +5.25 V to +16.5 V
vs. Temp (0°C to +70°C)
ANALOG INPUT AMPLIFIER
(Voltage-to-Current Converter)
Voltage Input Range
Single Supply
Dual Supply
Input Bias Current
(Either Input)
Input Offset Current
Input Resistance (Noninverting)
Input Offset Voltage
vs. Supply
VS = +4.75 V to +5.25 V
VS = +5.25 V to +16.5 V
vs. Temp (0°C to +70°C)
OUTPUT INTERFACE (Open Collector Output)
(Symmetrical Square Wave)
Output Sink Current in Logic “0”2
VOUT = 0.4 V max, +25°C
VOUT = 0.4 V max, 0°C to +70°C
Output Leakage Current in Logic “1”
0°C to +70°C
Logic Common Level Range
Rise/Fall Times (CT = 0.01 µF)
IIN = 1 mA
IIN = 1 µA
POWER SUPPLY
Voltage, Rated Performance
Voltage, Operating Range
Single Supply
Dual Supply
Quiescent Current
VS (Total) = 5 V
VS (Total) = 30 V
TEMPERATURE RANGE
Operating Range
(TA = +25ⴗC and VS (total) = 5 V to 16.5 V, unless otherwise noted. All testing done
@ VS = +5 V.)
Min
AD654JN/JR
Typ
Max
Units
500
kHz
0.1
0.4
%
%
+10
%
0.40
0.10
%/V
%/V
ppm/°C
(+VS – 4)
(+VS – 4)
V
V
30
5
250
0.5
50
nA
nA
MΩ
mV
0.1
0.03
4
0.25
0.1
0
0.06
0.20
–10
0.20
0.05
50
0
–VS
10
5
20
10
10
50
–VS
1.0
100
500
(+VS – 4)
mV/V
mV/V
µV/°C
mA
mA
nA
nA
V
µs
µs
0.2
1
4.5
16.5
V
4.5
±5
36
± 18
V
V
2.5
3.0
mA
mA
+85
°C
1.5
2.0
–40
NOTES
1
At f MAX = 250 kHz; R T = 1 kΩ, C T = 390 pF, IIN = 0 mA–1 mA.
1
At f MAX = 500 kHz; R T = 1 kΩ, C T = 200 pF, IIN = 0 mA–1 mA.
2
The sink current is the amount of current that can flow into Pin 1 of the AD654 while maintaining a maximum voltage of 0.4 V between Pin 1 and Logic Common.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
Specifications subject to change without notice.
–2–
REV. B
AD654
ABSOLUTE MAXIMUM RATING
Total Supply Voltage +VS to –VS . . . . . . . . . . . . . . . . . . . 36 V
Maximum Input Voltage
(Pins 3, 4) to –VS . . . . . . . . . . . . . . . . . . . . –300 mV to +VS
Maximum Output Current
Instantaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Sustained . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Logic Common to –VS . . . . . . . . . . . . . . . –500 mV to (+VS –4)
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD654JN
AD654JR
–40°C to +85°C
–40°C to +85°C
8-Lead Plastic DIP
8-Lead SOIC
N-8
SO-8
REV. B
–3–
AD654
CIRCUIT OPERATION
V/F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
OR CURRENT
The AD654’s block diagram appears in Figure 1. A versatile
operational amplifier serves as the input stage; its purpose is to
convert and scale the input voltage signal to a drive current in the
NPN follower. Optimum performance is achieved when, at the
full-scale input voltage, a 1 mA drive current is delivered to the
current-to-frequency converter (an astable multivibrator). The
drive current provides both the bias levels and the charging current
to the externally connected timing capacitor. This “adaptive” bias
scheme allows the oscillator to provide low nonlinearity over
the entire current input range of 100 nA to 2 mA. The square
wave oscillator output goes to the output driver which provides
a floating base drive to the NPN power transistor. This floating
drive allows the logic interface to be referenced to a level other
than –VS.
+VS
(+5V TO –VS +30)
The AD654 can accommodate a wide range of negative input
voltages with proper selection of the scaling resistor, as indicated
in Figure 2. This connection, unlike the buffered positive connection, is not high impedance because the signal source must
supply the 1 mA FS drive current. However, large negative voltages beyond the supply can be handled easily by modifying the
scaling resistors appropriately. If the input is a true current source,
R1 and R2 are not used. Again, diode CR1 prevents latch-up by
insuring Logic Common does not drop more than 500 mV below
–VS. The clamp diode (MBD101) protects the AD654 input
from “below –VS” inputs.
+VS
(+5V TO –VS +30)
RPU
+VLOGIC
CT
VIN
FOUT
OPTIONAL
RCOMP
RPU
OPTIONAL
RCOMP
OSC/
DRIVER
FOUT
FOUT =
OSC/
DRIVER
FOUT =
AD654
VIN
VIN
R1
AD654
R2
VIN
(10V) (R1 + R2) CT
(10V) (R1 + R2) CT
CLAMP
DIODE
CR1
R1
R2
+VLOGIC
CT
–VS
(0V TO –15V)
CR1
Figure 2. V-F Connections for Negative Input Voltages or
Current
–VS
(0V TO –15V)
Figure 1. Standard V-F Connection for Positive Input
Voltages
OFFSET CALIBRATION
In theory, two adjustments calibrate a V/F: scale and offset. In
practice, most applications find the AD654’s 1 mV max voltage
offset sufficiently low to forgo offset calibration. However, the
input amplifier’s 30 nA (typ) bias currents will generate an offset
due to the difference in dc sound resistance between the input
terminals. This offset can be substantial for large values of RT =
R1 + R2 and will vary as the bias currents drift over temperature.
Therefore, to maintain the AD654’s low offset, the application may
require balancing the dc source resistances at the inputs (Pins
3 and 4).
V/F CONNECTION FOR POSITIVE INPUT VOLTAGES
In the connection scheme of Figure 1, the input amplifier presents
a very high (250 MΩ) impedance to the input voltage, which
is converted into the proper drive current by the scaling resistors
at Pin 3. Resistors R1 and R2 are selected to provide a 1 mA
full-scale current with enough trim range to accommodate the
AD654’s 10% FS error and the components’ tolerances. Fullscale currents other than 1 mA can be chosen, but linearity will
be reduced; 2 mA is the maximum allowable drive. The AD654’s
positive input voltage range spans from –VS (ground in sink supply
operation) to four volts below the positive supply. Power supply rejection degrades as the input exceeds (+VS – 3.75 V) and at
(+VS – 3.5 V) the output frequency goes to zero.
For positive inputs, this is accomplished by adding a compensation
resistor nominally equal to RT in series with the input as shown
in Figure 3a. This limits the offset to the product of the 30 nA
bias current and the mismatch between the source resistance RT
and RCOMP. A second, smaller offset arises from the inputs’ 5 nA
offset current flowing through the source resistance RT or RCOMP.
For negative input voltage and current connections, the compensation resistor is added at Pin 4 as shown in Figure 3b in lieu of
grounding the pin directly. For both positive and negative inputs,
the use of RCOMP may lead to noise coupling at Pin 4 and should
therefore be bypassed for lowest noise operation.
As indicated by the scaling relationship in Figure 1, a 0.01 µF
timing capacitor will give a 10 kHz full-scale frequency, and
0.001 µF will give 100 kHz with a 1 mA drive current. Good V/F
linearity requires the use of a capacitor with low dielectric
absorption (DA), while the most stable operation over temperature calls for a component having a small tempco. Polystyrene,
polypropylene, or Teflon* capacitors are preferred for tempco and
dielectric absorption; other types will degrade linearity. The
capacitor should be wired very close to the AD654. In Figure 1,
Schottky diode CR1 (MBD101) prevents logic common from
dropping more than 500 mV below –VS. This diode is not
required if –VS is equal to logic common.
(OPTIONAL)
C
VIN
AD654
RCOMP
R1
R2
Figure 3a. Bias Current Compensation—Positive Inputs
*Teflon is a trademark of E.I. Du Pont de Nemours & Co.
–4–
REV. B
AD654
(OPTIONAL)
C
AD654
RCOMP
R1
VIN
R2
Figure 3b. Bias Current Compensation—Negative Inputs
If the AD654’s 1 mV offset voltage must be trimmed, the trim
must be performed external to the device. Figure 3c shows an
optional connection for positive inputs in which ROFF1 and
ROFF2 add a variable resistance in series with RT. A variable
source of ± 0.6 V applied to ROFF1 then adjusts the offset ± 1 mV.
Similarly, a ± 0.6 V variable source is applied to ROFF in Figure 3d to trim offset for negative inputs. The ± 0.6 V bipolar
source could simply be an AD589 reference connected as shown
in Figure 3e.
linearity, it is unnecessary for the end-user to perform this tedious
and time consuming test on a routine basis.
Sufficient FS calibration trim range must be provided to accommodate the worst-case sum of all major scaling errors. This
includes the AD654’s 10% full-scale error, the tolerance of the
fixed scaling resistor, and the tolerance of the timing capacitor.
Therefore, with a resistor tolerance of 1% and a capacitor tolerance
of 5%, the fixed part of the scaling resistor should be a maximum
of 84% of nominal, with the variable portion selected to allow
116% of the nominal.
If the input is in the form of a negative current source, the scaling
resistor is no longer required, eliminating the capability of trimming FS frequency in this fashion. Since it is usually not practical
to smoothly vary the capacitance for trimming purposes, an
alternative scheme such as the one shown in Figure 4 is needed.
Designed for a FS of 1 mA, this circuit divides the input into two
R2
100V
AD654
VIN
AD654
R4
392V
10kV
R3
1kV
IS
ROFF2
20V 5kV
8.25kV
R1
100V
ROFF1
10kV
1mA
FS
IR
*
ROFF
100kV
60.6V
60.6V
–V
Figure 3c. Offset Trim Positive Input (10 V FS)
60.6V
ROFF
5.6MV
8.25kV
5kV
Since the 1 mA FS input current is divided into two 500 µA legs
(one to ground and one to Pin 3), the total input signal current
(IS) is divided by a factor of two in this network. To achieve the
same conversion scale factor, CT must be reduced by a factor of
two. This results in a transfer unique to this hookup:
R1
10kV
+5V
R3
10kV
AD589
–
–5V
R2
10kV
f =
R5
100kV
60.6V
R4
10kV
Figure 3e. Offset Trim Bias Network
FULL-SCALE CALIBRATION
Full-scale trim is the calibration of the circuit to produce the
desired output frequency with a full-scale input applied. In most
cases this is accomplished by adjusting the scaling resistor RT.
Precise calibration of the AD654 requires the use of an accurate
voltage standard set to the desired FS value and an accurate
frequency meter. A scope is handy for monitoring output waveshape. Verification of converter linearity requires the use of a
switchable voltage source or DAC having a linearity error below
± 0.005%, and the use of long measurement intervals to minimize count uncertainties. Since each AD654 is factory tested for
REV. B
*OPTIONAL
OFFSET TRIM
and flowing into Pin 3; it constitutes the signal current IT to be
converted. The second path, through another 100 Ω resistor R2,
carries the same nominal current. Two equal valued resistors
offer the best overall stability, and should be either 1% discrete
film units, or a pair from a common array.
AD654
Figure 3d. Offset Trim Negative Input (–10 V FS)
+
IS
(20V) CT
Figure 4. Current Source FS Trim
10kV
VIN
f=
–5–
IS
(20 V ) CT
For calibration purposes, resistors R3 and R4 are added to the
network, allowing a ± 15% trim of scale factor with the values
shown. By varying R4’s value the trim range can be modified to
accommodate wider tolerance components or perhaps the calibration tolerance on a current output transducer such as the
AD592 temperature sensor. Although the values of R1–R4 shown
are valid for 1 mA FS signals only, they can be scaled upward
proportionately for lower FS currents. For instance, they should
be increased by a factor of ten for a FS current of 100 µA.
In addition to the offsets generated by the input amplifier’s bias
and offset currents, an offset voltage induced parasitic current
arises from the current fork input network. These effects are
minimized by using the bias current compensation resistor ROFF
and offset trim scheme shown in Figure 3e.
Although device warm-up drifts are small, it is good practice to
allow the devices operating environment to stabilize before trim,
AD654
between the various circuits in the system. Ceramic capacitors
of 0.1 µF to 1.0 µF should be applied between the supplyvoltage pins and analog signal ground for proper bypassing on
the AD654. A proper ground scheme appears in Figure 6.
and insure the supply, source and load are appropriate. If provision
is made to trim offset, begin by setting the input to 1/10,000 of
full scale. Adjust the offset pot until the output is 1/10,000 of
full scale (for example, 25 Hz for a FS of 250 kHz). This is most
easily accomplished using a frequency meter connected to the
output. The FS input should then be applied and the gain pot
should be adjusted until the desired FS frequency is indicated.
10V
CT
INPUT PROTECTION
8
The AD654 was designed to be used with a minimum of additional
hardware. However, the successful application of a precision IC
involves a good understanding of possible pitfalls and the use of
suitable precautions. Thus +VIN and RT pins should not be driven
more than 300 mV below –VS. Likewise, Logic Common should
not drop more than 500 mV below –VS. This would cause internal junctions to conduct, possibly damaging the IC. In addition
to the diode shown in Figures 1 and 2 protecting Logic Common,
a second Schottky diode (MBD101) can protect the AD654’s
inputs from “below –VS’’ inputs as shown in Figure 5. It is also
desirable not to drive +VIN and R T above +VS. In operation, the
converter will exhibit a zero output for inputs above (+VS – 3.5 V).
Also, control currents above 2 mA will increase nonlinearity.
The AD654’s 80 dB dynamic range guarantees operation from a
control current of 1 mA (nominal FS) down to 100 nA (equivalent to 1 mV to 10 V FS). Below 100 nA improper operation of
the oscillator may result, causing a false indication of input
amplitude. In many cases this might be due to short-lived noise
spikes which become added to input. For example, when scaled
to accept an FS input of 1 V, the –80 dB level is only 100 µV, so
when the mean input is only 60 dB below FS (1 mV), noise spikes
of 0.9 mV are sufficient to cause momentary malfunction.
7
0.1mF
6
5
+5V
AD654
RPU
GND
1
fOUT
2
3
DIGITAL
P.S.
4
RT
AGND
VIN
Figure 6. Proper Ground Scheme
OUTPUT INTERFACING CONSIDERATION
The output stage’s design allows easy interfacing to all digital logic
families. The output NPN transistor’s emitter and collector are
both uncommitted. The emitter can be tied to any voltage between
–VS and 4 volts below +VS, and the open collector can be pulled
up to a voltage 36 volts above the emitter regardless of +VS. The
high power output stage can sink over 10 mA at a maximum
saturation voltage of 0.4 V. The stage limits the output current
at 25 mA and can handle this limit indefinitely without damaging the device.
NONLINEARITY SPECIFICATION
The preferred method of specifying nonlinearity error is in terms
of maximum deviation from the ideal relationship after calibrating the converter at full scale. This error will vary with the full
scale frequency and the mode of operation. The AD654 operates
best at a 150 kHz full-scale frequency with a negative voltage input;
the linearity is typically within 0.05%. Operating at higher frequencies or with positive inputs will degrade the linearity as
indicated in the Specifications Table. Typical linearity at various
temperatures is shown in Figure 7.
This effect can be minimized by using a simple low-pass filter
ahead of the converter or a guard ring around the RT pin. The
filter can be assembled using the bias current compensation
resistor discussed in the previous section. For an FS of 10 kHz,
a single-pole filter with a time constant of 100 ms will be suitable,
but the optimum configuration will depend on the application
and the type of signal processing. Noise spikes are only likely to
be a cause of error when the input current remains near its minimum value for long periods of time; above 100 nA full integration
of additive input noise occurs. Like the inputs, the capacitor
terminals are sensitive to interference from other signals. The
timing capacitor should be located as close as possible to the
AD654 to minimize signal pickup in the leads. In some cases,
guard rings or shielding may be required.
10
MAXIMUM NONLINEARITY – %
5
AD654
IIN
fAMB = –408C
1
0.5
fAMB = 08C TO +858C
0.10
0.05
MBD101
0.01
10
Figure 5. Input Protection
150
250
350
FULL-SCALE FREQUENCY – kHz
500
Figure 7. Typical Nonlinearities at Different Full-Scale
Frequencies
DECOUPLING
It is good engineering practice to use bypass capacitors on the
supply-voltage pins and to insert small-valued resistors (10 to
100 Ω) in the supply lines to provide a measure of decoupling
–6–
REV. B
AD654
1N4148
R1
R2
1mF
R4
RT
VS
(10V TO 15V)
R3
+
AD654
AD589
140V
–
OSC/
DRIVER
Q1
2N3906
1mA/kV
CMOS
OUTPUT
RS
AD592
CT
0.01mF
R5
f=
TTL
OUTPUT
(1 LOAD)
R6
220V
IT
(10V) CT
Figure 8. Two-Wire Temperature-to-Frequency Converter
TWO-WIRE TEMPERATURE-TO-FREQUENCY
CONVERSION
Figure 8 shows the AD654 in a two-wire temperature-to-frequency
conversion scheme. The twisted pair transmission line serves the
dual purpose of supplying power to the device and also carrying
frequency data in the form of current modulation.
The positive supply line is fed to the remote V/F through a
140 Ω resistor. This resistor is selected such that the quiescent
current of the AD654 will cause less than one VBE to be dropped.
As the V/F oscillates, additional switched current is drawn through
RL when Pin 1 goes low. The peak level of this additional current causes Q1 to saturate, and thus regenerates the AD654’s
output square wave at the collector. The supply voltage to the
AD654 then consists of a dc level, less the resistive line drop, plus a
one VBE p-p square wave at the output frequency of the AD654.
This ripple is reduced by the diode/capacitor combination.
To set up the receiver circuit for a given voltage, the RS and RL
resistances are selected as shown in Table I. CMOS logic stages
can be driven directly from the collector of Q1, and a single TTL
load can be driven from the junction of RS and R6.
RS (⍀)
RL (⍀)
10 V
15 V
270
680
1.8k
2.7k
When scaling per K, resistors R1–R3 and the AD589 voltage
reference are not used. The AD592 produces a 1 µA/K current
output which drives Pin 3 of the AD654. With the timing
capacitor of 0.01 µF this produces an output frequency scaled to
10 Hz/K. When scaling per °C and °F, the AD589 and resistors
R1–R3 offset the drive current at Pin 3 by 273.2 µA for scaling
per °C and 255.42 µA for scaling per °F. This will result in frequencies sealed at 10 Hz/°C and 5.55 Hz/°F, respectively.
OPTOISOLATOR COUPLING
A popular method of isolated signal coupling is via optoelectronic isolators, or optocouplers. In this type of device, the signal is
coupled from an input LED to an output photo-transistor, with
light as the connecting medium. This technique allows dc to be
transmitted, is extremely useful in overcoming ground loop
problems between equipment, and is applicable over a wide
range of speeds and power.
Figure 9 shows a general purpose isolated V/F circuit using a
low cost 4N37 optoisolator. A +5 V power supply is assumed for
both the isolated (+5 V isolated) and local (+5 V local) supplies.
The input LED of the isolator is driven from the collector output of the AD654, with a 9 mA current level established by R1
for high speed, as well as for a 100% current transfer ratio.
Table I.
+VS
values shown in Table II. Since temperature is the parameter of
interest, an NPO ceramic capacitor is used as the timing capacitor for low V/F TC.
5V
(ISOLATED)
Table II.
5V
(LOCAL)
R1
390V
4N37
OPTO-ISOLATOR
(+VS ) R1 (⍀) R2 (⍀) R3 (⍀) R4 (⍀) R5 (⍀)
–
–
–
–
–
–
100k
100k
127k
127k
°C 10 V
15 V
6.49k
12.7k
4.02k
4.02k
1k
1k
95.3k
78.7k
22.6k F = 10 Hz/°C
36.5k
°F 10 V
15 V
6.49k
12.7k
4.42k
4.42k
1k
1k
154k
105k
22.6k F = 5.55 Hz/°F
36.5k
K
10 V
15 V
GRN
LED
F = 10 Hz/K
AD654
VIN
(0V TO 1V)
At the V/F end, the AD592C temperature transducer is interfaced with the AD654 in such a manner that the AD654 output
frequency is proportional to temperature. The output frequency
can be sealed and offset from K to °C or °F using the resistor
REV. B
74LS14
OSC/
DRIVER
R2
120V
RT
1kV
CT
1000pF
ISOLATED
LOCAL
Figure 9. Optoisolator Interface
–7–
R3
270V
Q1
2N3904
V/F OUTPUT
FS = 100kHz
TTL
AD654
At the receiver side, the output transistor is operated in the
photo-transistor mode; that is with the base lead (Pin 6) open.
This allows the highest possible output current. For reasonable
speed in this mode, it is imperative that the load impedance be
as low as possible. This is provided by the single transistor stage
current-to-voltage converter, which has a dynamic load impedance of less than 10 ohms and interfaces with TTL at the output.
Longer count periods not only result in the count having more
resolution, they also serve as an integration of noisy analog signals.
For example, a normal-mode 60 Hz sine wave riding on the input
of the AD654 will result in the output frequency increasing on
the positive half of the sine wave and decreasing on the negative
half of the sine wave. This effect is cancelled by selecting a count
period equal to an integral number of noise signal periods. A
100 ms count period is effective because it not only has an integral number of 60 Hz cycles (6), it also has an integral number
of 50 Hz cycles (5). This is also true of the 1 second and 10 second count period.
USING A STAND-ALONE FREQUENCY COUNTER/LED
DISPLAY DRIVER FOR VOLTMETER APPLICATIONS
Figure 10 shows the AD654 used with a stand-alone frequency
counter/LED display driver. With CT = 1000 pF and RT = 1 kΩ
the AD654 produces an FS frequency of 100 kHz when VIN =
+1 V. This signal is fed into the ICM7226A, a universal counter
system that drives common anode LEDs. With the FUNCTION
pin tied to D1 through a 10 kΩ resistor the ICM7226A counts the
frequency of the signal at AIN. This count period is selected by
the user and can be 10 ms, 100 ms, 1s, or 10 seconds, as shown on
Pin 21. The longer the period selected, the more resolution the
count will have. The ICM7226A then displays the frequency on
the LEDs, driving them directly as shown. Refreshing of the LEDs
is handled automatically by the ICM7226. The entire circuit operates on a single +5 V supply and gives a meter with 3, 4, or 5
digit resolution.
5V
AD654-BASED ANALOG-TO-DIGITAL CONVERSION
USING A SINGLE CHIP MICROCOMPUTER
The AD654 can serve as an analog-to-digital converter when
used with a single component microcomputer that has an interval timer/event counter such as the 8048. Figure 11 shows the
AD654, with a full-scale input voltage of +1 V and a full-scale
output frequency of 100 kHz, connected to the timer/counter
input Pin T1 of the 8048. Such a system can also operate on a
single +5 V supply.
The 8748 counter is negative edge triggered; after the STRT
CNT instruction is executed subsequent high to low transitions
on T1 increment the counter. The maximum rate at which the
counter may be incremented is once per three instruction cycles;
using a 6 MHz crystal, this corresponds to once every 7.5 µs, or
a maximum frequency of 133 kHz. Because the counter overflows
every 256 counts (8 bits), the timer interrupt is enabled. Each
overflow then causes a jump to a subroutine where a register is
incremented. After the STOP TCNT instruction is executed, the
number of overflows that have occurred will be the number in
this register. The number in this register multiplied by 256 plus
the number in the counter will be the total number of negative
edges counted during the count period. The count period is
handled simply by decrementing a register the number of times
necessary to correspond to the desired count time. After the
register has been decremented the required number of times the
STOP TCNT instruction is executed.
5V
1kV
8
1
825V
500V
7
2
AD654
3
+
1000pF
6
5
4
VIN
(0V TO 1V)
1kV
–
DI PIN 30
1
AIN
40
2
HOLD
39
10kV
NC
37
5
OSL JN
36
6
OSL OUT
35
7
NC
34
4
30kV
FUNCTION
8
dp
5V
g
22MV
5V
33
ICM7226A
9
e
10
g
11
a
D1
30
12
GND
D2
29
13
d
D3
28
14
b
D4
27
15
c
D5
26
16
f
V+
25
17
D6
24
18
D7
23
19
D8
22
20
RANGE
21
39pF
39pF
The total number of negative edges counted during the count
period is proportional to the input voltage. For example, if a 1 V
full-scale input voltage produces a 100 kHz signal and the count
period is 100 ms, then the total count will be 10,000. Scaling
from this maximum is then used to determine the input voltage,
i.e., a count of 5000 corresponds to an input voltage of 0.5 V.
As with the ICM7226, longer count times result in counts having more resolution; and they result in the integration of noisy
analog signals.
32
31
5V
5V
5V
D1 (10ms)
10kV
4
D2 (100ms)
D3 (1s)
8
D4 (10s)
8
D.P.
10MHz
CRYSTAL
38
3
f
e
d
c
b
a
LED
OVERFLOW
INDICATOR
D8
D7
D6
D5
D4
D3
D2
D1
NC = NO CONNECT
Figure 10. AD654 With Stand-Alone Frequency Counter/
LED Display Driver
–8–
REV. B
AD654
5V
VCC
20pF
FREQUENCY DOUBLING
GND
VDD
VSS
P10
XTAL1
20pF
Since the AD654’s output is a square-wave rather than a pulse
train, information about the input signal is carried on both
halves of the output waveform. The circuit in Figure 12 converts
the output into a pulse train, effectively doubling the output
frequency, while preserving the better low frequency linearity of
the AD654. This circuit also accommodates an input voltage
that is greater than the AD654 supply voltage.
PORT 1
6MHz
P17
XTAL2
1mF
P20
RESET
EA
NC
PORT 2
8048
SS
Resistors R1–R3 are used to scale the 0 V to +10 V input voltage
down to 0 V to +1 V as seen at Pin 4 of the AD654. Recall that
VIN must be less than VSUPPLY –4 V, or in this case less than 1 V.
The timing resistor and capacitor are selected such that this 0 V
to +1 V signal seen at Pin 4 results in a 0 kHz to 200 kHz output
frequency.
P27
INT
DB0
T0
DB7
T1
ALE PSEN PROG WR
NC
BUS
PORT
RD
The use of R4, C1 and the XOR gate doubles this 200 kHz
output frequency to 400 kHz. The AD654 output transistor is
basically used as a switch, switching capacitor C1 between a
charging mode and a discharging mode of operation. The voltages
seen at the input of the 74LS86 are shown in the waveform diagram. Due to the difference in the charge and discharge time
constants, the output pulse widths of the 74LS86 are not equal.
The output pulse is wider when the capacitor is charging due to
its longer rise time than fall time. The pulses should therefore be
counted on their rising, rather than falling, edges.
NC
NC = NO CONNECT
5V
10kV
1
2
+
8
AD654
7
1000pF
3
6
4
5
1kV
825V
1%
VIN
(0V TO 1V)
500V
–
D
A
Figure 11. AD654 VFC as an ADC
5V
RPU
2.87kV
AD654
R1
R2
8.06kV 2kV
OSC/
DRIVER
R4
1kV
C1
1000pF
VIN
(0V TO 10V)
R3
1kV
RT
1kV
CT
500pF
TRANSISTOR
OFF
ON
A
V
0
B
V
0
C
5
0
WAVEFORM DIAGRAM
Figure 12. Frequency Doubler
REV. B
–9–
A
74LS86
C
B
V/F OUTPUT
FS = 400MHz
AD654
+15V
10mF
+5V
+15V
MINIMUM
DISTANCE
0.1mF
V1
2
+
VIN
(0V TO 1V)
–
7
3
6
4
5
10mF
+
V4
R7
8.2V
V3
A3-c
V2
A2
LM360
10mF
Q2
RT = 1kV
68kV
J270
CT
100pF
1kV
0.1mF
Q1
8
AD654
A3 = 74LS86
D
A3-d
68kV
1
0.1mF
J270
18V
A3-a
5.9kV
1%
(32)
MINIMUM
DISTANCE
A3-b
470pF
0.1mF
A
10mF
D
–5V
Figure 13. 2 MHz, Frequency Doubling V/F
OPERATION AT HIGHER OUTPUT FREQUENCIES
Operation of the AD654 via the conventional output (Pins 1 and
2) is speed limited to approximately 500 kHz for reasons of TTL
logic compatibility. Although the output stage may become
speed limited, the multivibrator core itself is able to oscillate to
1 MHz or more. The designer may take advantage of this feature in
order to operate the device at frequencies in excess of 500 kHz.
Figure 13 illustrates this with a circuit offering 2 MHz full scale.
In this circuit the AD654 is operated at a full scale (FS) of 1 mA,
with a CT of 100 pF. This achieves a basic device FS frequency
of 1 MHz across CT. The P channel JFETs, Q1 and Q2, buffer
the differential timing capacitor waveforms to a low impedance
level where the push-pull signal is then ac coupled to the high speed
comparator A2. Hysteresis is used, via R7, for nonambiguous
switching and to eliminate the oscillations which would otherwise occur at low frequencies.
The output of the comparator is a complementary square wave
at 1 MHz FS. Unlike pulse train output V/F converters, each
half-cycle of the AD654 output conveys information about the
input. Thus it is possible to count edges, rather than full cycles
of the output, and double the effective output frequency. The
XOR gate following A2 acts as an edge detector producing a short
pulse for each input state transition. This effectively doubles the
V/F FS frequency to 2 MHz. The final result is a 1 V full-scale
input V/F with a 2 MHz full-scale output capability; typical
nonlinearity is 0.5%.
The net result of this is a very high speed circuit which does not
compromise the AD654 dynamic range. This is a result of the FET
buffers typically having only a few pA of bias current. The high
end dynamic range is limited, however, by parasitic package and
layout capacitances in shunt with CT, as well as those from each node
to ac ground. Minimizing the lead length between A2–6/A2–7 and
Q1/Q2 in PC layout will help. A ground plane will also help
stability. Figure 14 shows the waveforms V1–V4 found at the
respective points shown in Figure 13.
–10–
2V
5V
2V
5V
500ns
2V
V1
100
0
90
2V
V2
0
5V
V3
0
10
0%
5V
V4
0
Figure 14. Waveforms of 2 MHz Frequency Doubler
REV. B
AD654
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.430 (10.92)
0.348 (8.84)
8
5
0.280 (7.11)
0.240 (6.10)
PIN 1
1
4
0.100 (2.54)
BSC
0.210 (5.33)
MAX
0.325 (8.25)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
C900d–0–12/99 (rev. B)
8-Lead Plastic DIP (N-8)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
0.015 (0.381)
0.008 (0.204)
8-Lead SOIC (SO-8)
(Narrow Body)
0.1968 (5.00)
0.1890 (4.80)
8
0.1574 (4.00)
0.1497 (3.80) 1
5
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
x 458
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0098 (0.25)
0.0040 (0.10)
88
0.0500 (1.27)
0.0098 (0.25) 08
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
PRINTED IN U.S.A.
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
REV. B
–11–