LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 LMK0482xB Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner with Dual Loop PLLs Check for Samples: LMK04826B, LMK04828B 1 INTRODUCTION 1.1 Features 12 • JEDEC JESD204B Support • Ultra-Low RMS Jitter and Performance – 88 fs RMS jitter (12 kHz to 20 MHz) – 91 fs RMS jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz noise floor at 245.76 MHz • Up to 14 Differential Device Clocks from PLL2 – Up to 7 SYSREF Clocks – Maximum clock output frequency 3.1 GHz – LVPECL, LVDS, HSDS, LCPECL programmable outputs from PLL2 • Up to 1 buffered VCXO/Crystal output from PLL1 – LVPECL, LVDS, 2xLVCMOS programmable • Dual Loop PLLatinum™ PLL Architecture • PLL1 – Up to 3 redundant input clocks • Automatic and manual switch-over modes • Hitless switching and LOS Recovered ³GLUW\´ FORFN RU clean clock Crystal or VCXO – Integrated Low-Noise Crystal Oscillator Circuit – Holdover mode when input clocks are lost PLL2 – Normalized [1 Hz] PLL noise floor of –227 dBc/Hz – Phase detector rate up to 155 MHz – OSCin frequency-doubler – Two Integrated Low-Noise VCOs 50% duty cycle output divides, 1 to 32 (even and odd) Precision digital delay, dynamically adjustable 25 ps step analog delay Multi-mode: Dual PLL, single PLL, and clock distribution in 0 delay option Industrial Temperature Range: –40 to 85°C 3.15 V to 3.45 V operation Package: 64-pin QFN (9.0 x 9.0 x 0.8 mm) • • • • • • • • Device VCO0 Frequency VCO1 Frequency LMK04826 1840 to 1970 MHz 2440 to 2505 MHz LMK04828 2370 to 2630 MHz 2920 to 3080 MHz OSCout 0XOWLSOH ³FOHDQ´ clocks at different frequencies LMX2581 PLL+VCO CLKin0 DCLKout12 Backup Reference Clock CLKin1 SDCLKout13 LMK0482xB SDCLKout1 & SDCLKout3 DCLKout8 & DCLKout10 SDCLKout9 & SDCLKout11 DCLKout0 & DCLKout2 ADC FPGA DCLKout4, SDCLKout5 DAC DAC Serializer/ Deserializer 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PLLatinum is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 1.2 • • • • • www.ti.com Applications Wireless Infrastructure Data Converter Clocking Networking, SONET/SDH, DSLAM Medical / Video / Military / Aerospace Test and Measurement 1.3 Description The LMK04820 family is the industry's highest performance clock conditioner with JEDEC JESD204B support. The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can individually be configured as a high performance outputs for traditional clocking systems. The high performance combined with features like the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, glitchless analog delay make the LMK04820 family ideal for providing flexible high performance clocking trees. 1.4 Device Configuration Information spacer NSID Reference Inputs (1) OSCout (Buffered OSCin Clock) LVDS/ LVPECL/ LVCMOS (1) PLL2 Programmable LVDS/LVPECL/HSDS Outputs VCO0 Frequency VCO1 Frequency LMK04826BISQ Up to 3 Up to 1 14 1840 to 1970 MHz 2440 to 2505 MHz LMK04828BISQ Up to 3 Up to 1 14 2370 to 2630 MHz 2920 to 3080 MHz (1) 2 OSCout may also be third clock input, CLKin2. INTRODUCTION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 1.5 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Functional Block Diagrams and Operating Modes The LMK04820 Family is a flexible device that can be configured for many different use cases. The following simplified block diagrams help show the user the different use cases of the device. 1.5.1 DUAL PLL Figure 1-1 illustrates the typical use case of the LMK04820 family in dual loop mode. In dual loop mode the reference to PLL1 from CLKin0, CLKin1, or CLKin2. An external VCXO or tunable crystal will be used to provide feedback for the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO or low cost tunable crystal by using a narrow loop bandwidth. The VCXO or tunable crystal output may be buffered through the OSCout port. The VCXO or tunable crystal is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to seven divide/delay blocks which drive up to 14 clock outputs. Hitless switching and holdover functionality are optionally available when the input reference clock is lost. Holdover works by fixing the tuning voltage of PLL1 to the VCXO or tunable crystal. It is also possible to use an external VCO in place of PLL2's internal VCO. In this case one less CLKin is available as a reference. PLL1 PLL2 R N Phase Detector PLL1 External VCXO or Tunable Crystal External Loop Filter External Loop Filter OSCout OSCout* OSCin CLKinX CLKinX* Up to 3 inputs CPout1 Up to 1 OSCout 7 blocks CPout2 R Input Buffer N Phase Detector PLL2 Device Clock Divider Digital Delay Analog Delay Partially Integrated Loop Filter Dual Internal VCOs LMK0482xB SYSREF Digital Delay Analog Delay 7 Device Clocks DCLKoutX DCLKoutX* 7 SYSREF or Device Clocks SDCLKoutY SDCLKoutY* 1 Global SYSREF Divider Figure 1-1. Simplified Functional Block Diagram for Dual Loop Mode Table 1-1. Dual Loop Mode Register Configuration Field Register Address Function Value PLL1_NCLK_MUX 0x13F Selects the input to the PLL1 N divider 0 OSCin PLL2_NCLK_MUX 0x13F Selects the input to the PLL2 N divider 0 PLL2_P FB_MUX_EN 0x13F Enables the Feedback Mux 0 Disabled FB_MUX 0x13F Selects the output of the Feedback Mux X Don't care because FB_MUX is disabled OSCin_PD 0x140 Powers down the OSCin port 0 Powered up CLKin0_OUT_MUX 0x147 Selects where the output of CLKin0 is directed. 2 PLL1 CLKin1_OUT_MUX 0x147 Selects where the output of CLKin1 is directed. 2 PLL1 VCO_MUX 0x138 Selects the VCO 0, 1 or an external VCO 0 or 1 VCO 0 or VCO 1 Selected Value INTRODUCTION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 3 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 1.5.2 www.ti.com 0-DELAY DUAL PLL Figure 1-2 illustrates the use case of cascaded 0-delay dual loop mode. This configuration differs from duel loop mode Figure 1-1 in that the feedback for PLL2 is driven by a clock output instead of the VCO output. Figure 1-3 illustrates the use case of nested 0-delay dual loop mode. This configuration is similar to the duel PLL in Section 1.5.1 except that the feedback to the first PLL is driven by a clock output. This causes the clock outputs to have deterministic phase relationship with the clock input. Since all the clock outputs can be synchronized together, all the clock outputs can share the same deterministic phase relationship with the clock input signal. The feedback to PLL1 can be connected internally as shown using CLKout6, CLKout8, SYSREF, or externally using FBCLKin (CLKin1). It is also possible to use an external VCO in place of PLL2's internal VCO; but one less CLKin is available as a reference and external 0-delay feedback is not available. PLL1 PLL2 R N Phase Detector PLL1 External VCXO or Tunable Crystal External Loop Filter OSCout OSCout* OSCin CLKinX CLKinX* Up to 3 inputs CPout1 Up to 1 OSCout External Loop Filter CPout2 Divider Digital Delay Analog Delay R Input Buffer N Phase Detector PLL2 Partially Integrated Loop Filter Dual Internal VCOs Internal or external loopback, user programmable SDCLKoutY SDCLKoutY* 7 SYSREF or Device Clocks 7 blocks SYSREF Analog Delay Digital Delay 1 Global SYSREF Divider LMK0482xB DCLKoutX DCLKoutX* 7 Device Clocks Figure 1-2. Simplified Functional Block Diagram for Cascaded 0-delay Dual Loop Mode Table 1-2. Cascaded 0-delay Dual Loop Mode Register Configuration 4 Field Register Address Function Value PLL1_NCLK_MUX 0x13F Selects the input to the PLL1 N divider. 0 OSCin PLL2_NCLK_MUX 0x13F Selects the input to the PLL2 N divider 1 Feedback Mux FB_MUX_EN 0x13F Enables the Feedback Mux. 1 Feedback Mux Enabled FB_MUX 0x13F Selects the output of the Feedback Mux. 0, 1, or 2 Select between DCLKout6, DCLKout8, SYSREF OSCin_PD 0x140 Powers down the OSCin port. 0 Powered up CLKin0_OUT_MUX 0x147 Selects where the output of CLKin0 is directed. 0 PLL1 CLKin1_OUT_MUX 0x147 Selects where the output of CLKin1 is directed. 0 or 2 Fin or PLL1 VCO_MUX 0x138 Selects the VCO 0, 1 or an external VCO 0 or 1 VCO 0 or VCO 1 INTRODUCTION Selected Value Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 PLL1 PLL2 R N Phase Detector PLL1 External VCXO or Tunable Crystal External Loop Filter OSCout OSCout* OSCin CLKinX CLKinX* Up to 3 inputs CPout1 Up to 1 OSCout External Loop Filter CPout2 Divider Digital Delay Analog Delay R Input Buffer N Phase Detector PLL2 Partially Integrated Loop Filter Dual Internal VCOs Internal or external loopback, user programmable SDCLKoutY SDCLKoutY* 7 SYSREF or Device Clocks 7 blocks SYSREF Analog Delay Digital Delay 1 Global SYSREF Divider LMK0482xB DCLKoutX DCLKoutX* 7 Device Clocks Figure 1-3. Simplified Functional Block Diagram for Nested 0-delay Dual Loop Mode Table 1-3 illustrates nested 0-delay mode. This is the same as cascaded except the clock out feedback is to PLL1. The CLKin and CLKout have the same deterministic phase relationship but the VCXO's phase will not be deterministic to the CLKin or CLKouts. Table 1-3. Nested 0-delay Dual Loop Mode Register Configuration Field Register Address Function Value Selected Value PLL1_NCLK_MUX 0x13F Selects the input to the PLL1 N divider. 1 Feedback Mux PLL2_NCLK_MUX 0x13F Selects the input to the PLL2 N divider 0 PLL2 P FB_MUX_EN 0x13F Enables the Feedback Mux. 1 Enabled FB_MUX 0x13F Selects the output of the Feedback Mux. 0, 1, or 2 Select between DCLKout6, DCLKout8, SYSREF OSCin_PD 0x140 Powers down the OSCin port. 0 Powered up CLKin0_OUT_MUX 0x147 Selects where the output of CLKin0 is directed. 2 PLL1 CLKin1_OUT_MUX 0x147 Selects where the output of CLKin1 is directed. 0 or 2 Fin or PLL1 VCO_MUX 0x138 Selects the VCO 0, 1 or an external VCO 0 or 1 VCO 0 or VCO 1 INTRODUCTION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 5 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 1.5.3 www.ti.com DETAILED LMK04820 FAMILY BLOCK DIAGRAM CLKin0 R Divider (1 to 16,383) CLKin1*/ FBCLKin* CLKin1/ FBCLKin CLKin1 R Divider (1 to 16,383) CLKin1 also ExtVCO used for External VCO CLKin2 R Divider (1 to 16,383) R Delay CLKin MUX N1 Divider (1 to 16,383) N Delay Status_LD1 RESET/GPO SYNC Device Control CLKin_SEL0 Status_LD2 CLKin_SEL1 SCLK PLL1 N MUX Control Registers SPI SDIO Holdover CS* FBMux ExtVCO CLKout6 CLKout8 SYSREF Div FB Mux 2X 2X Mux OSCout/ CLKin2 FBMux OSCout*/ CLKin2* Phase Detector PLL1 CPout2 CLKin0* CLKin0 CPout1 Figure 1-4 illustrates the complete LMK04820 family block diagram. SPI Selectable N2 Prescaler (2 to 8) R2 Divider (1 to 4,095) Phase Detector PLL2 PLL2 N MUX Internal Dual Core VCO N2 Divider (1 to 262,143) Clock Distribution Path OSCin* OSCin Partially Integrated Loop Filter VCO MUX ExtVCO Div (1-32) Dig. Delay A. Delay Divider (8 to 8191) System Reference Control SYNC DCLKout12* DCLKout12 SDCLKout13* SDCLKout13 Dig. Delay A. Delay DCLKout0 DCLKout0* Dig. Delay DCLKout2 DCLKout2* Div (1-32) Dig. Delay A. Delay SDCLKout1 SDCLKout1* Div (1-32) A. Delay Dig. Delay A. Delay Dig. Delay Div (1-32) Div (1-32) Dig. Delay A. Delay SDCLKout3 SDCLKout3* A. Delay Dig. Delay SDCLKout5 SDCLKout5* DCLKout8 DCLKout8* SDCLKout9 SDCLKout9* Dig. Delay A. Delay DCLKout4 DCLKout4* SDCLKout11* SDCLKout11 Dig. Delay A. Delay DCLKout10* DCLKout10 A. Delay Dig. Delay Div (1-32) Div (1-32) Dig. Delay A. Delay A. Delay Dig. Delay SDCLKout7 SDCLKout7* Dig. Delay A. Delay DCLKout6 DCLKout6* A. Delay Figure 1-4. Detailed LMK04820 Family Block Diagram 6 INTRODUCTION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 1.6 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Connection Diagram 64-Pin QFN Package CLKin_SEL1 SDCLKout11* SDCLKout11 DCLKout10* DCLKout10 Vcc11_CG3 DCLKout8* DCLKout8 SDCLKout9* SDCLKout9 57 56 55 54 53 52 51 50 49 SDCLKout13 60 CLKin_SEL0 SDCLKout13* 61 58 DCLKout12 62 59 Vcc12_CG0 DCLKout12* 63 Clock Group 3 64 Clock Group 0 DCLKout0 1 48 Status_LD2 DCLKout0* 2 47 Vcc10_PLL2 SDCLKout1 3 46 CPout2 Vcc9_CP2 SDCLKout1* 4 45 RESET/GPO 5 44 OSCin* SYNC/SYSREF_REQ 6 43 OSCin NC 7 42 Vcc8_OSCin NC 8 41 OSCout*/CLKin2* LLP-64 Top down view NC 9 40 OSCout/CLKin2 Vcc1_VCO 10 39 Vcc7_OSCout LDObyp1 11 38 CLKin0* LDObyp2 12 37 CLKin0 SDCLKout3 13 36 Vcc6_PLL1 SDCLKout3* 14 35 CLKin1*/Fin*/FBCLKin* DCLKout2 15 34 CLKin1/Fin/FBCLKin DCLKout2* 16 33 Vcc5_DIG 26 27 28 29 30 31 32 Vcc4_CG2 DCLKout6 DCLKout6* SDCLKout7 SDCLKout7* Status_LD1 CPout1 23 SDCLKout5* 25 22 SDCLKout5 24 21 Vcc3_SYSREF DCLKout4 20 DCLKout4* 19 18 SCK 17 CS* SDIO Clock Group 1 Vcc2_CG1 DAP Clock Group 2 Table 1-4. Pin Descriptions (1) Pin Number Name(s) I/O Type 1, 2 DCLKout0, DCLKout0* O Programmable Device clock output 0. 3, 4 SDCLKout1, SDCLKout1* O Programmable SYSREF / Device clock output 1 5 RESET/GPO I/O CMOS Device reset input or GPO 6 SYNC/SYSREF_R EQ I/O CMOS Synchronization input or programmable status pin or SYSREF_REQ for requesting continuous SYSREF. (1) Description 7, 8, 9 NC 10 Vcc1_VCO PWR No Connection. These pins must be left floating. Power supply for VCO LDO. 11 LDObyp1 ANLG LDO Bypass, bypassed to ground with 10 µF capacitor. 12 LDObyp2 ANLG LDO Bypass, bypassed to ground with a 0.1 µF capacitor. 13, 14 SDCLKout3, SDCLKout3* O Programmable SYSREF / Device Clock output 3. 15, 16 DCLKout2, DCLKout2* O Programmable Device clock output 2. 17 Vcc2_CG1 18 CS* I CMOS Chip Select 19 SCK I CMOS SPI Clock PWR Power supply for clock outputs 2 and 3. See Section 7.2 section for recommended connections. INTRODUCTION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 7 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Table 1-4. Pin Descriptions (continued) Pin Number Name(s) I/O Type 20 SDIO I/O CMOS 21 Vcc3_SYSREF 22, 23 SDCLKout5, SDCKLout5* O Programmable SYSREF / Device clock output 5. 24, 25 DCLKout4, DCLKout4* O Programmable Device clock output 4. PWR PWR Description SPI Data Power supply for SYSREF divider and SYNC. 26 Vcc4_CG2 27, 28 DCLKout6, DCLKout6* O Programmable Device clock output 6. 29, 30 SDCLKout7, SDCLKout7* O Programmable SYSREF / Device clock output 7. 31 Status_LD1 I/O Programmable Programmable status pin. 32 CPout1 O ANLG Charge pump 1 output. 33 Vcc5_DIG PWR Power supply for the digital circuitry. 34, 35 8 (1) Power supply for clock outputs 4, 5, 6 and 7. CLKin1, CLKin1* I ANLG Reference Clock Input Port for PLL1. FBCLKin, FBCLKin* I ANLG Feedback input for external clock feedback input (0–delay mode). Fin, Fin* I ANLG External VCO Input (External VCO mode). PWR Power supply for PLL1, charge pump 1. I ANLG Reference Clock Input Port 0 for PLL1. PWR Power supply for OSCout port. Programmable Buffered output of OSCin port. 36 Vcc6_PLL1 37, 38 CLKin0, CLKin0* 39 Vcc7_OSCout 40,41 OSCout, OSCout* 42 Vcc8_OSCin 43, 44 OSCin, OSCin* 45 Vcc9_CP2 O I O PWR Power supply for OSCin ANLG Feedback to PLL1, Reference input to PLL2. AC coupled. PWR Power supply for PLL2 Charge Pump. ANLG Charge pump 2 output. PWR Power supply for PLL2. 46 CPout2 47 Vcc10_PLL2 48 Status_LD2 I/O Programmable Programmable status pin. 49, 50 SDCLKout9, SDCLKout9* O Programmable SYSREF / Device clock 9 51, 52 DCLKout8, DCLKout8* O Programmable Device clock output 8. 53 Vcc11_CG3 54, 55 DCLKout10, DCLKout10* PWR Power supply for clock outputs 8, 9, 10, and 11. O Programmable Device clock output 10. 56, 57 SDCLKout11, SDCLKout11* O Programmable SYSREF / Device clock output 11. 58 CLKin_SEL0 I/O Programmable Programmable status pin. 59 CLKin_SEL1 I/O Programmable Programmable status pin. 60, 61 SDCLKout13, SDCLKout13* O Programmable SYSREF / Device clock output 13. 62, 63 DCLKout12, DCLKout12* O Programmable Device clock output 12. 64 Vcc12_CG0 PWR Power supply for clock outputs 0, 1, 12, and 13. DAP DAP GND DIE ATTACH PAD, connect to GND. INTRODUCTION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 1 ......................................... 1 ............................................. 1 1.2 Applications .......................................... 2 1.3 Description ........................................... 2 1.4 Device Configuration Information .................... 2 1.5 Functional Block Diagrams and Operating Modes .. 3 1.6 Connection Diagram ................................. 7 ELECTRICAL SPECIFICATIONS .................... 10 2.1 Absolute Maximum Ratings ........................ 10 2.2 Package Thermal Resistance ...................... 10 2.3 Recommended Operating Conditions .............. 10 2.4 Electrical Characteristics ........................... 11 2.5 SPI Timing Diagram ................................ 24 2.6 Differential Voltage Measurement Terminology .... 25 INTRODUCTION 1.1 2 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Features 3 TYPICAL PERFORMANCE CHARACTERISTICS 4 FEATURES 28 4.1 28 3.1 4.2 4.3 4.4 4.5 4.6 ................... .............................................. Jitter Cleaning ...................................... JEDEC JESD204B Support ........................ Clock Output AC Characteristics 26 ..................... Frequency Holdover ................................ PLL2 Integrated Loop Filter Poles .................. 6 26 28 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*) ................................... 28 VCXO/Crystal Buffered Output 5 28 29 29 7 ...................................... ................................ 4.9 Clock Distribution ................................... 4.10 0-Delay ............................................. 4.11 Status Pins ......................................... FUNCTIONAL DESCRIPTIONS ...................... 5.1 Modes Of Operation ................................ 5.2 SYNC/SYSREF ..................................... 5.3 JEDEC JESD204B ................................. 5.4 Digital Delay ........................................ 5.5 SYSREF to Device Clock Alignment ............... 5.6 Input Clock Switching ............................... 5.7 Digital Lock Detect .................................. 5.8 Holdover ............................................ GENERAL PROGRAMMING INFORMATION ..... 6.1 Recommended Programming Sequence ........... 6.2 Register Map ....................................... 6.3 Device Register Descriptions ....................... APPLICATION INFORMATION ...................... 7.1 Digital Lock Detect Frequency Accuracy ........... 7.2 Pin Connection Recommendations ................. 7.3 Driving CLKin AND OSCin Inputs .................. 7.4 Power Supply ....................................... 7.5 Thermal Management .............................. 4.7 Internal VCOs 29 4.8 External VCO Mode 29 Contents Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 29 31 31 32 32 32 35 37 41 42 43 44 46 46 47 51 90 90 90 91 93 94 9 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com 2 ELECTRICAL SPECIFICATIONS 2.1 Absolute Maximum Ratings (1) (2) (3) Parameter Supply Voltage Symbol (4) Ratings Units V VCC -0.3 to 3.6 Input Voltage VIN -0.3 to (VCC + 0.3) V Storage Temperature Range TSTG -65 to 150 °C Lead Temperature (solder 4 seconds) TL +260 °C Junction Temperature TJ 150 °C Differential Input Current (CLKinX/X*, OSCin/OSCin*, FBCLKin/FBCLKin*, Fin/Fin*) IIN ±5 mA Moisture Sensitivity Level MSL 3 (1) "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not assure specific performance limits. For assured specifications and test conditions, see the Electrical Characteristics. The assured specifications apply only to the test conditions listed. This device is a high performance RF integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and up to 250 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations. Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Never to exceed 3.6 V. (2) (3) (4) 2.2 Package Thermal Resistance Table 2-1. 64-Lead QFN LMK0482xB Symbol Thermal Metric (1) NKD Units 64 Pins θJA (3) (4) (5) (6) (7) 2.3 10 24.3 (3) θJC(TOP) Junction-to-case(top) thermal resistance θJB Junction-to-board thermal resistance ΨJT Junction-to-top characterization parameter ΨJB Junction-to-board characterization parameter (6) 3.5 Junction-to-case(bottom) thermal resistance (7) 0.7 θJC(BOTTOM) (1) (2) (2) Junction-to-ambient thermal resistance 6.1 (4) 3.5 (5) 0.1 ° C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Recommended Operating Conditions Parameter Symbol Junction Temperature Min TJ Ambient Temperature TA -40 Supply Voltage VCC 3.15 Typical Max Unit 125 °C 25 85 °C 3.3 3.45 V ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 2.4 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Electrical Characteristics (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units 1 3 mA 565 665 mA 750 MHz Current Consumption ICC_PD ICC_CLKS Power Down Supply Current Supply Current 14 HSDS 8 mA clocks enabled PLL1 and PLL2 locked. (1) CLKin0/0*, CLKin1/1*, and CLKin2/2* Input Clock Specifications fCLKin Clock Input Frequency Clock Input Slew Rate VIDCLKin Clock Input Differential Input Voltage Figure 2-2 VSSCLKin VCLKin 0.001 (2) SLEWCLKin (3) Clock Input Single-ended Input Voltage 20% to 80% 0.15 0.5 V/ns 0.125 1.55 |V| 0.25 3.1 Vpp AC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 0 (Bipolar) 0.25 2.4 Vpp AC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 1 (MOS) 0.35 2.4 Vpp AC coupled Each pin AC coupled, CLKin0/1/2 CLKin0_BUF_TYPE = 0 (Bipolar) 0 |mV| Each pin AC coupled, CLKin0/1 CLKinX_BUF_TYPE = 1 (MOS) 55 |mV| DC offset voltage between CLKin2/CLKin2* (CLKin2* - CLKin2) Each pin AC coupled CLKin2_BUF_TYPE = 1 (MOS) 20 |mV| VCLKin- VIH High input voltage VCLKin- VIL Low input voltage DC coupled to CLKinX; CLKinX* AC coupled to Ground CLKinX_BUF_TYPE = 1 (MOS) fFBCLKin Clock Input Frequency for 0-delay with external feedback. |VCLKinX-offset| DC offset voltage between CLKinX/CLKinX* (CLKinX* - CLKinX) 2.0 VCC V 0.0 0.4 V 0.001 750 MHz FBCLKin/FBCLKin* and Fin/Fin* Input Specifications (3) (4) (4) fFin Clock Input Frequency for external VCO or distribution mode. AC coupled CLKin1_BUF_TYPE = 0 (Bipolar) 0.001 3100 MHz VFBCLKin/Fin Single Ended Clock Input Voltage AC coupled CLKin1_BUF_TYPE = 0 (Bipolar) 0.25 2.0 Vpp AC coupled; 20% to 80%; (CLKinX_BUF_TYPE = 0) 0.15 SLEWFBCLKin/Fin (1) (2) AC coupled CLKin1_BUF_TYPE = 0 (Bipolar) Slew Rate on CLKin (2) 0.5 V/ns See applications section Section 7.4 for Icc for specific part configuration and how to calculate Icc for a specific design. In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs. See Section 2.6 for definition of VID and VOD voltages. Assured by characterization. ATE tested at 2949.12 MHz. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 11 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units 40 MHz PLL1 Specifications fPD1 ICPout1SOURCE ICPout1SINK PLL1 Phase Detector Frequency PLL1 Charge Pump Source Current PLL1 Charge Pump Sink Current (1) (1) VCPout1 = VCC/2, PLL1_CP_GAIN = 0 50 VCPout1 = VCC/2, PLL1_CP_GAIN = 1 150 VCPout1 = VCC/2, PLL1_CP_GAIN = 2 250 … … VCPout1 = VCC/2, PLL1_CP_GAIN = 14 1450 VCPout1 = VCC/2, PLL1_CP_GAIN = 15 1550 VCPout1=VCC/2, PLL1_CP_GAIN = 0 -50 VCPout1=VCC/2, PLL1_CP_GAIN = 1 -150 VCPout1=VCC/2, PLL1_CP_GAIN = 2 -250 … … VCPout1=VCC/2, PLL1_CP_GAIN = 14 -1450 VCPout1=VCC/2, PLL1_CP_GAIN = 15 -1550 µA µA ICPout1%MIS Charge Pump Sink / Source Mismatch VCPout1 = VCC/2, T = 25 °C 1 ICPout1VTUNE Magnitude of Charge Pump Current Variation vs. Charge Pump Voltage 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C 4 % ICPout1%TEMP Charge Pump Current vs. Temperature Variation 4 % ICPout1 TRI Charge Pump TRI-STATE Leakage Current PN10kHz PLL 1/f Noise at 10 kHz offset. Normalized to 1 GHz Output Frequency PN1Hz Normalized Phase Noise Contribution 0.5 V < VCPout < VCC - 0.5 V 10 5 PLL1_CP_GAIN = 350 µA -117 PLL1_CP_GAIN = 1550 µA -118 PLL1_CP_GAIN = 350 µA -221.5 PLL1_CP_GAIN = 1550 µA -223 % nA dBc/Hz dBc/Hz PLL2 Reference Input (OSCin) Specifications fOSCin (4) (5) 12 (2) 500 MHz SLEWOSCin PLL2 Reference Clock minimum slew rate on OSCin (3) 20% to 80% 0.15 VOSCin Input Voltage for OSCin or OSCin* AC coupled; Single-ended (Unused pin AC coupled to GND) 0.2 2.4 VIDOSCin Differential voltage swing Figure 2-2 AC coupled 0.2 1.55 |V| VSSOSCin 0.4 3.1 Vpp |VOSCin-offset| DC offset voltage between OSCin/OSCin* (OSCinX* - OSCinX) Each pin AC coupled fdoubler_max (1) (2) (3) PLL2 Reference Input Doubler input frequency (4) 0.5 V/ns 20 Vpp |mV| (5) EN_PLL2_REF_2X = 1 ; OSCin Duty Cycle 40% to 60% 155 MHz This parameter is programmable FOSCin maximum frequency assured by characterization. Production tested at 122.88 MHz. In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs. Assured by characterization. ATE tested at 122.88 MHz. The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units 40 MHz Crystal Oscillator Mode Specifications FXTAL Crystal Frequency Range Fundamental mode crystal ESR = 200 Ω (10 to 30 MHz) ESR = 125 Ω (30 to 40 MHz) CIN Input Capacitance of OSCin port -40 to +85 °C 10 1 pF PLL2 Phase Detector and Charge Pump Specifications fPD2 Phase Detector Frequency (1) 155 VCPout2=VCC/2, PLL2_CP_GAIN = 0 ICPoutSOURCE ICPoutSINK PLL2 Charge Pump Source Current (2) PLL2 Charge Pump Sink Current (2) MHz 100 VCPout2=VCC/2, PLL2_CP_GAIN = 1 400 VCPout2=VCC/2, PLL2_CP_GAIN = 2 1600 VCPout2=VCC/2, PLL2_CP_GAIN = 3 3200 VCPout2=VCC/2, PLL2_CP_GAIN = 0 -100 VCPout2=VCC/2, PLL2_CP_GAIN = 1 -400 VCPout2=VCC/2, PLL2_CP_GAIN = 2 -1600 VCPout2=VCC/2, PLL2_CP_GAIN = 3 -3200 µA µA ICPout2%MIS Charge Pump Sink/Source Mismatch VCPout2=VCC/2, TA = 25 °C 1 ICPout2VTUNE Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation 0.5 V < VCPout2 < VCC - 0.5 V TA = 25 °C 4 % ICPout2%TEMP Charge Pump Current vs. Temperature Variation 4 % ICPout2TRI PN10kHz PN1Hz (1) (2) (3) (4) Charge Pump Leakage PLL 1/f Noise at 10 kHz offset Normalized to 1 GHz Output Frequency 0.5 V < VCPout2 < VCC - 0.5 V (3) . Normalized Phase Noise Contribution (4) 10 % 10 PLL2_CP_GAIN = 400 µA -118 PLL2_CP_GAIN = 3200 µA -121 PLL2_CP_GAIN = 400 µA -222.5 PLL2_CP_GAIN = 3200 µA -227 nA dBc/Hz dBc/Hz Assured by characterization. ATE tested at 122.88 MHz. This parameter is programmable A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f). A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat(f) - 20log(N) - 10log(fPDX). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fPDX is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 13 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units Internal VCO Specifications LMK04826 VCO Tuning Range fVCO LMK04828 VCO Tuning Range LMK04826 Fine Tuning Sensitivity KVCO LMK04828 Fine Tuning Sensitivity |ΔTCL| (1) 14 Allowable Temperature Drift for Continuous Lock (1) VCO0 1840 1970 VCO1 2440 2505 VCO0 2370 2630 VCO1 2920 3080 LMK04826 VCO0 11 to 19 LMK04826 VCO1 8 to 11 LMK04828 VCO0 at 2457.6 MHz 17 to 27 LMK04828 VCO1 at 2949.12 MHz 17 to 23 After programming for lock, no changes to output configuration are permitted to assure continuous lock MHz MHz MHz/V MHz/V 125 °C Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the 0x168 register was last programmed with PLL2_FCAL_DIS = 0, and still have the part stay in lock. The action of programming the 0x168 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the appropriate register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units Noise Floor L(f)CLKout L(f)CLKout L(f)CLKout L(f)CLKout (1) (2) LMK04826, VCO0, Noise Floor 20 MHz Offset (1) LMK04826, VCO1, Noise Floor 20 MHz Offset (1) LMK04828, VCO0, Noise Floor 20 MHz Offset (2) LMK04828, VCO1, Noise Floor 20 MHz Offset (2) 245.76 MHz 245.76 MHz 245.76 MHz 245.76 MHz LVDS -158.1 HSDS 6 mA -159.7 HSDS 8 mA -160.8 HSDS 10 mA -161.3 LVPECL16 /w 240 Ω -161.8 LVPECL20 /w 240 Ω -162.0 LCPECL -161.7 LVDS -157.5 HSDS 6 mA -158.9 HSDS 8 mA -159.8 HSDS 10 mA -160.3 LVPECL16 /w 240 Ω -160.8 LVPECL20 /w 240 Ω -160.7 LCPECL -160.7 LVDS -156.3 HSDS 6 mA -158.4 HSDS 8 mA -159.3 dBc/Hz dBc/Hz HSDS 10 mA -158.9 LVPECL16 /w 240 Ω -161.6 LVPECL20 /w 240 Ω -162.5 LCPECL -162.1 LVDS -155.7 HSDS 6 mA -157.5 HSDS 8 mA -158.1 HSDS 10 mA -157.7 LVPECL16 /w 240 Ω -160.3 LVPECL20 /w 240 Ω -161.1 LCPECL -160.8 dBc/Hz dBc/Hz Data collected using a Prodyn BIB-100G balun. Loop filter for PLL2 is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 303 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 151 kHz, phase margin = 64 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0. Data collected using ADT2-1T+ balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 344 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 233 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 15 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units CLKout Closed Loop Phase Noise Specifications a Commercial Quality VCXO (1) Offset = 10 kHz -134.8 Offset = 100 kHz L(f)CLKout LMK04826B VCO0 SSB Phase Noise Offset = 1 MHz (2) Offset = 10 MHz -135.4 LVDS -148.2 HSDS 8 mA LVPECL16 /w 240 Ω -148.6 LVDS -157.8 HSDS 8 mA -160.4 LVPECL16 /w 240 Ω -161.5 Offset = 10 kHz -134.3 Offset = 100 kHz L(f)CLKout LMK04826B VCO1 SSB Phase Noise Offset = 1 MHz (2) Offset = 10 MHz (1) (2) 16 dBc/Hz -133.7 LVDS -152.5 HSDS 8 mA LVPECL16 /w 240 Ω -153.6 LVDS -157.3 HSDS 8 mA -159.6 LVPECL16 /w 240 Ω -160.5 dBc/Hz VCXO used is a 122.88 MHz Crystek CVHD-950-122.880. Data collected using a Prodyn BIB-100G balun. Loop filter for PLL2 is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 303 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 151 kHz, phase margin = 64 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units CLKout Closed Loop Phase Noise Specifications a Commercial Quality VCXO (continued) (1) L(f)CLKout LMK04828 VCO0 SSB Phase Noise Offset = 1 kHz -124.3 Offset = 10 kHz -134.7 Offset = 100 kHz -136.5 Offset = 1 MHz (2) Offset = 10 MHz L(f)CLKout LMK04828 VCO1 SSB Phase Noise -156.4 HSDS 8 mA -159.1 LVPECL16 /w 240 Ω -160.8 Offset = 1 kHz -124.2 Offset = 10 kHz -134.4 Offset = 100 kHz -135.2 Offset = 1 MHz (2) Offset = 10 MHz (1) (2) -148.4 LVDS -151.5 LVDS -159.9 HSDS 8 mA -155.8 LVPECL16 /w 240 Ω -158.1 dBc/Hz dBc/Hz VCXO used is a 122.88 MHz Crystek CVHD-950-122.880. Data collected using ADT2-1T+ balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 344 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 233 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 17 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units CLKout Closed Loop Jitter Specifications a Commercial Quality VCXO (1) LMK04826B, VCO0 fCLKout = 245.76 MHz Integrated RMS Jitter (2) JCLKout LMK04826, VCO1 fCLKout = 245.76 MHz Integrated RMS Jitter (2) (1) (2) 18 LVDS, BW = 100 Hz to 20 MHz 106 LVDS, BW = 12 kHz to 20 MHz 104 HSDS 8 mA, BW = 100 Hz to 20 MHz 99 HSDS 8 mA, BW = 12 kHz to 20 MHz 97 LVPECL16 /w 240 Ω, BW = 100 Hz to 20 MHz 99 LVPECL16 /w 240 Ω, BW = 12 kHz to 20 MHz 96 LCPECL /w 240 Ω, BW = 100 Hz to 20 MHz 100 LCPECL /w 240 Ω, BW = 12 kHz to 20 MHz 97 LVDS, BW = 100 Hz to 20 MHz 99 LVDS, BW = 12 kHz to 20 MHz 97 HSDS 8 mA, BW = 100 Hz to 20 MHz 92 HSDS 8 mA, BW = 12 kHz to 20 MHz 90 LVPECL16 /w 240 Ω, BW = 100 Hz to 20 MHz 91 LVPECL20 /w 240 Ω, BW = 12 kHz to 20 MHz 89 LCPECL /w 240 Ω, BW = 100 Hz to 20 MHz 92 LCPECL /w 240 Ω, BW = 12 kHz to 20 MHz 89 fs rms fs rms VCXO used is a 122.88 MHz Crystek CVHD-950-122.880. Data collected using a Prodyn BIB-100G balun. Loop filter for PLL2 is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 303 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 151 kHz, phase margin = 64 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units CLKout Closed Loop Jitter Specifications a Commercial Quality VCXO (continued) (1) LMK04828, VCO0 fCLKout = 245.76 MHz Integrated RMS Jitter (2) JCLKout LMK04828, VCO1 fCLKout = 245.76 MHz Integrated RMS Jitter (2) (1) (2) LVDS, BW = 100 Hz to 20 MHz 112 LVDS, BW = 12 kHz to 20 MHz 109 HSDS 8 mA, BW = 100 Hz to 20 MHz 102 HSDS 8 mA, BW = 12 kHz to 20 MHz 99 LVPECL16 /w 240 Ω, BW = 100 Hz to 20 MHz 98 LVPECL20 /w 240 Ω, BW = 12 kHz to 20 MHz 95 LCPECL /w 240 Ω, BW = 100 Hz to 20 MHz 96 LCPECL /w 240 Ω, BW = 12 kHz to 20 MHz 93 LVDS, BW = 100 Hz to 20 MHz 108 LVDS, BW = 12 kHz to 20 MHz 105 HSDS 8 mA, BW = 100 Hz to 20 MHz 98 HSDS 8 mA, BW = 12 kHz to 20 MHz 94 LVPECL16 /w 240 Ω, BW = 100 Hz to 20 MHz 93 LVPECL20 /w 240 Ω, BW = 12 kHz to 20 MHz 90 LCPECL /w 240 Ω, BW = 100 Hz to 20 MHz 91 LCPECL /w 240 Ω, BW = 12 kHz to 20 MHz 88 fs rms fs rms VCXO used is a 122.88 MHz Crystek CVHD-950-122.880. Data collected using ADT2-1T+ balun. Loop filter is C1 = 47 pF, C2 = 3.9 nF, R2 = 620 Ω, C3 = 10 pF, R3 = 200 Ω, C4 = 10 pF, R4 = 200 Ω, PLL1_CP = 450 µA, PLL2_CP = 3.2 mA.. VCO0 loop filter bandwidth = 344 kHz, phase margin = 73 degrees. VCO1 Loop filter loop bandwidth = 233 kHz, phase margin = 70 degrees. CLKoutX_Y_IDL = 1, CLKoutX_Y_ODL = 0. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 19 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units Default Power On Reset Clock Output Frequency fCLKout-startup Default output clock frequency at device power on (1) fOSCout OSCout Frequency LMK04826 235 LMK04828 315 MHz (2) 500 MHz Clock Skew and Delay |TSKEW| DCLKoutX to SDCLKoutY FCLK = 245.76 MHz, RL= 100 Ω AC coupled (3) Same pair, Same format (4) SDCLKoutY_MUX = 0 (Device Clock) Maximum DCLKoutX or SDCLKoutY to DCLKoutX or SDCLKoutY FCLK = 245.76 MHz, RL= 100 Ω AC coupled Any pair, Same format (4) SDCLKoutY_MUX = 0 (Device Clock) 50 SYSREF to Device Clock setup time base reference. See Section 5.5 to adjust SYSREF to Device Clock setup time as required. SDCLKoutY_MUX = 1 (SYSREF) SYSREF_DIV = 30 SYSREF_DDLY = 8 (global) SDCLKoutY_DDLY = 1 (2 cycles, local) DCLKoutX_MUX = 1 (Div+DCC+HS) DCLKoutX_DIV = 30 DCLKoutX_DDLY_CNTH = 7 DCLKoutX_DDLY_CNTL = 6 DCLKoutX_HS = 0 -80 ps Maximum analog delay frequency DCLKoutX_MUX = 4 1536 MHz 395 |mV| tsJESD204B fADLYmax 25 |ps| LVDS Clock Outputs (DCLKoutX, SDCLKoutY, and OSCout) VOD Differential Output Voltage ΔVOD Change in Magnitude of VOD for complementary output states VOS Output Offset Voltage ΔVOS Change in VOS for complementary output states (4) 20 1.125 1.25 60 mV 1.375 V 35 |mV| Output Rise Time 20% to 80%, RL = 100 Ω, 245.76 MHz Output Fall Time 80% to 20%, RL = 100 Ω ISA ISB Output short circuit current - single ended Single-ended output shorted to GND T = 25 °C -24 24 mA ISAB Output short circuit current differential Complimentary outputs tied together -12 12 mA TR / TF (1) (2) (3) -60 T = 25 °C, DC measurement AC coupled to receiver input RL = 100 Ω differential termination 180 ps OSCout will oscillate at start-up at the frequency of the VCXO attached to OSCin port. Assured by characterization. ATE tested at 122.88 MHz. Equal loading and identical clock output configuration on each clock output is required for specification to be valid. Specification not valid for delay mode. LVPECL uses 120 Ω emitter resistor, LVDS and HSDS uses 560 Ω shunt. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units 6 mA HSDS Clock Outputs (DCLKoutX and SDCLKoutY) VCC 1.05 VOH T = 25 °C, DC measurement Termination = 50 Ω to VCC - 1.42 V VOL VOD Differential Output Voltage ΔVOD Change in VOD for complementary output states VCC 1.64 590 -80 |mV| 80 mVpp 8 mA HSDS Clock Outputs (DCLKoutX and SDCLKoutY) TR / T F Output Rise Time 245.76 MHz, 20% to 80%, RL = 100 Ω Output Fall Time 245.76 MHz, 80% to 20%, RL = 100 Ω 170 VCC 1.26 VOH T = 25 °C, DC measurement Termination = 50 Ω to VCC - 1.64 V VOL VOD Differential Output Voltage ΔVOD Change in VOD for complementary output states ps VCC 2.06 800 -115 |mV| 115 mVpp 10 mA HSDS Clock Outputs (DCLKoutX and SDCLKoutY) VCC 0.99 VOH T = 25 °C, DC measurement Termination = 50 Ω to VCC - 1.43 V VOL VCC 1.97 VOD ΔVOD 980 Change in VOD for complementary output states -115 mVpp 115 ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B mVpp 21 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units LVPECL Clock Outputs (DCLKoutX and SDCLKoutY) 20% to 80% Output Rise TR / TF 80% to 20% Output Fall Time RL = 100 Ω, emitter resistors = 240 Ω to GND DCLKoutX_TYPE = 4 or 5 (1600 or 2000 mVpp) 150 ps VCC 1.04 V VCC 1.80 V 760 |mV| VCC 1.09 V VCC 2.05 V 960 |mV| 1.57 V 0.62 V 950 |mV| 1600 mVpp LVPECL Clock Outputs (DCLKoutX and SDCLKoutY) VOH Output High Voltage VOL Output Low Voltage VOD Output Voltage Figure 2-3 DC Measurement Termination = 50 Ω to VCC - 2.0 V 2000 mVpp LVPECL Clock Outputs (DCLKoutX and SDCLKoutY) VOH Output High Voltage VOL Output Low Voltage VOD Output Voltage Figure 2-3 VOH Output High Voltage VOL Output Low Voltage VOD Output Voltage Figure 2-3 DC Measurement Termination = 50 Ω to VCC - 2.3 V LCPECL Clock Outputs (DCLKoutX and SDCLKoutY) DC Measurement Termination = 50 Ω to 0.5 V LVCMOS Clock Outputs (OSCout) fCLKout (1) (2) 22 Maximum Frequency (1) 5 pF Load 250 MHz VOH Output High Voltage 1 mA Load VCC 0.1 V VOL Output Low Voltage 1 mA Load IOH Output High Current (Source) VCC = 3.3 V, VO = 1.65 V 28 mA IOL Output Low Current (Sink) VCC = 3.3 V, VO = 1.65 V 28 mA DUTYCLK Output Duty Cycle (2) VCC/2 to VCC/2, FCLK = 100 MHz, T = 25 °C 50 % TR Output Rise Time 20% to 80%, RL = 50 Ω, CL = 5 pF 400 ps TF Output Fall Time 80% to 20%, RL = 50 Ω, CL = 5 pF 400 ps 0.1 V Assured by characterization. ATE tested to 10 MHz. Assumes OSCin has 50% input duty cycle. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units Digital Outputs (CLKin_SELX, Status_LDX, and RESET/GPO) VOH High-Level Output Voltage IOH = -500 µA CLKin_SELX_TYPE = 3, 4, or 6 Status_LDX_TYPE = 3, 4, or 6 RESET_TYPE = 3, 4, or 6 VOL Low-Level Output Voltage IOL = 500 µA CLKin_SELX_TYPE = 3 or 4 Status_LDX_TYPE = 3 or 4 RESET_TYPE = 3 or 4 VCC 0.4 V 0.4 V Digital Output (SDIO) VOH High-Level Output Voltage IOH = -500 µA ; During SPI read. SDIO_RDBK_TYPE = 0 VOL Low-Level Output Voltage IOL = 500 µA ; During SPI read. SDIO_RDBK_TYPE = 0 or 1 VIH High-Level Input Voltage VIL Low-Level Input Voltage VCC 0.4 V 0.4 V VCC V 0.4 V Digital Inputs (CLKinX_SEL, RESET/GPO, SYNC, SCK, SDIO, or CS*) 1.2 Digital Inputs (CLKinX_SEL) IIH IIL High-Level Input Current VIH = VCC Low-Level Input Current VIL = 0 V CLKin_SELX_TYPE = 0, (High Impedance) -5 5 CLKin_SELX_TYPE = 1 (Pull-up) -5 5 CLKin_SELX_TYPE = 2 (Pull-down) 10 80 CLKin_SELX_TYPE = 0, (High Impedance) -5 5 CLKin_SELX_TYPE = 1 (Pull-up) -40 -5 CLKin_SELX_TYPE = 2 (Pull-down) -5 5 10 80 µA µA Digital Input (RESET/GPO) IIH High-Level Input Current VIH = VCC IIL Low-Level Input Current VIL = 0 V RESET_TYPE = 2 (Pull-down) RESET_TYPE = 0 (High Impedance) -5 5 RESET_TYPE = 1 (Pull-up) -40 -5 RESET_TYPE = 2 (Pull-down) -5 5 µA µA Digital Inputs (SYNC) IIH High-Level Input Current VIH = VCC IIL Low-Level Input Current VIL = 0 V 25 -5 5 µA Digital Inputs (SCK, SDIO, CS*) IIH High-Level Input Current VIH = VCC 5 5 µA IIL Low-Level Input Current VIL = 0 -5 5 µA ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 23 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Electrical Characteristics (continued) (3.15 V < VCC < 3.45 V, -40 °C < TA < 85 °C. Typical values at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions and are not assured.) Symbol Parameter Conditions Min Typ Max Units SPI Interface Timing (1) 2.5 tds Setup time for SDI edge to SCLK rising edge See SPI Input Timing 10 ns tdH Hold time for SDI edge from SCLK rising edge See SPI Input Timing 10 ns tSCLK Period of SCLK See SPI Input Timing 50 (1) ns tHIGH High width of SCLK See SPI Input Timing 25 ns tLOW Low width of SCLK See SPI Input Timing 25 ns tcs Setup time for CS* falling edge to SCLK rising edge See SPI Input Timing 10 ns tcH Hold time for CS* rising edge from SCLK rising edge See SPI Input Timing 30 ns tdv SCLK falling edge to valid read back data See SPI Input Timing 20 ns 20 MHz SPI Timing Diagram Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the SCK signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CS* signal should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming. SDIO (WRITE) R/W W1 tdS tdH tcS tHIGH W0 A12 to A0, D7 to D2 D1 D0 SCLK SDIO (Read) tcH tLOW tSCLK D7 to D2 tdV D1 D0 Data valid only during read CS* Figure 2-1. SPI Timing Diagram 24 ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 2.6 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Differential Voltage Measurement Terminology The differential voltage of a differential signal can be described by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to understand and discern between the two different definitions when used. The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and non-inverting signal. The symbol for this first measurement is typically VID or VOD depending on if an input or output voltage is being described. The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value can be calculated as twice the value of VOD as described in the first description. Figure 2-2 illustrates the two different definitions side-by-side for inputs and Figure 2-3 illustrates the two different definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the non-inverting and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured. VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP). VID Definition VOD Definition VSS Definition for Input VSS Definition for Output Non-Inverting Clock Non-Inverting Clock VA VA 2· VID VID 2· VOD VOD VB VB Inverting Clock Inverting Clock VID = | VA - VB | VSS = 2· VID VOD = | VA - VB | VSS = 2· VOD GND GND Figure 2-2. Two Different Definitions for Differential Input Signals Figure 2-3. Two Different Definitions for Differential Output Signals Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information. ELECTRICAL SPECIFICATIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 25 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com 3 TYPICAL PERFORMANCE CHARACTERISTICS NOTE These plots show performance at frequencies beyond what the part is ensured to operate at to give the user an idea of the capabilities of the part, but they do not imply any sort of ensured specification. 3.1 Clock Output AC Characteristics Figure 3-1. LMK04826B DCLKout2 Phase Noise VCO_MUX = 0 (VCO0) VCO0 = 1966.08 MHz DCLKout2_MUX = 0 (Divider) DCLKout2_DIV = 8 DCLKout2 Frequency = 245.76 MHz LVPECL20 /w 240 Ω emitter resistors CLKout2_3_IDL=1 CLKout2_3_ODL=0 Balun Prodyn BIB-100G PLL2 Loop Filter Bandwidth = 303 kHz PLL2 Phase Margin = 73° 26 Figure 3-2. LMK04826B DCLKout2 Phase Noise VCO_MUX = 1 (VCO1) VCO Frequency = 2457.6 MHz DCLKout2_MUX = 0 (Divider) DCLKout2_DIV = 10 DCLKout2 Frequency = 245.76 MHz LVPECL20 /w 240 Ω emitter resistors CLKout2_3_IDL=1 CLKout2_3_ODL=0 Balun Prodyn BIB-100G PLL2 Loop Filter Bandwidth = 151 kHz PLL2 Phase Margin = 64° TYPICAL PERFORMANCE CHARACTERISTICS Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Figure 3-3. LMK04828B DCLKout2 Phase Noise VCO_MUX = 0 (VCO0) VCO0 = 2457.6 MHz DCLKout2_MUX = 0 (Divider) DCLKout2_DIV = 10 DCLKout2 Frequency = 245.76 MHz LVPECL20 /w 240 Ω emitter resistors CLKout2_3_IDL=1 CLKout2_3_ODL=0 Balun ADT2-1T+ PLL2 Loop Filter Bandwidth = 344 kHz PLL2 Phase Margin = 73° Copyright © 2013, Texas Instruments Incorporated Figure 3-4. LMK04828B DCLKout2 Phase Noise VCO_MUX = 1 (VCO1) VCO Frequency = 2949.12 MHz DCLKout2_MUX = 0 (Divider) DCLKout2_DIV = 12 DCLKout2 Frequency = 245.76 MHz LVPECL20 /w 240 Ω emitter resistors CLKout2_3_IDL=1 CLKout2_3_ODL=0 Balun ADT2-1T+ PLL2 Loop Filter Bandwidth = 233 kHz PLL2 Phase Margin = 70° TYPICAL PERFORMANCE CHARACTERISTICS Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 27 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com 4 FEATURES 4.1 Jitter Cleaning The dual loop PLL architecture of the LMK04820 family provides the lowest jitter performance over a wide range of output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop bandwidth (typically 10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated along its path or from other circuits. This “cleaned” reference clock provides the reference input to PLL2. The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (typically 50 kHz to 200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or tunable crystal. Ultra low jitter is achieved by allowing the external VCXO or Crystal’s phase noise to dominate the final output phase noise at low offset frequencies and the internal VCO’s phase noise to dominate the final output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance. 4.2 JEDEC JESD204B Support The LMK04820 family provides support for JEDEC JESD204B. The LMK04820 will clock up to 7 JESD204B targets using 7 device clocks (DCLKoutX) and 7 SYSREF clocks (SDCLKoutY). Each device clock is grouped with a SYSREF clock. It is also possible to re-program SYSREF clocks to behave as extra device clocks for applications which have non-JESD204B clock requirements. 4.3 Three PLL1 Redundant Reference Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*, and CLKin2/CLKin2*) The LMK04820 family has up to three reference clock inputs for PLL1. They are CLKin0, CLKin1, and CLKin2. The active clock is chosen based on CLKin_SEL_MODE. Automatic or manual switching can occur between the inputs. CLKin0, CLKin1, and CLKin2 each have their own PLL1 R dividers. CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin). CLKin2 is shared for use as OSCout. To use powerdown OSCout, see Section 6.3.3.1. Fast manual switching between reference clocks is possible with a external pins CLKin_SEL0 and CLKin_SEL1. 4.4 VCXO/Crystal Buffered Output The LMK04820 family provides OSCout, which by default is a buffered copy of the PLL1 feedback/PLL2 reference input. This reference input is typically a low noise VCXO or Crystal. When using a VCXO, this output can be used to clock external devices such as microcontrollers, FPGAs, CPLDs, etc. before the LMK0482xB is programmed. The OSCout buffer output type is programmable to LVDS, LVPECL, or LVCMOS. The VCXO/Crystal buffered output can be synchronized to the VCO clock distribution outputs by using Cascaded 0-Delay Mode. The buffered output of VCXO/Crystal has deterministic phase relationship with CLKin. 28 FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 4.5 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Frequency Holdover The LMK04820 family supports holdover operation to keep the clock outputs on frequency with minimum drift when the reference is lost until a valid reference clock signal is re-established. 4.6 PLL2 Integrated Loop Filter Poles The LMK04820 family features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter response. The integrated programmable resistors and capacitors compliment external components mounted near the chip. These integrated components can be effectively disabled by programming the integrated resistors and capacitors to their minimum values. 4.7 Internal VCOs The LMK04820 family has two internal VCOs, selected by VCO_MUX. The output of the selected VCO is routed to the Clock Distribution Path. This same selection is also fed back to the PLL2 phase detector through a prescaler and N-divider. 4.8 External VCO Mode The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK04820 family. Using an external VCO reduces the number of available clock inputs by one. 4.9 Clock Distribution The LMK04820 family features a total of 14 PLL2 clock outputs driven from the internal or external VCO. All PLL2 clock outputs have programmable output types. They can be programmed to LVPECL, LVDS, or HSDS, or LCPECL. If OSCout is included in the total number of clock outputs the LMK04820 family is able to distribute, then up to 15 differential clocks. OSCout may be a buffered version of OSCin, DCLKout6, DCLKout8, or SYSREF. The following sections discuss specific features of the clock distribution channels that allow the user to control various aspects of the output clocks. 4.9.1 DEVICE CLOCK DIVIDER Each device clock, DCLKoutX, has a single clock output divider. The divider supports a divide range of 1 to 32 (even and odd) with 50% output duty cycle using duty cycle correction mode. The output of this divider may also be directed to SDCLKoutY, where Y = X + 1. 4.9.2 SYSREF CLOCK DIVIDER The SYSREF clocks, SDCLKoutY, all share a common divider. The divider supports a divide range of 8 to 8191 (even and odd). FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 29 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 4.9.3 www.ti.com DEVICE CLOCK DELAY The device clocks include both a analog and digital delay for phase adjustment of the clock outputs. The analog delay allows a nominal 25 ps step size and range from 0 to 575 ps of total delay. Enabling the analog delay adds a nominal 500 ps of delay in addition to the programmed value. The digital delay allows a group of outputs to be delayed from 4 to 32 VCO cycles. The delay step can be as small as half the period of the clock distribution path. e.g. 2 GHz VCO frequency results in 250 ps coarse tuning steps. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event. There are 2 different ways to use the digital delay. 1. Fixed Digital Delay - Allows all the outputs to have a known phase relationship upon a SYNC event. Typically performed at startup. 2. Dynamic Digital Delay - Allows the phase relationships of clocks to change while clocks continue to operate. 4.9.4 SYSREF DELAY The global SYSREF divider includes a digital delay block which allows a global phase shift with respect to the other clocks. Each local SYSREF clock output includes both an analog and additional local digital delay for unique phase adjustment of each SYSREF clock. The local analog delay allows for 150 ps steps. The local digital delay and SYSREF_HS bit allows the each individual SYSREF output to be delayed from, 1.5 to 11 VCO cycles. The delay step can be as small as half the period of the clock distribution path by using the DCLKoutX_HS bit. e.g. 2 GHz VCO frequency results in 250 ps coarse tuning steps. 4.9.5 GLITCHLESS HALF SHIFT and GLITCHLESS ANALOG DELAY The device clocks include a features to ensure glitchless operation of the half shift and analog delay operations when enabled. 4.9.6 PROGRAMMABLE OUTPUT FORMATS For increased flexibility all LMK04820 family device and SYSREF clock outputs, DCLKoutX and SDCLKoutY, can be programmed to an LVDS, HSDS, LVPECL, or LCPECL output type. The OSCout can be programmed to an LVDS, LVPECL, or LVCMOS output type. Any LVPECL output type can be programmed to 1600, or 2000 mVpp amplitude levels. The 2000 mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000 mVpp differential swing for compatibility with many data converters and is also known as 2VPECL. LCPECL allows for DC coupling SYSREF to low voltage converters. 4.9.7 CLOCK OUTPUT SYNCHRONIZATION Using the SYNC input causes all active clock outputs to share a rising edge as programmed by fixed digital delay. The SYNC event must occur for digital delay values to take effect. 30 FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 4.10 0-Delay The LMK04820 family supports two types of 0-delay. 1. Cascaded 0-delay 2. Nested 0-delay Cascaded 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL2 input clock (OSCin) to the phase of a clock selected by the feedback mux. The 0-delay feedback may performed with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as selected by the FB_MUX. Because OSCin has a fixed deterministic phase relationship to the feedback clock, OSCout will also have a fixed deterministic phase relationship to the feedback clock. In this mode PLL1 input clock (CLKinX) also has a fixed deterministic phase relationship to PLL2 input clock (OSCin), this results in a fixed deterministic phase relationship between all clocks from CLKinX to the clock outputs. Nested 0-delay mode establishes a fixed deterministic phase relationship of the phase of the PLL1 input clock (CLKinX) to the phase of a clock selected by the feedback mux. The 0-delay feedback may performed with an internal feedback from CLKout6, CLKout8, SYSREF, or with an external feedback loop into the FBCLKin port as selected by the FB_MUX. Without using 0-delay mode there will be n possible fixed phase relationships from clock input to clock output depending on the clock output divide value. Using an external 0-delay feedback reduces the number of available clock inputs by one. 4.11 Status Pins The LMK0482xB provides status pins which can be monitored for feedback or in some cases used for input depending upon device programming. For example: • The CLKin_SEL0 pin may indicate the LOS (loss-of-signal) for CLKin0. • The CLKin_SEL1 pin may be an input for selecting the active clock input. • The Status_LD1 pin may indicate if the device is locked. • The Status_LD2 pin may indicate if PLL2 is locked. The status pins can be programmed to a variety of other outputs including PLL divider outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, etc. Refer to the programming section of this datasheet for more information. FEATURES Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 31 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com 5 FUNCTIONAL DESCRIPTIONS 5.1 Modes Of Operation The following section describes the settings to enable various modes of operation for the LMK04820 family. See Section 1.5 for visual diagrams of each mode. 5.2 SYNC/SYSREF The SYNC and SYSREF signals share the same clocking path. To properly use SYNC and/or SYSREF for JESD204B it is important to understand the SYNC/SYSREF system. Figure 5-1 illustrates the detailed diagram of a clock output block with SYNC circuitry included.Figure 5-2 illustrates the interconnects and highlights some important registers used in controlling the device for SYNC/SYSREF purposes. CLKoutX_Y_PD DCLKout6/8 to FB_MUX DCLKoutX_ADLY_PD VCO DDLY (4 to 32) DCLKoutX_HSg_PD Divider (1 to 32) DCLKoutX_ADLYg_PD HS/ DCC DCLKout0, 2, 4, 8, 10, 12 SDCLKoutY _POL DCLKoutX_DDLY_PD DCLKoutX _MUX DCLKoutX _ADLY _MUX DDDLYdX_EN DCLKoutX_ FMT Analog DLY CLKoutX_Y_ODL SYNC_ 1SHOT_EN CLKoutX_Y_IDL SYSREF_GBL_PD SDCLKoutY_DIS_MODE One Shot SYNC_ DISX SDCLKoutY_PD SYSREF/SYNC Legend SPI Register SDCLKoutY _POL Digital DLY SYSREF/SYNC Clock VCO/Distribution Clock Half Step Analog DLY SDCLKoutY _MUX SDCLKoutY _ADLY_EN SDCLKoutY_ FMT SDCLKout1, 3, 5, 9, 11, 13 SYSREF_CLR Figure 5-1. Device and SYSREF Clock Output Block 32 FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com CLKin0 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 CLKin0 _OUT _MUX SPI Register: SYNC_EN Must be set to enable any SYNC/SYSREF functionality PLL1 SYNC_PLL1_DLD Note: The SYNC/CLKin0 input is reclocked to the Dist Path PLL1_DLD SYNC_PLL2_DLD SYSREF_REQ_EN PLL2_DLD SYNC SYNC _MODE SYNC _POL SYSREF _MUX D PULSOR MODE SYSREF_PULSE_CNT VCO0 VCO1 VCO Dist. Path SYSREF _MUX DDLY External VCO SYSREF Divider SYNC/ SYSREF OSCout DCLKout6 SYNC_ DISSYSREF CLKin1 _OUT _MUX SYSREF_PLSR_PD SYSREF_PD SYSREF_DDLY_PD CLKin1 Pulsor DCLKout8 OSCin FB_MUX OSCout _MUX CLKin1 FB_MUX PLL1 DCLKout0, 2, 4, 8, 10, 12 VCO Frequency DDLY (4 to 32) Divider (1 to 32) Analog DLY DCC Output Buffer Digital DLY Analog DLY Output Buffer SYNC_ DISX SYSREF/SYNC Legend SYSREF_CLR SYSREF/SYNC Clock VCO/Distribution Clock SPI Register SDCLKout1, 3, 5, 9, 11, 13 Figure 5-2. SYNC/SYSREF Clocking Paths FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 33 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com To reset or synchronize a divider, the following conditions must be met: 1. SYNC_EN must be set. This ensures proper operation of the SYNC circuitry. 2. SYSREF_MUX and SYNC_MODE must be set to a proper combination to provide a valid SYNC/SYSREF signal. – If SYSREF block is being used, the SYSREF_PD bit must be clear. – If the SYSREF Pulsor is being used, the SYSREF_PLSR_PD bit must be clear. 3. SYSREF_DDLY_PD and DCLKoutX_DDLY_PD bits must be clear to power up the digital delay circuitry during SYNC as use requires. 4. The SYNC_DISX bit must be clear to allow SYNC/SYSREF signal to divider circuit. The SYSREF_MUX register selects the SYNC source which resets the SYSREF/CLKoutX dividers provided the corresponding SYNC_DISX bit is clear. 5. Other bits which impact the operation of SYNC such as SYNC_1SHOT_EN may be set as desired. Table 5-1 illustrates the some possible combinations of SYSREF_MUX and SYNC_MODE. Table 5-1. Some Possible SYNC Configurations Name SYNC_MODE SYSREF_MUX Other Description SYNC Disabled 0 0 CLKin0_OUT_MUX ≠ 0 No SYNC will occur. Pin or SPI SYNC 1 0 CLKin0_OUT_MUX ≠ 0 Basic SYNC functionality, SYNC pin polarity is selected by SYNC_POL. To achieve SYNC through SPI, toggle the SYNC_POL bit. Differential input SYNC 0 or 1 0 or 1 CLKin0_OUT_MUX = 0 Differential CLKin0 now operates as SYNC input. JESD204B Pulsor on pin transition. 2 2 SYSREF_PULSE_CNT sets pulse count Produce SYSREF_PULSE_CNT programmed number of pulses on pin transition. SYNC_POL can be used to cause SYNC via SPI. JESD204B Pulsor on SPI programming. 3 2 SYSREF_PULSE_CNT sets pulse count Programming SYSREF_PULSE_CNT register starts sending the number of pulses. 1 SYSREF operational, SYSREF Divider as required for training frame size. Allows precise SYNC for n-bit frame training patterns for non-JESD converters such as LM97600. 2 SYSREF_REQ_EN = 1 Pulsor powered up When SYNC pin is asserted, continuous SYSERF pulses occur. Turning on and off of the pulses is synchronized to prevent runt pulses from occurring on SYSREF. 3 SYSREF_PD = 0 SYSREF_DDLY_PD = 0 SYSREF_PLSR_PD = 1 SDCLKoutY_PD as required per output. Continuous SYSREF signal. Re-clocked SYNC External SYSREF request Continuous SYSREF 34 1 0 X FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 5.3 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 JEDEC JESD204B 5.3.1 HOW TO ENABLE SYSREF Table 5-2 summarizes the bits needed to make SYSREF functionality operational. Table 5-2. SYSREF Bits Registe r Field Value 0x140 SYSREF_PD 0 Must be clear, power-up SYSREF circuitry. 0x140 SYSREF_DDLY_ PD 0 Must be clear to power-up digital delay circuitry during initial SYNC to ensure deterministic timing. 0x143 SYNC_EN 1 Must be set, enable SYNC. 0x143 SYSREF_CLR 1→0 Description Do not hold local SYSREF DDLY block in reset except at start. Anytime SYSREF_PD = 1 because of user programming or device RESET, it is necessary to set SYSREF_CLR for 15 VCO clock cycles to clear the local SYSREF digital delay. Once cleared, SYSREF_CLR must be cleared to allow SYSREF to operate. Enabling JESD204B operation involves synchronizing all the clock dividers with the SYSREF divder, then configuring the actual SYSREF functionality. 5.3.1.1 Setup of SYSREF Example The following procedure is a programming example for a system which is to operate with a 3000 MHz VCO frequency. Use DCLKout0 and DCLKout2 to drive converters at 1500 MHz. Use DCLKout4 to drive an FPGA at 150 MHz. Synchronize the converters and FPGA using a two SYSREF pulses at 10 MHz. 1. Program registers 0x000 to 0x1fff as desired. Key to prepare for SYSREF operations: (a) Prepare for manual SYNC: SYNC_POL = 0, SYNC_MODE = 1, SYSREF_MUX = 0 (b) Setup output dividers as per example: DCLKout0_1_DIV and DCLKout2_3_DIV = 2 for frequency of 1500 MHz. DCLKout4_5_DIV for frequency of 150 MHz. (c) Setup output dividers as per example: SYSREF_DIV = 300 for 10 MHz SYSREF (d) Setup SYSREF: SYSREF_PD = 0, SYSREF_DDLY_PD = 0, SYNC_EN = 1, SYSREF_PLSR_PD = 0, SYSREF_PULSE_CNT = 1 (2 pulses) (e) Clear Local SYSREF DDLY: SYSREF_CLR = 1. 2. Establish deterministic phase relationships between SYSREF and Device Clock for JESD204B: (a) Set device clock and sysref divider digital delays: DCLKout0_1_DDLY, DCLKout2_3_DDLY, DCLKout4_5_DDLY, SYSREF_DDLY. (b) Set device clock digital delay half steps: DCLKout0_HS, DCLKout2_HS, DCLKout4_HS. (c) Set SYSREF clock digital delay as required to achieve known phase relationships: SDCLKout1_DDLY, SDCLKout3_DDLY, SDCLKout5_DDLY. (d) To allow SYNC to effect dividers: SYNC_DIS0 = 0, SYNC_DIS2 = 0, SYNC_DIS4 = 0, SYNC_DISSYSREF = 0 (e) Perform SYNC by toggling SYNC_POL = 1 then SYNC_POL = 0. 3. Now that dividers are synchronized, disable SYNC from resetting these dividers. It is not desired for SYSREF to reset it's own divider or the dividers of the output clocks. (a) Prevent SYNC (SYSREF) from affecting dividers: SYNC_DIS0 = 1, SYNC_DIS2 = 1, SYNC_DIS4 = 1, SYNC_DISSYSREF = 1. 4. Release reset of local SYSREF digital delay. (a) SYSREF_CLR = 0. Note this bit needs to be set for only 15 VCO clocks after SYSREF_PD = 0. 5. Set SYSREF operation. (a) Allow pin SYNC event to start pulsor: SYNC_MODE = 2. (b) Select pulsor as SYSREF signal: SYSREF_MUX = 2. 6. Complete! Now asserting the SYNC pin, or toggling SYNC_POL will result in a series of 2 SYSREF pulses. FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 35 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 5.3.1.2 www.ti.com SYSREF_CLR The local digital delay of the SDCLKout is implemented as a shift buffer. To ensure no un-wanted pulses occur at this SYSREF output at startup, when using SYSREF, requires clearing the buffers by setting SYSREF_CLR = 1 for 15 VCO clock cycles. After a reset, this bit is set, so it must be cleared before SYSREF output is used. 5.3.2 SYSREF MODES 5.3.2.1 SYSREF Pulsor This mode allows for the output of 1, 2, 4, or 8 SYSREF pulses for every SYNC pin event or SPI programming. This implements the gapped periodic functionality of the JEDEC JESD204B specification. When in SYSREF Pulsor mode, programming the field SYSREF_PULSE_CNT in register 0x13E will result in the pulsor sending the programmed number of pulses. 5.3.2.2 Continuous SYSREF This mode allows for continuous output of the SYSREF clock. Continuous operation of SYSREF is not recommended due to crosstalk from the SYSREF clock to device clock. JESD204B is designed to operate with a single burst of pulses to initialize the system at startup, after which it is theoretically not required to send another SYSREF since the system will continue to operate with deterministic phases. If continuous operation of SYSREF is required, consider using a SYSREF output from a non-adjacent output or SYSREF from the OSCout pin to minimize crosstalk. 5.3.2.3 SYSREF Request This mode allows an external source to synchronously turn on or off a continuous stream of SYSREF pulses using the SYNC/SYSREF_REQ pin. Setup the mode by programming SYSREF_REQ_EN and SYSREF_MUX = 2 (Pulsor). The pulsor does not need to be powered for this mode of operation. When the SYSREF_REQ pin is asserted, the SYSREF_MUX will synchronously be set to continuous mode providing continuous pulses at the SYSREF frequency until the SYSREF_REQ pin is un-asserted and the final SYSREF pulse will complete sending synchronously. 36 FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 5.4 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Digital Delay Digital (coarse) delay allows a group of outputs to be delayed by 4 to 32 VCO cycles. The delay step can be as small as half the period of the VCO cycle by using the DCLKoutX_HS bit. There are two different ways to use the digital delay: 1. Fixed digital delay 2. Dynamic digital delay In both delay modes, the regular clock divider is substituted with an alternative divide value. The substitute divide value consists of two values, DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL. The minimum _CNTH/_CNTL value is 2 and the maximum _CNTH/_CNTL value is 16. This will result in a minimum alternative divide value of 4 and a maximum of 32. 5.4.1 FIXED DIGITAL DELAY Fixed digital delay value takes effect on the clock outputs after a SYNC event. As such, the outputs will be LOW for a while during the SYNC event. Applications that cannot accept clock breakup when adjusting digital delay should use dynamic digital delay. 5.4.1.1 Fixed Digital Delay Example Assuming the device already has the following initial configurations, and the application should delay DCLKout2 by one VCO cycle compared to DCLKout0. • VCO frequency = 2949.12 MHz • DCLKout0 = 368.64 MHz (DCLKout0_DIV = 8) • DCLKout2 = 368.64 MHz (DCLKout2_DIV = 8) The following steps should be followed 1. Set DCLKout0_DDLY_CNTH = 4 and DCLKout2_DDLY_CNTH = 4. First part of delay for each clock. 2. Set DCLKout0_DDLY_CNTL = 4 and DCLKout2_DDLY_CNTL = 5. Second part of delay for each clock. 3. Set DCLKout2_DDLY_PD = 0 and DCLKout2_DDLY_PD = 0. Power up the digital delay circuit. 4. Set SYNC_DIS0 = 0 and SYNC_DIS2 = 0. Allow the output to be synchronized. 5. Perform SYNC by asserting, then unasserting SYNC. Either by using SYNC_POL bit or the SYNC pin. 6. Now that the SYNC is complete, to save power it is allowable to power down DCLKout2_DDLY_PD = 0 and/or DCLKout2_DDLY_PD = 1. 7. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 1. To prevent the output from being synchronized, very important for steady state operation when using JESD204B. DCLKout0 368.64 MHz No CLKout during SYNC DCLKout2 368.64 MHz SYNC event 1 VCO cycle delay Figure 5-3. Fixed Digital Delay Example FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 37 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 5.4.2 www.ti.com DYNAMIC DIGITAL DELAY Dynamic digital delay allows the phase of clocks to be changed with respect to each other with little impact to the clock signal. This is accomplished by substituting the regular clock divider with an alternate divide value for one cycle. This substitution will occur a number of times equal to the value programmed into the DDLYd_STEP_CNT field for all outputs with DDLYdX_EN = 1. • By programming a larger alternate divider (delay) value, the phase of the adjusted outputs will be delayed with respect to the other clocks. • By programming a smaller alternate divider (delay) value, the phase of the adjusted output will advanced with respect to the other clocks. The following table shows the recommended DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL alternate divide setting for delay by one VCO cycle. The clock will output high during the DCLKoutX_DDLY_CNTH time to permit a continuous output clock. The clock output will be low during the DCLKoutX_DDLY_CNTL time. Table 5-3. Recommended DCLKoutX_DDLY_CNTH/_CNTL values for delay by one VCO cycle Clock Divider _CNTH _CNTL Clock Divider _CNTH 2 2 3 17 9 9 3 3 4 18 9 10 4 2 3 19 10 10 5 3 3 20 10 11 6 3 4 21 11 11 7 4 4 22 11 12 8 4 5 23 12 12 9 5 5 24 12 13 10 5 6 25 13 13 11 6 6 26 13 14 12 6 7 27 14 14 13 7 7 28 14 15 14 7 8 29 15 15 15 8 8 30 15 16 (1) 16 (1) 38 8 9 31 16 (1) _CNTL 16 (1) To achieve _CNTH/_CNTL value of 16, 0 must be programmed into the _CNTH/_CNTL field. FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 5.4.3 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 SINGLE AND MULTIPLE DYNAMIC DIGITAL DELAY EXAMPLE In this example two separate adjustments will be made to the device clocks. In the first adjustment a single delay of 1 VCO cycle will occur between DCLKout2 and DCLKout0. In the second adjustment two delays of 1 VCO cycle will occur between DCLKout2 and DCLKout0. At this point in the example, DCLKout2 will be delayed 3 VCO cycles behind DCLKout0. Assuming the device already has the following initial configurations: • VCO frequency: 2949.12 MHz • DCLKout0 = 368.64 MHz, DCLKout0_DIV = 8 • DCLKout2 = 368.64 MHz, DCLKout2_DIV = 8 The following steps illustrate the example above: 1. Set DCLKout2_DDLY_CNTH = 4. First part of delay for DCLKout2. 2. Set DCLKout2_DDLY_CNTL = 5. Second part of delay for DCLKout2. 3. Set DCLKout2_DDLY_PD = 0. Enable the digital delay for DCLKout2. 4. Set DDLYd2_EN = 1. Enable dynamic digital delay for DCLKout2. 5. Set SYNC_DIS0 = 1 and SYNC_DIS2 = 0. Sync should be disabled to DCLKout0, but not DCLKout2. 6. Set SYNC_MODE = 3. Enable SYNC event from SPI write to DDLYd_STEP_CNT's register. 7. Set SYNC_MODE = 2, SYSREF_MUX = 2. Setup proper SYNC settings. 8. Set DDLYd_STEP_CNT = 1. This begins the first adjustment. Before step 7 DCLKout2 clock edge is aligned with DCLKout0. After step 7, DCLKout2 counts four VCO cycles high and then five VCO cycles low as programmed by DCLKout2_DDLY_CNTH and DCLKout2_DDLY_CNTL fieldss, effectively delaying DCLKout2 by one VCO cycle with respect to DCLKout0. This is the first adjustment. 8. Set DDLYd_STEP_CNT = 2. This begins the second adjustment. Before step 8, DCLKout2 clock edge was delayed 1 VCO cycle from DCLKout0. After step 8, DCLKout2 counts four VCO cycles high and then five VCO cycles low as programmed by DCLKout2_DDLY_CNTH and DCLKout2_DDLY_CNTL fields twice, delaying DCLKout2 by two VCO cycles with respect to DCLKout0. This is the second adjustment. FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 39 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com VCO 2949.12 MHz DCLKout0 368.64 MHz DCLKout2 368.64 MHz First Adjustment CNTH = 4 CNTL = 5 DCLKout2 368.64 MHz Second Adjustment CNTH = 4 CNTL = 5 CNTH = 4 CNTL = 5 Figure 5-4. Single and Multiple Adjustment Dynamic Digital Delay Example 40 FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 5.5 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 SYSREF to Device Clock Alignment To ensure proper JESD204B operation, the timing relationship between the SYSREF and the Device clock must be adjusted for optimum setup and hold time. The tsJESD204B defines the time between SYSREF and Device Clock for a specific condition of SYSREF divider and Device Clock digital delay. From this point, the SYSREF_DDLY. SDCLKoutY_DDLY, DCLKoutX_DDLY_CNTH, DCLKoutDDLY_CNTL, and DCLKoutX_MUX, SDCKLoutX_ADLY, etc. can be adjusted to provide the required setup and hold time between SYSREF and Device Clock. It is possible to digitally adjust the SYSREF up to 20 VCO cycles before the SYSREF. So for example with a 2949.12 MHz VCO frequency, tsJESD204B + 20 * (1/VCO Frequency) = -80 ps + 20 * (1/2949.12 MHz) = 6.7 ns. FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 41 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 5.6 www.ti.com Input Clock Switching Manual, pin select, and automatic are three different kinds clock input switching modes can be set with the CLKin_SEL_MODE register. Below is information about how the active input clock is selected and what causes a switching event in the various clock input selection modes. 5.6.1 INPUT CLOCK SWITCHING - MANUAL MODE When CLKin_SEL_MODE is 0, 1, or 2 then CLKin0, CLKin1, or CLKin2 respectively is always selected as the active input clock. Manual mode will also override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is disabled with EN_CLKinX = 0. If holdover is entered in this mode, then the device will re-lock to the selected CLKin upon holdover exit. 5.6.2 INPUT CLOCK SWITCHING - PIN SELECT MODE When CLKin_SEL_MODE is 3, the pins CLKin_SEL0 and CLKin_SEL1 select which clock input is active. Configuring Pin Select Mode The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input for pin select mode. The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input for pin select mode. If the CLKin_SELX_TYPE is set as output, the pin input value is considered "Low." The polarity of CLKin_SEL0 and CLKin_SEL1 input pins can be inverted with the CLKin_SEL_INV bit. Table 5-4 defines which input clock is active depending on CLKin_SEL0 and CLKin_SEL1 state. Table 5-4. Active Clock Input - Pin Select Mode, CLKin_SEL_INV = 0 Pin CLKin_SEL1 Pin CLKin_SEL0 Active Clock Low Low CLKin0 Low High CLKin1 High Low CLKin2 High High Holdover The pin select mode will override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX = 1) that could be switched to. 5.6.3 INPUT CLOCK SWITCHING - AUTOMATIC MODE When CLKin_SEL_MODE is 4, the active clock is selected in round-robin order of enabled clock inputs starting upon an input clock switch event. The switching order of the clocks is CLKin0 → CLKin1 → CLKin2 → CLKin0, etc. For a clock input to be eligible to be switched through, it must be enabled using EN_CLKinX. Starting Active Clock Upon programming this mode, the currently active clock remains active if PLL1 lock detect is high. To ensure a particular clock input is the active clock when starting this mode, program CLKin_SEL_MODE to the manual mode which selects the desired clock input (CLKin0, 1, or 2). Wait for PLL1 to lock PLL1_DLD = 1, then select this mode with CLKin_SEL_MODE = 4. 42 FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 5.7 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Digital Lock Detect Both PLL1 and PLL2 support digital lock detect. Digital lock detect compares the phase between the reference path (R) and the feedback path (N) of the PLL. When the time error, which is phase error, between the two signals is less than a specified window size (ε) a lock detect count increments. When the lock detect count reaches a user specified value, PLL1_DLD_CNT or PLL2_DLD_CNT, lock detect is asserted true. Once digital lock detect is true, a single phase comparison outside the specified window will cause digital lock detect to be asserted false. This is illustrated in Figure 5-5. NO START PLLX Lock Detected = False Lock Count = 0 YES YES Phase Error < g Increment PLLX Lock Count PLLX Lock Count = PLLX_DLD_CNT YES PLLX Lock Detected = True Phase Error < g NO NO Figure 5-5. Digital Lock Detect Flowchart This incremental lock detect count feature functions as a digital filter to ensure that lock detect isn't asserted for only a brief time when the phases of R and N are within the specified tolerance for only a brief time during initial phase lock. See Section 7.1 for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect. The digital lock detect signal can be monitored on the Status_LD1 or Status_LD2 pin. The pin may be programmed to output the status of lock detect for PLL1, PLL2, or both PLL1 and PLL2. 5.7.1 CALCULATING DIGITAL LOCK DETECT FREQUENCY ACCURACY See Section 7.1 for more detailed information on programming the registers to achieve a specified frequency accuracy in ppm with lock detect. The digital lock detect feature can also be used with holdover to automatically exit holdover mode. See Section 5.8.3 for more info. FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 43 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 5.8 www.ti.com Holdover Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed tuning voltage is set on CPout1 to operate PLL1 in open loop. 5.8.1 ENABLE HOLDOVER Program HOLDOVER_EN = 1 to enable holdover mode. Holdover mode can be configured to set the CPout1 voltage upon holdover entry to a fixed user defined voltage or a tracked voltage. 5.8.1.1 Fixed (Manual) CPout1 Holdover Mode By programming MAN_DAC_EN = 1, then the MAN_DAC value will be set on the CPout1 pin during holdover. The user can optionally enable CPout1 voltage tracking (TRACK_EN = 1), read back the tracked DAC value, then re-program MAN_DAC value to a user desired value based on information from previous DAC read backs. This allows the most user control over the holdover CPout1 voltage, but also requires more user intervention. 5.8.1.2 Tracked CPout1 Holdover Mode By programming MAN_DAC_EN = 0 and TRACK_EN = 1, the tracked voltage of CPout1 will be set on the CPout1 pin during holdover. When the DAC has acquired the current CPout1 voltage, the "DAC_Locked" signal is set which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or PLL2_LD_MUX respectively. Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector frequency divided by (DAC_CLK_MULT * DAC_CLK_CNTR). The DAC update rate should be programmed for ≤ 100 kHz to ensure DAC holdover accuracy. The ability to program slow DAC update rates, for example one DAC update per 4.08 seconds when using 1024 kHz PLL1 phase detector frequency with DAC_CLK_MULT = 16,384 and DAC_CLK_CNTR = 255, allows the device to "look-back" and set CPout1 at at previous "good" CPout1 tuning voltage values before the event which caused holdover to occurre. The current voltage of DAC value can be read back using RB_DAC_VALUE, see Section 6.3.9.7. 5.8.2 DURING HOLDOVER PLL1 is run in open loop mode. • PLL1 charge pump is set to TRI-STATE. • PLL1 DLD will be un-asserted. • The HOLDOVER status is asserted • During holdover If PLL2 was locked prior to entry of holdover mode, PLL2 DLD will continue to be asserted. • CPout1 voltage will be set to: – a voltage set in the MAN_DAC register (MAN_DAC_EN = 1). – a voltage determined to be the last valid CPout1 voltage (MAN_DAC_EN = 0). • PLL1 will attempt to lock with the active clock input. The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the PLL1_DLD_MUX or PLL2_DLD_MUX register to "Holdover Status." 44 FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 5.8.3 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 EXITING HOLDOVER Holdover mode can be exited in one of two ways. • Manually, by programming the device from the host. • Automatically, By a clock operating within a specified ppm of the current PLL1 frequency on the active clock input. 5.8.4 HOLDOVER FREQUENCY ACCURACY AND DAC PERFORMANCE When in holdover mode PLL1 will run in open loop and the DAC will set the CPout1 voltage. If Fixed CPout1 mode is used, then the output of the DAC will be a voltage dependant upon the MAN_DAC register. If Tracked CPout1 mode is used, then the output of the DAC will be the voltage at the CPout1 pin before holdover mode was entered. When using Tracked mode and MAN_DAC_EN = 1, during holdover the DAC value is loaded with the programmed value in MAN_DAC, not the tracked value. When in Tracked CPout1 mode the DAC has a worst case tracking error of ±2 LSBs once PLL1 tuning voltage is acquired. The step size is approximately 3.2 mV, therefore the VCXO frequency error during holdover mode caused by the DAC tracking accuracy is ±6.4 mV * Kv. Where Kv is the tuning sensitivity of the VCXO in use. Therefore the accuracy of the system when in holdover mode in ppm is: Holdover accuracy (ppm) = ± 6.4 mV × Kv × 1e6 VCXO Frequency Example: consider a system with a 19.2 MHz clock input, a 153.6 MHz VCXO with a Kv of 17 kHz/V. The accuracy of the system in holdover in ppm is: ±0.71 ppm = ±6.4 mV * 17 kHz/V * 1e6 / 153.6 MHz It is important to account for this frequency error when determining the allowable frequency error window to cause holdover mode to exit. 5.8.5 HOLDOVER MODE - AUTOMATIC EXIT OF HOLDOVER The LMK048xx device can be programmed to automatically exit holdover mode when the accuracy of the frequency on the active clock input achieves a specified accuracy. The programmable variables include PLL1_WND_SIZE and DLD_HOLD_CNT. See Section 7.1 to calculate the register values to cause holdover to automatically exit upon reference signal recovery to within a user specified ppm error of the holdover frequency. It is possible for the time to exit holdover to vary because the condition for automatic holdover exit is for the reference and feedback signals to have a time/phase error less than a programmable value. Because it is possible for two clock signals to be very close in frequency but not close in phase, it may take a long time for the phases of the clocks to align themselves within the allowable time/phase error before holdover exits. FUNCTIONAL DESCRIPTIONS Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 45 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com 6 GENERAL PROGRAMMING INFORMATION LMK04820 family devices are programmed using 24-bit registers. Each register consists of a 1-bit command field (R/W), a 2-bit multi-byte field (W1, W0), a 13-bit address field (A12 to A0) and a 8-bit data field (D7 to D0). The contents of each register is clocked in MSB first (R/W), and the LSB (D0) last. During programming, the CS* signal is held low. The serial data is clocked in on the rising edge of the SCK signal. After the LSB is clocked in the CS* signal goes high to latch the contents into the shift register. It is recommended to program registers in numeric order, for example 0x000 to 0x1FFF to achieve proper device operation. Each register consists of one more more fields which control the device functionality. See electrical characteristics and Figure 2-1 for timing details. W1 and W0 shall be written as 0. 6.1 Recommended Programming Sequence Registers are programmed in numeric order with 0x000 being the first and 0x1FFF being the last register programmed. The recommended programming sequence from POR involves: 1. Programming register 0x000 with RESET = 1. 2. Programming registers in numeric order from 0x000 to 0x165. 3. Programming registers 0x17C and 0x17D. 4. Programming registers 0x166 to 0x1FFF. Program register 0x17C (OPT_REG_1) and 0x17D (OPT_REG_2) before programming PLL2 in registers: 0x166, 0x167, and 0x168 to optimize VCO1 phase noise performance over temperature. 6.1.1 SPI LOCK When writing to SPI_LOCK, registers 0x1FFD, 0x1FFE, and 0x1FFF should all always be written sequentially. 6.1.2 SYSREF_CLR When using SYSREF output, SYSREF local digital delay block should be cleared using SYSREF_CLR bit. See Section 5.3.1.2 for more info. 46 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.2 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Register Map Table 6-1 provides the register map for device programming. Any register can be read from the same data address it is written to. Table 6-1. Register Map Address [11:0] Data 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 POWER DOWN 0x000 RESET 0 0 SPI_3WIRE _DIS 0x002 0 0 0 0 0x003 ID_DEVICE_TYPE 0x004 ID_PROD[15:8] 0x005 ID_PROD[7:0] 0x006 ID_MASKREV 0x00C ID_VNDR[15:8] 0x00D 0x100 ID_VNDR[7:0] 0 0x101 CLKout0_1 _ODL CLKout0_1 _IDL DCLKout0_DIV DCLKout0_DDLY_CNTH 0x103 DCLKout0_DDLY_CNTL DCLKout0_ ADLY_MUX DCLKout0_ADLY 0x104 0 DCLKout0 _HS SDCLKout1 _MUX 0x105 0 0 0 SDCLKout1_ ADLY_EN 0x106 DCLKout0 _ DDLY_PD DCLKout0 _ HSg_PD DCLKout0 _ ADLYg_PD DCLKout0 _ADLY _PD 0x107 SDCLKout1 _POL 0x108 0 0x109 CLKout0_1 _PD CLKout2_3 _IDL DCLKout2_DDLY_CNTL DCLKout2 _HS SDCLKout3 _MUX 0x10D 0 0 0 SDCLKout3 _ ADLY_EN 0x10E DCLKout2 _ DDLY_PD DCLKout2 _ HSg_PD DCLKout2 _ ADLYg_PD DCLKout2 _ADLY _PD 0x10F SDCLKout3 _POL 0x110 0 CLKout2_3 _PD DCLKout4_DDLY_CNTL 0 DCLKout4 _HS SDCLKout5 _MUX 0x115 0 0 0 SDCLKout5 _ ADLY_EN 0x116 DCLKout4 _ DDLY_PD DCLKout4 _ HSg_PD DCLKout4 _ ADLYg_PD DCLKout4 _ADLY _PD 0x117 SDCLKout5 _POL 0x118 0 Copyright © 2013, Texas Instruments Incorporated CLKout2_FMT DCLKout4_ ADLY_MUX 0x114 DCLKout6_DDLY_CNTH SDCLKout3 _PD DCLKout4_DIV DCLKout4_ADLY CLKout6_8 _IDL SDCLKout3_DIS_MODE DCLKout2 _POL DCLKout4_DDLY_CNTH CLKout6_7 _ODL SDCLKout3 _HS SDCLKout3_ADLY CLKout4_5 _IDL CLKout5_FMT DCLKout2_MUX SDCLKout3_DDLY CLKout3_FMT 0x113 CLKout0_FMT DCLKout2_ ADLY_MUX 0 0x111 SDCLKout1 _PD DCLKout2_DIV DCLKout2_ADLY CLKout4_5 _ODL SDCLKout1_DIS_MODE DCLKout0 _POL 0x10C 0x119 SDCLKout1_ADLY DCLKout2_DDLY_CNTH 0x10B SDCLKout1 _HS SDCLKout1_DDLY CLKout1_FMT CLKout2_3 _ODL DCLKout0_MUX DCLKout4_MUX SDCLKout5 _HS SDCLKout5_DDLY SDCLKout5_ADLY CLKout4_5 _PD SDCLKout5_DIS_MODE DCLKout4 _POL SDCLKout5 _PD CLKout4_FMT DCLKout6_DIV DCLKout6_DDLY_CNTL GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 47 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Table 6-1. Register Map (continued) Address [11:0] Data 7 6 5 0x11B 0 DCLKout6 _HS SDCLKout7 _MUX 0x11D 0 0 0 SDCLKout7 _ ADLY_EN 0x11E DCLKout6 _ DDLY_PD DCLKout6 _ HSg_PD DCLKout6 _ ADLYg_PD DCLKout6 _ADLY _PD 0x11F SDCLKout7 _POL 0x120 0 CLKout8_9 _ODL CLKout8_9 _IDL SDCLKout7_DIS_MODE DCLKout8_DDLY_CNTL SDCLKout9 _MUX 0x125 0 0 0 SDCLKout9 _ ADLY_EN 0x126 DCLKout8 _ DDLY_PD DCLKout8 _ HSg_PD DCLKout8 _ ADLYg_PD DCLKout8 _ADLY _PD 0x127 SDCLKout9 _POL 0x128 0 SDCLKout9_ADLY CLKout8_9 _PD CLKout10 _11_IDL SDCLKout9_DIS_MODE DCLKout10_DIV DCLKout10_DDLY_CNTL DCLKout10 _ ADLY_MUX 0x12C 0 DCLKout10 _HS SDCLKout11 _MUX 0x12D 0 0 0 SDCKLout11 _ ADLY_EN 0x12E DCLKout10 _ DDLY_PD DCLKout10 _ HSg_PD DLCLKout10 _ ADLYg_PD DCLKout10 _ ADLY_PD 0x12F SDCLKout11 _POL 0x130 0 DCLKout10_MUX SDCLKout11 _HS SDCLKout11_DDLY SDCLKout11_ADLY CLKout10 _11_PD SDCLKout11_DIS_MODE DCLKout10 _POL CLKout11_FMT CLKout12 _13_IDL SDCLKout11 _PD CLKout10_FMT DCLKout12_DIV DCLKout12_DDLY_CNTH DCLKout12_DDLY_CNTL DCLKout12_ ADLY_MUX DCLKout12_ADLY 0x134 0 DCLKout12 _HS SDCLKout13 _MUX 0x135 0 0 0 SDCLKout13 _ ADLY_EN 0x136 DCLKout12 _ DDLY_PD DCLKout12 _ HSg_PD DCLKout12 _ ADLYg_PD DCLKout12 _ ADLY_PD 0x137 SDCLKout13 _POL 0x138 0 0x139 0 0 0 0x13A 0 0 0 DCLKout12_MUX SDCLKout13 _HS SDCLKout13_DDLY SDCLKout13_ADLY CLKout12 _13_PD SDCLKout13_DIS_MODE DCLKout12 _POL CLKout13_FMT 0 SDCLKout13 _PD CLKout12_FMT OSCout _MUX 0x13B SDCLKout9 _PD CLKout8_FMT DCLKout10_ADLY VCO_MUX SDCLKout9 _HS DCLKout8 _POL CLKout9_FMT 0x133 DCLKout8_MUX SDCLKout9_DDLY DCLKout10_DDLY_CNTH 0x131 SDCLKout7 _PD CLKout6_FMT DCLKout8 _ ADLY_MUX DCLKout8 _HS CLKout12 _13 _ODL SDCLKout7 _HS DCLKout8_DIV 0 0x12B DCLKout6_MUX DCLKout6 _POL 0x124 OSCout_FMT 0 0 SYSREF_MUX SYSREF_DIV[12:8] SYSREF_DIV[7:0] 0 0 0 0x13D 0x13F CLKout6_7 _PD DCLKout8_ADLY 0x129 0 SDCLKout7_ADLY DCLKout8_DDLY_CNTH CLKout10 _11 _ODL 1 SDCLKout7_DDLY CLKout7 _FMT 0x123 0x13E 2 DCLKout6_ ADLY_MUX 0x11C 0x13C 3 DCLKout6_ADLY 0x121 48 4 SYSREF_DDLY[12:8] SYSREF_DDLY[7:0] 0 0 0 0 0 0 0 0 PLL2_NCLK _MUX PLL1_NCLK _MUX GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 0 SYSREF_PULSE_CNT FB_MUX FB_MUX _EN Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Table 6-1. Register Map (continued) Address [11:0] Data 7 6 5 4 3 2 1 0 SYSREF_PD SYSREF _DDLY_PD SYSREF _PLSR_PD DDLYd4_EN DDLYd2_EN DDLYd0_EN 0x140 PLL1_PD VCO_LDO_PD VCO_PD OSCin_PD SYSREF_GBL _PD 0x141 DDLYd_ SYSREF_EN DDLYd12 _EN DDLYd10 _EN DDLYd7_EN DDLYd6_EN 0 SYNC_PLL1 _DLD SYNC_DIS4 0x142 0 0 0x143 SYSREF_DDLY _CLR SYNC_1SHOT _EN SYNC_POL SYNC_EN SYNC_PLL2 _DLD 0x144 SYNC _DISSYSREF SYNC_DIS12 SYNC_DIS10 SYNC_DIS8 SYNC_DIS6 0x145 0 1 1 1 1 1 1 1 0x146 0 0 CLKin2_EN CLKin1_EN CLKin0_EN CLKin2_TYPE CLKin1_TYPE CLKin0_TYPE 0x147 CLKin_SEL _POL 0x148 0 0 CLKin_SEL0_MUX CLKin_SEL0_TYPE 0x149 0 SDIO_RDBK _TYPE CLKin_SEL1_MUX CLKin_SEL1_TYPE 0x14A 0 0 RESET_MUX 0x14B DDLYd_STEP_CNT CLKin_SEL_MODE LOS_TIMEOUT LOS_EN 0x14E TRACK_EN DAC_CLK_CNTR 0x151 0 0 0 HOLDOVER _ PLL1_DET 0 0 0 0 CLKin1_R[13:8] CLKin1_R[7:0] 0 0 CLKin2_R[13:8] CLKin2_R[7:0] 0 0 PLL1_N[13:8] 0x15A PLL1_N[7:0] PLL1 _CP_TRI PLL1_WND_SIZE 0 PLL1 _CP_POL PLL1_CP_GAIN 0 PLL1_DLD_CNT[13:8] 0x15D PLL1_DLD_CNT[7:0] 0 0 0x15F PLL1_R_DLY PLL1_N_DLY PLL1_LD_MUX 0 0 0 PLL1_LD_TYPE 0 0x161 PLL2_R[11:8] PLL2_R[7:0] 0x162 0x163 PLL2_P 0 0 0 0 0 PLL2_N_CAL[15:8] 0x165 PLL2_N_CAL[7:0] 0 0 0 0 0 0x167 PLL2_N[15:8] 0x168 PLL2_N[7:0] 0x169 0 PLL2_WND_SIZE Copyright © 2013, Texas Instruments Incorporated PLL2 _XTAL_EN OSCin_FREQ 0x164 0x166 HOLDOVER _EN CLKin0_R[13:8] 0x158 0x160 HOLDOVER _HITLESS _SWITCH CLKin0_R[7:0] 0x156 0x15E HOLDOVER _VTUNE_DET HOLDOVER_DLD_CNT[7:0] 0x154 0x15C HOLDOVER _LOS _DET HOLDOVER_DLD_CNT[13:8] 0x152 0x15B MAN_DAC[9:8] DAC_TRIP_HIGH 0 0x159 MAN_DAC _EN DAC_TRIP_LOW DAC_CLK_MULT 0 0x157 CLKin0_OUT_MUX RESET_TYPE HOLDOVER _ FORCE 0 0x150 0x155 SYNC_DIS0 MAN_DAC[7:0] 0 0x14F 0x153 SYNC_DIS2 CLKin1_OUT_MUX 0x14C 0x14D SYNC_MODE PLL2_CP_GAIN PLL2 _REF_2X_EN 0 PLL2_N_CAL[17:16] PLL2_FCAL _DIS PLL2_N[17:16] PLL2 _CP_POL PLL 2_CP_TRI 1 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 49 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com Table 6-1. Register Map (continued) Address [11:0] 0x16A Data 7 6 5 0 SYSREF_REQ_ EN 0 0 1 PLL2_LF_R4 0 PLL2_LF_R3 PLL2_LF_C4 0x16E PLL2_LF_C3 PLL2_LD_MUX 0 PLL2_PRE_PD PLL2_PD PLL2_LD_TYPE 0 0x17C OPT_REG_1 0x17D OPT_REG_2 0 0 0 0 0x182 0 0 0 0 0 RB_PLL1_ LD_LOST RB_PLL1_LD CLR_PLL1_ LD_LOST 0x183 0 0 0 0 0 RB_PLL2_ LD_LOST RB_PLL2_LD CLR_PLL2_ LD_LOST RB_CLKin2_ SEL RB_CLKin1_ SEL RB_CLKin0_ SEL X RB_CLKin1_ LOS RB_CLKin0_ LOS 0 RB_ HOLDOVER X X X 0x184 RB_DAC_VALUE[9:8] 0x185 0x188 50 2 PLL2_DLD_CNT[7:0] 0x16D 0x173 3 PLL2_DLD_CNT[15:8] 0x16B 0x16C 4 RB_DAC_VALUE[7:0] 0 0 X 0x1FFD SPI_LOCK[23:16] 0x1FFE SPI_LOCK[15:8] 0x1FFF SPI_LOCK[7:0] GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Device Register Descriptions The following section details the fields of each register, the Power On Reset Defaults, and specific descriptions of each bit. In some cases similar fields are located in multiple registers. In this case specific outputs may be designated as X or Y. In these cases the X will represent even numbers from 0 to 12 and the Y will represent odd numbers from 1 to 13. In the case where X and Y are both used in a bit name then Y = X + 1. 6.3.1 SYSTEM FUNCTIONS 6.3.1.1 RESET, SPI_3WIRE_DIS This register contains the RESET function. Register 0x000 Bit Name POR Default 7 RESET 0 0: Normal Operation 1: Reset (automatically cleared) 6:5 NA 0 Reserved 4 SPI_3WIRE_DIS 0 Disable 3 wire SPI mode. 4 Wire SPI mode is enabled by selecting SPI Read back in one of the output MUX settings. For example CLKin0_SEL_MUX. 0: 3 Wire Mode enabled 1: 3 Wire Mode disabled 3:0 NA NA 6.3.1.2 Description Reserved POWERDOWN This register contains the POWERDOWN function. Register 0x002 Bit Name POR Default 7:1 NA 0 Reserved 0 POWERDOWN 0 0: Normal Operation 1: Powerdown 6.3.1.3 Description ID_DEVICE_TYPE This register contains the product device type. This is read only register. Register 0x003 Bit Name 7:0 ID_DEVICE_TYPE 6.3.1.4 POR Default Description 6 PLL product device type. ID_PROD[15:8], ID_PROD These registers contain the product identifier. This is read only register. ID_PROD REGISTER CONFIGURATION, ID_PROD[15:0] MSB LSB 0x004[7:0] 0x005[7:0] Bit Registers Field Name POR Default 7:0 0x004 ID_PROD[15:8] 208 MSB of the product identifier. 7:0 0x005 ID_PROD 91 LSB of the product identifier. Copyright © 2013, Texas Instruments Incorporated Description GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 51 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.1.5 www.ti.com ID_MASKREV This register contains the IC version identifier. This is read only register. Register 0x006 Bit Name 7:0 ID_MASKREV 6.3.1.6 POR Default Description 37 IC version identifier for LMK04826 32 IC version identifier for LMK04828 ID_VNDR[15:8], ID_VNDR These registers contain the vendor identifier. This is read only register. ID_VNDR REGISTER CONFIGURATION, ID_VNDR[15:0] MSB LSB 0x00C[7:0] 0x00D[7:0] Register 0x00C, 0x00D Bit Registers Name POR Default 7:0 0x00C ID_VNDR[15:8] 81 MSB of the vendor identifier. 7:0 0x00D ID_VNDR 4 LSB of the vendor identifier. 52 Description GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.2 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 (0x100 - 0x138) Device Clock and SYSREF Clock Output Controls 6.3.2.1 CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV These registers control the input and output drive level as well as the device clock out divider values. Register 0x100, 0x108, 0x110, 0x118, 0x120, 0x128, and 0x130 Bit Name 7 NA 0 Reserved 6 CLKoutX_Y_ODL 0 Output drive level. 5 CLKoutX_Y_IDL 0 Input drive level. 4:0 (1) DCLKoutX_DIV POR Default Description DCLKoutX_DIV sets the divide value for the clock output, the divide may be even or odd. Both even or odd divides output a 50% duty cycle clock if duty cycle correction (DCC) is selected. Divider is unused if DCLKoutX_MUX = 2 (bypass), equivalent divide of 1. X=0→2 X=2→4 X=4→8 X=6→8 X=8→8 X = 10 → 8 X = 12 → 2 Field Value Divider Value 0 (0x00) 32 1 (0x01) 1 (1) 2 (0x02) 2 ... ... 30 (0x1E) 30 31 (0x1F) 31 Not valid if DCLKoutX_MUX = 0, Divider only. Not valid if DCLKoutX_MUX = 3 (Analog Delay + Divider) and DCLKoutX_ADLY_MUX = 0 (without duty cycle correction/halfstep). 6.3.2.2 DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL This register controls the digital delay high and low count values for the device clock outputs. Register 0x101, 0x109, 0x111, 0x119, 0x121, 0x129, 0x131 Bit Name POR Default Description Number of clock cycles the output will be high when digital delay is engaged. Field Value 7:4 DCLKoutX _DDLY_CNTH 5 Delay Values 0 (0x00) 16 1 (0x01) Reserved 2 (0x02) 2 ... ... 15 (0x0F) 15 Number of clock cycles the output will be low when dynamic digital delay is engaged. 3:0 DCLKoutX _DDLY_CNTL 5 Copyright © 2013, Texas Instruments Incorporated Field Value Delay Values 0 (0x00) 16 1 (0x01) Reserved 2 (0x02) 2 ... ... 15 (0x0F) 15 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 53 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.2.3 www.ti.com DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX These registers control the analog delay properties for the device clocks. Register 0x103, 0x10B, 0x113, 0x11B, 0x123, 0x12B, 0x133 Bit Name POR Default Description Device clock analog delay value. Setting this value results in a 500 ps timing delay in additional to the delay of each 25 ps step. Effective range is 500 ps to 1075 ps. Field Value 7:3 DCLKoutX_ALDY DCLKoutX_ADLY _MUX 2 0 Delay Value 0 (0x00) 0 ps 1 (0x01) 25 ps 2 (0x02) 50 ps ... ... 23 (0x17) 575 ps This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3. 0: Divided without duty cycle correction or half step. (1) 1: Divided with duty cycle correction and half step. 0 This selects the input to the device clock buffer. Field Value Mux Output 0 (0x0) 1:0 (1) DCLKoutX_MUX 0 1 (0x1) Divider only (1) Divider with Duty Cycle Correction and Half Step 2 (0x2) Bypass 3 (0x3) Analog Delay + Divider DCLKoutX_DIV = 1 is not valid. 6.3.2.4 DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS These registers set the half step for the device clock, the SYSREF output MUX, the SYSREF clock digital delay, and half step. Register 0x104, 0x10C, 0x114, 0x11C, 0x124, 0x12C, 0x134 Bit Name POR Default 7 NA 0 Description Reserved 6 DCLKoutX_HS 0 Sets the device clock half step value. Half shift must be zero (0) for a divide of 1. 0: 0 cycles 1: -0.5 cycles 5 SDCLKoutY_MUX 0 Sets the input the the SDCLKoutX outputs. 0: Device clock output 1: SYSREF output Sets the number of VCO cycles to delay the SDCLKout by. 4:1 0 54 SDCLKoutY_DDLY SDCLKoutY_HS 0 0 Field Value Delay Cycles 0 (0x00) Reserved 1 (0x01) 2 2 (0x02) 3 ... ... 10 (0x0A) 11 11 to 15 (0x0B to 0x0F) Reserved Sets the SYSREF clock half step value. 0: 0 cycles 1: -0.5 cycles GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.2.5 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY These registers set the analog delay parameters for the SYSREF outputs. Register 0x105, 0x10D, 0x115, 0x11D, 0x125, 0x12D, 0x135 Bit Name POR Default 7:5 NA 0 Description Reserved 4 SDCLKoutY _ADLY_EN 0 Enables analog delay for the SYSREF output. 0: Disabled 1: Enabled Sets the analog delay value for the SYSREF output. Selecting analog delay adds an additional 700 ps in propagation delay. Effective range is 700 ps to 2950 ps. 3:0 SDCLKoutY _ADLY 0 Copyright © 2013, Texas Instruments Incorporated Field Value Delay Value 0 (0x0) 0 ps 1 (0x1) 600 ps 2 (0x2) 750 ps (+150 ps from 0x1) 3 (0x3) 900 ps (+150 ps from 0x2) ... ... 14 (0xE) 2100 ps (+150 ps from 0xD) 15 (0xF) 2250 ps (+150 ps from 0xE) GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 55 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.2.6 www.ti.com DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD, DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD This register controls the power down functions for the digital delay, glitchless half step, glitchless analog delay, analog delay, outputs, and SYSREF disable modes. Register 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136 Bit Name POR Default 7 DCLKoutX _DDLY_PD 0 Powerdown the device clock digital delay circuitry. 0: Enabled 1: Powerdown 6 DCLKoutX _HSg_PD 1 Powerdown the device clock glitchless half step feature. 0: Enabled 1: Powerdown 5 DCLKoutX _ADLYg_PD 1 Powerdown the device clock glitchless analog delay feature. 0: Enabled, analog delay step size of one code is glitchless between values 1 to 23. 1: Powerdown 4 DCLKoutX _ADLY_PD 1 Powerdown the device clock analog delay feature. 0: Enabled 1: Powerdown CLKoutX_Y_PD X_Y = 0_1 → 1 X_Y = 2_3 → 1 X_Y = 4_5 → 0 X_Y = 6_7 → 0 X_Y = 8_9 → 0 X_Y = 10_11 → 0 X_Y = 12_13 → 1 3 Description Powerdown the clock group defined by X and Y. 0: Enabled 1: Powerdown Configures the output state of the SYSREF 2:1 0 (1) 56 SDCLKoutY _DIS_MODE SDCLKoutY_PD 0 1 Field Value Disable Mode 0 (0x00) Active in normal operation 1 (0x01) If SYSREF_GBL_PD = 1, the output is a logic low, otherwise it is active. 2 (0x02) If SYSREF_GBL_PD = 1, the output is a nominal Vcm voltage (1), otherwise it is active. 3 (0x03) Output is a nominal Vcm voltage (1) Powerdown SDCLKoutY and set to the state defined by SDCLKoutY_DIS_MODE If LVPECL mode is used with emitter resistors to ground, the output Vcm will be ~0 V, each pin will be ~0 V. GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.2.7 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 SDCLKoutY_POL, SDCLKoutY_FMT, DCLKoutX_POL, DCLKoutX_FMT These registers configure the output polarity, and format. REGISTERS 0x107, 0x10F, 0x117, 0x11F, 0x127, 0x12F, 0x137 Bit 7 Name SDCLKoutY_POL POR Default 0 Description Sets the polarity of SYSREF clocks. 0: Normal 1: Inverted Sets the output format of the SYSREF clocks 6:4 3 SDCLKoutY_FMT DCLKoutX_POL 0 0 Field Value Output Format 0 (0x00) Powerdown 1 (0x01) LVDS 2 (0x02) HSDS 6 mA 3 (0x03) HSDS 8 mA 4 (0x04) HSDS 10 mA 5 (0x05) LVPECL 1600 mV 6 (0x06) LVPECL 2000 mV 7 (0x07) LCPECL Sets the polarity of the device clocks. 0: Normal 1: Inverted Sets the output format of the device clocks. 2:0 DCLKoutX_FMT X=0→0 X=2→0 X=4→1 X=6→1 X=8→1 X = 10 → 1 X = 12 → 0 Copyright © 2013, Texas Instruments Incorporated Field Value Output Format 0 (0x00) Powerdown 1 (0x01) LVDS 2 (0x02) HSDS 6 mA 3 (0x03) HSDS 8 mA 4 (0x04) HSDS 10 mA 5 (0x05) LVPECL 1600 mV 6 (0x06) LVPECL 2000 mV 7 (0x07) LCPECL GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 57 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.3 www.ti.com SYSREF, SYNC, and Device Config 6.3.3.1 VCO_MUX, OSCout_MUX, OSCout_FMT This register selects the clock distribution source, and OSCout parameters. Register 0x138 Bit Name POR Default 7 NA 0 Description Reserved Selects clock distribution path source from VCO0, VCO1, or CLKin (external VCO) 6:5 VCO_MUX 4 OSCout_MUX 0 0 Field Value VCO Selected 0 (0x00) VCO 0 1 (0x01) VCO 1 2 (0x02) CLKin1 (external VCO) 3 (0x03) Reserved Select the source for OSCout: 0: Buffered OSCin 1: Feedback Mux Selects the output format of OSCout. When powered down, these pins may be used as CLKin2. 3:0 OSCout_FMT 6.3.3.2 4 Field Value OSCout Format 0 (0x00) Powerdown (CLKin2) 1 (0x01) LVDS 2 (0x02) Reserved 3 (0x03) Reserved 4 (0x04) LVPECL 1600 mVpp 5 (0x05) LVPECL 2000 mVpp 6 (0x06) LVCMOS (Norm / Inv) 7 (0x07) LVCMOS (Inv / Norm) 8 (0x08) LVCMOS (Norm / Norm) 9 (0x09) LVCMOS (Inv / Inv) 10 (0x0A) LVCMOS (Off / Norm) 11 (0x0B) LVCMOS (Off / Inv) 12 (0x0C) LVCMOS (Norm / Off) 13 (0x0D) LVCMOS (Inv / Off) 14 (0x0E) LVCMOS (Off / Off) SYSREF_MUX This register sets the source for the SYSREF outputs. Register 0x139 Bit Name POR Default 7:2 NA 0 Description Reserved Selects the SYSREF source. 1:0 58 SYSREF_MUX 0 Field Value SYSREF Source 0 (0x00) Normal SYNC 1 (0x01) Re-clocked 2 (0x02) SYSREF Pulser 3 (0x03) SYSREF Continuous GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.3.3 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 SYSREF_DIV[12:8], SYSREF_DIV[7:0] These registers set the value of the SYSREF output divider. Register 0x13A, 0x13B MSB LSB 0x13A[4:0] 0x13B[7:0] Bit Registers Name POR Default 7:5 0x13A NA 0 Description Reserved Divide value for the SYSREF outputs. 4:0 0x13A 7:0 0x13B 6.3.3.4 SYSREF_DIV[12:8] SYSREF_DIV[7:0] 12 0 Field Value Divide Value 0x00 to 0x07 Reserved 8 (0x08) 8 9 (0x09) 9 ... ... 8190 (0x1FFE) 8190 8191 (0X1FFF) 8191 SYSREF_DDLY[12:8], SYSREF_DDLY[7:0] These registers set the delay of the SYSREF digital delay value. SYSREF DIGITAL DELAY REGISTER CONFIGURATION, SYSREF_DDLY[12:0] MSB LSB 0x13C[4:0] 0x13D[7:0] Bit Registers Name 7:5 0x13C NA POR Default Description 0 Reserved Sets the value of the SYSREF digital delay. 4:0 7:0 0x13C 0x13D SYSREF_DDLY[12:8] SYSREF_DDLY[7:0] Copyright © 2013, Texas Instruments Incorporated 0 8 Field Value Delay Value 0x00 to 0x07 Reserved 8 (0x08) 8 9 (0x09) 9 ... ... 8190 (0x1FFE) 8190 8191 (0X1FFF) 8191 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 59 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.3.5 www.ti.com SYSREF_PULSE_CNT This register sets the number of SYSREF pulses if SYSREF is not in continuous mode. See Section 6.3.3.2 for further description of SYSREF's outputs. Programming the register causes the specified number of pulses to be output, if "SYSREF Pulses" is selected by SYSREF_MUX and SYSREF functionality is powered up. Register 0x13E Bit Name POR Default 7:2 NA 0 Description Reserved Sets the number of SYSREF pulses generated when not in continuous mode. See Section 6.3.3.2 for more information on SYSREF modes. Field Value 1:0 SYSREF_PULSE_CNT 6.3.3.6 3 Number of Pulses 0 (0x00) 1 pulse 1 (0x01) 2 pulses 2 (0x02) 4 pulses 3 (0x03) 8 pulses PLL2_NCLK_MUX, PLL1_NCLK_MUX, FB_MUX, FB_MUX_EN This register controls the feedback feature. Register 0x13F Bit Name POR Default Description 7:5 NA 0 Reserved 4 PLL2_NCLK_MUX 0 Selects the input to the PLL2 N Divider 0: PLL Prescaler 1: Feedback Mux 3 PLL1_NCLK_MUX 0 Selects the input to the PLL1 N Delay. 0: OSCin 1: Feedback Mux When in 0-delay mode, the feedback mux selects the clock output to be fed back into the PLL1 N Divider. 2:1 0 60 FB_MUX FB_MUX_EN 0 0 Field Value Source 0 (0x00) DCLKout6 1 (0x01) DCLKout8 2 (0x02) SYSREF 3 (0x03) External When using 0-delay, FB_MUX_EN must be set to 1 power up the feedback mux. 0: Feedback mux powered down 1: Feedback mux enabled GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.3.7 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 PLL1_PD, VCO_LDO_PD, VCO_PD, OSCin_PD, SYSREF_GBL_PD, SYSREF_PD, SYSREF_DDLY_PD, SYSREF_PLSR_PD This register contains powerdown controls for OSCin and SYSREF functions. Register 0x140 Bit Name POR Default 7 PLL1_PD 0 Powerdown PLL1 0: Normal operation 1: Powerdown 6 VCO_LDO_PD 0 Powerdown VCO_LDO 0: Normal operation 1: Powerdown 5 VCO_PD 0 Powerdown VCO 0: Normal operation 1: Powerdown 4 OSCin_PD 0 Powerdown the OSCin port. 0: Normal operation 1: Powerdown 0 Powerdown individual SYSREF outputs depending on the setting of SDCLKoutY_DIS_MODE for each SYSREF output. SYSREF_GBL_PD allows many SYSREF outputs to be controlled through a single bit. 0: Normal operation 1: Activate Powerdown Mode 1 Powerdown the SYSREF circuitry and divider. If powered down, SYSREF output mode cannot be used. SYNC cannot be provided either. 0: SYSREF can be used as programmed by individual SYSREF output registers. 1: Powerdown 3 SYSREF_GBL_PD 2 SYSREF_PD Description 1 SYSREF_DDLY_PD 1 Powerdown the SYSREF digital delay circuitry. 0: Normal operation, SYSREF digital delay may be used. Must be powered up during SYNC for deterministic phase relationship with other clocks. 1: Powerdown 0 SYSREF_PLSR_PD 1 Powerdown the SYSREF pulse generator. 0: Normal operation 1: Powerdown 6.3.3.8 DDLYdSYSREF_EN, DDLYdX_EN This register enables dynamic digital delay for enabled device clocks and SYSREF when DDLYd_STEP_CNT is programmed. Register 0x141 Bit Name POR Default 7 DDLYd _SYSREF_EN 0 Enables dynamic digital delay on SYSREF outputs 6 DDLYd12_EN 0 Enables dynamic digital delay on DCLKout12 5 DDLYd10_EN 0 Enables dynamic digital delay on DCLKout10 4 DDLYd8_EN 0 Enables dynamic digital delay on DCLKout8 3 DDLYd6_EN 0 Enables dynamic digital delay on DCLKout6 2 DDLYd4_EN 0 Enables dynamic digital delay on DCLKout4 1 DDLYd2_EN 0 Enables dynamic digital delay on DCLKout2 0 DDLYd0_EN 0 Enables dynamic digital delay on DCLKout0 Copyright © 2013, Texas Instruments Incorporated Description 0: Disabled 1: Enabled GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 61 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.3.9 www.ti.com DDLYd_STEP_CNT This register sets the number of dynamic digital delay adjustments occur. Upon programming, the dynamic digital delay adjustment begins for each clock output with dynamic digital delay enabled. Dynamic digital delay can only be started by SPI. Other registers must be set: SYNC_MODE = 3 Register 0x142 Bit Name POR Default 7:4 NA 0 Description Reserved Sets the number of dynamic digital delay adjustments that will occur. 3:0 DDLYd_STEP_CNT Field Value SYNC Generation 0 (0x00) No Adjust 0 1 (0x01) 1 step 2 (0x02) 2 steps 3 (0x03) 3 steps ... ... 14 (0x0E) 14 steps 15 (0x0F) 15 steps 6.3.3.10 SYSREF_CLR, SYNC_1SHOT_EN, SYNC_POL, SYNC_EN, SYNC_PLL2_DLD, SYNC_PLL1_DLD, SYNC_MODE This register sets general SYNC parameters such as polarization, and mode. Register 0x143 Bit Name POR Default Description 7 SYSREF_CLR 1 Set to clear local SYSREF DDLY Anytime SYSREF_PD = 1 because of user programming or device RESET, it is necessary to set SYSREF_CLR for 15 VCO clock cycles to clear the local SYSREF digital delay. Once cleared, SYSREF_CLR must be cleared to allow SYSREF to operate. 6 SYNC_1SHOT_EN 0 SYNC one shot enables edge sensitive SYNC. 0: SYNC is level sensitive and outputs will be held in SYNC as long as SYNC is asserted. 1: SYNC is edge sensitive, outputs will be SYNCed on rising edge of SYNC. This results in the clock being held in SYNC for a minimum amount of time. 5 SYNC_POL 0 Sets the polarity of the SYNC pin. 0: Normal 1: Inverted 4 SYNC_EN 1 Enables the SYNC functionality. 0: Disabled 1: Enabled 3 SYNC_PLL2_DLD 0 0: Off 1: Assert SYNC until PLL2 DLD = 1 2 SYNC_PLL1_DLD 0 0: Off 1: Assert SYNC until PLL1 DLD = 1 Sets the method of generating a SYNC event. Field Value 1:0 62 SYNC_MODE 1 SYNC Generation 0 (0x00) SYNC Disabled 1 (0x01) SYNC event generated from the SYNC Pin 2 (0x02) SYNC event generated from the SYNC Pin (For SYSREF_MUX = Pulsor) 3 (0x03) SYNC event generated from a SPI write (For SYSREF_MUX = Pulsor) GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.3.11 SYNC_DISSYSREF, SYNC_DISX SYNC_DISX will prevent a clock output from being synchronized or interrupted by a SYNC event or when outputting SYSREF. Register 0x144 Bit Name POR Default 7 SYNC_DISSYSREF 0 6 SYNC_DIS12 0 5 SYNC_DIS10 0 4 SYNC_DIS8 0 3 SYNC_DIS6 0 2 SYNC_DIS4 0 1 SYNC_DIS2 0 0 SYNC_DIS0 0 Description Prevent the SYSREF clocks from becoming synchronized during a SYNC event. If SYNC_DISSYSREF is enabled it will continue to operate normally during a SYNC event. Prevent the device clock output from becoming synchronized during a SYNC event or SYSREF clock. If SYNC_DIS bit for a particular output is enabled then it will continue to operate normally during a SYNC event or SYSREF clock. 6.3.3.12 FIXED REGISTER REGISTER 0x145. Always program this register to value 127. Bit Name POR Default 7:0 Fixed Register 0 Copyright © 2013, Texas Instruments Incorporated Description Always program to 127 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 63 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.4 www.ti.com (0x146 - 0x149) CLKin Control 6.3.4.1 CLKin2_EN, CLKin1_EN, CLKin0_EN, CLKin2_TYPE, CLKin1_TYPE, CLKin0_TYPE This register has CLKin enable and type controls. Register 0x146 Bit Name POR Default Description 7:6 NA 0 Reserved 5 CLKin2_EN 0 Enable CLKin2 to be used during auto-switching of CLKin_SEL_MODE. 0: Not enabled for auto mode 1: Enabled for auto mode 4 CLKin1_EN 1 Enable CLKin1 to be used during auto-switching of CLKin_SEL_MODE. 0: Not enabled for auto mode 1: Enabled for auto mode 3 CLKin0_EN 1 Enable CLKin0 to be used during auto-switching of CLKin_SEL_MODE. 0: Not enabled for auto mode 1: Enabled for auto mode 2 CLKin2_TYPE 0 1 CLKin1_TYPE 0 0: Bipolar 1: MOS 0 64 CLKin0_TYPE 0 There are two buffer types for CLKin0, 1, and 2: bipolar and CMOS. Bipolar is recommended for differential inputs like LVDS or LVPECL. CMOS is recommended for DC coupled single ended inputs. When using bipolar, CLKinX and CLKinX* must be AC coupled. When using CMOS, CLKinX and CLKinX* may be AC or DC coupled if the input signal is differential. If the input signal is single-ended the used input may be either AC or DC coupled and the unused input must AC grounded. GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.4.2 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 CLKin_SEL_POL, CLKin_SEL_MODE, CLKin1_OUT_MUX, CLKin0_OUT_MUX Register 0x147 Bit Name 7 CLKin_SEL_POL POR Default Description 0 Inverts the CLKin polarity for use in pin select mode. 0: Active High 1: Active Low Sets the mode used in determining the reference for PLL1. 6:4 CLKin_SEL_MODE 3 Field Value CLKin Mode 0 (0x00) CLKin0 Manual 1 (0x01) CLKin1 Manual 2 (0x02) CLKin2 Manual 3 (0x03) Pin Select Mode 4 (0x04) Auto Mode 5 (0x05) Reserved 6 (0x06) Reserved 7 (0x07) Reserved Selects where the output of the CLKin1 buffer is directed. 3:2 CLKin1_OUT_MUX 2 Field Value CLKin1 Destination 0 (0x00) Fin 1 (0x01) Feedback Mux (0-delay mode) 2 (0x02) PLL1 3 (0x03) Reserved Selects where the output of the CLKin0 buffer is directed. 1:0 CLKin0_OUT_MUX 2 Copyright © 2013, Texas Instruments Incorporated Field Value CLKin0 Destination 0 (0x00) SYSREF Mux 1 (0x01) Reserved 2 (0x02) PLL1 3 (0x03) Reserved GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 65 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.4.3 www.ti.com CLKin_SEL0_MUX, CLKin_SEL0_TYPE This register has CLKin_SEL0 controls. Register 0x148 Bit Name 7:6 NA POR Default Description 0 Reserved This set the output value of the CLKin_SEL0 pin. This register only applies if CLKin_SEL0_TYPE is set to an output mode 5:3 CLKin_SEL0_MUX 0 Field Value Output Format 0 (0x00) Logic Low 1 (0x01) CLKin0 LOS 2 (0x02) CLKin0 Selected 3 (0x03) DAC Locked 4 (0x04) DAC Low 5 (0x05) DAC High 6 (0x06) SPI Readback 7 (0x07) Reserved This sets the IO type of the CLKin_SEL0 pin. 2:0 66 CLKin_SEL0_TYPE 2 Field Value Configuration 0 (0x00) Input 1 (0x01) Input /w pull-up resistor 2 (0x02) Input /w pull-down resistor 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (push-pull) 5 (0x05) Reserved 6 (0x06) Output (open drain) GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Function Input mode, see Section 5.6.2 for description of input mode. Output modes; the CLKin_SEL0_MUX register for description of outputs. Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.4.4 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 SDIO_RDBK_TYPE, CLKin_SEL1_MUX, CLKin_SEL1_TYPE This register has CLKin_SEL1 controls and register readback SDIO pin type. Register 0x149 Bit Name 7 NA POR Default Description 0 Reserved 6 SDIO_RDBK_TYPE 1 Sets the SDIO pin to open drain when during SPI readback in 3 wire mode. 0: Output, push-pull 1: Output, open drain. This set the output value of the CLKin_SEL1 pin. This register only applies if CLKin_SEL1_TYPE is set to an output mode. 5:3 CLKin_SEL1_MUX 0 Field Value Output Format 0 (0x00) Logic Low 1 (0x01) CLKin1 LOS 2 (0x02) CLKin1 Selected 3 (0x03) DAC Locked 4 (0x04) DAC Low 5 (0x05) DAC High 6 (0x06) SPI Readback 7 (0x07) Reserved This sets the IO type of the CLKin_SEL1 pin. 2:0 CLKin_SEL1_TYPE 2 Copyright © 2013, Texas Instruments Incorporated Field Value Configuration 0 (0x00) Input 1 (0x01) Input /w pull-up resistor 2 (0x02) Input /w pull-down resistor 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (push-pull) 5 (0x05) Reserved 6 (0x06) Output (open drain) Function Input mode, see Section 5.6.2 for description of input mode. Output modes; see the CLKin_SEL1_MUX register for description of outputs. GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 67 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.5 www.ti.com RESET_MUX, RESET_TYPE This register contains control of the RESET pin. Register 0x14A Bit Name POR Default 7:6 NA 0 Description Reserved This sets the output value of the RESET pin. This register only applies if RESET_TYPE is set to an output mode. 5:3 RESET_MUX 0 Field Value Output Format 0 (0x00) Logic Low 1 (0x01) Reserved 2 (0x02) CLKin2 Selected 3 (0x03) DAC Locked 4 (0x04) DAC Low 5 (0x05) DAC High 6 (0x06) SPI Readback This sets the IO type of the RESET pin. Field Value 2:0 68 RESET_TYPE 2 Configuration Function 0 (0x00) Input 1 (0x01) Input /w pull-up resistor 2 (0x02) Input /w pull-down resistor 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (push-pull) 5 (0x05) Reserved 6 (0x06) Output (open drain) GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Reset Mode Reset pin high = Reset Output modes; see the RESET_MUX register for description of outputs. Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.6 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 (0x14B - 0x152) Holdover 6.3.6.1 LOS_TIMEOUT, LOS_EN, TRACK_EN, HOLDOVER_FORCE, MAN_DAC_EN, MAN_DAC[9:8] This register contains the holdover functions. Register 0x14B Bit Name POR Default Description This controls the amount of time in which no activity on a CLKin forces a clock switch event. Field Value 7:6 5 4 LOS_TIMEOUT LOS_EN TRACK_EN 0 Timeout 0 (0x00) 370 kHz 1 (0x01) 2.1 MHz 2 (0x02) 8.8 MHz 3 (0x03) 22 MHz 0 Enables the LOS (Loss-of-Signal) timeout control. Valid for MOS clock inputs. 0: Disabled 1: Enabled 1 Enable the DAC to track the PLL1 tuning voltage, optionally for use in holdover mode. After device reset, tracking starts at DAC code = 512. Tracking can be used to monitor PLL1 voltage in any mode. 0: Disabled 1: Enabled, will only track when PLL1 is locked. 3 HOLDOVER _FORCE 0 This bit forces holdover mode. When holdover mode is forced, if MAN_DAC_EN = 1, then the DAC will set the programmed MAN_DAC value. Otherwise the tracked DAC value will set the DAC voltage. 0: Disabled 1: Enabled. 2 MAN_DAC_EN 1 This bit enables the manual DAC mode. 0: Automatic 1: Manual 1:0 MAN_DAC[9:8] 2 See Section 6.3.6.2 for more information on the MAN_DAC settings. Copyright © 2013, Texas Instruments Incorporated GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 69 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.6.2 www.ti.com MAN_DAC[9:8], MAN_DAC[7:0] These registers set the value of the DAC in holdover mode when used manually. MAN_DAC[9:0] Bit Registers 7:2 0x14B MSB LSB 0x14B[1:0] 0x14C[7:0] POR Default Name Description See Section 6.3.6.1 for information on these bits. Sets the value of the manual DAC when in manual DAC mode. 1:0 0x14B 7:0 0x14C 6.3.6.3 MAN_DAC[9:8] MAN_DAC[7:0] 2 0 Field Value DAC Value 0 (0x00) 0 1 (0x01) 1 2 (0x02) 2 ... ... 1022 (0x3FE) 1022 1023 (0x3FF) 1023 DAC_TRIP_LOW This register contains the high value at which holdover mode is entered. Register 0x14D Bit Name POR Default 7:6 NA 0 Description Reserved Voltage from GND at which holdover is entered if HOLDOVER_VTUNE_DET is enabled. 5:0 70 DAC_TRIP_LOW 0 Field Value DAC Trip Value 0 (0x00) 1 x Vcc / 64 1 (0x01) 2 x Vcc / 64 2 (0x02) 3 x Vcc / 64 3 (0x03) 4 x Vcc / 64 ... ... 61 (0x17) 62 x Vcc / 64 62 (0x18) 63 x Vcc / 64 63 (0x19) 64 x Vcc / 64 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.6.4 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 DAC_CLK_MULT, DAC_TRIP_HIGH This register contains the multiplier for the DAC clock counter and the low value at which holdover mode is entered. Register 0x14E Bit Name POR Default Description This is the multiplier for the DAC_CLK_CNTR which sets the rate at which the DAC value is tracked. Field Value 7:6 DAC_CLK_MULT 0 DAC Multiplier Value 0 (0x00) 4 1 (0x01) 64 2 (0x02) 1024 3 (0x03) 16384 Voltage from Vcc at which holdover is entered if HOLDOVER_VTUNE_DET is enabled. 5:0 DAC_TRIP_HIGH 6.3.6.5 0 Field Value DAC Trip Value 0 (0x00) 1 x Vcc / 64 1 (0x01) 2 x Vcc / 64 2 (0x02) 3 x Vcc / 64 3 (0x03) 4 x Vcc / 64 ... ... 61 (0x17) 62 x Vcc / 64 62 (0x18) 63 x Vcc / 64 63 (0x19) 64 x Vcc / 64 DAC_CLK_CNTR This register contains the value of the DAC when in tracked mode. Register 0x14F Bit Name POR Default Description This with DAC_CLK_MULT set the rate at which the DAC is updated. The update rate is = DAC_CLK_MULT * DAC_CLK_CNTR / PLL1 PDF 7:0 DAC_CLK_CNTR 127 Copyright © 2013, Texas Instruments Incorporated Field Value DAC Value 0 (0x00) 0 1 (0x01) 1 2 (0x02) 2 3 (0x03) 3 ... ... 253 (0xFD) 253 254 (0xFE) 254 255 (0xFF) 255 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 71 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.6.6 www.ti.com HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET, HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN This register has controls for enabling clock in switch events. Register 0x150 Bit Name POR Default 7:5 NA 0 Reserved 4 HOLDOVER _PLL1_DET 0 This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low. 0: PLL1 DLD does not cause a clock switch event 1: PLL1 DLD causes a clock switch event 3 HOLDOVER _LOS_DET 0 This enables HOLDOVER when PLL1 LOS signal is detected. 0: Disabled 1: Enabled 2 HOLDOVER _VTUNE_DET 0 Enables the DAC Vtune rail detections. When the DAC achieves a specified Vtune, if this bit is enabled, the current clock input is considered invalid and an input clock switch event is generated. 0: Disabled 1: Enabled 1 HOLDOVER _HITLESS _SWITCH 1 Determines whether a clock switch event will enter holdover use hitless switching. 0: Hard Switch 1: Hitless switching (has an undefined switch time) 0 HOLDOVER_EN 1 Sets whether holdover mode is active or not. 0: Disabled 1: Enabled 6.3.6.7 Description HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0] HOLDOVER_DLD_CNT[13:0] MSB LSB 0x151[5:0] 0x152[7:0] This register has the number of valid clocks of PLL1 PDF before holdover is exited. Registers 0x151 and 0x152 Bit Registers Name POR Default 7:6 0x151 NA 0 Description Reserved The number of valid clocks of PLL1 PDF before holdover mode is exited. 5:0 7:0 72 0x151 0x152 HOLDOVER _DLD_CNT[13:8] HOLDOVER _DLD_CNT[7:0] 2 0 Field Value Count Value 0 (0x00) 0 1 (0x01) 1 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.7 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 (0x153 - 0x15F) PLL1 Configuration 6.3.7.1 CLKin0_R[13:8], CLKin0_R[7:0] CLKin0_R[13:0] MSB LSB 0x153[5:0] 0x154[7:0] These registers contain the value of the CLKin0 divider. Bit Registers Name POR Default 7:6 0x153 NA 0 Description Reserved The value of PLL1 N counter when CLKin0 is selected. 5:0 0x153 7:0 0x154 6.3.7.2 CLKin0_R[13:8] 0 CLKin0_R[7:0] 120 Field Value Divide Value 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 CLKin1_R[13:8], CLKin1_R[7:0] CLKin1_R[13:0] MSB LSB 0x155[5:0] 0x156[7:0] These registers contain the value of the CLKin1 R divider. REGISTERS 0x155 and 0x156 Bit Registers Name POR Default 7:6 0x155 NA 0 Description Reserved The value of PLL1 N counter when CLKin1 is selected. 5:0 7:0 0x155 0x156 CLKin1_R[13:8] CLKin1_R[7:0] Copyright © 2013, Texas Instruments Incorporated 0 150 Field Value Divide Value 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 73 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.7.3 www.ti.com CLKin2_R[13:8], CLKin2_R[7:0] MSB LSB 0x157[5:0] 0x158[7:0] REGISTERS 0x157 and 0x158 Bit Registers Name POR Default 7:6 0x157 NA 0 Description Reserved The value of PLL1 N counter when CLKin2 is selected. 5:0 0x157 7:0 0x158 6.3.7.4 CLKin2_R[13:8] 0 CLKin2_R[7:0] 150 Field Value Divide Value 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 ... ... 16382 (0x3FFE) 16382 16383 (0x3FFF) 16383 PLL1_N PLL1_N[13:8], PLL1_N[7:0] PLL1_N[13:0] MSB LSB 0x159[5:0] 0x15A[7:0] These registers contain the N divider value for PLL1. REGISTERS 0x159 and 0x15A Bit Registers Name POR Default 7:6 0x159 NA 0 Description Reserved The value of PLL1 N counter. 5:0 7:0 74 0x159 0x15A PLL1_N[13:8] PLL1_N[7:0] 0 120 Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 ... ... 4,095 (0xFFF) 4,095 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.7.5 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 PLL1_WND_SIZE, PLL1_CP_TRI, PLL1_CP_POL, PLL1_CP_GAIN This register controls the PLL1 phase detector. REGISTER 0x15B Bit Name POR Default Description PLL1_WND_SIZE sets the window size used for digital lock detect for PLL1. If the phase error between the reference and feedback of PLL1 is less than specified time, then the PLL1 lock counter increments. 7:6 5 4 PLL1_WND_SIZE PLL1_CP_TRI PLL1_CP_POL 3 Field Value Definition 0 (0x00) 4 ns 1 (0x01) 9 ns 2 (0x02) 19 ns 3 (0x03) 43 ns 0 This bit allows for the PLL1 charge pump output pin, CPout1, to be placed into TRI-STATE. 0: PLL1 CPout1 is active 1: PLL1 CPout1 is at TRI-STATE 1 PLL1_CP_POL sets the charge pump polarity for PLL1. Many VCXOs use positive slope. A positive slope VCXO increases output frequency with increasing voltage. A negative slope VCXO decreases output frequency with increasing voltage. 0: Negative Slope VCO/VCXO 1: Positive Slope VCO/VCXO This bit programs the PLL1 charge pump output current level. 3:0 PLL1_CP_GAIN 4 Copyright © 2013, Texas Instruments Incorporated Field Value Gain 0 (0x00) 50 µA 1 (0x01) 150 µA 2 (0x02) 250 µA 3 (0x03) 350 µA 4 (0x04) 450 µA ... ... 14 (0x0E) 1450 µA 15 (0x0F) 1550 µA GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 75 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.7.6 www.ti.com PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0] PLL1_DLD_CNT[13:0] MSB LSB 0x15C[5:0] 0x15D[7:0] This register contains the value of the PLL1 DLD counter. REGISTERS 0x15C and 0x15D Bit Registers Name POR Default 7:6 0x15C NA 0 5:0 7:0 76 0x15C 0x15D Description Reserved The reference and feedback of PLL1 must be within the window of phase error as specified by PLL1_WND_SIZE for this many phase detector cycles before PLL1 digital lock detect is asserted. PLL1_DLD _CNT[13:8] 32 PLL1_DLD _CNT[7:0] 0 Field Value Delay Value 0 (0x00) Reserved 1 (0x01) 1 2 (0x02) 2 3 (0x03) 3 ... ... 16,382 (0x3FFE) 16,382 16,383 (0x3FFF) 16,383 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.7.7 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 PLL1_R_DLY, PLL1_N_DLY This register contains the delay value for PLL1 N and R delays. REGISTER 0x15E Bit Name POR Default 7:6 NA 0 Description Reserved Increasing delay of PLL1_R_DLY will cause the outputs to lag from CLKinX. For use in 0delay mode. 5:3 PLL1_R_DLY 0 Field Value Gain 0 (0x00) 0 ps 1 (0x01) 205 ps 2 (0x02) 410 ps 3 (0x03) 615 ps 4 (0x04) 820 ps 5 (0x05) 1025 ps 6 (0x06) 1230 ps 7 (0x07) 1435 ps Increasing delay of PLL1_N_DLY will cause the outputs to lead from CLKinX. For use in 0delay mode. Field Value 2:0 PLL1_N_DLY 0 Copyright © 2013, Texas Instruments Incorporated Gain 0 (0x00) 0 ps 1 (0x01) 205 ps 2 (0x02) 410 ps 3 (0x03) 615 ps 4 (0x04) 820 ps 5 (0x05) 1025 ps 6 (0x06) 1230 ps 7 (0x07) 1435 ps GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 77 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.7.8 www.ti.com PLL1_LD_MUX, PLL1_LD_TYPE This register configures the PLL1 LD pin. REGISTER 0x15F Bit Name POR Default Description This sets the output value of the Status_LD1 pin. Field Value 7:3 PLL1_LD_MUX 1 MUX Value 0 (0x00) Logic Low 1 (0x01) PLL1 DLD 2 (0x02) PLL2 DLD 3 (0x03) PLL1 & PLL2 DLD 4 (0x04) Holdover Status 5 (0x05) DAC Locked 6 (0x06) Reserved 7 (0x07) SPI Readback 8 (0x08) DAC Rail 9 (0x09) DAC Low 10 (0x0A) DAC High 11 (0x0B) PLL1_N 12 (0x0C) PLL1_N/2 13 (0x0D) PLL2_N 14 (0x0E) PLL2_N/2 15 (0x0F) PLL1_R 16 (0x10) PLL1_R/2 17 (0x11) PLL2_R (1) 18 (0x12) PLL2_R/2 (1) Sets the IO type of the Status_LD1 pin. 2:0 (1) 78 PLL1_LD_TYPE 6 Field Value TYPE 0 (0x00) Reserved 1 (0x01) Reserved 2 (0x02) Reserved 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (push-pull) 5 (0x05) Reserved 6 (0x06) Output (open drain) Only valid when PLL2_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD). GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.8 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 (0x160 - 0x16E) PLL2 Configuration 6.3.8.1 PLL2_R[11:8], PLL2_R[7:0] PLL2_R[11:0] MSB LSB 0x160[3:0] 0x161[7:0] This register contains the value of the PLL2 R divider. REGISTERS 0x160 and 0x161 Bit Registers Name POR Default 7:4 0x160 NA 0 Description Reserved Valid values for the PLL2 R divider. 3:0 7:0 0x160 0x161 PLL2_R[11:8] PLL2_R[7:0] Copyright © 2013, Texas Instruments Incorporated 0 2 Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 3 (0x03) 3 ... ... 4,094 (0xFFE) 4,094 4,095 (0xFFF) 4,095 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 79 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.8.2 www.ti.com PLL2_P, OSCin_FREQ, PLL2_XTAL_EN, PLL2_REF_2X_EN This register sets other PLL2 functions. REGISTER 0x162 Bit Name POR Default Description The PLL2 N Prescaler divides the output of the VCO as selected by Mode_MUX1 and is connected to the PLL2 N divider. 7:5 PLL2_P 2 Field Value Value 0 (0x00) 8 1 (0x01) 2 2 (0x02) 2 3 (0x03) 3 4 (0x04) 4 5 (0x05) 5 6 (0x06) 6 7 (0x07) 7 The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin* port) must be programmed in order to support proper operation of the frequency calibration routine which locks the internal VCO to the target frequency. Field Value 4:2 1 0 80 OSCin_FREQ PLL2_XTAL_EN PLL2_REF_2X_EN 7 OSCin Frequency 0 (0x00) 0 to 63 MHz 1 (0x01) >63 MHz to 127 MHz 2 (0x02) >127 MHz to 255 MHz 3 (0x03) Reserved 4 (0x04) >255 MHz to 500 MHz 5 (0x05) to 7(0x07) Reserved 0 If an external crystal is being used to implement a discrete VCXO, the internal feedback amplifier must be enabled with this bit in order to complete the oscillator circuit. 0: Oscillator Amplifier Disabled 1: Oscillator Amplifier Enabled 1 Enabling the PLL2 reference frequency doubler allows for higher phase detector frequencies on PLL2 than would normally be allowed with the given VCXO or Crystal frequency. Higher phase detector frequencies reduces the PLL N values which makes the design of wider loop bandwidth filters possible. 0: Doubler Disabled 1: Doubler Enabled GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.8.3 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 PLL2_N_CAL PLL2_N_CAL[17:0] PLL2 never uses 0-delay during frequency calibration. These registers contain the value of the PLL2 N divider used with PLL2 pre-scaler during calibration for cascaded 0-delay mode. Once calibration is complete, PLL2 will use PLL2_N value. Cascaded 0-delay mode occurs when PLL2_NCLK_MUX = 1. MSB — LSB 0x163[1:0] 0x164[7:0] 0x165[7:0] REGISTERS 0x163, 0x164, and 0x165 Bit Registers Name POR Default 7:2 0x163 NA 0 1:0 0x163 PLL2_N _CAL[17:16] 0 7:0 0x164 PLL2_N_CAL[15:8] 0 7:0 0x165 PLL2_N_CAL[7:0] 12 6.3.8.4 Description Reserved Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 ... ... 262,143 (0x3FFFF) 262,143 PLL2_FCAL_DIS, PLL2_N PLL2_N[17:0] This register disables frequency calibration and sets the PLL2 N divider value. Programming register 0x168 starts a VCO calibration routine if PLL2_FCAL_DIS = 0. MSB — LSB 0x166[1:0] 0x167[7:0] 0x168[7:0] REGISTERS 0x166, 0x167, and 0x168 Bit Registers Name POR Default 7:3 0x166 NA 0 Reserved 2 0x166 PLL2_FCAL_DIS 0 This disables the PLL2 frequency calibration on programming register 0x168. 0: Frequency calibration enabled 1: Frequency calibration disabled 1:0 0x166 PLL2_N[17:16] 0 7:0 7:0 0x167 0x168 PLL2_N[15:8] PLL2_N[7:0] Copyright © 2013, Texas Instruments Incorporated 0 12 Description Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 ... ... 262,143 (0x3FFFF) 262,143 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 81 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.8.5 www.ti.com PLL2_WND_SIZE, PLL2_CP_GAIN, PLL2_CP_POL, PLL2_CP_TRI This register controls the PLL2 phase detector. REGISTER 0x169 Bit Name POR Default 7 NA 0 Description Reserved PLL2_WND_SIZE sets the window size used for digital lock detect for PLL2. If the phase error between the reference and feedback of PLL2 is less than specified time, then the PLL2 lock counter increments. This value must be programmed to 2 (3.7 ns). 6:5 PLL2_WND_SIZE 2 Field Value Definition 0 (0x00) Reserved 1 (0x01) Reserved 2 (0x02) 3.7 ns 3 (0x03) Reserved This bit programs the PLL2 charge pump output current level. The table below also illustrates the impact of the PLL2 TRISTATE bit in conjunction with PLL2_CP_GAIN. 4:3 2 82 PLL2_CP_GAIN PLL2_CP_POL 3 0 Field Value Definition 0 (0x00) 100 µA 1 (0x01) 400 µA 2 (0x02) 1600 µA 3 (0x03) 3200 µA PLL2_CP_POL sets the charge pump polarity for PLL2. The internal VCO requires the negative charge pump polarity to be selected. Many VCOs use positive slope. A positive slope VCO increases output frequency with increasing voltage. A negative slope VCO decreases output frequency with increasing voltage. Field Value Description 0 Negative Slope VCO/VCXO 1 Positive Slope VCO/VCXO 1 PLL2_CP_TRI 0 PLL2_CP_TRI TRI-STATEs the output of the PLL2 charge pump. 0: Disabled 1: TRI-STATE 0 Fixed Value 1 When programming register 0x169, this field must be set to 1. GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.8.6 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 SYSREF_REQ_EN, PLL2_DLD_CNT PLL2_DLD_CNT[15:0] MSB LSB 0x16A[5:0] 0x16B[7:0] This register has the value of the PLL2 DLD counter. REGISTERS 0x16A and 0x16B Bit Registers Name POR Default 7 0x16A NA 0 Reserved 6 0x16A SYSREF_REQ_EN 0 Enables the SYNC/SYSREF_REQ pin to force the SYSREF_MUX = 3 for continuous pulses. When using this feature enable pulser and set SYSREF_MUX = 2 (Pulsor). 5:0 7:0 0x16A 0x16B PLL2_DLD _CNT[13:8] PLL2_DLD_CNT Copyright © 2013, Texas Instruments Incorporated Description The reference and feedback of PLL2 must be within the window of phase error as specified by PLL2_WND_SIZE for PLL2_DLD_CNT cycles before PLL2 digital lock detect is asserted. 32 0 Field Value Divide Value 0 (0x00) Not Valid 1 (0x01) 1 2 (0x02) 2 3 (0x03) 3 ... ... 16,382 (0x3FFE) 16,382 16,383 (0x3FFF) 16,383 GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 83 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.8.7 www.ti.com PLL2_LF_R4, PLL2_LF_R3 This register controls the integrated loop filter resistors. REGISTER 0x16C Bit Name POR Default 7:6 NA 0 Description Reserved Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components. Internal loop filter resistor R4 can be set according to the following table. 5:3 PLL2_LF_R4 0 Field Value Resistance 0 (0x00) 200 Ω 1 (0x01) 1 kΩ 2 (0x02) 2 kΩ 3 (0x03) 4 kΩ 4 (0x04) 16 kΩ 5 (0x05) Reserved 6 (0x06) Reserved 7 (0x07) Reserved Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components. Internal loop filter resistor R3 can be set according to the following table. 2:0 84 PLL2_LF_R3 0 Field Value Resistance 0 (0x00) 200 Ω 1 (0x01) 1 kΩ 2 (0x02) 2 kΩ 3 (0x03) 4 kΩ 4 (0x04) 16 kΩ 5 (0x05) Reserved 6 (0x06) Reserved 7 (0x07) Reserved GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.8.8 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 PLL2_LF_C4, PLL2_LF_C3 This register controls the integrated loop filter capacitors. REGISTER 0x16D Bit Name POR Default Description Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components. Internal loop filter capacitor C4 can be set according to the following table. 7:4 PLL2_LF_C4 0 Field Value Resistance 0 (0x00) 10 pF 1 (0x01) 15 pF 2 (0x02) 29 pF 3 (0x03) 34 pF 4 (0x04) 47 pF 5 (0x05) 52 pF 6 (0x06) 66 pF 7 (0x07) 71 pF 8 (0x08) 103 pF 9 (0x09) 108 pF 10 (0x0A) 122 pF 11 (0x0B) 126 pF 12 (0x0C) 141 pF 13 (0x0D) 146 pF 14 (0x0E) Reserved 15 (0x0F) Reserved Internal loop filter components are available for PLL2, enabling either 3rd or 4th order loop filters without requiring external components. Internal loop filter capacitor C3 can be set according to the following table. 3:0 PLL2_LF_C3 0 Copyright © 2013, Texas Instruments Incorporated Field Value Resistance 0 (0x00) 10 pF 1 (0x01) 11 pF 2 (0x02) 15 pF 3 (0x03) 16 pF 4 (0x04) 19 pF 5 (0x05) 20 pF 6 (0x06) 24 pF 7 (0x07) 25 pF 8 (0x08) 29 pF 9 (0x09) 30 pF 10 (0x0A) 33 pF 11 (0x0B) 34 pF 12 (0x0C) 38 pF 13 (0x0D) 39 pF 14 (0x0E) Reserved 15 (0x0F) Reserved GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 85 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 6.3.8.9 www.ti.com PLL2_LD_MUX, PLL2_LD_TYPE This register sets the output value of the Status_LD2 pin. REGISTER 0x16E Bit Name POR Default Description This sets the output value of the Status_LD2 pin. Field Value 7:3 PLL2_LD_MUX 2 MUX Value 0 (0x00) Logic Low 1 (0x01) PLL1 DLD 2 (0x02) PLL2 DLD 3 (0x03) PLL1 & PLL2 DLD 4 (0x04) Holdover Status 5 (0x05) DAC Locked 6 (0x06) Reserved 7 (0x07) SPI Readback 8 (0x08) DAC Rail 9 (0x09) DAC Low 10 (0x0A) DAC High 11 (0x0B) PLL1_N 12 (0x0C) PLL1_N/2 13 (0x0D) PLL2_N 14 (0x0E) PLL2_N/2 15 (0x0F) PLL1_R 16 (0x10) PLL1_R/2 17 (0x11) PLL2_R (1) 18 (0x12) PLL2_R/2 (1) Sets the IO type of the Status_LD2 pin. 2:0 (1) 86 PLL2_LD_TYPE 6 Field Value TYPE 0 (0x00) Reserved 1 (0x01) Reserved 2 (0x02) Reserved 3 (0x03) Output (push-pull) 4 (0x04) Output inverted (push-pull) 5 (0x05) Reserved 6 (0x06) Output (open drain) Only valid when PLL1_LD_MUX is not set to 2 (PLL2_DLD) or 3 (PLL1 & PLL2 DLD). GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.9 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 (0x16F - 0x1FFF) Misc Registers 6.3.9.1 PLL2_PRE_PD, PLL2_PD REGISTER 0x173 Bit Name 7 N/A 6 PLL2_PRE_PD 5 PLL2_PD 4:0 N/A 6.3.9.2 Description Reserved Powerdown PLL2 prescaler 0: Normal Operation 1: Powerdown Powerdown PLL2 0: Normal Operation 1: Powerdown Reserved OPT_REG_1 This register must be written with the following value depending on which LMK04820 family part is used to optimize VCO1 phase noise performance over temperature. This register must be written before writing register 0x168 when using VCO1. REGISTER 0x17C Bit Name 7:0 OPT_REG_1 6.3.9.3 Description 24: LMK04826 21: LMK04828 OPT_REG_2 This register must be written with the following value depending on which LMK04820 family part is used to optimize VCO1 phase noise performance over temperature. This register must be written before writing register 0x168 when using VCO1. REGISTER 0x17D Bit Name 7:0 OPT_REG_2 6.3.9.4 Description 119: LMK04826 51: LMK04828 RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST REGISTER 0x182 Bit Name 7:3 N/A 2 RB_PLL1_LD_LOST 1 RB_PLL1_LD 0 CLR_PLL1_LD_LOST 6.3.9.5 Description Reserved This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD is low. Read back 0: PLL1 DLD is high. Read back 1: PLL1 DLD is low. To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0. 0: RB_PLL1_LD_LOST will be set on next falling PLL1 DLD edge. 1: RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL1_LD_LOST to become set again. RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST REGISTER 0x0x183 Bit Name 7:3 N/A 2 RB_PLL2_LD_LOST 1 RB_PLL2_LD Description Reserved This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD is low. Read back 0: PLL2 DLD is high. Read back 1: PLL2 DLD is low. Copyright © 2013, Texas Instruments Incorporated GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 87 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Bit Name 0 Description CLR_PLL2_LD_LOST 6.3.9.6 www.ti.com To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0. 0: RB_PLL2_LD_LOST will be set on next falling PLL2 DLD edge. 1: RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL2_LD_LOST to become set again. RB_DAC_VALUE(MSB), RB_CLKinX_SEL, RB_CLKinX_LOS This register provides read back access to CLKinX selection indicator and CLKinX LOS indicator. The 2 MSBs are shared with the RB_DAC_VALUE. See RB_DAC_VALUE section. REGISTER 0x184 Bit Name 7:6 RB_DAC_VALUE[9:8] 5 RB_CLKin2_SEL Read back 0: CLKin2 is not selected for input to PLL1. Read back 1: CLKin2 is selected for input to PLL1. 4 RB_CLKin1_SEL Read back 0: CLKin1 is not selected for input to PLL1. Read back 1: CLKin1 is selected for input to PLL1. 3 RB_CLKin0_SEL Read back 0: CLKin0 is not selected for input to PLL1. Read back 1: CLKin0 is selected for input to PLL1. 2 N/A 1 RB_CLKin1_LOS Read back 1: CLKin1 LOS is active. Read back 0: CLKin1 LOS is not active. 0 RB_CLKin0_LOS Read back 1: CLKin0 LOS is active. Read back 0: CLKin0 LOS is not active. 6.3.9.7 Description See RB_DAC_VALUE section. RB_DAC_VALUE Contains the value of the DAC for user readback. Field Name RB_DAC_VALUE MSB LSB 0x184 [7:6] 0x185 [7:0] REGISTERS 0x184 and 0x185 Bit Registers Name POR Default 7:6 0x184 RB_DAC_ VALUE[9:8] 2 7:0 0x185 RB_DAC_ VALUE[7:0] 0 6.3.9.8 Description DAC value is 512 on power on reset, if PLL1 locks upon power-up the DAC value will change. RB_HOLDOVER Blank REGISTER 0x188 88 Bit Name 7:5 N/A 4 RB_HOLDOVER 3:0 N/A Description Reserved Read back 0: Not in HOLDOVER. Read back 1: In HOLDOVER. Reserved GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B Copyright © 2013, Texas Instruments Incorporated LMK04826B, LMK04828B www.ti.com 6.3.9.9 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 SPI_LOCK Prevents SPI registers from being written to, except for 0x1FFD, 0x1FFE, 0x1FFF. These registers must be written to sequentially and in order: 0x1FFD, 0x1FFE, 0x1FFF. These registers cannot be read back. MSB — LSB 0x1FFD [7:0] 0x1FFE [7:0] 0x1FFF [7:0] REGISTERS 0x1FFD, 0x1FFE, and 0x1FFF Bit Registers Name POR Default 7:0 0x1FFD SPI_LOCK[23:16] 0 0: Registers unlocked. 1 to 255: Registers locked 7:0 0x1FFE SPI_LOCK[15:8] 0 0: Registers unlocked. 1 to 255: Registers locked 7:0 0x1FFF SPI_LOCK[7:0] 83 0 to 82: Registers locked 83: Registers unlocked 84 to 256: Registers locked Copyright © 2013, Texas Instruments Incorporated Description GENERAL PROGRAMMING INFORMATION Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 89 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 www.ti.com 7 APPLICATION INFORMATION 7.1 Digital Lock Detect Frequency Accuracy The digital lock detect circuit is used to determine PLL1 locked, PLL2 locked, and holdover exit events. A window size and lock count register are programmed to set a ppm frequency accuracy of reference to feedback signals of the PLL for each event to occur. When a PLL digital lock event occurs the PLL's digital lock detect is asserted true. When the holdover exit event occurs, the device will exit holdover mode. Event PLL Window size Lock count PLL1 Locked PLL1 PLL1_WND_SIZE PLL1_DLD_CNT PLL2 Locked PLL2 PLL2_WND_SIZE PLL2_DLD_CNT Holdover exit PLL1 PLL1_WND_SIZE HOLDOVER_DLD_CNT For a digital lock detect event to occur there must be a “lock count” number of phase detector cycles of PLLX during which the time/phase error of the PLLX_R reference and PLLX_N feedback signal edges are within the user programmable "window size." Since there must be at least "lock count" phase detector events before a lock event occurs, a minimum digital lock event time can be calculated as "lock count" / fPDX where X = 1 for PLL1 or 2 for PLL2. By using Equation 1, values for a "lock count" and "window size" can be chosen to set the frequency accuracy required by the system in ppm before the digital lock detect event occurs: ppm = 1e6 × PLLX_WND_SIZE × fPDX PLLX_DLD_CNT (1) The effect of the "lock count" value is that it shortens the effective lock window size by dividing the "window size" by "lock count". If at any time the PLLX_R reference and PLLX_N feedback signals are outside the time window set by "window size", then the “lock count” value is reset to 0. 7.1.1 Minimum Lock Time Calculation Example To calculate the minimum PLL2 digital lock time given a PLL2 phase detector frequency of 40 MHz and PLL2_DLD_CNT = 10,000. Then the minimum lock time of PLL2 will be 10,000 / 40 MHz = 250 µs. 7.2 7.2.1 Pin Connection Recommendations VCC PINS AND DECOUPLING All Vcc pins must always be connected. 7.2.2 UNUSED CLOCK OUTPUTS Leave unused clock outputs floating and powered down. 7.2.3 UNUSED CLOCK INPUTS Unused clock inputs can be left floating. 90 APPLICATION INFORMATION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 7.3 7.3.1 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Driving CLKin AND OSCin Inputs DRIVING CLKin PINS WITH A DIFFERENTIAL SOURCE Both CLKin ports can be driven by differential signals. It is recommended that the input mode be set to bipolar (CLKinX_BUF_TYPE = 0) when using differential reference clocks. The LMK04820 family internally biases the input pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with either LVDS or LVPECL are shown in Figure 7-1 and Figure 7-2. 100: Trace (Differential) LVDS 100: CLKinX 0.1 PF LMK048XX Input 0.1 PF CLKinX* 240: Figure 7-1. CLKinX/X* Termination for an LVDS Reference Clock Source LVPECL Ref Clk 0.1 PF 0.1 PF 100: Trace (Differential) 100: CLKinX 0.1 PF LMK048XX Input 0.1 PF 240: CLKinX* Figure 7-2. CLKinX/X* Termination for an LVPECL Reference Clock Source Finally, a reference clock source that produces a differential sine wave output can drive the CLKin pins using the following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in the Section 2.4 table. 100: Trace (Differential) Differential Sinewave Clock Source 100: CLKinX 0.1 PF 0.1 PF LMK048XX Input CLKinX* Figure 7-3. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source APPLICATION INFORMATION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 91 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 7.3.2 www.ti.com DRIVING CLKin PINS WITH A SINGLE-ENDED SOURCE The CLKin pins of the LMK04820 family can be driven using a single-ended reference clock source, for example, either a sine wave source or an LVCMOS/LVTTL source. Either AC coupling or DC coupling may be used. In the case of the sine wave source that is expecting a 50 Ω load, it is recommended that AC coupling be used as shown in the circuit below with a 50 Ω termination. NOTE The signal level must conform to the requirements for the CLKin pins listed in the Section 2.4 table. CLKinX_BUF_TYPE is recommended to be set to bipolar mode (CLKinX_BUF_TYPE = 0). 0.1 PF 50: Trace Clock Source CLKinX 50: 0.1 PF LMK048XX CLKinX* Figure 7-4. CLKinX/X* Single-ended Termination If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC coupling may be used. If DC coupling is used, the CLKinX_BUF_TYPE should be set to MOS buffer mode (CLKinX_BUF_TYPE = 1) and the voltage swing of the source must meet the specifications for DC coupled, MOS-mode clock inputs given in the table of Section 2.4. If AC coupling is used, the CLKinX_BUF_TYPE should be set to the bipolar buffer mode (CLKinX_BUF_TYPE = 0). The voltage swing at the input pins must meet the specifications for AC coupled, bipolar mode clock inputs given in the table of Section 2.4. In this case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC coupling capacitor is sufficient. Figure 7-5. DC Coupled LVCMOS/LVTTL Reference Clock 92 APPLICATION INFORMATION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com 7.4 SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Power Supply 7.4.1 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS From Table 7-1 the current consumption can be calculated for any configuration. Data below is typical and not assured. Table 7-1. Typical Current Consumption for Selected Functional Blocks (TA = 25 °C, VCC = 3.3 V) Typical ICC (mA) Power dissipat ed in device (mW) Power dissipat ed externall y (mW) 131.5 433.95 - 6 19.8 - 3 9.9 - Block Condition Core Dual Loop, Internal VCO0 VCO VCO1 is selected OSCin Doubler Doubler is enabled CLKin Any one of the CLKinX is enabled 4.9 16.17 - Holdover is enabled HOLDOVER_EN = 1 1.3 4.29 - Hitless switch is enabled HOLDOVER_HITLESS_S WITCH = 1 0.9 2.97 - Track mode Core and Functional Blocks Holdover SYNC_EN = 1 SYSREF PLL1 and PLL2 locked EN_PLL2_REF_2X = 1 TRACK_EN = 1 2.5 8.25 - Required for SYNC and SYSREF functionality 7.6 25.08 - Enabled SYSREF_PD = 0 27.2 89.76 - Dynamic Digital Delay enabled SYSREF_DDLY_PD = 0 5 16.5 - Pulser is enabled SYSREF_PLSR_PD = 0 4.1 13.53 SYSREF Pulses mode SYSREF_MUX = 2 3 9.9 SYSREF Continuous mode SYSREF_MUX = 3 3 9.9 66.33 Clock Group Enabled Any one of the CLKoutX_Y_PD = 0 20.1 IDL Any one of the CLKoutX_Y_IDL = 1 2.2 7.26 ODL Andy one of the CLKoutX_Y_ODL = 1 3.2 10.56 Divider Only DCLKoutX_MUX = 0 13.6 44.88 Divider + DCC + HS DCLKoutX_MUX = 1 17.7 58.41 Analog Delay + Divider DCLKoutX_MUX = 3 13.6 44.88 Clock Divider Clock Output Buffers LVDS HSDS 100 Ω differential termination 6 19.8 - HSDS 6 mA, 100 Ω differential termination 8.8 29.04 - HSDS 8 mA, 100 Ω differential termination 11.6 38.28 - HSDS 10 mA, 100 Ω differential termination 19.4 64.02 - OSCout Buffers LVDS LVCMOS 100 Ω differential termination 18.5 61.05 - LVCMOS Pair 150 MHz 42.6 140.58 - LVCMOS Single 150 MHz 27 89.1 - APPLICATION INFORMATION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 93 LMK04826B, LMK04828B SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 7.5 www.ti.com Thermal Management Power consumption of the LMK04820 family of devices can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125°C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125°C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. 7.2 mm 0.2 mm 1.46 mm 1.15 mm Figure 7-6. Recommended Land and Via Pattern 94 APPLICATION INFORMATION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B LMK04826B, LMK04828B www.ti.com SNAS605 AP – MARCH 2013 – REVISED JUNE 2013 Changes from Revision AO (March 2013) to Revision AP • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Page Changed datasheet title from LMK04828 to LMK0482xB ...................................................................... 1 Added LMK04826 to frequency table ............................................................................................. 1 Changed - increased LMK04828B VCO0 maximum frequency from 2600 MHz to 2630 MHz ............................ 1 Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz ......... 1 Changed image from LMK04828B to LMK0482xB .............................................................................. 1 Changed LMK04828 family to LMK04820 family ................................................................................ 2 Added LMK04826 to Device Configuration Information Table ................................................................. 2 Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz .................................. 2 Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz ......... 2 Changed image from LMK04828 to LMK0482xB ................................................................................ 3 Changed - corrected value of PLL2_P selection to be 0 to correspond with register programming definition. .......... 3 Changed image from LMK04828 to LMK0482xB ................................................................................ 4 Changed image from LMK04828 to LMK0482xB ................................................................................ 5 Changed thermal table header from LMK04828B to LMK0482xB ........................................................... 10 Added LMK04826 VCO Range Specification ................................................................................... 14 Changed - increased LMK04828B VCO0 max frequency from 2600 MHz to 2630 MHz ................................. 14 Changed - expanded LMK04828B VCO1 frequency range from 2945 - 3005 MHz to 2920 MHz - 3080 MHz ....... 14 Added LMK04826 KVCO Specification ............................................................................................ 14 Added clarification of LMK04828 specification vs LMK04826 specification for KVCO ...................................... 14 Added LMK04826 noise floor data ............................................................................................... 15 Changed - clarified phase noise data section header ......................................................................... 16 Added LMK04826 phase noise data ............................................................................................. 16 Added LMK04826 jitter data ...................................................................................................... 18 Added LMK04826 fCLKout-startup spec .............................................................................................. 20 Added clarification of LMK04828 specification vs. LMK04826 specification for fCLKout-startup .............................. 20 Added LMK04826B Phase Noise Performance Graph for VCO0 ............................................................ 26 Added LMK04826B Phase Noise Performance Graph for VCO1 ............................................................ 26 Added Added PLL2 loop filter bandwidth and phase margin info to plot .................................................... 27 Changed LMK04828 to LMK0482xB in VCXO/Crystal Buffered Output section ........................................... 28 Changed LMK04828 to LMK0482xB in Status Pins section .................................................................. 31 Added LMK04826 register setting ................................................................................................ 52 Added LMK04826 register setting ................................................................................................ 87 Added LMK04826 register setting ................................................................................................ 87 APPLICATION INFORMATION Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links :LMK04826B, LMK04828B 95 PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) LMK04826BISQ/NOPB ACTIVE WQFN NKD 64 1000 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR K04826BISQ LMK04826BISQE/NOPB ACTIVE WQFN NKD 64 250 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR K04826BISQ LMK04826BISQX/NOPB ACTIVE WQFN NKD 64 2000 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR K04826BISQ LMK04828BISQ/NOPB ACTIVE WQFN NKD 64 1000 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR K04828BISQ LMK04828BISQE/NOPB ACTIVE WQFN NKD 64 250 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR K04828BISQ LMK04828BISQX/NOPB ACTIVE WQFN NKD 64 2000 Green (RoHS & no Sb/Br) SN Level-3-260C-168 HR K04828BISQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 3-Jul-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMK04826BISQ/NOPB WQFN NKD 64 LMK04826BISQE/NOPB WQFN NKD LMK04826BISQX/NOPB WQFN NKD LMK04828BISQ/NOPB WQFN LMK04828BISQE/NOPB LMK04828BISQX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 64 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 64 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 NKD 64 1000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 WQFN NKD 64 250 178.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 WQFN NKD 64 2000 330.0 16.4 9.3 9.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMK04826BISQ/NOPB WQFN NKD 64 1000 367.0 367.0 38.0 LMK04826BISQE/NOPB WQFN NKD 64 250 213.0 191.0 55.0 LMK04826BISQX/NOPB WQFN NKD 64 2000 367.0 367.0 38.0 LMK04828BISQ/NOPB WQFN NKD 64 1000 367.0 367.0 38.0 LMK04828BISQE/NOPB WQFN NKD 64 250 213.0 191.0 55.0 LMK04828BISQX/NOPB WQFN NKD 64 2000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA NKD0064A SQA64A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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