EtronTech EM562081 256K x 8 Low Power SRAM Preliminary, Rev 1.0 7/2001 Features • Single power supply voltage of 2.7V to 3.6V • Power down features using CE1# and CE2 • Low operating current : 25mA(max. for 70 ns) • Maximum Standby current : 10µA at 3.6 V • Data retention supply voltage: 1.5V to 3.6V • Direct TTL compatibility for all input and output • Wide operating temperature range: -40°C to 85°C • Package type: 36-ball TFBGA, 6x8mm asserted low. There are three control inputs. CE1# and CE2 are used to select the device and for data retention control, and output enable (OE#) provides fast memory access. Data byte control pin (LB#,UB#) provides lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating range from -40°C to 85°C, the EM562081 can be used in environments exhibiting extreme temperature conditions. Pin Assignment Ordering Information Part Number Speed IDDS2 Package EM562081BC-70 70 ns 10 µA 6x8 BGA EM562081BC-85 85 ns 10 µA 6x8 BGA Pin Names Symbol Function A0 - A17 Address Inputs DQ0-DQ7 Data Inputs/Outputs CE1#,CE2 Chip Enable Inputs OE# Output Enable WE# Read/Write Control Input GND Ground VDD Power Supply NC No Connection 1. 36-Ball BGA (CSP), Top View 1 2 3 4 5 6 A A0 A1 CE 2 A3 A6 A8 B DQ 4 A2 WE# A4 A7 DQ 0 C DQ 5 NC A5 D G ND V DD E V DD G ND F DQ 6 G DQ 7 H A9 DQ 1 NC A1 7 DQ 2 O E# C E 1# A16 A15 DQ 3 A1 0 A1 1 A12 A13 A14 Overview The EM562081 is a 2,097,152-bit SRAM organized as 262,144 words by 8 bits. It is designed with advanced CMOS technology. This Device operates from a single 2.7V to 3.6V power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when chip enable (CE1#) is asserted high or (CE2) is Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech EM562081 Block Diagram A0 VDD MEMORY CELL ARRAY 256KX8 GND A17 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SENSE AMP COLUMN ADDRESS DECODER WE# CE1# CE2 OE# POWER DOWN CIRCUIT Preliminary 2 Rev 1.0 July 2001 EtronTech EM562081 Operating Mode Mode CE1# CE2 OE# WE# DQ0~DQ7 Power Read L H L H DOUT Active Write L H X L DIN Active Output Deselect L H H H High-Z Active H X X X High-Z Standby X L X X High-Z Standby Standby Note: X = don't care. H = logic high. L = logic low. Absolute Maximum Ratings Supply voltage, VDD -0.3 to +4.6V Input voltages, VIN -0.3 to +4.6V Input and output voltages, VI/O -0.5 to VDD + 0.5V Operating temperature, TOPR -40 to +85°C Storage temperature, TSTRG -55 to +150°C Soldering Temperature (10s), TSOLDER 240°C Power dissipation, PD 0.6 W DC Recommended Operating Conditions (Ta=-40° C to 85° C) Symbol Parameter Min Typ Max VDD Power Supply Voltage 2.7 − 3.6 VIH Input High Voltage VIL Input Low Voltage VDR Data Retention Supply Voltage 2.2 (2) -0.3 1.5 − Unit V (1) VDD + 0.3 V − 0.6 V − 3.6 V Note: (1) Overshoot : VDD +2.0V in case of pulse width ≤ 20ns (2) Undershoot : -2.0V in case of pulse width ≤ 20ns Preliminary 3 Rev 1.0 July 2001 EtronTech EM562081 DC Characteristics (Ta = -40° C to 85° C, VDD = 2.7V to 3.6V) Parameter Symbol Input low current IIL Test Conditions IIN = 0V to VDD Min Typ* Max Unit -1 − 1 µA Output low voltage VOL IOL = 2.1 mA - − 0.4 V Output high voltage VOH IOH = -1.0 mA 2.2 − − V IDD1 Cycle time = min − 10 25 IDD2 VDD = 3.6 V , CE1# = VIL and CE2 = VIH and IOUT = 0mA Other Input = VIH / VIL Cycle time = 1µs − − 5 IDDS1 CE1# = VIH or CE2 = VIL − − 0.5 mA − 1 10 µA Operating current Standby current mA IDDS2** CE1# ≥ VDD – 0.2V or CE2 ≤ 0.2V, (Note) Notes: * Typical value are measured at Ta = 25°C, and not 100% tested. ** In standby mode with CE1# ≥ VDD - 0.2V, these limits are assured for the condition CE2 ≥ VDD - 0.2V or CE2 ≤ 0.2V. Capacitance (Ta = 25° C; f = 1 MHz) Parameter Input capacitance Symbol Min Typ Max Unit CIN − − 10 pF Test Conditions VIN = GND COUT − − 10 pF VOUT = GND Notes: This parameter is periodically sampled and is not 100% tested. Output capacitance Preliminary 4 Rev 1.0 July 2001 EtronTech EM562081 AC Characteristics and Operating Conditions (Ta = -40° C to 85° C, V DD = 2.7V to 3.6V) Read Cycle EM562081 Symbol -85 Parameter -70 Unit Min Max Min Max tRC Read cycle time 85 − 70 − tAA Address access time − 85 − 70 tCO1 Chip Enable (CE1#) Access Time − 85 − 70 tCO2 Chip Enable (CE2) Access Time − 85 − 70 tOE Output enable access time − 45 − 35 tLZ Chip Enable Low to Output in Low-Z 10 − 10 − tOLZ Output enable Low to Output in Low-Z 3 − 3 − tHZ Chip Enable High to Output in High-Z − 35 − 25 tOHZ Output Enable High to Output in High-Z − 35 − 25 tOH Output Data Hold Time 10 − 10 − ns Write Cycle EM562081 Symbol -85 Parameter -70 Unit Min Max Min Max tWC Write cycle time 85 − 70 − tWP Write pulse width 55 − 55 − tCW Chip Enable to end of write 70 − 60 − tAS Address setup time 0 − 0 − tWR Write Recovery time 0 − 0 − tWHZ WE# Low to Output in High-Z − 35 − 30 tOW WE# High to Output in Low-Z 5 − 5 − tDS Data Setup Time 35 − 30 − tDH Data Hold Time 0 − 0 − ns AC Test Condition • Output load: 50pF + one TTL gate • Input pulse level: 0.4V, 2.4V • Timing measurements: 0.5 x VDD • tR, tF: 5ns Preliminary 5 Rev 1.0 July 2001 EtronTech EM562081 Read Cycle (See Note 1) tRC A ddr es s tOH tAA tCO1 CE 1# CE 2 tCO2 tHZ tOE O E# tOHZ tOLZ tLZ D O UT Preliminary VALID DATA OUT 6 Rev 1.0 July 2001 EtronTech EM562081 Write Cycle1 (WE# Controlled)(See Note 4) tW C A d d re s s tA S tW P tW R W E# tC W CE 1 # CE 2 tC W tW H Z D O UT t OW (S e e N o te 2 ) (S e e N o te 3 ) tD S D IN Preliminary (S e e N o te 5 ) t DH V A L ID D A T A IN 7 Rev 1.0 (S e e N o te 5 ) July 2001 EtronTech EM562081 Write Cycle 2 (CE1# Controlled)(See Note 4) tWC Addres s tA S tWP tWR W E# t CW C E1# C E2 t CW tW H Z D OU T tL Z t DS D IN Preliminary ( S e e N ot e 5 ) t DH V A L ID DA TA I N 8 Rev 1.0 July 2001 EtronTech EM562081 Write Cycle 3 (CE2 Controlled)(See Note 4) tWC Addres s tA S tWP tWR W E# t CW C E1# C E2 t CW tW H Z D OU T tL Z t DS D IN Preliminary ( S e e N ot e 5 ) t DH V A L ID DA TA I N 9 Rev 1.0 July 2001 EtronTech EM562081 Write Cycle4 (UB#, LB# Controlled)(See Note 4) tWC Addres s tWP tWR W E# t CW C E1# C E2 t CW t W HZ D OU T tL Z t DS D IN ( S e e N ot e 5 ) t DH V A L ID DA TA I N Note: (1) WE# remains HIGH for the read cycle. (2) If CE1# goes LOW (or CE2 goes HIGH) with or after WE# goes LOW, the outputs will remain at high impedance. (3) If CE1# goes HIGH (or CE2 goes LOW) coincident with or before WE# goes HIGH, the outputs will remain at high impedance. (4) If OE# is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. Preliminary 10 Rev 1.0 July 2001 EtronTech EM562081 Data Retention Characteristics (Ta = -40° C to 85° C) Symbol Parameter VDR Data Retention Supply Voltage IDR Data Retention Current CE1# ≥ VDD - 0.2V, CE2 ≤ 0.2V, VIN ≥ VDD - 0.2V or VIN ≤ 0.2V VDD = 1.5V, CE1# ≥ VDD - 0.2V, CE2 ≤ 0.2V, VIN ≥ VDD - 0.2V or VIN ≤ 0.2V tSDR Chip Deselect to Data Retention Mode Time tRDR Recovery Time Min Typ Max Unit 1.5 − 3.6 V − 0.5 3 µA 0 − − ns tRC − − ns CE1# Controlled Data Retention Mode (see Note1) t SDR Data Retention Mode tRDR VDD 2.7V 2.2V VDR Note 1 CE1# GND CE2 Controlled Data Retention Mode (see Note2) D at a R et e nt io n M od e VD D 2.7 V CE2 tRDR tSD R VD R No te 2 0 .4 V GN D Note: (1) If CE1# controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2V or CE2 ≥ VDD - 0.2V. (2) In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2V. Preliminary 11 Rev 1.0 July 2001 EtronTech EM562081 BGA (CSP) Package Diagrams 36-Ball (6.00mm x 8.00mm) BGA (CSP) Units in mm T OP VIEW BO TTO M VIE W 2 C 0.25 S C 0.30 PIN 1 CORNER 1 0.10 S 3 4 5 6 6 5 4 PIN 1 CORNER A B 0.05(48X) 3 2 1 -B0.75 -A- 3.75 0.20( 4X) 0.15 -C - Preliminary SEA TING P LA NE 12 Rev 1.0 July 2001